Superspeed ultra-wideband radio cluster concurrent detection analysis and countering system

Abstract

The invention is suitable for the technical field of radio attack and anti-penetration technology and electronic warfare application, and relates to an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countering system, which comprises a core subnet cluster control system, the wireless communication module is responsible for man-machine interface interaction operation related to radio detection and countering, radio bottom layer detection and countering related parameter configuration, internal subnet communication, child node control, child node state detection query, system state monitoring, radar scanning and external communication; the ultra-wideband cluster radio frequency power amplification system is used for amplifying the power of radio frequency signals output by each sub-node of the core sub-network cluster control system so as to meet the requirements of long-distance radio cluster concurrent detection, countering, penetration testing and analysis; and the NAS storage server is used for receiving the spectrum detection data of the central control node in the core subnet cluster control system and realizing the function of a radio detection spectrum recorder. The detection analysis and countering system provided by the invention is high in flexibility, expansibility and compatibility.

Description

Technical Field

[0001] The present invention belongs to the field of radio attack and defense penetration technology and electronic warfare application technology, and in particular to an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system. Background Art

[0002] Wireless communication has been widely used in various fields (including but not limited to automotive electronics, smart security, smart home, military electronics, satellite communications, wireless radar, radio countermeasures, industrial control and power, etc.). The detection and countermeasure of traditional wireless signals are mainly based on two design concepts: hardware definition (HDR) and software definition (SDR). The main feature of the SDR software-defined radio detection and countermeasure system is that it relies heavily on CPU computing power and modulation and demodulation detection or countermeasure algorithm efficiency, and has high requirements on the professional quality and R&D testing experience of R&D personnel. At the same time, it has extremely high requirements on software high-end processing capabilities such as software programming ability, underlying driver optimization, mathematics, and CPU instruction set operation optimization. In addition, the real-time and quality of radio detection and countermeasure are relatively lower than those of the hardware-defined radio detection and countermeasure system under the same hardware platform. The main feature of the HDR hardware-defined radio reconnaissance and countermeasure system is that the radio detection and countermeasure efficiency and comprehensive performance are very high, but it is insufficient in flexibility and scalability, and at the same time, it has high requirements on the professional quality of RF R&D personnel.

[0003] The underlying technical hardware architecture of traditional radio detection and countermeasure systems is mostly composed of three parts: RF front-end, intermediate frequency conversion, and baseband processing. The overall design is relatively complex, the cost is high, and the R&D and debugging cycle is long and difficult. The key indicators of the relevant radio underlying detection and countermeasures cannot be changed on a large scale and flexibly after the design is completed, resulting in its related products or technologies being only applicable to a single radio detection and countermeasure application scenario. Although there are many similar radio reconnaissance and countermeasure related products on the market (such as drone countermeasure guns), most of them can only meet specific or single radio reconnaissance and countermeasure application scenarios, and have great limitations. They cannot meet large-scale applications and promotion, and are even less capable of meeting the requirements of complex radio confrontation in the future. The core technical indicators related to radio underlying detection and countermeasures, such as the underlying signal link, transmission rate, bit error rate, throughput rate, bit stream, effective bit load rate, analog baseband signal, bandwidth, signal-to-noise ratio, backdoor bug and other real baseband signal transmission characteristics are not visible to users and mainly rely on the unilateral interpretation of the technical manual provided by the manufacturer.

[0004] Therefore, how to provide a radio detection and countermeasure system with high flexibility, scalability and compatibility to combine software defined radio (SDR) and high-speed hardware defined radio (HDR) is an urgent problem to be solved by personnel in this technical field. Summary of the invention

[0005] The purpose of the present invention is to provide an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system to solve the problems of insufficient flexibility, scalability and compatibility of radio signal detection and countermeasure systems in the prior art.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] The present invention provides an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system, comprising:

[0008] The core subnet cluster control system is responsible for the human-machine interface interaction operations related to radio detection and countermeasures, the configuration of radio bottom-level detection and countermeasures related parameters, internal subnet communication, subnode control, subnode status detection query, system status monitoring, radar scanning and external communication;

[0009] Ultra-wideband cluster radio frequency power amplification system, used to amplify the power of radio frequency signals output by each sub-node of the core subnet cluster control system to meet the needs of long-distance radio cluster concurrent detection, countermeasures, penetration testing and analysis;

[0010] NAS storage server, used to receive spectrum detection data of the central control node in the core subnet cluster control system, and realize the function of radio detection spectrum recorder;

[0011] The core subnet cluster control system is communicatively connected with the ultra-wideband cluster radio frequency power amplification system and the NAS storage server respectively.

[0012] Furthermore, the core subnet cluster control system includes a central control node and a radio reconnaissance and countermeasure sub-node. The central control node includes a CPU / MCU module unit, an LCD display module, an external PS / 2 keyboard, a VGA interface driver chip circuit, a CANFD driver circuit, an Ethernet driver circuit, an ADC voltage divider and IO detection circuit, an RTC clock circuit, a FLASH storage circuit, and a first power management module. The CPU / MCU module unit is respectively communicatively connected with the LCD display module, the external PS / 2 keyboard, the VGA interface driver chip circuit, the CANFD driver circuit, the Ethernet driver circuit, the ADC voltage divider and IO detection circuit, the RTC clock circuit, and the FLASH storage circuit.

[0013] Furthermore, the rated input voltage of the first power management module is +5V and the output voltage is +3.3V, which is used to power the CPU / MCU module unit, LCD display module, external PS / 2 keyboard, VGA interface driver chip circuit, CANFD driver circuit, Ethernet driver circuit, ADC voltage divider and IO detection circuit, RTC clock circuit, and FLASH storage circuit.

[0014] Furthermore, the radio reconnaissance and countermeasure sub-node includes a wireless receiving link and a wireless transmitting link, and the wireless receiving link includes a first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, a high-speed parallel accumulator circuit module, a high-speed DAC module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration demodulation module, a first MCU / CPU / ADC module, a first RS232 / UART interface circuit, a first TCP / IP Ethernet chip / circuit, a first external trigger circuit, an RX1 balun balancing circuit, a pre-stage low-noise amplifier circuit, and an LED indication circuit. The first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MC The U / CPU / ADC module and the RX1 balun balancing circuit are respectively communicatively connected, the high-speed DAC module is respectively communicatively connected with the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, and the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module is respectively communicatively connected, the high-speed hardware PLL phase-locked loop variable configuration demodulation module is communicatively connected with the first MCU / CPU / ADC module, the high-speed FIFO receiving module is communicatively connected with the first MCU / CPU / ADC module, the first MCU / CPU / ADC module is also communicatively connected with the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, and the LED indication circuit, and the RX1 balun balancing circuit is also communicatively connected with the front-stage low-noise amplifier circuit.

[0015] Furthermore, the wireless transmission link includes a second high-performance zero-IF architecture wireless transceiver integrated chip circuit, a high-speed FIFO transmission module, a second MCU / CPU / ADC module, a second RS232 / UART interface circuit, a second TCP / IP Ethernet chip / circuit, a second external trigger circuit, a TX1 balun balancing circuit, a RF power amplifier module and a second power management module. The second high-performance zero-IF architecture wireless transceiver integrated chip circuit is respectively communicated with the high-speed FIFO transmission module, the second MCU / CPU / ADC module, and the TX1 balun balancing circuit. The high-speed FIFO transmission module is communicated with the second MCU / CPU / ADC module. The second MCU / CPU / ADC module is also communicated with the second RS232 / UART interface circuit, the second TCP / IP Ethernet chip / circuit, and the second external trigger circuit. The TX1 balun balancing circuit is also communicated with the RF power amplifier module.

[0016] Furthermore, the rated input voltage of the second power management module is +5V, and the output voltages include +3.3V, +2.85V, +2.5V and +1.3V, +5V is used to power the high-speed parallel accumulator circuit module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the second MCU / CPU / ADC module, the front-stage low-noise amplifier circuit, and the RF power amplifier module, and +3.3V is used to power the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, the second high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, the high-speed DAC module, the high-speed FIFO receiving module, and the high-speed F IFO sending module, the first RS232 / UART interface circuit, the second RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, and the second TCP / IP Ethernet chip / circuit are powered, +2.85V is used to power the first high-performance zero-IF architecture wireless transceiver integrated chip circuit and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit, +2.5V is used to power the high-speed FIFO receiving module and the high-speed FIFO sending module, and +1.3V is used to power the first high-performance zero-IF architecture wireless transceiver integrated chip circuit and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit.

[0017] Furthermore, the ultra-wideband cluster radio frequency power method system includes a plurality of ultra-wideband radio frequency power amplification modules, and each of the ultra-wideband radio frequency power amplification modules is connected to one of the radio reconnaissance and countermeasure sub-nodes.

[0018] Furthermore, the spectrum detection data received by the NAS storage server includes real-time dynamic scanning RSSI signal strength values, detected radio baseband signal raw data, real-time or triggered baseband decoding data, and various radio detection and counter-trigger events.

[0019] Compared with the prior art, the ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by the present invention has at least the following beneficial effects:

[0020] Most of the related products of radio reconnaissance and countermeasure in the existing technology can only meet specific or single radio reconnaissance and countermeasure application scenarios, have great limitations, and cannot meet large-scale application and promotion. The present invention utilizes internal dual networking technology (Ethernet and CANFD LAN dual networking) and introduces key design elements of clustered concurrent detection and countermeasures (each cluster unit has multiple independent radio detection & countermeasure nodes), which greatly improves the key core technical indicators of the system's radio detection and countermeasures such as high-speed dynamic response, high bandwidth, high sensitivity, and frequency coverage. At the same time, the system also integrates and associates high-speed software and hardware trigger countermeasure mechanisms, trigger sources, and trigger events related to radio detection and countermeasures to form a radio attack and defense closed-loop detection and countermeasure link, effectively improving the comprehensive performance of the radio detection and countermeasure system. With the help of NAS large-capacity network storage technology, the function of a large-capacity and long-term radio detection spectrum recorder is further realized to facilitate users' targeted offline analysis in the later stage. The present invention also effectively combines software-defined radio (SDR) and high-speed hardware-defined radio (HDR) to ensure the flexibility, scalability, and compatibility of traditional software-defined radio (SDR) detection and countermeasure applications. At the same time, it also has the exclusive technical characteristics of hardware-defined radio (HDR), and the entire system has high flexibility, scalability, and compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the scheme of the present invention, a brief introduction is given below to the figures required for use in the description of the embodiments. Obviously, the figures described below are some embodiments of the present invention. For ordinary technicians in this field, other figures can be obtained based on these figures without paying any creative work.

[0022] Figure 1 A schematic diagram of the overall architecture of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a central control node architecture of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0024] Figure 3A circuit diagram of an LCD display screen module of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0025] Figure 4 An external PS / 2 keyboard circuit diagram of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0026] Figure 5 A VGA interface driver chip circuit diagram of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0027] Figure 6 A CANFD driving circuit diagram of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0028] Figure 7 An ADC voltage division and IO detection circuit diagram of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0029] Figure 8 An RTC clock circuit diagram of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0030] Fig. 9 A FLASH storage circuit diagram of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0031] Fig.10 A schematic diagram of power supply for a first power management module of a central control node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0032] Fig.11 A wireless receiving link architecture diagram of a radio reconnaissance and countermeasure sub-node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0033] Fig.12A wireless transmission link architecture diagram of a radio reconnaissance and countermeasure sub-node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0034] Fig.13 A circuit diagram of a high-speed parallel accumulator circuit module in a wireless receiving link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0035] Fig.14 A circuit diagram of a high-speed DAC module in a wireless receiving link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0036] Fig.15 A circuit diagram of a high-speed FIFO receiving module in a wireless receiving link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0037] Fig.16 A high-speed hardware PLL phase-locked loop variable configuration demodulation module architecture diagram of a wireless receiving link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0038] Fig.17 A first external trigger circuit diagram in a wireless receiving link of a radio reconnaissance and countermeasure sub-node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0039] Fig.18 An RX1 balun balancing circuit diagram in a wireless receiving link of a radio reconnaissance and countermeasure sub-node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0040] Fig.19 A front-stage low-noise amplifier circuit diagram of a wireless receiving link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0041] Fig. 20An LED indication circuit diagram in a wireless receiving link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0042] Fig.21 A circuit diagram of a high-speed FIFO sending module in a wireless sending link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0043] Fig. 22 A second external trigger circuit diagram in a wireless transmission link of a radio reconnaissance and countermeasure sub-node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0044] Fig.23 A TX1 balun balancing circuit diagram in a wireless transmission link of a core subnet cluster control system of a radio reconnaissance and countermeasure subnode of an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present invention;

[0045] Fig.24 A circuit diagram of a radio frequency power amplifier module in a wireless transmission link of a core subnet cluster control system of a radio reconnaissance and countermeasure sub-node of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention;

[0046] Fig.25 A schematic diagram of power supply for a second power management module in a wireless transmission link of a radio reconnaissance and countermeasure sub-node of a core subnet cluster control system of an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field of the present invention; the terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. For example, the directions or positions indicated by the terms "length", "width", "up", "down", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the drawings, which are only for the convenience of description and should not be understood as limitations on the present technical solution.

[0048] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions; the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. In the specification and claims of the present invention and the above-mentioned drawings, when an element is referred to as being "fixed to" or "mounted on" or "disposed on" or "connected to" another element, it may be directly or indirectly located on the other element. For example, when an element is referred to as being "connected to" another element, it may be directly or indirectly connected to the other element.

[0049] In addition, reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0050] The present invention provides an ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system, which is applied to the detection and countermeasure process of wireless signals. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system includes:

[0051] The core subnet cluster control system is responsible for the human-machine interface interaction operations related to radio detection and countermeasures, the configuration of radio bottom-level detection and countermeasures related parameters, internal subnet communication, subnode control, subnode status detection query, system status monitoring, radar scanning and external communication; the ultra-wideband cluster RF power amplification system is used to amplify the power of the RF signal output by each subnode of the core subnet cluster control system to meet the concurrent detection, countermeasures, penetration testing and analysis of long-distance radio clusters; the NAS storage server is used to receive the spectrum detection data of the central control node in the core subnet cluster control system to realize the function of the radio detection spectrum recorder.

[0052] The detection, analysis and countermeasure system provided by the present invention has higher flexibility, scalability and compatibility than the prior art.

[0053] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0054] The present invention provides an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system, which is applied to the detection and countermeasure process of wireless signals. Figures 1 to 25In this embodiment, the ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system includes:

[0055] The core subnet cluster control system can work independently and is mainly responsible for the core functions such as human-machine interface interaction operations related to radio detection and countermeasures, radio bottom-level detection and countermeasures related parameter configuration, internal subnet communication, subnode control, subnode status detection query, system status monitoring, radar scanning, external communication, etc.; the ultra-wideband cluster RF power amplification system is mainly responsible for further power amplification of the RF signals output by each subnode of the core subnet cluster control system to meet the application scenarios of long-distance radio cluster concurrent detection, countermeasures, penetration testing, and analysis; the NAS storage server is a large-capacity storage server that receives spectrum detection data from the central control node in the core subnet cluster control system. It is mainly used to realize the function of radio detection spectrum recorder and record the relevant spectrum data of radio detection (including but not limited to real-time dynamic scanning RSSI signal strength value, detected radio baseband signal raw data, real-time or triggered baseband decoding data, various radio detection and countermeasure trigger events, etc.); the core subnet cluster control system is communicated and connected with the ultra-wideband cluster RF power amplification system and the NAS storage server respectively.

[0056] Furthermore, in this embodiment, the core subnet cluster control system includes a central control node, a radio reconnaissance and countermeasure sub-node, the central control node includes a CPU / MCU module unit, an LCD display module, an external PS / 2 keyboard, a VGA interface driver chip circuit, a CANFD driver circuit, an Ethernet driver circuit, an ADC voltage divider and IO detection circuit, an RTC clock circuit, a FLASH storage circuit, and a first power management module. The CPU / MCU module unit is communicated and connected with the LCD display module, the external PS / 2 keyboard, the VGA interface driver chip circuit, the CANFD driver circuit, the Ethernet driver circuit, the ADC voltage divider and IO detection circuit, the RTC clock circuit, and the FLASH storage circuit respectively, and the central control The node is an important control node of the core subnet cluster control system. It uses an external PS2 keyboard as its command input. It is mainly responsible for the relevant parameter configuration, trigger configuration, system status monitoring, spectrum recording storage drive, and external communication of each radio detection and countermeasure sub-node. At the same time, it performs human-computer interaction through the 10.1-inch LCD screen UI interface to display relevant UI interface operation menus, system information, radio dynamic scanning, detection and countermeasure parameter configuration related information. Secondly, it is also responsible for driving and reading the RTC clock circuit to ensure that the clock display is normal, responsible for driving the external FLASH chip, and convenient for storing necessary configuration information. In addition, through the external DAC voltage divider and IO detection circuit, the external lithium battery voltage and the main and standby power supply status are monitored in real time.

[0057] Specifically, the main functions of the CPU / MCU module unit include:

[0058] Drive an external PS / 2 keyboard through the standard PS / 2 interface (PS2_CLK, PS2_DAT), detect external keyboard input, and facilitate human-machine interface operation; drive a 10.1-inch LCD display through the RGB565 standard interface to display UI interface human-machine interaction operations, radio detection & countermeasures, related parameter configuration, status detection and other related information; convert the LCD screen display content into a standard VGA interface output through the RGB565 standard interface to facilitate external display display; drive the CANFD driver chip (CAN_H, CAN_L) through the CANFD interface to communicate with each sub-node in the subnet; drive the Ethernet driver chip through the RMII interface chip, communicate with each sub-node within the subnet or the external network; drive the RTC clock chip through the I2C interface (SCL, SCK) to read the real-time clock; drive the FLASH chip through the I2C interface (SCL, SCK) to store the necessary configuration information; detect the lithium battery voltage and the external main and standby power status through the ADC voltage divider circuit and IO detection circuit; realize the radio detection spectrum recorder function, drive the external NAS large-capacity network storage server, and record the relevant spectrum data of radio detection (including but not limited to the RSSI signal strength value of real-time dynamic scanning, the original data of detected radio baseband signals, real-time or triggered baseband decoding data, various radio detection & counter-trigger events, etc.).

[0059] Specifically, the LCD display module is driven by the CPU / MCU module unit and is used for UI interface display to facilitate human-computer interaction. The displayed content includes but is not limited to relevant UI interface operation menus, system information, radio dynamic scanning, detection and countermeasure parameter configuration and other related information.

[0060] Specifically, the external PS / 2 keyboard is driven by the CPU / MCU module unit, PS2_CLK is the clock input signal of this circuit module (driven by the CPU / MCU module unit), PS2_DAT is the bidirectional data transmission signal of this circuit module (driven or collected by the CPU / MCU module unit), and the driving interface circuit is shown in the figure. The external PS2 keyboard is used as its command input to facilitate human-computer UI interface interaction.

[0061] Specifically, the VGA interface driver chip circuit is driven by the CPU / MCU module unit, converting the standard RGB565 video signal (provided by the high-performance CPU / MCU module unit circuit) into a VGA interface output, facilitating synchronous display on an external display.

[0062] Specifically, the CANFD drive circuit is driven by the CPU / MCU module unit and communicates with each radio detection and countermeasure sub-node inside the subnet. CAN_RX is the output signal of this circuit module, which is output to the CANFD interface of the CPU / MCU module unit. CAN_TX is the input signal of this circuit module, which is driven by the CPU / MCU module unit. CAN_SLEEP is the sleep control input signal of this circuit module, which is provided by the CPU / MCU module unit. CAN_H and CAN_L are standard CANFD output signals, which are brought out through the 2Pin terminal block.

[0063] Specifically, the Ethernet driving circuit is driven by the CPU / MCU module unit through the RMII interface, communicates with the radio detection and countermeasure sub-nodes within the subnet or the external network, and communicates with the external NAS large-capacity network storage server to realize the spectrum recorder function and record the relevant spectrum data of radio detection (including but not limited to the RSSI signal strength value of real-time dynamic scanning, the original data of detected radio baseband signals, real-time or triggered baseband decoding data, various radio detection & countermeasure trigger events, etc.).

[0064] Specifically, the ADC voltage divider circuit uses precision resistor voltage divider to detect the lithium battery voltage. BAT_DAC is the output signal of this circuit module, which is output to the CPU / MCU module unit for external lithium battery voltage collection; the IO detection circuit detects the external input switch quantity through the NPN MOS tube, which is used to detect the main and standby power status of the system. IO_INPUT is connected to the external main and standby power switch quantity, and the CHECK_IO signal is output to the CPU / MCU module unit.

[0065] Specifically, the RTC clock circuit provides accurate time and is driven by the CPU / MCU module unit through a standard I2C interface. SCL is the I2C interface clock signal, which is provided by the CPU / MCU module unit output. SDA is the bidirectional data transmission signal of the I2C interface.

[0066] Specifically, the FLASH storage circuit is used to store necessary configuration information and is driven by the CPU / MCU module unit through a standard I2C interface. SCL is the I2C interface clock signal, which is provided by the CPU / MCU module unit output. SDA is the bidirectional data transmission signal of the I2C interface.

[0067] Specifically, the first power management module is responsible for supplying power to each circuit unit module in the device, with a rated input voltage of +5V / DC and an output voltage of +3.3V.

[0068] Furthermore, in this embodiment, the radio reconnaissance and countermeasure sub-node includes a wireless receiving link and a wireless transmitting link, and the wireless receiving link includes a first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, a high-speed parallel accumulator circuit module, a high-speed DAC module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration demodulation module, a first MCU / CPU / ADC module, a first RS232 / UART interface circuit, a first TCP / IP Ethernet chip / circuit, a first external trigger circuit, an RX1 balun balancing circuit, a pre-stage low-noise amplifier circuit, an LED indication circuit, a first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and a high-speed parallel accumulator circuit module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration The demodulation module, the first MCU / CPU / ADC module, and the RX1 balun balancing circuit are respectively communicatively connected, the high-speed DAC module is respectively communicatively connected with the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, and the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module is respectively communicatively connected with the first MCU / CPU / ADC module, the high-speed FIFO receiving module is communicatively connected with the first MCU / CPU / ADC module, the first MCU / CPU / ADC module is also communicatively connected with the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, and the LED indication circuit, and the RX1 balun balancing circuit is also communicatively connected with the front-stage low-noise amplifier circuit.

[0069] Specifically, the first high-performance zero-IF architecture wireless transceiver integrated chip circuit is one of the core circuit modules of the radio reconnaissance and countermeasure sub-node. It is designed based on the wireless transceiver integrated chip of the zero-IF architecture and adopts the concept of software-defined radio technology. Its main function is to configure the various working parameters of the chip (SPI bus configuration) through the first MCU / CPU / ADC module circuit of the back stage, including but not limited to the wireless receiving channel, wireless receiving frequency, bandwidth, amplifier circuit working mode, filtering characteristics, ADC sampling rate, output interface, baseband signal output characteristics and other parameters, select the specified wireless receiving channel, make it work in a specific wireless receiving working state, and receive The frequency can be accurately and continuously adjusted within the range of 70MHz to 6GHz, so as to flexibly adapt to receive wireless signals of different frequencies, ensuring the flexibility, scalability and compatibility of wireless applications; the external specific radio signal is received through the external antenna, and after precise processing by the internal pre-low noise amplifier, local oscillator mixer, AGC / MGC amplifier circuit, filter circuit, DAC, ADC and other internal unit circuits of this circuit module, a specific baseband IQ orthogonal signal is output to the outside for use by the subsequent circuit module. The input signal of this circuit module is the RX balun balanced circuit (RX1) of the front stage 1 channel, which adopts differential signal interface input, which can effectively suppress common mode noise and interference, and improve The signal-to-noise ratio of the wireless receiving signal, the RESET signal is the internal reset signal of the circuit, which is controlled by the first MCU / CPU / ADC module circuit module of the subsequent stage. The output signals VREF_CMP1 and VREF_CMP2 are the output signals of the internal DAC auxiliary unit of the circuit, which provide the "high-speed hardware PLL phase-locked loop variable configuration demodulation module" of the subsequent stage with the judgment comparison reference voltage required for hardware demodulation of the baseband signal. I[0:11] and Q[0:11] are the original baseband IQ orthogonal output signals of the circuit module. Each baseband IQ orthogonal signal is independently output by a 12-bit parallel port and synchronously output to the high-speed parallel accumulator circuit module of the subsequent stage. And the high-speed FIFO receiving module effectively improves the sampling rate and throughput rate of the wireless receiving baseband signal, ensuring the technical prerequisites of high-speed wireless communication transmission from the hardware bottom layer. DATA_CLK is the clock indication signal of the baseband IQ orthogonal output signal, which can be configured in SDR or DDR working mode according to the actual application, and synchronously output to the DAC module and high-speed FIFO receiving module of the subsequent stage. RX_FRAME is the baseband IQ orthogonal signal transmission status indication signal, which is output to the first MCU / CPU / ADC module circuit of the subsequent stage. RESET is the reset control signal of this circuit module, which is controlled by the first MCU / CPU / ADC module circuit of the subsequent stage.

[0070] Specifically, the high-speed parallel accumulator circuit module is one of the core embodiments of the hardware defined radio (HDR) technology concept. It is composed of an I signal high-speed parallel accumulator, a Q signal high-speed parallel accumulator and an addend initialization configuration circuit. Its main function is to perform independent symbol accumulation operations on the two original baseband IQ orthogonal digital signals output by the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage, and each signal is initialized to 0x7ff (decimal value is 2047). The two signed positive and negative AC orthogonal IQ signals (decimal value range is -2047 to +2047) output by the block are converted into orthogonal IQ signals greater than 0 (value range is 0 to +4047) respectively, which is convenient for the subsequent high-speed DAC module to process. The input signal of the circuit is the two original baseband IQ orthogonal signals I[0:11] and Q[0:11] output by the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage, and the output signal is the two accumulated IQ orthogonal signals IADD[0:11] and QADD[0:11], which serve as the input signal of the subsequent high-speed DAC module circuit.

[0071] Specifically, the high-speed DAC module is one of the core embodiments of the hardware-defined radio (HDR) technology concept. It is composed of I signal high-speed DAC and Q signal high-speed DAC circuit units. Its main function is to perform high-speed DAC conversion on the two IQ orthogonal signals IADD[0:11] and QADD[0:11] output by the previous high-speed parallel accumulator circuit module, and convert the two IQ orthogonal digital signals into IQ orthogonal differential current analog signals for use by the subsequent high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit. The input signal of this module circuit is the previous The high-speed parallel accumulator circuit module outputs two signals, IADD[0:11] and QADD[0:11], and the DATA_CLK input signal is the DAC conversion clock drive signal, which is provided by the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) of the previous stage. The output signals of this module circuit are the current differential signals Iia1 and Iia2 of the I orthogonal signal and the current differential signals Qia1 and Qia2 of the Q orthogonal signal, which provide suitable baseband demodulation input signals to the high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit of the subsequent stage.

[0072] Specifically, the high-speed FIFO receiving module is one of the most core embodiments of the high-speed software defined radio (HDR) technical concept. It is composed of an I signal high-speed receiving FIFO, a Q signal high-speed receiving FIFO, and a FIFO bypass control circuit unit. Its main function is to receive the IQ orthogonal signal output by the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage, cache the IQ orthogonal digital signal in the high-speed FIFO, reduce the computing and processing pressure of the first MCU / CPU / ADC module of the subsequent stage, and effectively improve the processing capability of high-speed baseband signal demodulation. The input signals I[0:11] and Q[0:11] are the IQ orthogonal signals output by the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage. The input signal DATA_CLK is the reference clock signal of the IQ orthogonal signal output of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage. The input signals RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the reset signal, write FIFO control signal, and read FIFO control signal of this circuit module, which are controlled by the first MCU / CPU / ADC module circuit of the subsequent stage. Iout[0:11] and Qout[0:11] are the baseband orthogonal signal FIFO output signals of this circuit, which are provided to the first MCU / CPU / ADC module of the subsequent stage for use, combined with the radio scanning penetration application, so as to meet the functions of digital storage, software demodulation, operation processing, and analysis of baseband orthogonal signals. The FIFO bypass control circuit controls whether the FIFO high-speed buffer is directly bypassed, and flexibly switches the internal IQ data stream reference clock indication signal. In the bypass mode, the FIFO high-speed buffer function is disabled, and the IQ data channel of the first MCU / CPU / ADC module in the rear stage and the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module in the front stage are directly connected, which is convenient for real-time processing of IQ data streams in low-speed wireless communication applications.

[0073] Specifically, the high-speed hardware PLL phase-locked loop variable configuration demodulation module is one of the core embodiments of the hardware defined radio (HDR) technology concept. It is designed based on the high-speed hardware PLL phase-locked loop variable configuration automatic tracking technology and high-speed analog switch matrix technology. It is composed of the I signal high-speed hardware PLL phase-locked loop variable configuration demodulation module and the Q signal high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit unit. Its main function is to perform real-time and synchronous hardware demodulation on the IQ orthogonal current differential signal output by the previous high-speed DAC module. The demodulation mode also supports baseband amplitude signal demodulation (AM) and frequency The output signal DEMOD_OUT_ASK1 of this circuit module is the baseband amplitude signal demodulation (AM) digital output signal, and the DEMOD_OUT_ASK2 signal is the baseband amplitude signal demodulation (AM) auxiliary output signal, which can provide auxiliary output for n-ASK standard baseband signal demodulation. The output signal DEMOD_OUT_PFSK1 is the baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM) digital output signal, and the output signal DEMOD_OUT_PFSK2 is the baseband rate signal demodulation. Modulation (FM) and baseband phase signal demodulation (PM) auxiliary output signals are used to indicate the current baseband signal frequency and phase lock status. All output signals are used by the first MCU / CPU / ADC module circuit module in the subsequent stage. ASK_CH_SEL_A, ASK_CH_SEL_B, and ASK_CH_SEL_C are the input control signals of this module circuit. According to the characteristics of baseband signals with different attributes, a specific baseband amplitude signal demodulation (AM) high-speed analog matrix switch channel is selected. PFSK_CH_SEL_A, PFSK_CH_SEL_B, and PFSK _CH_SEL_C is the input control signal of this module circuit. According to the baseband signal characteristics of different properties, it selects specific baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM) high-speed analog matrix switch channels, which effectively improves the diversified application scenarios of baseband signal demodulation and ensures the flexibility, compatibility and scalability of baseband signal demodulation. VREF_CMP1 and VREF_CMP2 are the DAC auxiliary output signals of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage, which provide the baseband signal judgment comparison reference voltage for this circuit module.

[0074] Specifically, the first MCU / CPU / ADC module is mainly responsible for controlling the circuit parameters of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage according to the control instructions sent by the external digital interface, configuring the relevant parameters to make it work in a specific wireless receiving state, and at the same time controlling and driving the high-speed FIFO receiving module and the high-speed hardware PLL phase-locked loop variable configuration demodulation module of the previous stage to ensure that the various circuit modules inside the device work efficiently and collaboratively. This circuit module also receives the digital baseband IQ orthogonal signal output by the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the previous stage, and can directly perform software demodulation processing and analysis on the digital baseband signal based on software-defined radio technology to flexibly adapt to different wireless reception application scenarios. This circuit module is also responsible for receiving and processing The hardware demodulation output signal of the front-stage high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit is processed. Compared with software demodulation, the hardware demodulation output efficiency and rate are higher, and the stability and anti-interference are stronger, which effectively reduces the MCU / CPU operation and processing pressure of this circuit module, and can significantly improve the hardware demodulation capability of high-speed wireless signals. DEMOD_OUT_ASK1 is the baseband amplitude signal demodulation (AM) digital output signal of this circuit module, and DEMOD_OUT_ASK2 is the baseband amplitude signal demodulation (AM) auxiliary output signal of this circuit module. Both are provided by the front-stage high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit, which can realize the function of hardware baseband amplitude signal demodulation. Combined with the relevant auxiliary signal output, it can further realize the n-ASK multi-standard baseband signal hardware demodulation function. DEMOD_OUT_PFSK1 is the baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM) digital input signal of this circuit module, and DEMOD_OUT_PFSK2 is the baseband rate signal demodulation (FM) and baseband phase signal demodulation (PM) auxiliary input signal of this circuit module, which is used to indicate the current baseband signal frequency and phase lock status. They are provided by the first high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit of the previous stage, and can realize the functions of hardware-based baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM). Combined with relevant auxiliary Auxiliary signal output can further realize the n-FSK, n-PSK multi-standard baseband signal hardware demodulation function. ASK_CH_SEL_A, ASK_CH_SEL_B, ASK_CH_SEL_C are the output control signals of this module circuit, which control the previous high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit to select a specific baseband amplitude signal demodulation (AM) high-speed analog matrix switch configuration channel. PFSK_CH_SEL_A, PFSK_CH_SEL_B, PFSK_CH_SEL_C are the output control signals of this module circuit.Control the previous stage high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit to select specific baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM) high-speed analog matrix switch configuration channels. RSTN, WEN, WRST, WCLK, REN, RRST, RCLK are the FIFO reset signal, write FIFO control signal, and read FIFO control signal of this circuit module. They are mainly responsible for controlling the previous stage high-speed FIFO receiving module circuit to work in coordination with other circuit modules. The Iout[0:11] and Qout[0:11] signals are provided by the previous stage high-speed FIFO receiving module. RX_FRAME is the IQ baseband signal transmission status indication signal, which is provided by the previous stage first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit (RX link) module circuit output. The SPI bus is the previous stage first high-performance zero intermediate frequency architecture wireless transceiver. The parameter configuration / reading bus of the integrated chip circuit (RX link) module circuit, RESET is the reset control signal of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module circuit of the previous stage. This circuit module is also responsible for driving the first TCP / IP Ethernet chip / circuit module and the first RS232 / UART interface circuit module to realize external wired interface communication transmission, which can meet the functional realization of wireless base stations and wireless routing gateways. At the same time, it also receives the trigger signals RX_EXT_TRG_IN1 and RX_EXT_TRG_IN2 of the first external trigger circuit module to ensure fast, accurate and directional wireless receiving capabilities. This circuit module communicates internally with the first MCU / CPU / ADC module circuit through an internal high-speed communication bus to ensure the real-time and high efficiency of data interaction within the device. At the same time, the module circuit is also mainly responsible for controlling the circuit parameters of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module of the front stage according to the control instructions sent by the external digital interface, configuring relevant parameters to make it work in a specific wireless transmission state, and at the same time controlling and driving the high-speed FIFO transmission module of the front stage to ensure that the various circuit modules inside the device work efficiently and collaboratively. This circuit module outputs special The original IQ orthogonal baseband digital signal is given to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module of the previous stage to flexibly adapt to different wireless transmission application scenarios. RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the FIFO reset signal, write FIFO control signal, and read FIFO control output signal of this circuit module. It is mainly responsible for controlling the previous high-speed FIFO transmission module circuit to work in coordination with other circuit modules. TX_FRAME is the IQ baseband signal transmission status indication signal, which is output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module of the previous stage.The SPI bus is the parameter configuration / reading bus of the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit (TX link) module of the previous stage, and RESET is the reset control signal of the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit (TX link) module of the previous stage. This circuit module is also responsible for driving the LED indication circuit, the first TCP / IP Ethernet chip / circuit module, and the first RS232 / UART interface circuit module to realize external wired interface communication transmission, which can meet the functional realization of wireless base stations and wireless routing gateways. At the same time, it also receives the trigger signals TX_EXT_TRG_IN1 and TX_EXT_TRG_IN2 of the first external trigger circuit module to ensure fast, accurate, and directional wireless transmission capabilities. This circuit module communicates internally with the first MCU / CPU / ADC module circuit through an internal high-speed communication bus to ensure the real-time and high efficiency of data interaction within this device. ,

[0075] Specifically, the first RS232 / UART interface circuit is driven by the first MCU / CPU / ADC module, has a high and adjustable communication rate, can realize RS232 / UART-based communication, supports protocol trigger function, and the trigger mode can support flexible configuration of RS232 / UART / Ethernet and output through the wiring terminal.

[0076] Specifically, the first TCP / IP Ethernet chip / circuit is driven by the first MCU / CPU / ADC module based on the RMII interface, which can realize high-speed network communication based on TCP / IP Ethernet and support protocol triggering function. The triggering mode can support flexible configuration of RJ45 Ethernet communication protocol and lead out through the RJ45 interface.

[0077] Specifically, the first external trigger circuit is a key circuit part for realizing directional, high-speed, precise wireless reception of external trigger, comparator trigger, edge trigger, and manual trigger functions. It outputs two signals, RX_EXT_TRG_IN1 and RX_EXT_TRG_IN2, to the first MCU / CPU / ADC module circuit through DC coupling of resistor voltage division. According to the remote instructions or the data configured in advance by the user, the trigger functions of the above-mentioned different modes are realized and brought out through the wiring terminals.

[0078] Specifically, the RX balun balancing circuit is composed of a 1-channel independent balun balancing circuit. Its main function is to achieve impedance matching between the front-end and rear-end circuits, convert the RF front-end wireless signal from single-ended to differential and then output it in a balanced manner to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the rear stage, effectively suppress the RF front-end common-mode noise and external interference, and improve the RF front-end input signal signal-to-noise ratio. The RFIN signal is provided by the output of the front-end low-noise amplifier circuit, which further enhances the sensitivity of the received signal and meets the needs of long-distance radio signal detection.

[0079] Specifically, the front-stage low-noise amplifier circuit is a low-noise amplifier circuit for the front-stage radio frequency receiving signal. The purpose is to further enhance the sensitivity of the receiving signal to meet the needs of long-distance radio signal detection. The input side is connected to an external antenna, and the RXRF_OUT signal is the output signal of this circuit module, which is output to the next-stage RX balun balancing circuit.

[0080] Specifically, the LED indication circuit is used to indicate the working status of each radio reconnaissance & countermeasure sub-node. LED_RUN, LED_SCAN, and LED_ATK represent the sub-node running light, radar scanning indicator light, and radio counterattack indicator light, respectively. The three control signals are all provided by the first MCU / CPU / ADC module.

[0081] Specifically, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) is designed based on the wireless transceiver integrated chip with zero-IF architecture and adopts the concept of software-defined radio technology. Its main function is to configure the various working parameters of the chip (SPI bus configuration) through the second MCU / CPU / ADC module circuit module of the subsequent stage, including but not limited to wireless transmission channel, wireless transmission frequency, bandwidth, amplifier circuit working mode, filtering characteristics, ADC sampling rate, output interface, baseband signal output characteristics and many other parameters, select the specified wireless transmission channel, and make it work in a specific wireless transmission working state. The transmission frequency can be accurately and continuously adjusted in the range of 46.875MHz to 6GHz, so as to flexibly adapt to the transmission of wireless signals of different frequencies, thereby ensuring the flexibility, scalability and compatibility of wireless applications. The specific IQ baseband orthogonal signal stream is driven by the second MCU / CPU / ADC module circuit of the back stage, and is buffered by the high-speed FIFO sending module circuit. After being precisely processed by many internal unit circuits such as the DAC, filtering circuit, AGC / MGC amplification circuit, local oscillator mixer, and front low noise amplifier in this circuit module, a specific radio signal is sent through the balun balanced circuit and the external antenna. The output signal of this circuit module is the balun balanced circuit (TX1) of the front stage 1 channel, which adopts the differential signal interface output, which can effectively suppress common mode noise and interference and improve the signal-to-noise ratio of the wireless transmission signal. Iout[0:11] and Qout[0:11] are the original The baseband IQ orthogonal input signal is provided by the subsequent high-speed FIFO sending module. Each baseband orthogonal signal is independently output by a 12-bit parallel port, which effectively improves the sampling rate and throughput rate of the wireless transmission baseband signal, and ensures the technical prerequisites for high-speed wireless communication transmission from the hardware bottom layer. DATA_CLK is the clock indication signal of the baseband IQ orthogonal output signal, which can be configured in SDR or DDR working mode according to the actual application, and synchronously output to the subsequent high-speed FIFO sending module. TX_FRAME is the baseband IQ orthogonal signal transmission status indication signal, and RESET is the reset control signal of this circuit module, which is controlled by the second MCU / CPU / ADC module circuit module of the subsequent stage.

[0082] Specifically, the high-speed FIFO sending module is one of the most core embodiments of the high-speed software-defined radio (HDR) technical concept. It is composed of an I signal high-speed sending FIFO, a Q signal high-speed sending FIFO, and a FIFO bypass control circuit unit. Its main function is to receive the IQ orthogonal signal output by the second MCU / CPU / ADC module circuit of the subsequent stage, cache the high-speed IQ orthogonal digital signal in the high-speed FIFO, and then output it to the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module of the previous stage, thereby reducing the computing and processing pressure of the second MCU / CPU / ADC module of the subsequent stage, and effectively improving the sending / modulation processing capability of the high-speed baseband signal. The input signals I[0:11] and Q[0:11] are for the second MCU / CPU / ADC module of the subsequent stage. The block outputs the IQ orthogonal output signal, the input signal DATA_CLK is the reference clock signal of the IQ orthogonal input signal of the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module of the previous stage, the input signals RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the reset signal, write FIFO control signal, and read FIFO control signal of this circuit module, which are controlled by the second MCU / CPU / ADC module circuit of the subsequent stage, Iout[0:11] and Qout[0:11] are the baseband IQ orthogonal signal FIFO output signals of this circuit, which are provided to the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) of the previous stage for use, and are used to realize software-defined radio baseband signal modulation output. The FIFO bypass control circuit controls whether the FIFO high-speed buffer is directly bypassed, and flexibly switches the internal IQ data stream reference clock indication signal. In bypass mode, the FIFO high-speed buffer function is disabled, and the IQ data channel of the second MCU / CPU / ADC module in the rear stage and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module in the front stage are directly connected, which is convenient for real-time processing of IQ data streams in low-speed wireless communication applications.

[0083] Specifically, the second external trigger circuit is a key circuit part for realizing directional, high-speed, and precise wireless transmission of external trigger, comparator trigger, edge trigger, and manual trigger functions. It outputs two signals, TX_EXT_TRG_IN1 and TX_EXT_TRG_IN2, to the second MCU / CPU / ADC module circuit through DC coupling of resistor voltage division (it can also be collected through MOS tube input). According to the remote instructions or data configured in advance by the user, the trigger functions of the above-mentioned different modes are realized and brought out through the wiring terminals.

[0084] Specifically, the TX balun balanced circuit is composed of a 1-channel independent balun balanced circuit. Its main function is to achieve impedance matching between the front-end and rear-end circuits, convert the RF front-end wireless signal from differential balance to single-ended and then output it to the rear-end antenna, effectively suppress the RF front-end common-mode noise and external interference, and improve the RF transmission signal signal-to-noise ratio. RFOUT is the output signal of this circuit module, which is provided to the input end of the first-stage RF power amplifier module to further amplify the RF signal.

[0085] Specifically, the RF power amplifier module is a full-bandwidth wireless RF power amplifier module with a high bandwidth design that supports full-band RF signal power amplification. TXRF_IN is the RF input signal, which is provided by the TX balun balanced circuit and output to an external antenna, and is led out through an SMA interface.

[0086] Specifically, the second power management module is the internal power management module of each radio reconnaissance and countermeasure sub-node, which is responsible for supplying power to each circuit unit module in the device. The rated input voltage is +5V / DC, and the output voltages are: +3.3V, 2.85V, +2.5V, +1.3. +5V is used to supply power to the high-speed parallel accumulator circuit module, the PLL high-speed hardware phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the second MCU / CPU / ADC module, the RF power amplifier module, and the front-stage low-noise amplifier circuit. +3.3V is output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link), the high-speed DAC module, and the high FIFO receiver. Module, the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link), and the high-speed FIFO sending module, +2.85V is output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link), +2.5V is output to the high-speed FIFO receiving module and the high-speed FIFO sending module, and +1.3V is output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link).

[0087] In some other embodiments, the relevant FIFO modules of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) can also be deleted and eliminated according to actual specific circumstances, and directly bypassed to achieve the purpose of saving space and cost.

[0088] Furthermore, in this embodiment, the ultra-wideband cluster RF power amplification system is a high-power radio transmission system, which is mainly responsible for further power amplification of the RF signal output by each sub-node of the core subnet cluster control system to meet the application scenarios of long-distance radio cluster concurrent detection, countermeasures, penetration testing, and analysis. The system adopts a cluster design internally, and is composed of 20 power amplification modules. Each module corresponds to a radio reconnaissance and countermeasure sub-node radio transmission output signal to meet the requirements of radio cluster concurrent countermeasure high-power transmission. RFIN is the RF input signal, and the output signal is connected to an external high-power antenna. A 50-ohm impedance matching circuit has been integrated and designed internally.

[0089] Furthermore, the NAS storage server is a large-capacity storage server that uses mature standard products on the market, communicates through network protocols, and receives spectrum detection data from the central control node in the core subnet cluster control system. It is mainly used to realize the function of a radio detection spectrum recorder and record relevant spectrum data of radio detection (including but not limited to real-time dynamic scanning of RSSI signal strength values, detected radio baseband signal raw data, real-time or triggered baseband decoding data, various radio detection & countermeasure trigger events, etc.).

[0090] The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system described in the above embodiment is compared with the existing technology. Most of the related products of radio reconnaissance and countermeasure in the existing technology can only meet specific or single radio reconnaissance and countermeasure application scenarios, have great limitations, and cannot meet large-scale application and promotion. The present invention utilizes internal dual networking technology (Ethernet and CANFD LAN dual networking) and introduces key design elements of clustered concurrent detection and countermeasures (each cluster unit has multiple independent radio detection & countermeasure nodes), which greatly improves the key core technical indicators of the system's radio detection and countermeasures such as high-speed dynamic response, high bandwidth, high sensitivity, and frequency coverage. At the same time, the system also integrates and associates high-speed software and hardware trigger countermeasure mechanisms, trigger sources, and trigger events related to radio detection and countermeasures to form a radio attack and defense closed-loop detection and countermeasure link, effectively improving the comprehensive performance of the radio detection and countermeasure system. With the help of NAS large-capacity network storage technology, the function of a large-capacity and long-term radio detection spectrum recorder is further realized to facilitate users' later targeted analysis. The present invention also effectively combines software-defined radio (SDR) and high-speed hardware-defined radio (HDR) to ensure the flexibility, scalability, and compatibility of traditional software-defined radio (SDR) detection and countermeasure applications. At the same time, it also has the exclusive technical characteristics of hardware-defined radio (HDR), and the entire system has high flexibility, scalability, and compatibility.

[0091] Obviously, the embodiments described above are only preferred embodiments of the present invention, rather than all embodiments. The preferred embodiments of the present invention are shown in the accompanying drawings, but they do not limit the patent scope of the present invention. The present invention can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive. Although the present invention has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific embodiments, or to perform equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of the present invention, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present invention.

Claims

1. An ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system, characterized in that: include: The core subnet cluster control system is responsible for the human-machine interface interaction operations related to radio detection and countermeasures, the configuration of radio bottom-level detection and countermeasures related parameters, internal subnet communication, subnode control, subnode status detection query, system status monitoring, radar scanning and external communication; Ultra-wideband cluster radio frequency power amplification system, used to amplify the power of radio frequency signals output by each sub-node of the core subnet cluster control system to meet the needs of long-distance radio cluster concurrent detection, countermeasures, penetration testing and analysis; NAS storage server, used to receive spectrum detection data of the central control node in the core subnet cluster control system, and realize the function of radio detection spectrum recorder; The core subnet cluster control system is communicatively connected with the ultra-wideband cluster radio frequency power amplification system and the NAS storage server respectively.

2. The ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system according to claim 1, characterized in that: The core subnet cluster control system includes a central control node and a radio reconnaissance and countermeasure sub-node. The central control node includes a CPU / MCU module unit, an LCD display module, an external PS / 2 keyboard, a VGA interface driver chip circuit, a CANFD driver circuit, an Ethernet driver circuit, an ADC voltage divider and IO detection circuit, an RTC clock circuit, a FLASH storage circuit, and a first power management module. The CPU / MCU module unit is respectively communicatively connected with the LCD display module, the external PS / 2 keyboard, the VGA interface driver chip circuit, the CANFD driver circuit, the Ethernet driver circuit, the ADC voltage divider and IO detection circuit, the RTC clock circuit, and the FLASH storage circuit.

3. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 2, characterized in that: The rated input voltage of the first power management module is +5V and the output voltage is +3.3V, which is used to power the CPU / MCU module unit, LCD display module, external PS / 2 keyboard, VGA interface driver chip circuit, CANFD driver circuit, Ethernet driver circuit, ADC voltage divider and IO detection circuit, RTC clock circuit, and FLASH storage circuit.

4. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 2, characterized in that: The radio reconnaissance and countermeasure sub-node includes a wireless receiving link and a wireless sending link, and the wireless receiving link includes a first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, a high-speed parallel accumulator circuit module, a high-speed DAC module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration demodulation module, a first MCU / CPU / ADC module, a first RS232 / UART interface circuit, a first TCP / IP Ethernet chip / circuit, a first external trigger circuit, an RX1 balun balancing circuit, a front-stage low-noise amplifier circuit, and an LED indication circuit. The first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, the RX1 balun balancing circuit, the front-stage low-noise amplifier circuit, and the LED indication circuit. The CPU / ADC module and the RX1 balun balancing circuit are respectively communicatively connected, the high-speed DAC module is respectively communicatively connected with the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, and the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module is respectively communicatively connected with the first MCU / CPU / ADC module, the high-speed FIFO receiving module is communicatively connected with the first MCU / CPU / ADC module, the first MCU / CPU / ADC module is also communicatively connected with the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, and the LED indication circuit, and the RX1 balun balancing circuit is also communicatively connected with the pre-stage low-noise amplifier circuit.

5. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 4, characterized in that: The wireless transmission link includes a second high-performance zero-IF architecture wireless transceiver integrated chip circuit, a high-speed FIFO transmission module, a second MCU / CPU / ADC module, a second RS232 / UART interface circuit, a second TCP / IP Ethernet chip / circuit, a second external trigger circuit, a TX1 balun balancing circuit, a RF power amplifier module and a second power management module. The second high-performance zero-IF architecture wireless transceiver integrated chip circuit is communicatively connected to the high-speed FIFO transmission module, the second MCU / CPU / ADC module, and the TX1 balun balancing circuit respectively. The high-speed FIFO transmission module is communicatively connected to the second MCU / CPU / ADC module. The second MCU / CPU / ADC module is also communicatively connected to the second RS232 / UART interface circuit, the second TCP / IP Ethernet chip / circuit, and the second external trigger circuit respectively. The TX1 balun balancing circuit is also communicatively connected to the RF power amplifier module.

6. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 5, characterized in that: The rated input voltage of the second power management module is +5V, and the output voltages include +3.3V, +2.85V, +2.5V and +1.3V. +5V is used to power the high-speed parallel accumulator circuit module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the second MCU / CPU / ADC module, the front-stage low-noise amplifier circuit, and the RF power amplifier module. +3.3V is used to power the first high-performance zero-IF architecture wireless transceiver integrated chip circuit, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit, the high-speed DAC module, the high-speed FIFO receiving module, and the high-speed FIFO receiving module. O sending module, the first RS232 / UART interface circuit, the second RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, and the second TCP / IP Ethernet chip / circuit are powered, +2.85V is used to power the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the second high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, +2.5V is used to power the high-speed FIFO receiving module and the high-speed FIFO sending module, and +1.3V is used to power the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the second high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit.

7. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 1, characterized in that: The ultra-wideband cluster radio frequency power method system includes a plurality of ultra-wideband radio frequency power amplification modules, each of which is connected to one of the radio reconnaissance and countermeasure sub-nodes.

8. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 1, characterized in that: The spectrum detection data received by the NAS storage server includes the RSSI signal strength value of real-time dynamic scanning, the original data of detected radio baseband signals, real-time or triggered baseband decoding data, and various radio detection and countermeasure triggering events.

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