A time synchronization method and system for wireless deterministic networks

Abstract

The application provides a time synchronization method and system for a wireless deterministic network, and relates to the technical field of communication.The method comprises the following steps: a handshake protocol based on a Linux kernel is designed, and a message with an identifier is generated; the message is identified and a time stamp is inserted when the message is sent through a MAC layer, and the message is identified and a time stamp is captured when the message is received through the MAC layer; synchronization error compensation calculation is performed according to the obtained time stamp information, and the synchronization error compensation comprises phase error compensation and frequency error compensation; a compensation filter is designed, and the calculated compensation data is input into the compensation filter for screening; and the screened compensation data is input into a clock system for compensation, and synchronization is completed.The application can effectively inhibit the influence of asymmetric transmission delay in a wireless time synchronization mechanism and abnormal compensation data of wireless transmission on time synchronization precision, so that the precision and reliability of time synchronization are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a time synchronization method and system for wireless deterministic network. BACKGROUND

[0002] Traditional industrial fieldbus is gradually replaced by real-time Ethernet based on IEEE 802.3 standard with the demand of modern industrial scale expansion and intelligentization. Real-time Ethernet technologies such as Profinet, EtherCAT, SERCOS III, Time-Sensitive Networking (TSN) and Time-Triggered Ethernet (TTE) can provide deterministic transmission because the data transmission in these networks is almost according to precise time, which ensures that time-critical services have no resource competition. The time synchronization technology of Profinet IRTd is based on the improvement of IEEE 1588 precision time protocol. EtherCAT utilizes a unique distributed time synchronization mechanism. Powerlink adopts a timestamp-based synchronization mechanism. SERCOS III adopts a coherent frame time synchronization mechanism based on coherent frames. In addition, TSN improves PTP to general PTP (gPTP) in IEEE 802.1AS. TTE specifies a time synchronization method in AS6802 to ensure the reliability and security of the network. However, these precise time synchronization technologies are based on wired networks and are not suitable for wireless networks.

[0003] Due to the many limitations of wired networks in industrial site wiring and equipment diagnosis, many industrial plants are transforming wired network information transmission and exchange into wireless networks. The first step is to establish accurate wireless time synchronization. The current wireless time synchronization implementation scheme is GPS and NTP, etc. Among them, GPS can achieve nanosecond-level synchronization accuracy, but is affected by the surrounding environment, terrain, and has high implementation and maintenance costs, so it is not suitable for application in industrial production. NTP is widely used in Ethernet time synchronization, but its synchronization accuracy is at the millisecond level and cannot meet the requirements of industrial production. IEEE 1588 precision time protocol mechanism has the characteristics of simplicity, reliability, high precision and flexible deployment. IEEE 1588 protocol and software timestamp are used for IEEE 802.11 wireless LAN synchronization system, but under different network loads, the transmission asymmetric delay it produces is large, which greatly affects the synchronization accuracy. These time synchronization methods have special requirements for the experimental environment or poor compatibility with general protocols.

[0004] A wearable device wireless time synchronization method based on physical layer cross technology communication is disclosed in Chinese invention patent CN116939801A. The local clock is corrected by receiving and transmitting synchronization messages through a wireless radio frequency coordinator, but the protocol stack asymmetric transmission delay is not considered, and the synchronization accuracy is insufficient.

[0005] A wireless time synchronization method is disclosed in Chinese invention patent CN117336848A. The clock is calibrated through interpolation calculation, bidirectional time measurement and clock difference calculation in the time comparison process. This method does not filter abnormal values in the compensation data in the implementation of the time synchronization protocol, and the time synchronization stability is insufficient.

[0006] The time synchronization method for wireless deterministic network suitable for industry needs to consider hardware cost, deployment flexibility, reliability and other characteristics. The mechanism of IEEE 1588 precise time synchronization protocol has the above characteristics, but as a wired network protocol, it needs to be further integrated and adapted for wireless network. In the integration and adaptation process, the key difficulties of wireless time synchronization are: first, the timestamp insertion position. The traditional integration method sets the timestamp insertion position in the application layer of the wireless protocol stack, but under different network loads, the asymmetric transmission delay caused by the protocol stack will reduce the time compensation measurement accuracy, and the time synchronization accuracy is poor. Second, the application layer needs to design an adaptive software protocol stack to apply hardware timestamps. Third, in the time and frequency compensation part, it is difficult to adjust the frequency of the hardware clock. Fourth, the reliability and determinacy of wireless network data transmission are worse than wired network. In the time synchronization process, the generation of abnormal values will greatly affect the stability of time synchronization. Therefore, a high-reliability time synchronization architecture based on the integration of wireless network and IEEE 1588 basic mechanism is needed to ensure the accuracy and stability of wireless time synchronization. SUMMARY

[0007] To solve the above problems, the purpose of the present application is to provide a time synchronization method and system for wireless deterministic network. Without affecting the function and time delay measurement mechanism of the wireless protocol stack, the timestamp insertion and time synchronization related modules are built in the MAC layer of the wireless network, effectively reducing the uncertain time delay caused by the measurement message passing through the protocol stack, and improving the time synchronization accuracy. The high-speed parallel time compensation filtering module in the MAC layer is used to improve the stability of time synchronization.

[0008] To solve the above technical problems, the present application provides the following technical solutions:

[0009] On the one hand, a time synchronization method for wireless deterministic network is provided, which comprises the following steps:

[0010] S1, a handshake protocol based on Linux kernel is designed, and a message with identifier is generated;

[0011] S2, the message is identified and inserted with a timestamp when it is sent through the MAC layer, and the message is identified and captured with a timestamp when it is received through the MAC layer;

[0012] S3, synchronization error compensation calculation is performed according to the obtained timestamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation;

[0013] S4, a compensation filter is designed, and the calculated compensation data is input into the compensation filter for screening;

[0014] S5, the screened compensation data is input into the clock system for compensation, and synchronization is completed.

[0015] Optionally, the clock system is a hardware clock system, including a mixed mode clock manager, a reset signal, a phase compensation interface, a frequency compensation interface, and an output end.

[0016] The mixed mode clock manager IP core is used to obtain a clock with a frequency of 125 MHz to drive the clock system; the reset signal is used to reset and restart the clock system; the phase compensation interface and the frequency compensation interface are connected to the compensation filter and used to correct the clock system; and the time information output by the output end is used as a timestamp, and the time synchronization accuracy of the master clock and the slave clock is checked through a pulse per second (PPS).

[0017] Optionally, the insertion / capture position of the timestamp is set between the MAC layer data sending / receiving queue and the OFDM module.

[0018] Optionally, the format of the message is designed based on a wireless frame, the header contains a source MAC address, a destination MAC address, and related information, a plurality of special data fields are defined in the payload part of the wireless frame, including an identifier field and a time information field.

[0019] The identifier field is set to 2 bytes, and is used to distinguish three types of synchronization messages: pcap_send_pkt_b, pcap_send_pkt_c, and pcap_seend_pkt_d; and the time information field is set to 32 bytes, and contains time records and compensation data of each synchronization period.

[0020] Optionally, the phase error compensation specifically includes:

[0021] The master clock sends a pcap_send_pkt_b message to the slave clock, and records a sending time T1; and the slave clock receives the message and records a receiving time T2.

[0022] The slave clock initiates the reverse transmission delay calculation by sending a pcap_send_pkt_c message to the master clock, and records the sending time T3, and the master clock records the receiving time T4 of the pcap_send_pkt_c message;

[0023] The master clock sends a pcap_send_pkt_d message carrying the timestamp T4;

[0024] The four timestamps T1-T4 are collected for calculating the offset time between the master clock and the slave clock; assuming that the network transmission path is symmetrical, the link delay formula is as follows:

[0025] (1)

[0026] The slave clock calculates the offset time by the following formula:

[0027] (2)

[0028] (3)

[0029] Wherein, T master is the master clock time, T slave is the slave clock time, and T offset is the offset time of the master clock and the slave clock.

[0030] Optionally, the frequency error compensation specifically includes:

[0031] When the slave clock receives the pcap_send_pkt_b message, a timestamp is recorded; after receiving the pcap_send_pkt_b message twice, the clock frequency of the slave clock is corrected by comparing the following two types of timestamp intervals: the timestamp interval received in the slave clock and the timestamp interval sent in the master clock;

[0032] After multiple interactions of the pcap_send_pkt_b message, the formula of the master-slave frequency ratio is as follows:

[0033] (4)

[0034] Wherein, T1(1) is the sending time of the master clock sending the pcap_send_pkt_b message to the slave clock for the first time, T1(n) is the sending time of the master clock sending the pcap_send_pkt_b message to the slave clock for the nth time; T2(1) is the receiving time recorded by the slave clock for receiving the message for the first time, and T2(n) is the receiving time recorded by the slave clock for receiving the message for the nth time; n≥2;

[0035] The minimum clock period of the master clock and the slave clock is 8ns, so the frequency error compensation means that the clock system increases 1ns after each frequency compensation clock total period;

[0036] The frequency error compensation formula is as follows:

[0037] (5)

[0038] (6)

[0039] (7)

[0040] (8)

[0041] (9)

[0042] T offset is the phase error compensation data calculated in formula (3); F offset represents the frequency parameter that needs to be compensated in the current clock state; F offset_clk indicates that the final frequency error compensation data is obtained by superimposing calculation of the previously calculated frequency error compensation data and the newly calculated frequency error compensation data.

[0043] Optionally, the compensation filter comprises a compensation data register and a comparator;

[0044] The compensation data register is used to record previous compensation data and current compensation data, and the comparator is used to check whether the current compensation data exceeds the range, and the comparison rule is: if the absolute difference between the current compensation data and the previous compensation data is equal to or less than the comparison threshold, the current compensation data is used to update the time offset between the master clock and the slave clock, otherwise, the current compensation data is set to "0", and the next measurement is waited for, so as to avoid that abnormal data affects the time synchronization process.

[0045] On the other hand, a time synchronization system for a wireless deterministic network is provided for implementing any of the above methods, and the system comprises: an ARM-based handshake protocol design module, a FPGA-based clock system, a timestamp identification and capture module, a synchronization error compensation calculation module, a compensation data filtering module and a compensation module;

[0046] The handshake protocol design module is used for designing a handshake protocol based on a Linux kernel to generate a message with an identifier; the timestamp identification and capture module is used for identifying and inserting a timestamp when the message is sent through a MAC layer and identifying and capturing a timestamp when the message is received through the MAC layer; the synchronization error compensation calculation module is used for performing synchronization error compensation calculation according to the acquired timestamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation; the compensation data filtering module is used for designing a compensation filter to input the calculated compensation data into the compensation filter for screening; and the compensation module is used for inputting the screened compensation data into the clock system for compensation to complete synchronization.

[0047] In another aspect, an electronic device is provided, the electronic device comprising:

[0048] a processor;

[0049] a memory having computer readable instructions stored thereon, the computer readable instructions, when loaded and executed by the processor, implement the steps of the time synchronization method.

[0050] In another aspect, a computer readable storage medium is provided, the computer readable storage medium having program code stored therein, the program code being executable by a processor to implement the steps of the time synchronization method.

[0051] The technical solution provided by the application has at least the following beneficial effects:

[0052] (1) The time synchronization architecture is built in the MAC layer of the hardware part to perform time synchronization, and the position of inserting and capturing the timestamp is set between the MAC layer data transceiving queue and OFDM, so that the asymmetric delay of the protocol stack is minimized as much as possible.

[0053] (2) A handshake protocol is designed to complete the transmission of time information, and the frame format defined in the protocol contains various time information, thereby improving the flexibility and expandability of the protocol stack.

[0054] (3) A frequency compensation calculation mode is designed to solve the problem of difficult adjustment of the hardware time frequency compensation, and the new frequency compensation data can be obtained through the timestamp information, phase compensation information and the frequency compensation information of the last time, and the time is increased or decreased by 1ns after each time of frequency compensation data, so that the compensation is completed, and the time error of the clock system is prevented from continuously increasing after phase synchronization.

[0055] (4) A compensation data filtering module is designed after the synchronization error compensation calculation module to inhibit abnormal compensation data from entering the local clock, thereby improving the stability of time synchronization and the synchronization precision and reliability of the entire time synchronization system.

[0056] The time synchronization method and system for wireless deterministic network provided by the application can effectively inhibit the influence of asymmetric transmission delay and abnormal compensation data of wireless transmission on time synchronization precision in wireless time synchronization mechanism, thereby improving the precision and reliability of time synchronization. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0058] Figure 1 is a flow chart of the time synchronization method for wireless deterministic network provided by the embodiments of the present application;

[0059] Figure 2 is an architecture schematic diagram of the time synchronization method for wireless deterministic network provided by the embodiments of the present application;

[0060] Figure 3 is a high-reliability clock system schematic diagram provided by the embodiments of the present application;

[0061] Figure 4 is a synchronization message format schematic diagram provided by the embodiments of the present application;

[0062] Figure 5 is a phase error compensation schematic diagram provided by the embodiments of the present application;

[0063] Figure 6 is a frequency error compensation schematic diagram provided by the embodiments of the present application;

[0064] Figure 7 is a compensation data filter schematic diagram provided by the embodiments of the present application;

[0065] Figure 8 is a WiFi time synchronization experiment platform schematic diagram provided by the embodiments of the present application. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be described clearly and completely in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the protection scope of the present application.

[0067] In the embodiments of the present application, the words such as "for example", "for instance", "such as", or "for example" are used to represent an example, an illustration or an explanation. Any embodiment or design solution described in the present application as "for example" should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. In fact, the word "for example" is intended to present the concept in a specific way.

[0068] The embodiments of the present application provide a time synchronization method for a wireless deterministic network, which can be implemented by an electronic device, which can be a terminal or a server. Figure 1 As shown in the figure, the processing flow of the method can include the following steps:

[0069] S1, a handshake protocol based on a Linux kernel is designed, and a message with an identifier is generated;

[0070] S2, the message is identified and a time stamp is inserted when it is sent through a MAC layer, and the message is identified and a time stamp is captured when it is received through the MAC layer;

[0071] S3, synchronization error compensation calculation is performed according to the obtained time stamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation;

[0072] S4, a compensation filter is designed, and the calculated compensation data is input into the compensation filter for screening;

[0073] S5, the screened compensation data is input into a clock system for compensation, and synchronization is completed.

[0074] Figure 2 is an architecture schematic diagram of the time synchronization method described in the embodiments of the present application. Radio frequency front end (RFFE) is a general module for signal reception and transmission, and the present application does not modify this module, so it will not be further introduced. As shown in the figure, Figure 2The middle (a) shows the software part, which contains the main part of the Linux application. In order to implement the IEEE 1588 basic mechanism of the wireless network, the application designs a custom handshake protocol based on the Linux kernel. In the linuxptp, the software or hardware timestamp is configured for the outgoing and incoming data packets. In the embodiment of the application, only the hardware timestamp in the MAC layer is enabled. The handshake protocol with identifier is built to provide a channel for the timestamp interaction. In the custom handshake protocol, three identification codes are created to enable the device to identify the frame type and give a response. These main functions pcap_send_pkt_b, pcap_send_pkt_c and pcap_send_pkt_d are three different types of synchronization messages, pthread_create and pcap-loop_pkt are used to create a listening thread and a loop to obtain the synchronization field in the message. Other Linux components in the wireless protocol stack remain unchanged, such as the wireless driver.

[0075] Figure 2 The middle (b) shows the hardware part, which represents the newly designed module in the FPGA. The wireless protocol stack MAC layer and all newly designed time synchronization related modules are implemented on the FPGA. In the embodiment of the application, a high-reliability hardware clock system is designed to provide a nanosecond clock instead of using a software clock. At the output interface of the MAC layer of the wireless protocol stack, once the packet is identified to contain the special identifier field in the custom handshake protocol, the timestamp is inserted at the end of the packet between the sending queue and the OFDM processing module. Similarly, at the input interface, once the packet is identified to contain the special identifier field in the custom handshake protocol, the timestamp is extracted and recorded, and the special identifier is parsed to obtain the time related information required for synchronization. After all the time records are collected, the timestamp information is immediately transmitted to the synchronization error compensation calculation module for calculation of phase error compensation and frequency error compensation, and the precision of phase compensation can reach 1 ns and the precision of frequency compensation can reach -192 dB.

[0076] Then, due to the abnormal data that may occur, the compensation information may not be accurate and may have an unexpected impact on the clock system. In order to ensure the reliability and stability of the time synchronization, a compensation filter is designed to filter out the wrong compensation data. Finally, the screened compensation data enters the clock system, compensates the clock, and completes the synchronization.

[0077] Further, as shown in Figure 3 The clock system is a hardware clock system, which includes a mixed mode clock manager, a reset signal, a phase compensation interface, a frequency compensation interface, and an output end.

[0078] The mixed mode clock manager IP core is used to obtain a clock with a frequency of 125 MHz to drive the clock system. The reset signal is used to reset and restart the clock system, and its input is the lock signal of the mixed mode clock manager IP, which is pulled up when the 125 Mhz clock is stable. Therefore, the minimum scale of the clock system is 8 ns. The phase compensation interface and the frequency compensation interface are connected to the compensation filter for correcting the clock system. The time information output by the output end is used as a time stamp: 48-bit second clock and 32-bit nanosecond clock. Finally, the time synchronization accuracy of the master clock and the slave clock is checked by the second pulse PPS, and the pulse width is configured as 80 ns.

[0079] In the embodiment of the application, the insertion / capture position of the time stamp is arranged between the MAC layer data sending / receiving queue and the OFDM module, so that the asymmetric delay of the protocol stack can be reduced to the minimum.

[0080] Further, as Figure 4 shown, the format of the message is designed based on a wireless frame, and the header includes a source MAC address, a destination MAC address and other related information. In order to record the time information used for synchronization, a plurality of special data fields are defined in the payload part of the wireless frame, including an identifier field and a time information field.

[0081] The identifier field is set to 2 bytes, which is used to distinguish three types of synchronization messages: pcap_send_pkt_b, pcap_send_pkt_c and pcap_seend_pkt_d. The special identification value of pcap_send_pkt_b is 0x86bb, the special identification value of pcap_send_pkt_c is 0x86cc, and the special identification value of pcap_seend_pkt_d is 0x869d. The signaling exchange process will be discussed later.

[0082] The time information field is set to 32 bytes, which includes the time record and compensation data of each synchronization period. Therefore, the hardware compensation data can be transmitted to the Linux application layer and broadcast to other local network synchronization devices, which provides a reference for the subsequent research on time synchronization in the local area network. Only the record T4 and the time stamp segment are enabled in the master clock, and only the record T4 segment is closed in the slave clock. In order to follow the data check method used in the wireless protocol stack, the last data segment is a check data segment to ensure data reliability.

[0083] Further, clock compensation is divided into phase compensation and frequency compensation, and the principle of phase synchronization method is usually similar. The master and slave clocks record timestamps by exchanging time synchronization messages, and calculate the round-trip delay by measuring the message interaction time. Assuming that the network transmission path is symmetrical, the slave clock can self-correct by time difference to achieve synchronization with the master clock. As shown in Figure 5 The phase error compensation specifically includes:

[0084] The master clock (master node clock) sends a pcap_send_pkt_b message to the slave clock (slave node clock) and records the sending time T1, and the slave clock receives the message and records the receiving time T2;

[0085] The slave clock initiates reverse transmission delay calculation by sending a pcap_send_pkt_c message to the master clock, and records the sending time T3, and the master clock records the receiving time T4 of the pcap_send_pkt_c message;

[0086] The master clock sends a pcap_send_pkt_d message carrying the timestamp T4.

[0087] Since the design of the present application adopts a single-step mode, the transmission time T1 of the pcap_send_pkt_b message is carried by itself, so the timestamp recorded in the embodiment of the present application is closer to the physical layer. The four timestamps T1-T4 are collected to calculate the offset time between the master clock and the slave clock.

[0088] Assuming that the network transmission path is symmetrical, the link delay formula is as follows:

[0089] (1)

[0090] The slave clock calculates the offset time by the following formula:

[0091] (2)

[0092] (3)

[0093] Where, T master is the master clock time, T slave is the slave clock time, and T offset is the offset time of the master clock and the slave clock.

[0094] The above calculation method is based on the case that the clock frequencies between the master clock and the slave clock are the same, if they have different frequencies, the calculated offset will be offset after a long time running, therefore a frequency compensation method is needed. Not all synchronization messages need to participate in frequency compensation, when the slave clock receives the pcap_send_pkt_b message, it will record a receiving timestamp. After receiving the pcap_send_pkt_b message twice, the clock frequency of the slave clock is corrected by comparing the interval of the following two types of timestamps: the interval of the timestamps received in the slave clock and the interval of the timestamps sent in the master clock.

[0095] As shown in Figure 6 , after multiple interactions of the pcap_send_pkt_b message, the formula of the master-slave frequency ratio is as follows:

[0096] (4)

[0097] Wherein, T1(1) is the sending time of the master clock sending the pcap_send_pkt_b message to the slave clock for the first time, T1(n) is the sending time of the master clock sending the pcap_send_pkt_b message to the slave clock for the nth time; T2(1) is the receiving time recorded by the slave clock receiving the message for the first time, T2(n) is the receiving time recorded by the slave clock receiving the message for the nth time; n≥2.

[0098] In the design of the application, it is considered that the FPGA is not suitable for directly using division operation to control the clock frequency, and the minimum clock period of the master clock and the slave clock is 8ns, therefore the frequency error compensation represents that the clock system increases 1ns after each frequency compensation clock total period.

[0099] The frequency error compensation formula is as follows:

[0100] (5)

[0101] (6)

[0102] (7)

[0103] (8)

[0104] (9)

[0105] T offset is the phase error compensation data calculated in formula (3); F offset represents the frequency parameter that needs to be compensated in the current clock state; F offset_clkThe final frequency error compensation data is obtained by superimposing the previously calculated frequency error compensation data and the newly calculated frequency error compensation data.

[0106] Further, the calculated compensation data needs to be filtered. Several filtering algorithms such as Kalman filter can effectively reduce the random noise caused by clock bias and frequency drift in the calculation and measurement process, but they are extremely susceptible to abnormal data, which seriously affects the filtering accuracy. Therefore, in the embodiment of the present application, a compensation filter is designed to reduce the influence of abnormal data.

[0107] As shown in Figure 7 , the compensation filter includes a compensation data register and a comparator. The compensation data register is used to record the previous compensation data and the current compensation data, and the comparator is used to check whether the current compensation data exceeds the range, aiming to ensure that abnormal values do not affect the local clock. The comparison rule is: if the absolute difference between the current compensation data and the previous compensation data is equal to or less than the comparison threshold, the current compensation data is used to update the time offset between the master clock and the slave clock, otherwise, the current compensation data is set to "0", waiting for the next measurement, to avoid abnormal data affecting the time synchronization process.

[0108] The experimental verification part first establishes an experimental platform to evaluate the performance of the proposed wireless time synchronization method. Then the single-hop Wi-Fi synchronization performance under different network loads is analyzed, which are generated by mobile phones and personal computers (PCs) connected to the same AP.

[0109] The test platform of the experimental study is as shown in Figure 8The two wireless devices of master and slave nodes are ZedBoard development kits with AD-FMCOMMS3, which are two openwifi software-defined radio (SDR) boards without wireless time synchronization protocol. AD-FMComms3 is an FMC board of AD9361, which is a highly integrated RF agile transceiver. Based on the open source WiFi project, a complete set of time synchronization modules are added to the MAC layer of the FPGA program part, and the hardware description file is compiled. Then the hardware description file is loaded into the two boards, and after restarting the board, the hardware description file is successfully loaded. One of the two boards is configured as an AP mode, and the other is configured as a client mode. The AP connects with the client (slave node) and the mobile phone (iperf3 client) through WiFi, and the AP connects with the PC (iperf3 server) through wired network. The ARM part of the two wireless boards runs the custom handshake protocol, and the master node periodically sends synchronization messages to the slave node. The slave node responds to the master node according to the handshake protocol. The slave node collects the time information when exchanging messages in the MAC layer, calculates the phase / frequency error with the master node and compensates it. The iperf3 server and client apply network load to the AP to verify the stability of time synchronization from the side, and test the accuracy and reliability of the design.

[0110] All experiments were carried out in the laboratory, and the oscilloscope, logic analyzer and analysis software were used to analyze the clock error log and PPS signal of the master local clock and the slave local clock. Through analysis, the accuracy of time synchronization was measured. First, the comparison threshold of the compensation filter was determined through multiple short-term experiments. According to the requirement of synchronization accuracy, the approximate experimental range of the comparison threshold is about 1us. Then, the local optimal compensation threshold is used for subsequent long-term experiments. It should be noted that all experimental evaluations use the results collected in the stable stage of time synchronization, and the master and slave devices synchronize twice per second. The experiment runs for one hour.

[0111] Correspondingly, the embodiment of the application also provides a time synchronization system for a wireless deterministic network, which comprises: an ARM-based handshake protocol design module, an FPGA-based clock system, a timestamp identification and capture module, a synchronization error compensation calculation module, a compensation data filtering module and a compensation module.

[0112] The handshake protocol design module is used for designing a handshake protocol based on a Linux kernel, and generating a message with an identifier; the timestamp identification and capture module is used for identifying and inserting a timestamp when the message is sent through a MAC layer, and identifying and capturing a timestamp when the message is received through the MAC layer; the synchronization error compensation calculation module is used for performing synchronization error compensation calculation according to the acquired timestamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation; the compensation data filtering module is used for designing a compensation filter, and inputting the calculated compensation data into the compensation filter for screening; and the compensation module is used for inputting the screened compensation data into the clock system for compensation, and completing synchronization.

[0113] The system of the embodiment can be used to perform Figure 1 The technical solutions of the method embodiment have similar implementation principles and technical effects, and details are not described herein.

[0114] In the embodiment, the wireless deterministic network time synchronization precision and stability are improved by the time synchronization method and system for the wireless deterministic network, a time synchronization architecture for the wireless deterministic network is designed and implemented, including a software part of an application layer and a hardware part of a MAC layer. The time synchronization mechanism is run on a development board including ARM and FPGA components. In order to establish a time synchronization process similar to the PTP mechanism, a handshake protocol of a custom frame format is designed on the basis of a wireless frame. In addition, a hardware time synchronization related module is designed in the wireless MAC layer, aiming to identify special time synchronization messages, so that the accurate hardware timestamp is closer to the PHY layer. In order to process time related information by hardware, the frequency compensation clock calculation method is designed to compensate for the frequency of the hardware clock. In order to make the time compensation value more stable, a compensation filter is designed to reduce abnormal values affecting the time synchronization precision, and the time synchronization precision and stability are improved.

[0115] Therefore, compared with the prior art, the present application has the following advantages:

[0116] (1) Wireless protocol stack hardware timestamp mechanism: for the transmission asymmetric delay problem of the time synchronization message caused by the protocol stack transmission delay, the timestamp insertion position is set between the MAC layer data transceiver queue and the OFDM module, which effectively reduces the asymmetric delay of the timestamp generated by the protocol stack, guarantees the symmetry of the time synchronization message transmission path between the synchronization devices, and improves the accuracy of the time synchronization error measurement.

[0117] (2) Wireless synchronization frame handshake mechanism: in view of the problem that the hardware clock system is not suitable for the application layer of the protocol stack, a handshake protocol of a self-defined frame format is designed in the application layer of the wireless network protocol stack, and the flexibility and expandability of the hardware clock system are improved.

[0118] (3) Frequency compensation clock calculation method: in view of the problem that the frequency compensation adjustment of the hardware clock system is difficult, a frequency compensation clock calculation method is designed, the frequency compensation is completed by increasing or decreasing 1 ns of the time of the frequency compensation clock each time, and the time error of the clock system after phase synchronization is avoided from continuously becoming larger.

[0119] (4) Time compensation filtering mechanism: in view of the uncertainty of the wireless network and the problem of abnormal values of the time synchronization error compensation data, a filtering mechanism of time error compensation is designed, the absolute difference between the newly calculated compensation data and the last compensation data is continuously compared with a threshold value as a parameter, so as to adjust the reliability of the compensation data, whether the compensation data is allowed to correct the local clock is judged according to the reliability, and the stability of the time synchronization is improved.

[0120] In an example embodiment, the present application also provides an electronic device, which comprises:

[0121] a processor;

[0122] a memory, wherein computer readable instructions are stored on the memory, and the computer readable instructions are loaded and executed by the processor to implement the steps of the time synchronization method.

[0123] In an example embodiment, the present application also provides a computer readable storage medium, wherein at least one instruction is stored in the computer readable storage medium, and the at least one instruction is loaded and executed by a processor to implement the steps of the time synchronization method. For example, the computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0124] It should be noted that in this document, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or terminal device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or terminal device including the element.

[0125] Reference in the specification to "one embodiment", "an embodiment", "an example embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment.

[0126] It should be understood that the term "and / or" as used herein merely means that there are three relationships, for example, A and / or B, which can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In addition, the character " / " herein generally means that the front and rear associated objects are in an "or" relationship, but can also mean an "and / or" relationship, which can be understood in the context of the front and rear text.

[0127] In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or the like means any combination of the items, including a single item or any combination of multiple items. For example, at least one of a, b, or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be singular or plural.

[0128] It should be understood that the size of the sequence number of the above-mentioned processes in various embodiments of the present application does not mean the order of execution, and the execution order of the processes should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0129] In several embodiments provided by the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0130] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0131] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit.

[0132] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0133] The present application covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present application. In order to make the public have a thorough understanding of the present application, specific details are described in the following preferred embodiments of the present application, and the present application can also be completely understood without the description of these details to those skilled in the art. In addition, in order to avoid unnecessary confusion to the essence of the present application, well-known methods, processes, flows, elements and circuits, etc. are not described in detail.

[0134] The above is only the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A time synchronization method for a wireless deterministic network, characterized in that, The method comprises the following steps: S1, designing a handshake protocol based on a Linux kernel to generate a message with an identifier; S2, identifying and inserting a time stamp when the message is sent through a MAC layer, and identifying and capturing a time stamp when the message is received through the MAC layer; S3, performing synchronization error compensation calculation according to the obtained time stamp information, wherein the synchronization error compensation comprises phase error compensation and frequency error compensation; The phase error compensation specifically comprises: The master clock sends a pcap_send_pkt_b message to the slave clock and records a sending time T1, and the slave clock receives the message and records a receiving time T2; The slave clock starts reverse transmission delay calculation by sending a pcap_send_pkt_c message to the master clock and records a sending time T3, and the master clock records a receiving time T4 of the pcap_send_pkt_c message; The master clock sends a pcap_send_pkt_d message carrying the time stamp T4; The four time stamps T1-T4 are collected to calculate the offset time between the master clock and the slave clock; assuming that the network transmission path is symmetrical, the link delay formula is as follows: T link_delay = ((T4 - T1) - (T3 - T2)) / 2 (1) The slave clock calculates the offset time through the following formula: T master = T slave + T offset (2) T offset = ((T4 - T3) - (T2 - T1)) / 2 (3) where T master is the master clock time, T slave is the slave clock time, T offset is the offset time of the master clock from the slave clock; The frequency error compensation specifically comprises: When the slave clock receives the pcap_send_pkt_b message, a time stamp is recorded; after receiving the pcap_send_pkt_b message twice, the clock frequency of the slave clock is corrected by comparing the time stamp intervals received in the slave clock and the time stamp intervals sent in the master clock; After multiple interactions of the pcap_send_pkt_b message, the formula of the master-slave frequency ratio is as follows: F r = (T1(n) - T1(1)) / (T2(n) - T2(1)) (4) Wherein, T1(1) is the sending time of the master clock sending the pcap_send_pkt_b message to the slave clock for the first time, T1(n) is the sending time of the master clock sending the pcap_send_pkt_b message to the slave clock for the nth time; T2(1) is the receiving time recorded by the slave clock for receiving the message for the first time, and T2(n) is the receiving time recorded by the slave clock for receiving the message for the nth time; n≥2; The minimum clock period of the master clock and the slave clock is 8ns, so the frequency error compensation represents that the clock system increases 1ns after each frequency compensation clock total period; The frequency error compensation formula is as follows: T interval_1 = T1(n) - T1(n - 1) (5) T interval_2 = T2(n) - T2(n - 1) (6) T interval_2_r = T interval_2 + T offset (7) F offset = T interval_2_r / (T interval_1 -T interval_2_r ) (8) F offset_clk = (F offset_clk * F offset ) / ((F offset_clk + F offset )*8) (9) T offset is the phase error compensation data calculated in formula (3); F offset represents the frequency parameter that needs to be compensated in the current clock state; F offset_clk indicates that the final frequency error compensation data is obtained by superimposed calculation of the previously calculated frequency error compensation data and the newly calculated frequency error compensation data; S4, designing a compensation filter, and inputting the calculated compensation data into the compensation filter for screening; S5, inputting the screened compensation data into the clock system for compensation to complete synchronization.

2. The time synchronization method of claim 1, wherein, The clock system is a hardware clock system, comprising a mixed mode clock manager, a reset signal, a phase compensation interface, a frequency compensation interface, and an output end. The mixed mode clock manager IP core is used to obtain a clock with a frequency of 125 MHz to drive the clock system; the reset signal is used to reset and restart the clock system; the phase compensation interface and the frequency compensation interface are connected to the compensation filter to correct the clock system; and the time information output by the output end is used as a time stamp and is used to check the time synchronization accuracy of the master clock and the slave clock through a pulse per second (PPS).

3. The time synchronization method of claim 1, wherein, The insertion / capture position of the time stamp is arranged between a MAC layer data sending / receiving queue and an OFDM module.

4. The time synchronization method of claim 1, wherein, The format of the message is designed based on a wireless frame, a header includes a source MAC address, a destination MAC address and related information, and a plurality of special data fields are defined in a payload part of the wireless frame, including an identifier field and a time information field. The identifier field is set to 2 bytes and is used to distinguish three types of synchronization messages: pcap_send_pkt_b, pcap_send_pkt_c and pcap_send_pkt_d; and the time information field is set to 32 bytes and includes time records and compensation data of each synchronization period.

5. The time synchronization method of claim 1, wherein, The compensation filter includes a compensation data register and a comparator. The compensation data register is used to record previous compensation data and current compensation data, and the comparator is used to check whether the current compensation data is out of range, and the comparison rule is that if an absolute difference between the current compensation data and the previous compensation data is equal to or less than a comparison threshold, the current compensation data is used to update a time offset between the master clock and the slave clock, otherwise, the current compensation data is set to "0" and is waited for next measurement to avoid that abnormal data affects a time synchronization process.

6. A time synchronization system for a wireless deterministic network, the system being configured to implement the method of any one of claims 1 to 5, characterized in that, The system includes an ARM-based handshake protocol design module, a FPGA-based clock system, a time stamp identification and capture module, a synchronization error compensation calculation module, a compensation data filtering module and a compensation module. The handshake protocol design module is used to design a handshake protocol based on a Linux kernel to generate a message with an identifier; the time stamp identification and capture module is used to identify and insert a time stamp when a message is sent through a MAC layer, and identify and capture a time stamp when a message is received through the MAC layer; the synchronization error compensation calculation module is used to perform synchronization error compensation calculation according to obtained time stamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation; the compensation data filtering module is used to design a compensation filter to input calculated compensation data to the compensation filter for screening; and the compensation module is used to input screened compensation data to the clock system for compensation to complete synchronization.

7. An electronic device, comprising: The electronic device includes: a processor; a memory having computer readable instructions stored thereon, the computer readable instructions being loaded and executed by the processor to implement the method of any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium has program code stored therein, and the program code can be called and executed by the processor to implement the method of any one of claims 1 to 5.

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