Semiconductor structure and method for manufacturing the same

Abstract

The embodiments of the present disclosure relate to the field of semiconductors and provide a semiconductor structure and a manufacturing method thereof, wherein the structure comprises: a substrate, the substrate comprising a plurality of fins extending along a first direction and arranged at intervals along a second direction; an isolation layer, the isolation layer being located between adjacent fins, and the top surface of the isolation layer being no higher than the top surface of the fins; a plurality of stacked structures, the stacked structures corresponding one-to-one to the fins, each stacked structure being located on a corresponding fin, the stacked structures comprising a plurality of active layers stacked and spaced apart along a third direction on the fins, the active layers extending along the first direction and comprising a source region, a channel region, and a drain region arranged in sequence along the first direction; a plurality of word lines, the word lines corresponding one-to-one to the stacked structures, the word lines extending along the third direction and covering at least one side surface of the channel region in the corresponding stacked structure, the bottom surface of the word lines being in contact with the top surface of the isolation layer; a dielectric layer, the dielectric layer covering at least the side surface of the word lines away from the stacked structure, wherein the material of the dielectric layer is a low dielectric constant material.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Memory is a storage component used to store programs and various data. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers and is composed of many repeated storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. One of the source, drain, or drain of the transistor is connected to a bit line structure, and the other of the source, drain, or drain is connected to a capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor for storage through the bit line structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate including a plurality of fins extending along a first direction and arranged at intervals along a second direction; an isolation layer, the isolation layer being located between adjacent fins, and the top surface of the isolation layer being no higher than the top surface of the fins; a plurality of stacked structures, the stacked structures corresponding one-to-one to the fins, each stacked structure being located on a corresponding fin, the stacked structures including a plurality of active layers stacked and spaced apart along a third direction on the fins, the active layers extending along the first direction and including a source region, a channel region and a drain region arranged in sequence along the first direction; a plurality of word lines, the word lines corresponding one-to-one to the stacked structures, the word lines extending along the third direction and covering at least one side surface of the channel region in the corresponding stacked structure, the bottom surface of the word line being in contact with the top surface of the isolation layer; a dielectric layer, the dielectric layer covering at least the side surface of the word line away from the stacked structure, wherein the material of the dielectric layer is a low dielectric constant material.

[0006] In some embodiments, a top surface of the fin protrudes from a top surface of the isolation layer along a third direction, and the word line further covers a side surface of the fin protruding from the top surface of the isolation layer.

[0007] In some embodiments, a height difference between a top surface of the fin and a top surface of the isolation layer is less than half of a height of the fin.

[0008] In some embodiments, the dielectric layer also extends to a position between adjacent stacked structures that is opposite to the source region along the second direction and to a position opposite to the drain region along the second direction; the semiconductor structure also includes an insulating layer, which is located at least between the fin and the corresponding stacked structure, and between adjacent active layers in the stacked structure, and also between the dielectric layer and the source region, and between the dielectric layer and the drain region.

[0009] In some embodiments, the semiconductor structure further includes an air gap extending along a third direction. The air gap is at least located between adjacent word lines and is located on a side of the dielectric layer away from the word lines.

[0010] In some embodiments, the air gap also extends along the first direction, and the air gap is located between adjacent stacked structures; the isolation layer includes a first isolation portion located below the air gap and a second isolation portion located on both sides of the air gap along the second direction, and the top surface of the first isolation portion is lower than the top surface of the second isolation portion.

[0011] In some embodiments, the air gap includes a first gap portion and a second gap portion connected along a third direction, the first gap portion is located between the dielectric layers, the second gap portion is located below the dielectric layer, and the width of the second gap portion along the second direction is greater than the width of the first gap portion along the second direction.

[0012] In some embodiments, the isolation layer includes: a first isolation layer located on the substrate surface between adjacent fins; and a second isolation layer located on the surface of the first isolation layer, wherein the material of the second isolation layer is different from that of the first isolation layer.

[0013] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: providing an initial substrate and forming a stacking structure on the surface of the initial substrate, the stacking structure including alternatingly stacked sacrificial layers and semiconductor layers; patterning the stacking structure and part of the initial substrate, with the remaining initial substrate serving as a substrate, the substrate including a plurality of fins extending along a first direction and arranged along a second direction, the remaining semiconductor layer serving as an active layer, the active layer extending along the first direction and including a source region, a channel region and a drain region arranged in sequence along the first direction, and a plurality of active layers stacked along a third direction on the top surface of the fin to constitute a stacking structure; forming an isolation layer, the isolation layer being located between adjacent fins, and the top surface of the isolation layer being no higher than the top surface of the fin; forming a word line, the word line corresponding to the stacking structure one-to-one, and the word line extending along the third direction and covering at least one side of the channel region in the corresponding stacking structure, and the bottom surface of the word line contacting the top surface of the isolation layer; forming a dielectric layer, the dielectric layer covering at least the side of the word line away from the stacking structure, wherein the dielectric layer is a material with a low dielectric constant.

[0014] In some embodiments, before forming the dielectric layer, the method further includes: forming a filling layer, the filling layer being located on the surface of the isolation layer and filling the gap between the stacked structures; forming the dielectric layer, including: patterning the filling layer to form a dielectric groove; forming a dielectric layer at least on the sidewalls of the dielectric groove, with an air gap sandwiched between the dielectric layers located on the sidewalls of the dielectric groove.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] In the semiconductor structure provided by the embodiment of the present disclosure, the substrate includes multiple fins, and adjacent fins are insulated by an isolation layer. The stacked structure on the fin can be used to form a transistor structure, and each stacked structure has multiple active layers, that is, each stacked structure can form a plurality of transistors stacked along a third direction, thereby improving the integration density of the semiconductor structure. The word line covers at least one side of the channel region of the active layer in the stacked structure to achieve control of the transistor, wherein the bottom surface of the word line contacts the top surface of the isolation layer, and the top surface of the isolation layer is not higher than the top surface of the fin. In this way, the word line can fully cover the side of the channel region of the active layer closest to the fin in the stacked structure, thereby facilitating the word line's control of the transistor closest to the fin in the stacked structure. In addition, the surface of the word line away from the stacked structure is covered with a dielectric layer, so that adjacent word lines can be insulated by the dielectric layer, while also facilitating the reduction of parasitic capacitance between adjacent word lines or parasitic capacitance between word lines and other stacked structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figures 1 to 10 Schematic diagrams of various semiconductor structures provided in accordance with an embodiment of the present disclosure;

[0019] Figures 11 to 21 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, which is at least beneficial to improving the performance of the semiconductor structure.

[0021] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0022] Figures 1 to 10 Schematic diagram of various semiconductor structures provided by an embodiment of the present disclosure, wherein: Figures 2 to 6 for Figure 1 Schematic diagram of various cross-sectional structures along the AA1 direction, Figure 9 and Figure 10 for Figure 7 Schematic diagrams of various cross-sectional structures along the BB1 ​​direction. The semiconductor structure provided by this embodiment will be described in detail below in conjunction with the accompanying drawings, as follows:

[0023] refer to Figures 1 to 10 The semiconductor structure includes: a substrate 100, the substrate 100 includes a plurality of fins 101 extending along a first direction X and arranged at intervals along a second direction Y; an isolation layer 200, the isolation layer 200 is located between adjacent fins 101, and the top surface of the isolation layer 200 is not higher than the top surface of the fin 101; a plurality of stacked structures 300, the stacked structures 300 correspond to the fins 101 one by one, each stacked structure 300 is located on a corresponding fin 101, and the stacked structures 300 include a plurality of active layers 301 stacked and spaced apart along a third direction Z on the fin 101, the active layers 301 extends along a first direction X and includes a source region 311, a channel region 321 and a drain region 331 arranged in sequence along the first direction; a plurality of word lines 400, the word lines 400 correspond to the stacked structures 300 one by one, and the word lines 400 extend along a third direction Z and cover at least one side of the channel region 321 in the corresponding stacked structure 300, and the bottom surface of the word line 400 contacts the top surface of the isolation layer 200; a dielectric layer 500, the dielectric layer 500 at least covers the side of the word line 400 away from the stacked structure 300, wherein the material of the dielectric layer 500 is a low dielectric constant material.

[0024] In the semiconductor structure provided by the embodiments of the present disclosure, a substrate 100 includes a plurality of fins 101, with adjacent fins 101 insulated by an isolation layer 200. A stacked structure 300 on the fins 101 can be used to form a transistor structure, and each stacked structure 300 includes multiple active layers 301. That is, each stacked structure 300 can form a plurality of transistors stacked along a third direction Z, thereby improving the integration density of the semiconductor structure. A word line 400 covers at least one side surface of a channel region 321 of an active layer 301 in the stacked structure 300 to control the transistor. The bottom surface of the word line 400 contacts the top surface of the isolation layer 200, and the top surface of the isolation layer 200 is no higher than the top surface of the fin 101. Thus, the word line 400 fully covers the side surface of the channel region 321 of the active layer 301 in the stacked structure 300 closest to the fin 101, thereby facilitating the word line 400's control of the transistor closest to the fin 101 in the stacked structure 300. In addition, the surface of the word line 400 away from the stacked structure 300 is covered with a dielectric layer 500, so that adjacent word lines 400 can be insulated by the dielectric layer 500, which is beneficial to reducing the parasitic capacitance between adjacent word lines 400 or the parasitic capacitance between the word line 400 and other stacked structures 300.

[0025] The material of substrate 100 may include a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 100 may include: a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, a basic semiconductor includes germanium (Ge); a compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and an alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0026] exist Figure 1 In the example, taking the case where the top surface of the fin 101 protrudes from the top surface of the isolation layer 200 along the third direction Z, the word line 400 also covers the side surface of the fin 101 that protrudes from the top surface of the isolation layer 200. In some embodiments, the top surface of the fin can also be flush with the top surface of the isolation layer. In this way, the word line 400 can fully cover the side surface of the channel region 321 of the active layer 301 in the stacked structure 300 that is closest to the fin 101, thereby facilitating the word line 400's control over the transistor in the stacked structure 300 that is closest to the fin 101.

[0027] In some embodiments, the height difference between the top surface of the fin 101 and the top surface of the isolation layer 200 relative to the surface of the substrate 100 between adjacent fins 101 is less than half the height of the fin 101. It will be appreciated that the bottom surface of the word line 400 contacts the top surface of the isolation layer 200. To avoid excessive height differences between the bottom surface of the word line 400 and the top surface of the fin 101, which could lead to leakage between the word line 400 and the substrate 100, the height difference between the top surface of the isolation layer 200 and the top surface of the fin 101 needs to be controlled within an appropriate range.

[0028] The material of the isolation layer 200 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0029] In some embodiments, reference Figure 2 The isolation layer 200 may include: a first isolation layer 201, the first isolation layer 201 is located on the surface of the substrate 100 between adjacent fins 101; a second isolation layer 202, the second isolation layer 202 is located on the surface of the first isolation layer 201, and the material of the second isolation layer 202 is different from that of the first isolation layer 201.

[0030] When forming the isolation layer 200, since the top surface of the isolation layer 200 is not higher than the top surface of the fin 101, in order to control the height difference between the top surface of the isolation layer 200 and the top surface of the fin 101, a first isolation layer 201 and a second isolation layer 202 made of different materials can be set. In this way, when the word line 400 is subsequently formed, the second isolation layer 202 can serve as an etching stop layer for the word line hole to avoid the depth of the word line 400 being too deep, thereby avoiding the bottom surface of the word line 400 being too much lower than the top surface of the fin 101, thereby causing leakage problems between the word line 400 and the substrate 100.

[0031] The materials of the first isolation layer 201 and the second isolation layer 202 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0032] In some embodiments, the semiconductor structure may further include an insulating layer 302, which is located between adjacent active layers 301 and between the active layer 301 and the fin 101. Thus, the insulating layer 302 can insulate the transistor structures formed by adjacent active layers 301 from each other and from the substrate 100, thereby preventing leakage between adjacent transistor structures or between the transistor structure and the substrate 100 and improving the stability of the semiconductor structure.

[0033] The material of the insulating layer 302 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0034] It should be noted that in Figure 1 and Figure 2In the embodiment, the number of active layers 301 stacked in the stacked structure 300 is 2, which does not limit the number of active layers 301 in the stacked structure 300. In some embodiments, the number of active layers in the stacked structure may also be 3, 5, or 8.

[0035] The material of active layer 301 includes elemental semiconductor materials or compound semiconductor materials. Elemental semiconductor materials may include germanium, silicon, selenium, boron, tellurium, or antimony; compound semiconductor materials may include gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon. In some embodiments, the material of active layer 301 may also include an oxide semiconductor, such as at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide).

[0036] The source region 311 and the drain region 331 are used to form the source and drain of the transistor, respectively. In some embodiments, the source region 311 and the drain region 331 may contain dopant ions. For example, both the source region 311 and the drain region 331 may contain N-type ions, including phosphorus ions, arsenic ions, or antimony ions; or both the source region 311 and the drain region 331 may contain P-type ions, including boron ions, indium ions, or gallium ions. The dopant ion type of the source region 311 and the drain region 331 may be the same as that of the channel region 321 to form a junctionless transistor; the dopant ion type of the source region 311 and the drain region 331 may be different from that of the channel region 321 to form a junction transistor.

[0037] It should be noted that Figure 1 The positions of the source region 311 and the drain region 331 shown in the figure do not constitute a limitation of the source region 311 and the drain region 331. In some embodiments, the positions of the source region 311 and the drain region 331 can be interchangeable.

[0038] exist Figure 1 In the description, the word line 400 covering both sides of the active layer 301 is used as an example, which does not limit the manner in which the word line 400 covers the channel region 321 of the active layer 301. In some embodiments, the word line may also cover only one side of the channel region of the active layer in the stacked structure along the second direction.

[0039] In some embodiments, reference Figure 3The word line 400 may include a first sub-word line 401 and a second sub-word line 402. The first sub-word line 401 and the second sub-word line 402 respectively cover two opposite side surfaces of the stacked structure 300 along the second direction Y, and the first sub-word line 401 and the second sub-word line 402 are insulated from each other. Thus, the first sub-word line 401 and the second sub-word line 402 can each control the transistor formed by the active layer 301 in the stacked structure 300, thereby improving the controllability of the semiconductor structure.

[0040] In some embodiments, reference Figure 4 The word line 400 may further include a third sub-word line 403, which is located on the top surface of the stacked structure 300 and is in electrical contact with the first sub-word line 401 and the second sub-word line 402. Thus, the first sub-word line 401 and the second sub-word line 402 may be electrically connected via the third sub-word line 403. That is, the first sub-word line 401, the second sub-word line 402, and the third sub-word line 403 together constitute a single word line 400, and the word line 400 covers two opposite side surfaces of the active layer 301 in the corresponding stacked structure 300 along the second direction Y. This increases the contact area between the word line 400 and the channel region 321 of the active layer 301, thereby improving the gate control capability.

[0041] In some embodiments, reference Figure 5 The first sub-word line 401 can also extend to the second sub-word line 402 through the area between the active layers 301, and the second sub-word line 402 can also extend to the first sub-word line 401 through the area between the active layers 301. The first sub-word line 401 and the second sub-word line 402 contact each other through the area between the active layers 301 to facilitate a transistor with a full-surround gate structure.

[0042] In some embodiments, the word line 400 may include a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer covers the surface of the channel region of the active layer, and the gate conductive layer covers the surface of the gate dielectric layer away from the active layer.

[0043] The material of the gate dielectric layer includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material or a combination thereof.

[0044] The material of the gate conductive layer includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium or tungsten.

[0045] exist Figures 1 to 5 In the example, the dielectric layer 500 only covers the surface of the word line 400 away from the active layer 300, which does not constitute a limitation on the thickness of the dielectric layer 500 along the second direction Y. In some embodiments, referring to Figure 6 , the dielectric layer 500 may also fill the gaps between adjacent word lines 400 .

[0046] refer to Figure 4 and Figure 5 When the word line 400 includes a third sub-word line 403 , the dielectric layer 500 may further cover side surfaces of the third sub-word line 403 to prevent parasitic capacitance from being generated between adjacent third sub-word lines 403 .

[0047] The dielectric layer 500 is made of a low-k material, meaning that the dielectric constant of the dielectric layer 500 is less than or equal to 4, such as 4, 3.8, 2.7, or 1. The low-k material can reduce parasitic capacitance between adjacent word lines 400. Alternatively, when the word line 400 covers only one side of the stacked structure 300, the dielectric layer 500 can reduce parasitic capacitance between the word line 400 and the stacked structure 300.

[0048] The dielectric layer 500 may be made of fluorinated polymer, low dielectric constant glass fiber, microporous high-quality polymer, fluoropolyurethane, porous low dielectric constant fatty acid methyl ester, etc., such as SiON, SiCN, SiOC or SiOCN.

[0049] In some embodiments, reference Figure 7 The dielectric layer 500 also extends to positions between adjacent stacked structures 300 that are directly opposite the source region 211 along the second direction Y, and to positions that are directly opposite the drain region 331 along the second direction Y. This can improve the isolation effect of the dielectric layer 500 and further reduce the possibility of leakage between word lines 400 through areas not directly opposite the word lines 400.

[0050] Furthermore, the insulating layer may be located between the dielectric layer and the source region and between the dielectric layer and the drain region to fill the gaps between the semiconductor structures and simultaneously insulate adjacent device structures, thereby improving the stability of the semiconductor structure.

[0051] In some embodiments, reference Figures 1 to 5 as well as Figure 7 The semiconductor structure may further include an air gap 600 extending along a third direction Z. The air gap 600 is located at least between adjacent word lines 400 and on a side of the dielectric layer 500 away from the word lines 400. The air gap 600 has a low dielectric constant, thereby further improving the insulation between adjacent word lines 400 and preventing parasitic capacitance from being generated between adjacent word lines 400.

[0052] refer to Figure 7When the dielectric layer 500 further extends to a position between adjacent stacked structures 300 that is directly opposite the source region 211 along the second direction Y and to a position directly opposite the drain region 331 along the second direction Y, the air gap 600 can further extend along the first direction X and be located between adjacent stacked structures 300. In this way, non-directly opposite regions between adjacent word lines 400 can also be isolated by the air gap 600, thereby further reducing the possibility of parasitic capacitance between the word lines 400.

[0053] refer to Figure 8 The isolation layer 200 may include a first isolation portion 210 located below the air gap 600 and second isolation portions 220 located on both sides of the air gap 600 along the second direction Y. The top surface of the first isolation portion 210 is lower than the top surface of the second isolation portion 220. In other words, the air gap 600 extends into the isolation layer 200 along the third direction Z. In this way, the air gap 600 can isolate the bottoms of adjacent word lines 400, prevent leakage between the bottoms of adjacent word lines 400, and improve the stability of the semiconductor structure.

[0054] exist Figure 8 In the embodiment, the width of the air gap 600 is greater than the width of the dielectric layer 500 along the first direction X, but this does not constitute a limitation between the width of the air gap 600 and the width of the dielectric layer 500. In some embodiments, the width of the air gap along the first direction may be equal to the width of the dielectric layer.

[0055] In some embodiments, reference Figure 9 The dielectric layer 500 may also cover the side surfaces of the second isolation portion 220. In other words, the dielectric layer 500 also extends into the isolation layer 200. The dielectric layer 500 and the air gap 600 in the isolation layer 200 work together to insulate the bottoms of adjacent word lines 400, thereby improving the insulation performance between adjacent word lines 400.

[0056] In some embodiments, reference Figure 10 The air gap 600 includes a first gap portion 601 and a second gap portion 602 connected along the third direction Z. The first gap portion 601 is located between the dielectric layers 500, and the second gap portion 602 is located below the dielectric layer 500. The width of the second gap portion 602 along the second direction Y is greater than the width of the first gap portion 601 along the second direction Y. In other words, the gap width of the air gap 600 in the isolation layer 200 is greater than the gap width of the air gap 600 between the dielectric layers 500. As a result, the second gap portion 602 in the isolation layer 200 can have better dielectric properties, further preventing the possibility of leakage between the bottoms of adjacent word lines 400.

[0057] In some embodiments, the width of the second gap 602 along the second direction Y is less than or equal to the gap width between the adjacent word lines 400 along the second direction Y, and greater than or equal to the gap width between the adjacent dielectric layers 500 along the second direction Y. In this way, the isolation performance of the air gap 600 in the isolation layer 200 can be improved while preventing the second gap 602 from exposing the bottom surface of the word line 400.

[0058] In some embodiments, the width of the air gap 600 along the second direction ranges from 10 nm to 50 nm, such as 10 nm, 13 nm, 19 nm, 25 nm, 31 nm, 36.5 nm, 42 nm, 46.6 nm, or 50 nm. It is understood that the width of the air gap 600 needs to be within an appropriate range so that the air gap 600 can isolate adjacent word lines 400 while avoiding the problem of the air gap 600 being too wide and unable to be subsequently sealed.

[0059] It can be understood that the above embodiments can be arbitrarily combined without conflict to obtain new embodiments.

[0060] In a semiconductor structure provided by an embodiment of the present disclosure, a substrate 100 includes a plurality of fins 101, with adjacent fins 101 insulated by an isolation layer 200. A stacked structure 300 on the fins 101 can be used to form a transistor structure, and each stacked structure 300 includes multiple active layers 301. That is, each stacked structure 300 can form a plurality of transistors stacked along a third direction Z, thereby improving the integration density of the semiconductor structure. A word line 400 covers at least one side surface of a channel region 321 of an active layer 301 in the stacked structure 300 to control the transistor. The bottom surface of the word line 400 contacts the top surface of the isolation layer 200, and the top surface of the isolation layer 200 is no higher than the top surface of the fin 101. Thus, the word line 400 fully covers the side surface of the channel region 321 of the active layer 301 in the stacked structure 300 closest to the fin 101, thereby facilitating the word line 400's control of the transistor closest to the fin 101 in the stacked structure 300. In addition, the surface of the word line 400 away from the stacked structure 300 is covered with a dielectric layer 500, so that adjacent word lines 400 can be insulated by the dielectric layer 500, which is beneficial to reducing the parasitic capacitance between adjacent word lines 400 or the parasitic capacitance between the word line 400 and other stacked structures 300.

[0061] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure to improve the performance of the formed semiconductor structure. It should be noted that for the parts that are the same or corresponding to the above-mentioned embodiments, reference can be made to the corresponding description of the above-mentioned embodiments, and will not be repeated in detail below.

[0062] Figures 11 to 21 This is a schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure, wherein: Figures 13 to 21 for Figure 12 Schematic diagrams of various cross-sectional structures along the CC1 direction. The following will describe in detail the semiconductor structure manufacturing method provided by this embodiment in conjunction with the accompanying drawings, as follows:

[0063] refer to Figure 11 , providing an initial substrate 110 and forming a stacked structure 310 on the surface of the initial substrate 110 , the stacked structure 310 includes sacrificial layers 312 and semiconductor layers 320 that are alternately stacked.

[0064] The material of the sacrificial layer 312 includes one of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide. The material of the semiconductor layer 320 includes an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material can be germanium, silicon, selenium, boron, tellurium, or antimony; the compound semiconductor material can be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon. In some embodiments, the material of the semiconductor layer 320 can also include an oxide semiconductor, for example, at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide).

[0065] refer to Figure 12 , a patterned stacked structure 310 and a portion of the initial substrate 110, the remaining initial substrate 110 serves as the substrate 100, the substrate 100 includes a plurality of fins 101 extending along a first direction X and arranged along a second direction Y, the remaining semiconductor layer 320 serves as an active layer 301, the active layer 301 extends along the first direction X and includes a source region 311, a channel region 321 and a drain region 331 arranged in sequence along the first direction X, and the plurality of active layers 301 stacked along a third direction Z on the top surface of the fin 101 constitute a stacked structure 300.

[0066] In some embodiments, patterning the stacked structure and a portion of the initial substrate includes: forming a mask layer that covers a surface of the stacked structure; etching the stacked structure and a portion of the initial substrate using the mask layer as an etching pattern; and removing the mask layer. The mask layer can serve as a protective layer for the stacked structure, preventing damage to the top surface of the stacked structure from the etching process.

[0067] In some embodiments, the mask layer includes a protective layer and a hard mask layer. The protective layer covers the surface of the stacked structure, and the hard mask layer covers the surface of the protective layer. The protective layer can serve as a transition layer between the hard mask layer and the stacked structure to prevent the hard mask layer from being too hard and causing misalignment between the stacked structure.

[0068] The material of the protection layer includes silicon oxide, and the material of the hard mask layer includes silicon nitride.

[0069] refer to Figure 13 , forming an isolation layer 200 , the isolation layer 200 is located between adjacent fins 101 , and the top surface of the isolation layer 200 is not higher than the top surface of the fin 101 .

[0070] The following example takes the top surface of the isolation layer 200 being lower than the top surface of the fin 101 as an example, which does not limit the height relationship between the top surfaces of the isolation layer 200 and the fin 101. In some embodiments, the top surface of the isolation layer may also be flush with the top surface of the fin.

[0071] In some embodiments, reference Figure 14 Before forming the isolation layer 200, the process also includes removing the sacrificial layer 312. Forming the isolation layer 200 includes: forming an initial first isolation layer (not shown), the initial first isolation layer being located on the surface of the substrate 100 and filling the gaps between adjacent stacked structures 300 and the gaps between the active layers 301 in the stacked structures 300; removing a portion of the initial first isolation layer along the third direction Z, the initial first isolation layer between adjacent fins 101 serving as the first isolation layer 201, and the initial first isolation layer between the active layers 301 serving as the insulating layer 302; and forming a second isolation layer 202, the second isolation layer 202 covering the surface of the first isolation layer 201, the material of the second isolation layer 202 being different from the material of the first isolation layer 201. In this way, the insulating layer 302 and the first isolation layer 201 can be formed simultaneously in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure. Furthermore, the first isolation layer 201 and the second isolation layer 202 are made of different materials, allowing the second isolation layer 202 to serve as an etch stop layer during the subsequent etching of the wordline holes. This prevents the wordline holes from being too deep, which would cause the bottom surface of the subsequently formed wordline to be too deep below the top surface of the fin 101, thereby causing leakage between the wordline and the substrate. In one example, after forming the first isolation layer 201, a selective deposition process can be used to form the second isolation layer 202 on the surface of the first isolation layer 201 facing away from the substrate 100. In other examples, after forming the first isolation layer 201, an initial second isolation material can be deposited to fill the space between the fin 101 and the stacked structure 300. After planarizing the initial second isolation material, etching back is performed to form the second isolation layer 202.

[0072] In some embodiments, an isolation layer may be formed first, and then the sacrificial layer may be removed and an insulating layer may be formed.

[0073] The following description will be made by taking the isolation layer 200 including the first isolation layer 201 and the second isolation layer 202 as an example, which does not constitute a limitation on the structure of the isolation layer 200. In some embodiments, the isolation layer may also be a single-layer or three-layer structure.

[0074] refer to Figure 15 , forming a filling layer 700 , the filling layer 700 is located on the top surface of the isolation layer 200 and fills the gaps between adjacent stacked structures 300 .

[0075] The material of the filling layer 700 includes silicon oxide, silicon nitride or silicon oxynitride.

[0076] In one example, a dielectric layer may be formed first, and then the word lines may be formed.

[0077] For example, reference Figure 16 The filling layer 700 is patterned to form a dielectric trench 510; the dielectric layer 500 is formed at least on the sidewalls of the dielectric trench 510. In some embodiments, a dielectric layer may also be formed on the bottom surface and sidewalls of the dielectric trench.

[0078] refer to Figure 17 , forming a spacer layer 520 , which fills the remaining dielectric trenches 510 between the dielectric layers 500 .

[0079] The material of the spacer layer 520 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0080] refer to Figure 18 , patterning the filling layer 700 to form a word line hole; filling the word line hole to form a word line 400, the word line 400 corresponds to the stacked structure 300 one by one, and the word line 400 extends along the third direction Z and covers at least one side of the channel region 321 in the corresponding stacked structure 300, the bottom surface of the word line 400 contacts the top surface of the isolation layer 200, and the dielectric layer 500 covers at least the side of the word line 400 away from the stacked structure 300, wherein the dielectric layer 500 is a material with a low dielectric constant.

[0081] In some embodiments, reference Figure 19 After forming the word line 400 , the following steps may be further included: removing the spacer layer 520 , and sandwiching the air gap 600 between the dielectric layer 500 and the sidewall of the dielectric trench 510 .

[0082] In another example, the word lines may be formed first and then the dielectric layer may be formed.

[0083] For example, reference Figure 20 , patterning the filling layer 700 to form a word line hole; filling the word line hole to form a word line 400, the word line 400 corresponds to the stacked structure 300 one by one, and the word line 400 extends along the third direction Z and covers at least one side of the channel region 321 in the corresponding stacked structure 300, and the bottom surface of the word line 400 contacts the top surface of the isolation layer 200.

[0084] refer to Figure 21, patterning the filling layer 700 to form a dielectric trench 510; forming a dielectric layer 500 at least on the sidewalls of the dielectric trench 510, and sandwiching the air gap 600 between the dielectric layers 500 located on the sidewalls of the dielectric trench 510.

[0085] After the air gap is formed, a portion of the isolation layer may be etched along the third direction to extend the air gap into the isolation layer, thereby preventing leakage between the bottoms of adjacent word lines.

[0086] In some embodiments, the portion of the isolation layer exposed by the air gap can be further removed along the second direction. Thus, the air gap can include a first gap portion and a second gap portion, with the first gap portion located between the dielectric layers and the second gap portion located below the dielectric layer. The width of the second gap portion along the second direction is greater than the width of the first gap portion along the second direction. In other words, the width of the air gap in the isolation layer is greater than the width of the air gap between the dielectric layers. Thus, the second gap portion in the isolation layer can have better dielectric properties, further preventing leakage between the bottoms of adjacent word lines.

[0087] In some embodiments, a wet etching process may be used to remove the portion of the isolation layer exposed by the air gap along the second direction.

[0088] In some embodiments, the air gap 600 may be sealed with tetraethylorthosilicate (TEOS). Since TEOS has a poor filling ability, the top of the air gap 600 may be sealed without filling the air gap, thereby forming the air gap 600 into a closed cavity.

[0089] In a semiconductor structure manufacturing method provided by an embodiment of the present disclosure, a plurality of fins 101 are formed on a substrate 100, with adjacent fins 101 insulated by an isolation layer 200. A stacked structure 300 on the fins 101 can be used to form a transistor structure, and each stacked structure 300 includes multiple active layers 301. That is, each stacked structure 300 can form multiple transistors stacked along a third direction Z, thereby improving the integration density of the semiconductor structure. A word line 400 covers at least one side surface of a channel region 321 of an active layer 301 in the stacked structure 300 to control the transistor. The bottom surface of the word line 400 contacts the top surface of the isolation layer 200, and the top surface of the isolation layer 200 is no higher than the top surface of the fin 101. Thus, the word line 400 fully covers the side surface of the channel region 321 of the active layer 301 in the stacked structure 300 closest to the fin 101, thereby facilitating the word line 400's control of the transistor closest to the fin 101 in the stacked structure 300. In addition, the surface of the word line 400 away from the stacked structure 300 is covered with a dielectric layer 500, so that adjacent word lines 400 can be insulated by the dielectric layer 500, which is beneficial to reducing the parasitic capacitance between adjacent word lines 400 or the parasitic capacitance between the word line 400 and other stacked structures 300.

[0090] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a plurality of fins extending along a first direction and arranged at intervals along a second direction; an isolation layer, wherein the isolation layer is located between adjacent fins, and a top surface of the isolation layer is not higher than a top surface of the fin; a plurality of stacked structures, each stacked structure corresponding to the fin portion one by one, each stacked structure being located on a corresponding fin portion, the stacked structure comprising a plurality of active layers stacked and spaced apart along a third direction on the fin portion, the active layers extending along the first direction and comprising a source region, a channel region, and a drain region sequentially arranged along the first direction; a plurality of word lines, each corresponding to the stacked structures one by one, extending along the third direction and covering at least one side surface of the channel region in the corresponding stacked structure, wherein a bottom surface of the word line contacts a top surface of the isolation layer; a dielectric layer, the dielectric layer covering at least a side of the word line away from the stacked structure, wherein the dielectric layer is made of a low dielectric constant material; The dielectric layer also extends to a position between adjacent stacked structures that is opposite to the source region along the second direction and to a position opposite to the drain region along the second direction; the semiconductor structure also includes an insulating layer, which is located between the fin and the corresponding stacked structure, and between adjacent active layers in the stacked structure, and also between the dielectric layer and the source region, and between the dielectric layer and the drain region.

2. The semiconductor structure according to claim 1, wherein: The top surface of the fin protrudes from the top surface of the isolation layer along the third direction, and the word line further covers the side surface of the fin protruding from the top surface of the isolation layer.

3. The semiconductor structure according to claim 2, wherein: A height difference between a top surface of the fin and a top surface of the isolation layer is less than half of a height of the fin.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: Also includes: An air gap extends along the third direction, and the air gap is at least located between adjacent word lines and on a side of the dielectric layer away from the word lines.

5. The semiconductor structure according to claim 4, wherein: The air gap also extends along the first direction, and the air gap is located between adjacent stacked structures; the isolation layer includes a first isolation portion located below the air gap and a second isolation portion located on both sides of the air gap along the second direction, and the top surface of the first isolation portion is lower than the top surface of the second isolation portion.

6. The semiconductor structure according to claim 5, wherein: The air gap includes a first gap portion and a second gap portion connected along the third direction, the first gap portion is located between the dielectric layers, the second gap portion is located below the dielectric layer, and the width of the second gap portion along the second direction is greater than the width of the first gap portion along the second direction.

7. The semiconductor structure according to claim 1, wherein: The isolation layer comprises: a first isolation layer, wherein the first isolation layer is located on the surface of the substrate between adjacent fins; A second isolation layer is located on the surface of the first isolation layer, and the material of the second isolation layer is different from that of the first isolation layer.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Providing an initial substrate and forming a stacked structure on a surface of the initial substrate, wherein the stacked structure includes sacrificial layers and semiconductor layers stacked alternately; Patterning the stacked structure and a portion of the initial substrate, with the remaining initial substrate serving as a substrate, the substrate comprising a plurality of fins extending along a first direction and arranged along a second direction, the remaining semiconductor layer serving as an active layer, the active layer extending along the first direction and comprising a source region, a channel region, and a drain region sequentially arranged along the first direction, and the plurality of active layers stacked along a third direction on top of the fins forming a stacked structure; forming an isolation layer, wherein the isolation layer is located between adjacent fins, and a top surface of the isolation layer is not higher than a top surface of the fin; forming word lines, each corresponding to the stacked structures one by one, extending along the third direction and covering at least one side surface of the channel region in the corresponding stacked structure, wherein a bottom surface of the word line contacts a top surface of the isolation layer; forming a dielectric layer, the dielectric layer covering at least a side of the word line away from the stacked structure, wherein the dielectric layer is made of a material with a low dielectric constant; The dielectric layer also extends to a position between adjacent stacked structures that is opposite to the source region along the second direction and to a position opposite to the drain region along the second direction; the semiconductor structure also has an insulating layer formed thereon, the insulating layer being formed between the fin and the corresponding stacked structure, and between adjacent active layers in the stacked structure, and also between the dielectric layer and the source region, and between the dielectric layer and the drain region.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: Before forming the dielectric layer, the method further comprises: forming a filling layer, wherein the filling layer is located on a surface of the isolation layer and fills the gaps between the stacked structures; The forming of the dielectric layer comprises: patterning the filling layer to form a dielectric trench; The dielectric layer is formed at least on the sidewalls of the dielectric trench, and an air gap is sandwiched between the dielectric layers located on the sidewalls of the dielectric trench.

Images