3D stacked semiconductor device and manufacturing method thereof, and electronic device

Abstract

A 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device, the manufacturing method comprising: alternately depositing a first insulating layer and a conductive layer on a substrate to obtain a stacked structure; patterning and etching the stacked structure to form a plurality of first trenches in the stacked structure, wherein the patterned conductive layer includes a bit line, a plurality of first sub-sections, and a plurality of second sub-sections; filling the first trenches with a sacrificial layer; etching the patterned conductive layer to form a plurality of second trenches penetrating each patterned conductive layer; filling the second trenches with a second insulating layer; removing the sacrificial layer and filling the first trenches with the first insulating layer; etching and removing the first insulating layer on a side of the first trench away from the bit line to expose a patterned stacked structure formed by the alternating stacked conductive layer and the first insulating layer; and etching the exposed first insulating layer in the patterned stacked structure. The manufacturing method of the present application makes it easy to control the morphology of the through-holes and trenches formed by etching.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of design and manufacturing of semiconductor devices, and in particular to a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of dynamic random access memory (DRAM) technology, DRAM memory is gradually moving towards a three-dimensional (3D) structure to achieve higher integration. 3D DRAM, due to its exponentially increased storage density, has become a key direction for future DRAM development. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] The embodiments of the present application provide a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method has a simple process and can easily control the morphology of the through holes and grooves formed by etching, thereby reducing the process difficulty of device manufacturing.

[0005] The present invention provides a 3D stacked semiconductor device and a method for manufacturing the same. The 3D stacked semiconductor device includes: different layers of memory cells and word lines stacked and distributed in a direction perpendicular to a substrate; each layer includes multiple columns of memory cells, each memory cell includes a transistor and a capacitor; the word lines run through the different layers of memory cells;

[0006] The manufacturing method comprises:

[0007] Alternatingly depositing a first insulating layer and a conductive layer on a substrate to obtain a stacked structure;

[0008] Performing pattern etching on the stack structure along a direction toward the substrate to form a plurality of first trenches extending along a first direction parallel to the substrate in the stack structure, wherein the patterned conductive layer includes a bit line, a plurality of first sub-portions and a plurality of second sub-portions respectively connected to both sides of the bit line and spaced apart;

[0009] filling a sacrificial layer in the first trench;

[0010] Etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate;

[0011] filling the second trench with a second insulating layer;

[0012] removing the sacrificial layer and filling the first trench with the first insulating layer;

[0013] Etching and removing the first insulating layer on a side of the first trench away from the bit line to expose a patterned stack structure formed by alternately stacked conductive layers and first insulating layers;

[0014] The first insulating layer exposed in the patterned stack structure is etched.

[0015] In an exemplary embodiment of the present application, etching the patterned conductive layer along a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending along a second direction parallel to the substrate includes:

[0016] Along the direction toward the substrate, the patterned stack structure formed by the alternating stacked conductive layers and the first insulating layer and the sacrificial layer in the first groove are etched simultaneously through a single etching process to form a plurality of second grooves that penetrate each patterned conductive layer and extend along a second direction parallel to the substrate.

[0017] In an exemplary embodiment of the present application, removing the sacrificial layer includes: after filling the second trench with a second insulating layer, removing the sacrificial layer.

[0018] In an exemplary embodiment of the present application, etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate, and filling the second trenches with a second insulating layer includes:

[0019] The patterned stack structure formed by alternately stacked conductive layers and first insulating layers is etched along a direction toward the substrate to form first through holes penetrating the conductive layers at ends of the first and second sub-portions of the conductive layers away from the bit lines.

[0020] In an exemplary embodiment of the present application, removing the sacrificial layer and filling the first trench with the first insulating layer includes:

[0021] After forming the first through hole, filling the first through hole with the second insulating layer;

[0022] After forming the first through hole, filling the first through hole with the second insulating layer;

[0023] After the first through hole is filled with the second insulating layer, the sacrificial layer is removed, the second insulating layer is deposited on the inner wall of the first trench, and the first insulating layer is filled in the first trench.

[0024] In an exemplary embodiment of the present application, etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate, and filling the second trenches with a second insulating layer further comprises:

[0025] After filling the first trench with the first insulating layer, etching the first insulating layer in regions corresponding to the first through-hole at both ends of the first trench in a direction toward the substrate to form second through-holes at both ends of the first trench, wherein the second through-holes are connected to the first through-hole to form the second trench;

[0026] A second insulating layer is filled in the second through hole.

[0027] In an exemplary embodiment of the present application, etching the first insulating layer exposed in the patterned stack structure includes:

[0028] The first insulating layer exposed in the patterned stacked structure is etched, and a length of the first insulating layer etched away in the patterned stacked structure in the first direction is equal to a length of an inner electrode of the capacitor to be formed.

[0029] An embodiment of the present application further provides a 3D stacked semiconductor device, the 3D stacked semiconductor device comprising:

[0030] A plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate, and periodically distributed; each layer includes multiple columns of memory cells, and the memory cells include transistors; the transistors include a first electrode, a second electrode, a gate electrode, a semiconductor layer surrounding the sidewalls of the gate electrode, and a gate insulating layer disposed between the sidewalls of the gate electrode and the semiconductor layer, the semiconductor layer connecting the first electrode and the second electrode; the gate electrode extends in a direction perpendicular to the substrate;

[0031] a plurality of bit lines extending along a first direction parallel to the substrate, wherein transistors of two columns of memory cells located in the same layer and adjacent to each other in a second direction parallel to the substrate are connected to the same bit line;

[0032] The bit line and the first electrode and the second electrode of the transistor located in the same layer are located in the same conductive layer;

[0033] The conductive layers located in different layers have the same length in a first direction parallel to the substrate.

[0034] In an exemplary embodiment of the present application, the 3D stacked semiconductor device may further include:

[0035] a plurality of first insulating layers located at different layers, wherein the plurality of first insulating layers and the conductive layer are alternately distributed from bottom to top along a direction perpendicular to the substrate; and

[0036] a through hole penetrating each of the first insulating layers and each of the conductive layers, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer and extending in a direction perpendicular to the substrate are sequentially distributed in the through hole from inside to outside;

[0037] wherein the apertures of the through holes in the first insulating layers located in different layers are the same; and / or,

[0038] The apertures of the through holes in the conductive layers at different layers are the same.

[0039] An embodiment of the present application further provides an electronic device, which includes the 3D stacked semiconductor device provided in the above embodiment of the present application.

[0040] The manufacturing method of the 3D stacked semiconductor device of the embodiment of the present application uses at least two-step etching processes to form the first trench and the second trench (which may include the first through-hole and the second through-hole) respectively. It is easy to control the morphology of the trench and through-hole formed by etching, making it easy to control the length of the conductive layers of different layers, and it is easy to obtain conductive layers of different layers with the same length, thereby reducing the process difficulty of device manufacturing. Moreover, after the first trench is formed, a sacrificial layer with a different etching selectivity from the first insulating layer and the second insulating layer is used to fill the first trench, and the sacrificial layer is easily etched away in subsequent steps. The manufacturing method is simple in process and easy to implement.

[0041] In addition, the manufacturing method of the 3D stacked semiconductor device in the embodiment of the present application can use different etching methods to separately etch the stacked structure (simultaneously etch the first insulating layer and the conductive layer) and the first insulating layer in the stacked structure. For example, the stacked structure can be first dry-etched, and then the first insulating layer in the stacked structure can be laterally etched by wet etching and / or gas etching. The morphology of the film layer of the semiconductor device obtained by this method is easy to control, which reduces the process difficulty of device manufacturing.

[0042] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0044] Figure 1 A cross-sectional view of a 3D stacked semiconductor device according to an exemplary embodiment of the present application;

[0045] Figure 2 A process flow chart of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application;

[0046] Figure 3A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a stacked structure;

[0047] Figure 3B for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0048] Figure 3C for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0049] Figure 3D for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0050] Figure 4A A schematic cross-sectional view of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to a substrate after forming a first trench;

[0051] Figure 4B for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction;

[0052] Figure 4C for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0053] Figure 4D for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0054] Figure 4E for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0055] Figure 5AA schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device after forming a sacrificial layer according to an exemplary embodiment of the present application;

[0056] Figure 5B for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0057] Figure 5C for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0058] Figure 5D for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0059] Figure 6A A schematic cross-sectional view of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to a substrate after forming a first through hole;

[0060] Figure 6B for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction;

[0061] Figure 6C for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0062] Figure 6D for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0063] Figure 6E for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0064] Figure 7A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after depositing a second insulating layer in a first through hole;

[0065] Figure 7B for Figure 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0066] Figure 7C for Figure 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0067] Figure 7D for Figure 7AA schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0068] Figure 8A A schematic longitudinal cross-sectional view in the aa' direction after the first trench is filled with a first insulating layer according to a method for manufacturing a 3D stacked semiconductor device of an exemplary embodiment of the present application;

[0069] Figure 8B for Figure 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0070] Figure 8C for Figure 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0071] Figure 8D for Figure 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0072] Figure 9A A schematic longitudinal cross-sectional view in the aa' direction after the second insulating layer is filled in the second through hole according to a method for manufacturing a 3D stacked semiconductor device of an exemplary embodiment of the present application;

[0073] Figure 9B for Figure 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0074] Figure 9C for Figure 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0075] Figure 9D for Figure 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0076] Figure 10A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first insulating layer from a portion of the first trench area;

[0077] Figure 10B for Figure 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0078] Figure 10C for Figure 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0079] Figure 10D for Figure 10AA schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0080] Figure 11A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first insulating layer from a portion of the stacked structure;

[0081] Figure 11B for Figure 11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0082] Figure 11C for Figure 11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0083] Figure 11D for Figure 11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0084] Figure 12A A schematic longitudinal cross-sectional view along the aa' direction of another method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a second trench by one etching;

[0085] Figure 12B for Figure 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0086] Figure 12C for Figure 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0087] Figure 12D for Figure 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0088] Figure 13A A schematic longitudinal cross-sectional view along the aa' direction of another method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing a sacrificial layer;

[0089] Figure 13B for Figure 13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0090] Figure 13C for Figure 13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0091] Figure 13D for Figure 13AFIG. 1 is a schematic longitudinal cross-sectional view of the semiconductor device along the dd' direction.

[0092] The meanings of the various symbols in the accompanying drawings are:

[0093] 10-substrate; 11-first insulating layer; 12-conductive layer; 13-second insulating layer; 14-sacrificial layer; 20-first trench; 21-first through hole; 22-second through hole; 23-second trench; 31-bit line; 32-first sub-section; 33-second sub-section; 41-first electrode; 42-second electrode; 43-external electrode; 50-hard mask; 60-memory cell; 61-transistor; 62-capacitor; 70-word line; 71-gate electrode; 80-semiconductor layer; K-through hole. DETAILED DESCRIPTION

[0094] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0095] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0096] The ordinal numbers such as “first” and “second” in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0097] In this application, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on this application. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in the disclosure are not limited and may be appropriately replaced according to the circumstances.

[0098] In this application, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0099] In this application, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0100] In this application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in this application, unless otherwise specified, "source electrode" and "drain electrode" may be interchanged.

[0101] In the present disclosure, “electrical connection” or “connection” includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupling connection, such as coupled to), or physical direct connection. There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0102] In this application, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0103] In this application, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0104] The phrase "A and B are disposed in the same layer" in this application means that A and B are distributed on the same horizontal plane, or, although not on the same horizontal plane, are located in different areas of the same support surface. In one embodiment, A and B are formed simultaneously through the same patterning process on the same film layer.

[0105] In the embodiments of this application, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, if A and B are formed from the same material into a single film layer and are simultaneously connected through the same patterning process, or if B is directly grown on A via epitaxial growth, the two materials may not be identical.

[0106] In this application, "pore size" refers to the average pore size measured at multiple locations.

[0107] In the present application, the first direction parallel to the substrate can be understood as a lateral direction. In various embodiments of the present application, the interval distribution can be understood as a separate, independent distribution.

[0108] An embodiment of the present application provides a method for manufacturing a 3D stacked semiconductor device. Figure 1 FIG. 1 is a cross-sectional view of a 3D stacked semiconductor device according to an exemplary embodiment of the present application. Figure 1 As shown, the 3D stacked semiconductor device includes: different layers of memory cells 60 and word lines 70 stacked and distributed in a direction perpendicular to the substrate; each layer includes multiple columns of memory cells 60, each memory cell 60 includes a transistor 61 and a capacitor 62; the word lines 70 run through different layers of memory cells 60.

[0109] like Figure 2 As shown, the manufacturing method includes:

[0110] Alternately depositing first insulating layers and conductive layers on the substrate to obtain a stacked structure of multiple first insulating layers and multiple conductive layers;

[0111] Performing pattern etching on the stack structure along a direction toward the substrate to form a plurality of first trenches extending along a first direction parallel to the substrate in the stack structure, wherein the patterned conductive layer includes a bit line, a plurality of first sub-portions and a plurality of second sub-portions respectively connected to both sides of the bit line and spaced apart;

[0112] filling a sacrificial layer in the first trench;

[0113] Etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate;

[0114] filling the second trench with a second insulating layer;

[0115] removing the sacrificial layer and filling the first trench with the first insulating layer;

[0116] Etching and removing the first insulating layer on a side of the first trench away from the bit line to expose a patterned stack structure formed by alternately stacked conductive layers and first insulating layers;

[0117] The first insulating layer exposed in the patterned stack structure is etched.

[0118] In an exemplary embodiment of the present application, etching the patterned conductive layer along a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending along a second direction parallel to the substrate includes:

[0119] Along the direction toward the substrate, the patterned stack structure formed by the alternating stacked conductive layers and the first insulating layer and the sacrificial layer in the first groove are etched simultaneously through a single etching process to form a plurality of second grooves that penetrate each patterned conductive layer and extend along a second direction parallel to the substrate.

[0120] In an exemplary embodiment of the present application, removing the sacrificial layer includes: after filling the second trench with a second insulating layer, removing the sacrificial layer.

[0121] In an exemplary embodiment of the present application, etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate, and filling the second trenches with a second insulating layer includes:

[0122] The patterned stack structure formed by alternately stacked conductive layers and first insulating layers is etched along a direction toward the substrate to form first through holes penetrating the conductive layers at ends of the first and second sub-portions of the conductive layers away from the bit lines.

[0123] In an exemplary embodiment of the present application, removing the sacrificial layer and filling the first trench with the first insulating layer includes:

[0124] After forming the first through hole, filling the first through hole with the second insulating layer;

[0125] After forming the first through hole, filling the first through hole with the second insulating layer;

[0126] After the first through hole is filled with the second insulating layer, the sacrificial layer is removed, the second insulating layer is deposited on the inner wall of the first trench, and the first insulating layer is filled in the first trench.

[0127] In an exemplary embodiment of the present application, etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate, and filling the second trenches with a second insulating layer further comprises:

[0128] After filling the first trench with the first insulating layer, etching the first insulating layer in regions corresponding to the first through-hole at both ends of the first trench in a direction toward the substrate to form second through-holes at both ends of the first trench, wherein the second through-holes are connected to the first through-hole to form the second trench;

[0129] A second insulating layer is filled in the second through hole.

[0130] In an exemplary embodiment of the present application, etching the first insulating layer exposed in the patterned stack structure includes:

[0131] The first insulating layer exposed in the patterned stacked structure is etched, and a length of the first insulating layer etched away in the patterned stacked structure in the first direction is equal to a length of an inner electrode of the capacitor to be formed.

[0132] The technical solution of the embodiment of the present application is further illustrated below through the manufacturing process of the 3D stacked semiconductor device of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0133] Figure 3A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a stacked structure; Figure 3B for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 3C for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 3D for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 4A A schematic cross-sectional view of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to a substrate after forming a first trench; Figure 4B for Figure 4AA schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction; Figure 4C for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 4D for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 4E for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 5A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device after forming a sacrificial layer according to an exemplary embodiment of the present application; Figure 5B for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 5C for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 5D for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 6A A schematic cross-sectional view of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to a substrate after forming a first through hole;

[0134] Figure 6B for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction; Figure 6C for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 6D for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 6E for Figure 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 7A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after depositing a second insulating layer in a first through hole; Figure 7B for Figure 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0135] Figure 7C for Figure 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 7D for Figure 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 8AA schematic longitudinal cross-sectional view in the aa' direction after the first trench is filled with a first insulating layer according to a method for manufacturing a 3D stacked semiconductor device of an exemplary embodiment of the present application; Figure 8B for Figure 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 8C for Figure 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 8D for Figure 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction;

[0136] Figure 9A A schematic longitudinal cross-sectional view in the aa' direction after the second insulating layer is filled in the second through hole according to a method for manufacturing a 3D stacked semiconductor device of an exemplary embodiment of the present application; Figure 9B for Figure 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 9C for Figure 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 9D for Figure 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 10A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first insulating layer from a portion of the first trench area; Figure 10B for Figure 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 10C for Figure 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 10D for Figure 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 11A A schematic longitudinal cross-sectional view along the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first insulating layer from a portion of the stacked structure; Figure 11B for Figure 11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 11C for Figure 11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 11D for Figure 11A FIG. 1 is a schematic longitudinal cross-sectional view of the semiconductor device along the dd' direction.

[0137] like Figures 3A to 11D As shown, in an exemplary embodiment of the present application, the method for manufacturing the 3D stacked semiconductor device may include:

[0138] S10: providing a substrate 10, and alternately depositing a first insulating layer 11 and a conductive layer 12 on the substrate 10 to obtain a stacked structure consisting of the first insulating layer 11 and the conductive layer 12 distributed in layers, such as Figures 3A to 3D shown.

[0139] In an exemplary embodiment of the present application, the material of the first insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) or other silicon-containing film layers.

[0140] In an exemplary embodiment of the application, the material of the conductive layer may be any one or more of a conductive metal, a nitride of a conductive metal, and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc. The conductive layer may be a single layer or a multilayer structure, for example, it may be a multilayer structure formed by Ti, TiN, and W. For example, Ti, TiN, and W may be deposited in sequence on the side of the first insulating layer 11 away from the substrate 10 to form a conductive layer of a multilayer structure. Providing TiN between the side of W close to the substrate 10 and the first insulating layer 11 can prevent W from being oxidized by the oxygen-containing first insulating layer 11, so the film layer formed by TiN can be called an anti-oxidation layer. Of course, the first insulating layer may be an oxygen-free film layer, and then the conductive layer does not need to add an anti-oxidation layer.

[0141] In an exemplary embodiment of the present application, Ti may be deposited by a chemical vapor deposition (CVD) process; TiN may be deposited by an atomic layer deposition (ALD) process; and W may be deposited by a CVD or ALD process.

[0142] In an exemplary embodiment of the present application, the substrate 10 may be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functional functions or circuits are already distributed, and the device involved in the inventive construction of the embodiment of the present application is arranged on the upper main surface of the supporting structure.

[0143] Figures 3A to 3D The stacked structure shown in the figure includes four first insulating layers 11 and three conductive layers 12, which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 11 and conductive layers 12 that are alternately arranged.

[0144] S20: depositing a second insulating layer 13 on the surface of the stacked structure; and performing pattern etching on the stacked structure.

[0145] Exemplarily, patterning and etching the stacked structure may include:

[0146] Defining a photolithography pattern, performing photolithography, and etching the second insulating layer 13 and the stacked structure in a direction toward the substrate 10 to form a plurality of first trenches 20 extending along a first direction parallel to the substrate 10 in the stacked structure, obtaining a patterned first insulating layer 11 and a patterned conductive layer 12 that are alternately stacked;

[0147] The patterned conductive layer 12 includes bit lines 31, a plurality of spaced-apart first sub-parts 32, and a plurality of spaced-apart second sub-parts 33; wherein, the bit lines 31 connect the first sub-parts 32 and the second sub-parts 33, the plurality of spaced-apart first sub-parts 32 and the plurality of spaced-apart second sub-parts 33 are respectively located on both sides of the bit lines 31, the bit lines 31, the plurality of first sub-parts 32, and the plurality of second sub-parts 33 can form a "rich" character-shaped structure, the bit lines 31 serve as the main body of the "rich" character-shaped structure, and the plurality of first sub-parts 32 and the plurality of second sub-parts 33 serve as the branches of the "rich" character-shaped structure; the first sub-parts 32 can extend along the first direction, the second sub-parts 33 can extend along the first direction, the bit lines 31 can extend along a second direction parallel to the substrate 10, and the second direction intersects the first direction; the pattern of the patterned first insulating layer 11 is the same as the pattern of the patterned conductive layer 12, as Figures 4A to 4E shown.

[0148] One end of the first sub-part 32 connected to the bit line 31 serves as the first electrode 41 of the transistor, and one end of the first sub-part 32 far from the bit line 31 forms a second electrode 42 of a transistor by being disconnected from the bit line 31 subsequently. The bit line 31 and the first electrode 41 of the transistor connected thereto can be an integral structure, or the bit line 31 and the first electrode 41 of the transistor connected thereto are shared; one end of the second sub-part 33 far from the bit line 31 forms a second electrode 42 of an adjacent transistor by being disconnected from the bit line 31 subsequently, and the bit line 31 is connected to the first electrode 41 of the transistor, or the bit line 31 and the first electrode 41 of the transistor are shared.

[0149] Exemplarily, the material of the second insulating layer can be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the material of the second insulating layer and the first insulating layer are different, so that when etching and removing one of the insulating layers subsequently, the first insulating layer and the second insulating layer can have different etching rates, thereby removing the insulating layer that is desired to be removed. For example, in this embodiment, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.

[0150] For example, the first direction and the second direction may be perpendicular to each other. For example, the first direction may be as follows: Figure 1 The a-a' direction or the bb' direction shown in FIG. 1 , the second direction may be as follows Figure 1 The c-c' direction or d-d' direction shown.

[0151] For example, the first trench 20 may extend in a direction perpendicular to the substrate 10 , and the first trench 20 may extend into the substrate 10 .

[0152] S30: Depositing a sacrificial layer 14 filling the first trench 20 on the substrate 10, such as 5A to 5D shown.

[0153] Exemplarily, the sacrificial layer may be formed of a material having an etching rate significantly different from that of the first insulating layer and the second insulating layer under the same etching conditions, for example, water-soluble organic carbon (SOC) may be used, but is not limited to SOC.

[0154] S40 : etching the patterned conductive layer 12 to form first through holes 21 penetrating the conductive layers 12 at ends of the first sub-portion 32 and the second sub-portion 33 away from the bit line 31 .

[0155] For example, step S40 may include: defining a photolithographic pattern, performing photolithography, and etching the sacrificial layer 14, the second insulating layer 13, the patterned first insulating layer 11 and the patterned conductive layer 12 that are alternately stacked in a direction toward the substrate 10, forming a first through hole 21 penetrating each conductive layer 12 at an end of the first sub-portion 32 and the second sub-portion 33 away from the bit line 31, as shown in FIG. Figures 6A to 6E shown.

[0156] For example, the first through hole 21 may extend in a direction perpendicular to the substrate 10. The first through hole 21 may penetrate each patterned first insulating layer 11 to expose the substrate 10.

[0157] For example, Figure 6B As shown, the apertures of the first through holes 21 in the first insulating layers 11 located in different layers are the same, namely, D.

[0158] For example, Figure 6B As shown, the apertures of the first through holes 21 in the conductive layers 12 at different layers are the same, d. The lengths of the conductive layers 12 remaining in the first direction after etching the first through holes 21 are the same, L.

[0159] The first insulating layer 11 and the conductive layer 12 have different etching rates, and D may be greater than d.

[0160] S50: depositing a second insulating layer 13 filling the first through hole 21 on the substrate 10, and removing all the sacrificial layers 14, as shown in FIG. 7A to 7D shown.

[0161] S60: depositing a second insulating layer 13 covering the sidewalls of the first trench 20 and a first insulating layer 11 filling the first trench 20 on the substrate 10, and planarizing the second insulating layer 13 and the first insulating layer 11 on the top surface of the substrate 10 by a chemical mechanical polishing (CMP) process. The planarized second insulating layer 13 still covers the stacked structure formed by the alternately stacked first insulating layer 11 and the conductive layer, such as Figures 8A to 8D shown.

[0162] S70 : forming second through holes 22 communicating with the first through holes 21 at both ends of the first trench 20 , and filling the second through holes 22 with the second insulating layer 13 .

[0163] Exemplarily, step S70 may include: defining a photolithographic pattern, performing photolithography, and etching the first insulating layer 11 located at both ends of the first trench 20 and in the region corresponding to the first through hole 21 in a direction toward the substrate 10, thereby forming second through holes 22 located at both ends of the first trench 20, and the second through holes 22 are connected to the first through holes 21 to form a second trench 23 extending along the second direction; depositing a second insulating layer 13 filling the second through holes 22 on the substrate 10, and performing CMP on the second insulating layer 13 on the top surface of the substrate 10, such as 9A to 9D The second insulating layer 13 in the second trench 23 can subsequently serve as a supporting layer (or frame) for supporting the capacitor.

[0164] S80 : etching and removing the first insulating layer 11 on a side of the first trench 20 close to the second through hole 22 to expose the alternately stacked first insulating layer 11 and conductive layer 12 .

[0165] Exemplarily, step S80 may include: depositing a hard mask 50 on the surface of the substrate 10 obtained in step S70, defining a photolithographic pattern, performing photolithography, and etching the hard mask 50, the second insulating layer 13, and the first insulating layer 11 located on a side of the first trench 20 close to the second through hole 22 in a direction toward the substrate 10, removing the first insulating layer 11 on a side of the first trench 20 close to the second through hole 22, and retaining the first insulating layer 11 on a side of the first trench 20 close to the bit line 31, as shown in FIG. 10A to 10D shown.

[0166] S90: etching and removing the second insulating layer 13 on the sidewall of the exposed area of ​​the patterned stack structure to expose the first insulating layer 11 of the patterned stack structure, removing the hard mask 50, and performing a transverse etching on the exposed first insulating layer 11 of the patterned stack structure in the first trench 20, as shown in FIG. 11A to 11D shown.

[0167] Etching the first insulating layer 11 in a portion of the stacked structure provides space for the subsequent deposition of the capacitor's dielectric layer and external electrodes. The ends of the first subsection 32 and second subsection 33 of the conductive layer 12, away from the bit line 31, serve as the capacitor's internal electrodes. The capacitor's internal electrodes and the second electrode 42 of the transistor connected thereto form an integrated structure. Therefore, the length of the etched first insulating layer 11 in the stacked structure in the first direction is the desired length of the capacitor's internal electrodes.

[0168] Figure 12A A schematic longitudinal cross-sectional view along the aa' direction of another method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a second trench by one etching; Figure 12B for Figure 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 12C for Figure 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 12D for Figure 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the dd' direction; Figure 13A A schematic longitudinal cross-sectional view along the aa' direction of another method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing a sacrificial layer; Figure 13B for Figure 13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 13C for Figure 13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 13D for Figure 13A FIG. 1 is a schematic longitudinal cross-sectional view of the semiconductor device along the dd' direction.

[0169] like 12A to 13D As shown, in another exemplary embodiment of the present application, the method for manufacturing the 3D stacked semiconductor device may include the following steps.

[0170] S10': the same as step S10.

[0171] S20': the same as step S20.

[0172] S30': the same as step S30.

[0173] S40': defining a photolithographic pattern, performing photolithography, and etching the sacrificial layer 14, the second insulating layer 13, the patterned first insulating layer 11 and the patterned conductive layer 12 that are alternately stacked in a direction toward the substrate 10, forming a second trench 23 penetrating each conductive layer 12 at an end of the first sub-portion 32 and the second sub-portion 33 away from the bit line 31, and the second trench 23 extends along a second direction parallel to the substrate 10, as shown in FIG. 12A to 12D shown.

[0174] In this embodiment, the second trench 23 is directly formed by one etching in step S40 ′.

[0175] For example, Figure 12A As shown, the apertures of the first through holes 21 in the first insulating layers 11 located in different layers are the same, namely, D.

[0176] For example, Figure 12A As shown, the apertures of the first through holes 21 in the conductive layers 12 at different layers are the same, d. The lengths of the conductive layers 12 remaining in the first direction after etching the first through holes 21 are the same, L.

[0177] The first insulating layer 11 and the conductive layer 12 have different etching rates, and D may be greater than d.

[0178] S50': depositing a second insulating layer 13 filling the second trench 23 on the substrate 10, and removing all the sacrificial layers 14, as shown in FIG. 13A to 13D shown.

[0179] S60': After removing the sacrificial layer 14, the space vacated in the first trench 20 is filled with the first insulating layer 11 to obtain the following 9A to 9D The device structure shown.

[0180] The subsequent steps are the same as S80 to S90.

[0181] Exemplarily, the manufacturing method of the 3D stacked semiconductor device may further include: after completing step S90, depositing a dielectric layer and a conductive film layer in the exposed areas of the first sub-portion 32 and the second sub-portion 33 of the conductive layer 12 away from one end of the bit line 31 to respectively form the dielectric layer and external electrode of the capacitor to be formed, thereby obtaining the capacitor.

[0182] Exemplarily, the manufacturing method of the 3D stacked semiconductor device may further include: before or after forming the capacitor, etching a through hole K penetrating each patterned conductive layer in the patterned stack structure, the through hole K disconnecting the first sub-portion 32 to form the first electrode 41 and the second electrode 42 of a transistor, and the through hole K disconnecting the second sub-portion 33 to form the first electrode 41 and the second electrode 42 of another transistor; and, depositing a semiconductor layer and a gate insulating layer on the inner wall of the through hole K in sequence, and filling a gate electrode in the through hole K, so that the gate electrodes of a column of transistors located in different layers can be connected together to form a word line extending in a direction perpendicular to the substrate.

[0183] The manufacturing method of the 3D stacked semiconductor device of the embodiment of the present application adopts at least two-step etching processes to form the first trench and the second trench (which may include the first through-hole and the second through-hole) respectively. It is easy to control the morphology of the trench and through-hole formed by etching, making it easy to control the length of the conductive layers of different layers, and easy to obtain conductive layers of different layers with the same length, thereby reducing the process difficulty of device manufacturing. Moreover, after the first trench is formed, a sacrificial layer with a different etching selectivity from the first insulating layer and the second insulating layer is used to fill the first trench, and the sacrificial layer is easily etched away in subsequent steps (for example, a SOC that is easily etched away). The manufacturing method has a simple process and is easy to implement.

[0184] In addition, the manufacturing method of the 3D stacked semiconductor device in the embodiment of the present application can use different etching methods to separately etch the stacked structure (simultaneously etch the first insulating layer and the conductive layer) and the first insulating layer in the stacked structure. For example, the stacked structure can be first dry-etched, and then the first insulating layer in the stacked structure can be laterally etched by wet etching and / or gas etching. The morphology of the film layer of the semiconductor device obtained by this method is easy to control, which reduces the process difficulty of device manufacturing.

[0185] The present application also provides a 3D stacked semiconductor device, such as Figure 1 As shown, the 3D stacked semiconductor device includes: a plurality of memory cells 60 and a plurality of bit lines 31 .

[0186] Multiple memory cells 60 are distributed in different layers, stacked and periodically arranged in a direction perpendicular to the substrate 10. Each layer includes multiple columns of memory cells 60, each of which includes a transistor 61. The transistor 61 includes a first electrode 41, a second electrode 42, a gate electrode 71, a semiconductor layer 80 surrounding the sidewalls of the gate electrode 71, and a gate insulating layer (not shown) disposed between the sidewalls of the gate electrode 71 and the semiconductor layer 80. The semiconductor layer 80 is located between the first electrode 41 and the second electrode 42 and is connected to the first electrode 41 and the second electrode 42, respectively. The gate electrode 71 extends in a direction perpendicular to the substrate 10.

[0187] A plurality of bit lines 31 extend along a first direction parallel to the substrate 10 , and transistors 61 of two columns of memory cells 60 located in the same layer and adjacent in a second direction parallel to the substrate 10 are connected to the same bit line 31 ;

[0188] The bit line 31 and the first electrode 41 and the second electrode 42 of the transistor 61 located in the same layer are located in the same conductive layer 12;

[0189] The conductive layers 12 located in different layers have the same length in a first direction parallel to the substrate 10 .

[0190] For example, the first direction and the second direction may be perpendicular to each other. For example, the first direction may be as follows: Figure 1 The bb' direction shown in FIG. 1 may be the second direction as shown in FIG. Figure 1 c-c' direction shown.

[0191] In the exemplary embodiments of the present application, Figure 1 As shown, the 3D stacked semiconductor device may further include: a plurality of first insulating layers 11 located at different layers, and the plurality of first insulating layers 11 and the conductive layers 12 are alternately distributed from bottom to top along a direction perpendicular to the substrate 10 .

[0192] In the exemplary embodiments of the present application, Figure 1 As shown, the 3D stacked semiconductor device may further include: a through hole K penetrating each first insulating layer 11 and each conductive layer 12, wherein the through hole K is sequentially distributed from the inside to the outside with a word line 70, the gate insulating layer surrounding the side wall of the word line 70, and a plurality of semiconductor layers 80 surrounding different regions of the side wall of the gate insulating layer and extending in a direction perpendicular to the substrate 10.

[0193] Exemplarily, the apertures of the through holes K in the first insulating layers 11 located in different layers are the same.

[0194] Exemplarily, the diameters of the through holes K in the conductive layers 12 located at different layers are the same.

[0195] In the exemplary embodiments of the present application, Figure 1 As shown, the semiconductor layer 80 may surround the gate electrode 71 .

[0196] Here, "surrounding" can be understood as partial surrounding or full surrounding. In some embodiments, the surrounding can be full surrounding, that is, at least the entire side wall of the gate electrode is surrounded by the semiconductor layer, and the cross-section of the semiconductor layer after surrounding is a closed ring. The cross-section is cut along a direction perpendicular to the substrate and extending parallel to the first direction. The entire side wall and one end face of the gate electrode are surrounded by the semiconductor layer, and this kind of surrounding also belongs to full surrounding. In some embodiments, the surrounding can be partial surrounding, that is, part of the side wall of the gate electrode is surrounded by the semiconductor layer, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers. For example, the opposite side surfaces of the gate electrode are surrounded by the semiconductor layer, and the cross-section of the semiconductor layer is a ring with two openings.

[0197] In an exemplary embodiment of the present application, the material of the semiconductor layer may be silicon or polysilicon with a band gap smaller than 1.65 eV, or a wide band gap material, such as a metal oxide material with a band gap larger than 1.65 eV.

[0198] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0199] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. Materials such as the above can be used as long as the leakage current of the transistor can meet the requirements. The specific adjustment can be made according to the actual situation.

[0200] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0201] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0202] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0203] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it may be a metal alloy containing the aforementioned metals;

[0204] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0205] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0206] In an exemplary embodiment of the present application, the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The following will exemplarily illustrate the characteristics of the gate insulating layer of the present application.

[0207] Low-K materials, such as silicon oxide.

[0208] High-K materials, in some embodiments, may include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. For example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0209] The above-mentioned memory cell may be a memory cell including a transistor, wherein the transistor may be an access transistor. The memory cell may further include other components, such as a capacitor in a 1T1C memory cell, or a read transistor and a storage node in a 2T0C memory cell.

[0210] In an exemplary embodiment of the present application, the capacitor includes an inner electrode, an outer electrode 43, and a dielectric layer located between the inner electrode and the outer electrode (the inner electrode and the dielectric layer are both covered by the outer electrode, Figure 1 not shown).

[0211] In an exemplary embodiment of the present application, the material of the dielectric layer may be silicon oxide or a High-K dielectric material, and the High-K dielectric material may include but is not limited to hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0212] In an exemplary embodiment of the present application, the 3D stacked semiconductor device may be a 3D memory, such as a 3D DRAM, etc. The 3D memory may have a 1T1C or 2T (including a read transistor and a write transistor) structure.

[0213] An embodiment of the present application further provides an electronic device, which includes the 3D stacked semiconductor device provided in the above embodiment of the present application.

[0214] In an exemplary embodiment of the present application, the electronic device may be a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0215] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A 3D stacked semiconductor device and a method for manufacturing the same, characterized in that: The 3D stacked semiconductor device includes: different layers of memory cells and word lines stacked and distributed in a direction perpendicular to the substrate; each layer includes multiple columns of memory cells, each memory cell includes a transistor and a capacitor; the word lines run through the different layers of memory cells; The manufacturing method comprises: Alternatingly depositing a first insulating layer and a conductive layer on a substrate to obtain a stacked structure; Performing pattern etching on the stack structure along a direction toward the substrate to form a plurality of first trenches extending along a first direction parallel to the substrate in the stack structure, wherein the patterned conductive layer includes a bit line, a plurality of first sub-portions and a plurality of second sub-portions respectively connected to both sides of the bit line and spaced apart; filling a sacrificial layer in the first trench; Etching the patterned conductive layer in a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending in a second direction parallel to the substrate; filling the second trench with a second insulating layer; removing the sacrificial layer and filling the first trench with the first insulating layer; Etching and removing the first insulating layer on a side of the first trench away from the bit line to expose a patterned stack structure formed by alternately stacked conductive layers and first insulating layers; The first insulating layer exposed in the patterned stack structure is etched.

2. The manufacturing method according to claim 1, characterized in that The etching of the patterned conductive layer along a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending along a second direction parallel to the substrate comprises: Along the direction toward the substrate, the patterned stack structure formed by the alternating stacked conductive layers and the first insulating layer and the sacrificial layer in the first groove are etched simultaneously through a single etching process to form a plurality of second grooves that penetrate each patterned conductive layer and extend along a second direction parallel to the substrate.

3. The manufacturing method according to claim 2, characterized in that The removing of the sacrificial layer includes: after filling the second trench with a second insulating layer, removing the sacrificial layer.

4. The manufacturing method according to claim 1, characterized in that The etching of the patterned conductive layer along a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending along a second direction parallel to the substrate, and filling the second trenches with a second insulating layer comprises: The patterned stack structure formed by alternately stacked conductive layers and first insulating layers is etched along a direction toward the substrate to form first through holes penetrating the conductive layers at ends of the first and second sub-portions of the conductive layers away from the bit lines.

5. The manufacturing method according to claim 4, characterized in that The removing the sacrificial layer and filling the first trench with the first insulating layer includes: After forming the first through hole, filling the first through hole with the second insulating layer; After the first through hole is filled with the second insulating layer, the sacrificial layer is removed, the second insulating layer is deposited on the inner wall of the first trench, and the first insulating layer is filled in the first trench.

6. The manufacturing method according to claim 5, characterized in that The etching of the patterned conductive layer along a direction toward the substrate to form a plurality of second trenches penetrating each patterned conductive layer and extending along a second direction parallel to the substrate, and filling the second trenches with a second insulating layer further comprises: After filling the first trench with the first insulating layer, etching the first insulating layer in regions corresponding to the first through-hole at both ends of the first trench in a direction toward the substrate to form second through-holes at both ends of the first trench, wherein the second through-holes are connected to the first through-hole to form the second trench; A second insulating layer is filled in the second through hole.

7. The manufacturing method according to claim 5, characterized in that The etching of the first insulating layer exposed in the patterned stack structure comprises: The first insulating layer exposed in the patterned stacked structure is etched, and a length of the first insulating layer etched away in the patterned stacked structure in the first direction is equal to a length of an inner electrode of the capacitor to be formed.

8. A 3D stacked semiconductor device, characterized in that: Obtained by the manufacturing method according to any one of claims 1 to 7, the 3D stacked semiconductor device comprises: A plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate, and periodically distributed; each layer includes multiple columns of memory cells, and the memory cells include transistors; the transistors include a first electrode, a second electrode, a gate electrode, a semiconductor layer surrounding the sidewalls of the gate electrode, and a gate insulating layer disposed between the sidewalls of the gate electrode and the semiconductor layer, the semiconductor layer connecting the first electrode and the second electrode; the gate electrode extends in a direction perpendicular to the substrate; a plurality of bit lines extending along a first direction parallel to the substrate, wherein transistors of two columns of memory cells located in the same layer and adjacent to each other in a second direction parallel to the substrate are connected to the same bit line; The bit line and the first electrode and the second electrode of the transistor located in the same layer are located in the same conductive layer; The conductive layers located in different layers have the same length in a first direction parallel to the substrate.

9. The 3D stacked semiconductor device according to claim 8, wherein: Also includes: a plurality of first insulating layers located at different layers, wherein the plurality of first insulating layers and the conductive layer are alternately distributed from bottom to top along a direction perpendicular to the substrate; and a through hole penetrating each of the first insulating layers and each of the conductive layers, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer and extending in a direction perpendicular to the substrate are sequentially distributed in the through hole from inside to outside; wherein the apertures of the through holes in the first insulating layers located in different layers are the same; and / or, The apertures of the through holes in the conductive layers at different layers are the same.

10. An electronic device, characterized in that: A semiconductor device comprising the 3D stack according to claim 8 or 9.

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