Three-dimensional memory, manufacturing method thereof and memory system

Abstract

The embodiment of the invention discloses a three-dimensional memory, a manufacturing method thereof and a memory system, and the three-dimensional memory comprises a stacking structure which comprises gate layers and first dielectric layers which are alternately stacked; the channel column penetrates through the stacking structure along a first direction; along a second direction perpendicular to the first direction, each channel column comprises a barrier layer, a storage layer, a tunneling layer and a channel layer which are arranged in sequence; wherein the storage layer comprises a plurality of storage sub-layers corresponding to the grid layer, and the storage sub-layers are electrically isolated from one another.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and more particularly to a three-dimensional memory and a manufacturing method thereof, and a memory system. Background Art

[0002] A three-dimensional memory may generally include stacked mutually insulated gate layers and a channel column that penetrates the gate layer. Along the radial direction of the channel column, the channel column includes a barrier layer, a storage layer (charge trapping layer), a tunneling layer, and a channel layer. When the memory is programmed, electrons in the channel layer are injected into the storage layer through the tunneling layer under the action of the gate layer voltage, and the traps in the storage layer capture electrons to achieve information storage.

[0003] In order to improve the storage density of three-dimensional memory, the number of gate layer stacks can be increased, or the radial size of the channel pillar can be reduced to increase the number of storage units per unit wafer area, thereby increasing the storage density. However, regardless of whether the number of gate layer stacks is increased or the size of the channel pillar is reduced, the film morphology of the channel pillar is difficult to control, which reduces the performance of the device and the stability of the three-dimensional memory. How to improve the stability of three-dimensional memory has become an urgent problem to be solved. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a three-dimensional memory, comprising:

[0005] A stacked structure comprising alternately stacked gate layers and first dielectric layers;

[0006] A channel column penetrates the stack structure along a first direction; along a second direction perpendicular to the first direction, the channel column includes: a blocking layer, a storage layer, a tunneling layer and a channel layer arranged in sequence; wherein the storage layer includes a plurality of storage sublayers corresponding to the gate layer, and the storage sublayers are electrically isolated from each other.

[0007] In some embodiments, the first dielectric layer at least penetrates the barrier layer and the storage layer along the second direction, and the storage layer is divided into a plurality of storage sub-layers by the first dielectric layer.

[0008] In some embodiments, in the first direction, the storage layer includes a second dielectric layer located between two adjacent storage sublayers; and in the second direction, the barrier layer is located between the first dielectric layer and the second dielectric layer.

[0009] In some embodiments, the first dielectric layer penetrates at least a portion of the thickness of the barrier layer along the second direction.

[0010] In some embodiments, the blocking layer includes a first blocking sublayer and a second blocking sublayer, and the second blocking sublayer is located between the first blocking sublayer and the second dielectric layer; wherein the dielectric constant of the first blocking sublayer is greater than the dielectric constant of the second blocking sublayer; and the first dielectric layer penetrates at least part of the thickness of the first blocking sublayer along the second direction.

[0011] In some embodiments, in the first direction, the second dielectric layer is located between the two gate layers.

[0012] In some embodiments, in the first direction, a size of the storage sublayer is greater than or equal to a size of the gate layer.

[0013] In some embodiments, an orthographic projection of the gate layer in the second direction falls within an orthographic projection of the storage sublayer in the second direction.

[0014] In some embodiments, the three-dimensional memory further comprises:

[0015] A protection layer, wherein the protection layer at least covers the top surface and the bottom surface of the gate layer in the first direction, and the protection layer is located between two adjacent first dielectric layers; and the dielectric constant of the protection layer is greater than the dielectric constant of the first dielectric layer.

[0016] In some embodiments, the gate layer includes:

[0017] A connecting layer and a conductive layer; wherein the connecting layer surrounds the conductive layer; and the connecting layer is located between two adjacent first dielectric layers.

[0018] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a three-dimensional memory is provided, comprising:

[0019] forming a stacked structure, the stacked structure comprising alternately stacked dielectric material layers and sacrificial layers;

[0020] forming a channel hole penetrating the stacked structure along a first direction;

[0021] Etching a portion of the dielectric material layer along a second direction perpendicular to the first direction through the channel hole to form an opening between two adjacent sacrificial layers;

[0022] forming a first stop layer at one end of the sacrificial layer exposed from the sidewall of the channel hole;

[0023] forming a second stop layer in the opening;

[0024] On the first stop layer and the second stop layer, a barrier layer, a storage layer, a tunnel layer and a channel layer are sequentially formed;

[0025] removing the sacrificial layer and the first stop layer, forming a first gap between adjacent dielectric material layers, and forming a gate layer in the first gap;

[0026] removing the dielectric material layer and the second stop layer to form a second gap between adjacent gate layers;

[0027] The storage layer is separated by the second gap to form a plurality of storage sub-layers; wherein the storage sub-layers correspond to the gate layer and the storage sub-layers are electrically isolated from each other;

[0028] A first dielectric layer is formed in the second gap.

[0029] In some embodiments, a method of forming the first stop layer includes:

[0030] An end of the sacrificial layer exposed from the sidewall of the channel hole is oxidized, and a portion of the sacrificial layer forms the first stop layer.

[0031] In some embodiments, a method of forming the second stop layer includes:

[0032] A second stop material layer is formed in the opening and on the first stop layer, and a portion of the second stop material layer on the first stop layer is etched away to form the second stop layer.

[0033] In some embodiments, the step of isolating the storage layer through the second gap to form a plurality of storage sub-layers comprises:

[0034] The barrier layer and the storage layer are etched so that the second gap at least penetrates the barrier layer and the storage layer in the second direction to form the storage sublayer.

[0035] In some embodiments, the method of forming the barrier layer includes:

[0036] A first blocking sublayer and a second blocking sublayer are sequentially formed on the first stop layer and the second stop layer; wherein the dielectric constant of the first blocking sublayer is greater than the dielectric constant of the second blocking sublayer.

[0037] In some embodiments, the second gap exposes the first blocking sublayer, and / or the second gap penetrates at least a portion of the thickness of the first blocking sublayer in the second direction; and the step of isolating the storage layer through the second gap to form a plurality of storage sublayers includes:

[0038] Part of the storage layer is oxidized to form a second dielectric layer; wherein the second dielectric layer divides the storage layer into a plurality of storage sub-layers.

[0039] In some embodiments, in the first direction, the second dielectric layer is located between two adjacent gate layers.

[0040] In some embodiments, in the first direction, a size of the storage sublayer is greater than or equal to a size of the gate layer.

[0041] In some embodiments, an orthographic projection of the gate layer in the second direction falls within an orthographic projection of the storage sublayer in the second direction.

[0042] In some embodiments, the method of forming the gate layer includes:

[0043] A connection layer is formed on an inner wall of the first gap, and a conductive layer is formed in the first gap including the connection layer; wherein the conductive layer is surrounded by the connection layer.

[0044] In some embodiments, the manufacturing method further comprises:

[0045] Before forming the first dielectric layer, a protective layer is formed at least on the top surface and the bottom surface of the gate layer; wherein the dielectric constant of the protective layer is greater than the dielectric constant of the first dielectric layer; and the protective layer is located between two adjacent first dielectric layers.

[0046] According to a third aspect of an embodiment of the present disclosure, a memory system is provided, including:

[0047] A memory device comprising one or more three-dimensional memories according to any one of claims 1 to 10; and

[0048] A memory controller is coupled to the memory device and controls the memory device.

[0049] The storage layer of the disclosed embodiment includes multiple storage sub-layers corresponding to the gate layer, and the storage sub-layers are electrically isolated from each other, thereby reducing the mutual migration of electrons between the storage sub-layers, reducing the offset of the threshold voltage, reducing the probability of failure of verification operations in the programming (writing) stage, reducing the probability of read failure, and improving the stability of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1a to Figure 1c is a schematic diagram of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present disclosure;

[0051] Figure 2a to Figure 2b is a schematic diagram of another method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present disclosure;

[0052] Figure 3 is a structural schematic diagram 1 of a three-dimensional memory according to an embodiment of the present disclosure;

[0053] Figure 4 is a second structural schematic diagram of a three-dimensional memory according to an embodiment of the present disclosure;

[0054] Figure 5 is a schematic diagram of a three-dimensional memory structure according to an embodiment of the present disclosure Figure 3 ;

[0055] Figure 6 is a schematic diagram of a three-dimensional memory structure according to an embodiment of the present disclosure Figure 4 ;

[0056] Figure 7 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0057] Figures 8a to 8l is a schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0058] Figures 9a to 9c is a schematic diagram of another method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0059] Fig.10 is a schematic diagram showing an exemplary system having a memory system according to an embodiment of the present disclosure;

[0060] Fig.11a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0061] Fig.11b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0062] Fig.12 is a schematic diagram showing an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0063] Fig.13 is a schematic diagram showing an exemplary memory device including a memory array and a peripheral circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] The technical solution of the present disclosure is further elaborated in detail below in conjunction with the accompanying drawings and specific embodiments of the specification.

[0065] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, but are not used to describe a specific order or sequence.

[0066] In the embodiments of the present disclosure, the term “A is in contact with B” includes the situation where A is in direct contact with B, or the situation where A is in indirect contact with B with other components interposed between A and B.

[0067] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. Furthermore, a layer may include multiple sublayers.

[0068] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning of “on” something with intervening features or layers.

[0069] It should be noted that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0070] In a three-dimensional NAND memory, a stacking structure in which a gate layer and a dielectric layer are alternately stacked is included, and a channel column runs through the stacking structure. Generally, the storage layer in a channel column is usually a continuous film layer structure, and the gate layer controls a section of the storage layer corresponding to it, while the part of the storage layer corresponding to the dielectric layer will not be controlled by the gate layer, that is, the electrons only need to be stored in a section of the storage layer corresponding to the gate layer. It can be understood that the storage layer is a continuous film layer structure, and the electrons of the storage layers corresponding to the adjacent gate layers will migrate to each other, resulting in leakage, causing the threshold voltage to shift, resulting in the verification operation of the programming (writing) stage to fail, or making it impossible to read correctly. When the number of stacked layers increases, the size of the channel column decreases, the morphology uniformity of the channel column is poor, the film thickness uniformity of the storage layer is also poor, and the storage layer's ability to bind or capture electrons decreases, which will increase the risk of leakage between the storage layers corresponding to the gate layer and reduce the stability of the three-dimensional memory. In this regard, an exemplary embodiment of the present disclosure proposes a method for manufacturing a three-dimensional memory, which interrupts a continuous memory layer by etching to form mutually electrically isolated memory sublayers, each memory sublayer corresponding to a gate layer, thereby reducing mutual leakage between memory sublayers and improving the stability of the three-dimensional memory. Some steps of the manufacturing method may include:

[0071] Reference Figure 1a As shown, a stacked structure is formed, the stacked structure includes alternately stacked dielectric layers 111 and sacrificial layers 112; the stacked structure is etched to form a channel hole 13 that penetrates the stacked structure. The penetration direction of the channel hole 13 can be the z direction in the figure, or a direction with a certain angle with the z direction. The stacked structure can be formed on a substrate or a semiconductor layer, and the substrate can be thinned, and a punching and wiring process is performed on the opposite surface of the substrate away from the stacked structure, which is not shown in the drawings of the embodiments of the present disclosure.

[0072] Reference Figure 1b As shown, through Figure 1a The channel hole 13 in the sacrificial layer 112 is partially etched along the x direction to reduce the size of the sacrificial layer 112 in the x direction to form an opening 14 between two adjacent dielectric layers 111. Exemplarily, the etching process may include but is not limited to dry etching, wet etching or any combination thereof. In the etching process for forming the opening 14, the etching rate of the dielectric layer 111 is low or substantially not etched, and the etching rate of the sacrificial layer 112 is high, thereby facilitating the formation of the opening 14 and the protection of the dielectric layer 111. Exemplarily, the constituent materials of the dielectric layer 111 may include but are not limited to insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The constituent materials of the sacrificial layer 112 may include but are not limited to materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and silicon. The constituent materials of the sacrificial layer 112 and the dielectric layer 111 are different in order to improve the etching selectivity. The dielectric layer 111 may be silicon oxide or aluminum oxide, and the sacrificial layer 112 may be silicon nitride.

[0073] Exemplarily, the deposition process for forming the dielectric layer 111 and the sacrificial layer 112 may include, but is not limited to, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0074] Reference Figure 1c As shown, in Figure 1b A barrier layer 131 is formed on the sidewall of the middle opening 14, and the barrier layer 131 does not fill the opening 14. The remaining space of the opening 14 is filled with an electron-trapping material to form a storage sublayer 133. The surface of the storage sublayer 133 leaking out of the channel hole 13 along the x direction is flush with the surface of the barrier layer 131 leaking out of the channel hole 13 along the x direction. Then, a tunneling layer 134 and a channel layer 135 covering the storage sublayer 133 and the barrier layer 131 are sequentially formed along the sidewall of the channel hole 13. The remaining space of the channel hole 13 is filled with a dielectric material to form a core 136, thereby forming a three-dimensional memory 100. The core 136 can be used to support the channel pillar 130, and the core 136 can have an air gap to reduce stress concentration. Exemplarily, the material combination of the barrier layer 131-storage sublayer 133-tunneling layer 134 can be silicon oxide-silicon nitride-silicon oxide, and the channel layer 135 can be a semiconductor material, such as polysilicon.

[0075] In some embodiments, the sacrificial layer 112 is replaced with a conductive material to form Figure 1c The gate layer 121. The constituent materials of the gate layer 121 may include, but are not limited to, conductive materials such as tungsten, platinum, gold, silver, chromium, titanium, nickel, copper, aluminum or polysilicon.

[0076] like Figure 1cAs shown, the storage sublayer 133 corresponds to the gate layer 121 in the x direction. The gate layer 121, as the word line of the memory, controls the electrons in the channel layer 135 to enter the storage sublayer 133 by applying voltage to complete the writing of data. The storage sublayer 133 captures electrons so that they will not leak in the power-off state to save data. Two adjacent storage sublayers 133 are electrically isolated by the blocking layer 131 and the dielectric layer 111 in the z direction. Compared with the continuous storage layer 132, the electrons in the storage layer 132 corresponding to the gate layer 121 can be reduced from migrating to the storage layer 132 corresponding to the dielectric layer 111, thereby reducing the offset of the threshold voltage, reducing the probability of verification operation failure in the programming (writing) stage, and reducing the probability of read failure.

[0077] In some specific embodiments, Figure 1b After the opening 14 is formed, the size (diameter) of the channel hole 13 in the x direction will increase, thereby reducing the integration density of the final channel column 130 and reducing the storage capacity.

[0078] According to some aspects of the embodiments of the present disclosure, another method for manufacturing a three-dimensional memory is provided, the method comprising:

[0079] Reference Figure 2a As shown, a stacked structure is formed, the stacked structure includes alternately stacked dielectric material layers 113 and gate layers 121; a channel column 130 is formed that penetrates the stacked structure, and along the x direction (radial direction of the channel column 130), the channel column 130 sequentially includes: a barrier layer 131, a storage layer 132, a tunneling layer 134, a channel layer 135, and a core 136; the barrier layer 131, the storage layer 132, the tunneling layer 134, and the channel layer 135 are arranged around the core 136. Here, the manufacturing method of the channel hole 13, the formation of the channel column 130 in the channel hole 13, and the replacement of the sacrificial layer 112 with a conductive material to form a gate is omitted in the drawings.

[0080] Reference Figure 2b As shown, the dielectric material layer 113 between two adjacent gate layers 121 is etched away to form a gap between the adjacent gate layers 121, and the barrier layer 131 and the storage layer 132 are continuously etched along the x direction based on the gap to expand the size of the gap in the x direction. At this time, the gap between the two adjacent gate layers 121 may only penetrate the barrier layer 131 and the storage layer 132, and / or at least penetrate a portion of the thickness of the tunnel layer 134. The gap stops at the channel layer 135 and does not extend into the channel layer 135. The gap interrupts the storage layer 132 in the z direction into non-continuous storage sublayers 133, and one storage sublayer 133 corresponds to one gate layer 121 in the x direction. Subsequently, the gap is filled with a dielectric material to isolate the two adjacent gate layers 121. This manufacturing method does not cause the diameter of the channel pillar 130 to expand.

[0081] In some specific embodiments, in combination Figure 2b As shown, referring to the enlarged view of a partial area of ​​the circled channel pillar 130 and the gate layer 121, when etching the dielectric material layer 113, the etching time increases accordingly due to the increase in the etching amount, which will cause etching to the barrier layer 131, resulting in the removal of a portion of the barrier layer 131 corresponding to the gate layer 121, and a gap appears between the gate layer 121 and the barrier layer 131, resulting in the collapse of the stacking structure, thereby reducing the manufacturing yield.

[0082] In view of this, some aspects of the embodiments of the present disclosure provide a three-dimensional memory 200, referring to Figure 3 As shown, the three-dimensional memory 200 includes:

[0083] A stacked structure, comprising alternately stacked gate layers 220 and first dielectric layers 212;

[0084] The channel pillar 230 penetrates the stack structure along a first direction; along a second direction perpendicular to the first direction, the channel pillar 230 includes: a blocking layer 231, a storage layer 232, a tunneling layer 233 and a channel layer 234 arranged in sequence; wherein the storage layer 232 includes a plurality of storage sublayers 2321 corresponding to the gate layer 220, and the storage sublayers 2321 are electrically isolated from each other.

[0085] In the embodiment of the present disclosure, the first direction in which the channel pillar 230 penetrates the stack structure may be the z direction, or a direction having a certain angle with the z direction, and the second direction is perpendicular to the first direction, and may be the x direction.

[0086] The channel pillar 230 may include a core 235, and along the radial direction (x direction) of the channel pillar 230, from the outside to the inside, a barrier layer 231 surrounding the core 235, a storage layer 232, a tunneling layer 233, and a channel layer 234. Exemplarily, the barrier layer 231 and the tunneling layer 233 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide (high dielectric material). The storage layer 232 includes an electron-trapping material such as silicon nitride. The channel layer 234 may include a semiconductor material, and ion implantation may be performed to perform element doping. Exemplarily, the combination of the barrier layer 231-storage layer 232-tunneling layer 233-channel layer 234 of the embodiment of the present disclosure may be: silicon oxide-silicon nitride-silicon oxide-polysilicon. The barrier layer 231 may include one material layer, or may include a multilayer material layer of multiple material layers. The embodiment of the present disclosure takes one channel pillar 230 as an example for description, and may include a plurality of channel pillars 230 , without limiting the number and array arrangement of the channel pillars 230 .

[0087] The storage layer 232 of the disclosed embodiment includes storage sub-layers 2321 that are electrically isolated from each other. The storage layer 232 is isolated into multiple isolation sub-layers by insulating materials. Each storage sub-layer 2321 corresponds to each gate layer 220 in the x-direction. The gate layer 220 serves as a word line of the three-dimensional memory 200. One storage sub-layer 2321 corresponds to one storage unit. The gate layer 220 can control the amount of electrons captured by the corresponding storage sub-layer 2321 to achieve programming of different data states. Different amounts of electrons captured by the storage sub-layer 2321 correspond to different threshold voltages and to different on-voltages on the gate layer 220, thereby corresponding to different read voltages and different programming verification voltages.

[0088] In some embodiments, reference Figure 3 As shown, the first dielectric layer 212 between two adjacent gate layers 220 extends toward the channel layer 234 along the x direction, penetrating the storage layer 232 to divide the storage layer 232 into a plurality of storage sub-layers 2321; or the storage layer 232 itself includes an insulating layer located between adjacent storage sub-layers 2321, as shown in FIG. Figures 4 to 6 The second dielectric layer 2322 shown electrically isolates the storage sublayer 2321, thereby reducing the mutual migration of electrons between the storage sublayers 2321, reducing the offset of the threshold voltage, reducing the probability of verification operation failure in the programming (writing) stage, reducing the probability of read failure, and improving device stability.

[0089] In some embodiments, reference Figure 3 As shown, the first dielectric layer 212 at least penetrates the barrier layer 231 and the storage layer 232 along the second direction, and the storage layer 232 is divided into a plurality of storage sub-layers 2321 by the first dielectric layer 212 .

[0090] In the channel pillar 230, the storage sublayer 2321 plays a role in trapping charges, and the first dielectric layer 212 can sequentially penetrate the blocking layer 231 and the storage layer 232 along the x direction, dividing the storage layer 232 into a plurality of mutually electrically isolated storage sublayers 2321. After penetrating the storage layer 232, the first dielectric layer 212 can continue to extend toward the channel layer 234, penetrate part or all of the tunneling layer 233, and stop at the surface of the channel layer 234, while still maintaining the good morphology of the tunneling layer 233 portion corresponding to the gate layer 220 and the channel layer 234. In the embodiment of the present disclosure, the first dielectric layer 212 can extend to any position of the tunneling layer 233 on the premise of completely penetrating the storage layer 232, thereby expanding the manufacturing process window and reducing the manufacturing cost.

[0091] In some embodiments, the barrier layer 231 may include multiple film layers, such as Figure 3The first blocking sublayer 2311 and the second blocking sublayer 2312 are shown, and the second blocking sublayer 2312 is located between the first blocking sublayer 2311 and the storage sublayer 2321. The first dielectric layer 212 penetrates the first blocking sublayer 2311, the second blocking sublayer 2312 and the storage layer 232, and divides the storage layer 232 into a plurality of storage sublayers 2321. The dielectric constant of the first blocking sublayer 2311 is greater than the dielectric constant of the second blocking sublayer 2312, and the thickness of the blocking layer 231 in the x direction can be reduced while improving the insulation performance of the blocking layer 231. Figure 3 The first dielectric layer 212 penetrates the first blocking sublayer 2311 , the second blocking sublayer 2312 , the storage layer 232 and the tunneling layer 233 , and stops at a surface of the channel layer 234 close to the tunneling layer 233 in the x direction.

[0092] In some embodiments of the method for manufacturing the three-dimensional memory 200, in the region between the two gate layers 220, at least the barrier layer 231 and the storage layer 232 are etched through to form a storage sublayer 2321, and the first barrier sublayer 2311 is used as a stop layer or an etching rate adjustment layer to reduce the etching of the barrier layer 231 corresponding to the gate layer 220, thereby reducing Figure 2b There is a risk of a gap between the middle gate layer 220 and the barrier layer 231 causing structure collapse.

[0093] Exemplarily, the constituent materials of the first dielectric layer 212 include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In some specific embodiments, when the constituent materials of the first dielectric layer 212, the barrier layer 231, and the tunneling layer 233 are the same, that is, silicon oxide, there may be no obvious boundary between the first dielectric layer 212, the barrier layer 231, and the tunneling layer 233. When the barrier layer 231 is a multi-layer film structure, for example, a multi-layer film structure composed of high dielectric materials (HK materials) such as silicon oxide and aluminum oxide, the silicon oxide layer (e.g., Figure 3 There may be no obvious physical boundary between the second blocking sublayer 2312 in the three-dimensional memory 200 and the tunneling layer 233. When the blocking layer 231 is a single film layer, the blocking layer 231 may include hk material. When the first dielectric layer 212 is a material different from silicon oxide such as silicon or silicon oxynitride, the blocking layer 231 includes silicon oxide and hk material, the tunneling layer 233 is silicon oxide, and the storage layer 232 is silicon nitride, there may be a physical boundary between the film layers composed of different materials. It can be understood that whether the physical boundary exists or is obvious can more clearly explain the structure of the three-dimensional memory 200, and does not affect the electrical function realization of components such as the channel pillar 230 and the gate layer 220.

[0094] In some embodiments, reference Figures 4 to 6As shown, in the first direction, the storage layer 232 includes a second dielectric layer 2322 located between two adjacent storage sub-layers 2321 ; in the second direction, the blocking layer 231 is located between the first dielectric layer 212 and the second dielectric layer 2322 .

[0095] Different from Figure 3 The storage layer 232 structure shown as being penetrated into a discontinuous structure, the storage layer 232 of the disclosed embodiment is a continuous structure, and the storage layer 232 includes a plurality of storage sublayers 2321 and a second dielectric layer 2322 between adjacent storage sublayers 2321. In some embodiments, the second dielectric layer 2322 may be conformal to the storage sublayer 2321, and two oppositely disposed surfaces of the second dielectric layer 2322 in the x-direction may be flush with two oppositely disposed surfaces of the storage sublayer 2321 in the x-direction, respectively, so that the second dielectric layer 2322 completely penetrates the storage layer 232 in the x-direction, reducing electron migration between the storage sublayers 2321. For example, the surface of the second dielectric layer 2322 in the positive x-direction may be flush with the surface of the storage sublayer 2321 in the positive x-direction.

[0096] In some embodiments of the method for manufacturing the three-dimensional memory 200, the second dielectric layer 2322 is formed by oxidizing a portion of the storage layer 232 corresponding to the first dielectric layer 212, that is, by oxidizing a portion of the storage layer 232 corresponding to the region between two adjacent gate layers 220, and the unoxidized portion of the storage layer 232 forms a storage sublayer 2321, thereby Figures 4 to 6 The storage layer 232 including the second dielectric layer 2322 is a continuous structure.

[0097] In some embodiments, the storage layer 232 includes silicon nitride, and the second dielectric layer 2322 is silicon oxide or silicon oxynitride oxidized from silicon nitride. In other embodiments, the storage layer 232 may be divided into storage sublayers 2321 by element doping a portion of the storage layer 232 corresponding to the region between the two gate layers 220 to form an insulating second dielectric layer 2322. The doping process may include ion implantation or diffusion, and the doping elements may include, but are not limited to, oxygen, carbon, etc.

[0098] In some embodiments, the second dielectric layer 2322 formed by oxidation or doping extends in the z direction due to diffusion of elements or heat treatment annealing, so that a portion of the second dielectric layer 2322 corresponds to the gate layer 220, that is, the orthographic projection of the gate layer 220 in the x direction overlaps with the orthographic projection of the second dielectric layer 2322 in the x direction. The boundary where the second dielectric layer 2322 contacts the storage sublayer 2321 can be a straight line as shown in the figure, or a curve or other irregular shapes.

[0099] In some specific embodiments, when the first dielectric layer 212, the second dielectric layer 2322, the barrier layer 231, and the tunneling layer 233 are made of the same material, that is, silicon oxide, there may be no obvious boundary between the first dielectric layer 212, the barrier layer 231, the second dielectric layer 2322, and the tunneling layer 233. When the barrier layer 231 is a multi-layer film structure, for example, a multi-layer film structure composed of a high dielectric material (hk material) such as silicon oxide and aluminum oxide, the silicon oxide layer (e.g., Figure 4 There may be no obvious physical boundary between the second blocking sublayer 2312 in the second dielectric layer 2322 and the tunneling layer 233.

[0100] In some embodiments, the first dielectric layer 212 penetrates at least a portion of the thickness of the barrier layer 231 along the second direction.

[0101] In some embodiments, reference Figure 4 As shown, the barrier layer 231 is a continuous film layer in the z direction, and the barrier layer 231 is located between the first dielectric layer 212 and the second dielectric layer 2322 in the x direction; wherein the barrier layer 231 and the second dielectric layer 2322 extend along the z direction, and the first dielectric layer 212 extends along the x direction. In some embodiments, the first dielectric layer 212 may extend into the barrier layer 231 or penetrate the entire barrier layer 231, and the first dielectric layer 212 stops at the surface of the second dielectric layer 2322 without extending into the second dielectric layer 2322 (not shown in the figure).

[0102] In some embodiments, reference Figure 4 As shown, the blocking layer 231 includes a first blocking sublayer 2311 and a second blocking sublayer 2312, wherein the second blocking sublayer 2312 is located between the first blocking sublayer 2311 and the second dielectric layer 2322; wherein the dielectric constant of the first blocking sublayer 2311 is greater than the dielectric constant of the second blocking sublayer 2312; at this time, the first dielectric layer 212 does not extend into the first blocking sublayer 2311 and stops at the surface of the first blocking sublayer. In some other embodiments, the first dielectric layer 212 penetrates at least a portion of the thickness of the first blocking sublayer 2311 along the second direction, and the first dielectric layer 212 extends into the first blocking sublayer 2311 or penetrates the first blocking sublayer 2311, or even penetrates the second blocking sublayer 2312 and stops at the surface of the second dielectric layer 2322. Figure 5 In the embodiment, the first dielectric layer 212 penetrates through the first blocking sub-layer 2311 and stops on a surface of the second blocking sub-layer 2312 close to the first blocking sub-layer 2311 in the x direction.

[0103] The first dielectric layer 212 of the embodiment of the present disclosure can extend in the entire blocking layer 231 along the x-direction. The first dielectric layer 212 stops at the side surface of the second dielectric layer 2322 close to the blocking layer 231. The first dielectric layer 212 does not reduce the dimensions of the storage sublayer 2321 and the second dielectric layer 2322 in the z-direction and the x-direction. On the premise of maintaining the good morphology of the storage sublayer 2321 and the second dielectric layer 2322, it is also beneficial to improve the manufacturing process window of the first dielectric layer 212 and other structures, which is beneficial to reducing the manufacturing cost.

[0104] In some embodiments, in combination Figure 4 and Figure 5 As shown, in the first direction, the second dielectric layer 2322 is located between the two gate layers 220 .

[0105] In the z direction, the second dielectric layer 2322 is located between two adjacent gate layers 220, and the orthographic projection of the gate layer 220 in the z direction may not overlap with the orthographic projection of the second dielectric layer 2322 in the z direction. The orthographic projection of the second dielectric layer 2322 in the x direction falls between the orthographic projections of the two adjacent gate layers 220 in the x direction. The orthographic projection of the second dielectric layer 2322 in the x direction may not overlap with the orthographic projection of the gate layer 220 in the x direction or may have a small overlap. The size of the overlapping part in the z direction may account for 0 to 10% of the size of the orthographic projection of the entire gate layer 220 in the z direction, or less.

[0106] In some embodiments, in the z direction, the size of the storage sublayer 2321 is greater than or equal to the size of the gate layer 220. In some embodiments, the orthographic projection of the gate layer 220 in the x direction falls within the orthographic projection of the storage sublayer 2321 in the x direction. While increasing the size of the storage sublayer 2321 to increase the electron capture performance and the amount of electron capture, the size of the storage sublayer 2321 corresponding to the gate layer 220 in the x direction is also increased, so that all parts of the gate layer 220 have corresponding storage sublayers 2321, thereby increasing the voltage load of the gate layer 220 and reducing the tip discharge between the gate layers 220. Figures 3 to 5 As an example, the size of the storage sublayer 2321 in the z direction is equal to the size of the gate layer 220 in the z direction, and the orthographic projection of the gate layer 220 in the x direction falls exactly within the orthographic projection of the storage sublayer 2321 in the x direction. In some other specific embodiments, the size of the storage sublayer 2321 in the z direction may be greater than the size of the gate layer 220 in the z direction.

[0107] The gate layer 220 of the embodiment of the present disclosure may be a single conductive structure or a conductive structure including a connecting layer 221 . The connecting layer 221 is used to increase the adhesion between the gate layer 220 and the first dielectric layer 212 , reduce void defects, and improve device yield.

[0108] In some embodiments, in combination Figures 3 to 5 As shown, the gate layer 220 includes:

[0109] A connecting layer 221 and a conductive layer 222 ; wherein the connecting layer 221 surrounds the conductive layer 222 ; and the connecting layer 221 is located between two adjacent first dielectric layers 212 .

[0110] Exemplarily, the constituent materials of the conductive layer 222 may include: conductive materials such as tungsten, platinum, gold, silver, chromium, titanium, nickel, copper, aluminum or polysilicon. The constituent materials of the connection layer 221 may include, but are not limited to: metal nitrides or metal silicides. Taking the conductive layer 222 as tungsten and the connection layer 221 as titanium nitride as an example, the connection layer 221 may surround and contact the six surfaces outside the conductive layer 222, and the six surfaces may include the top and bottom surfaces in the z direction, and four side surfaces parallel to the z direction. Titanium nitride reduces the surface tension between tungsten and the first dielectric layer 212 (silicon oxide), improves the adhesion, and titanium nitride has a lower resistance, which can maintain the good conductivity of the gate layer 220 while reducing the void defects.

[0111] In some embodiments, reference Figure 6 As shown, the three-dimensional memory 200 further includes:

[0112] The protective layer 241 covers at least the top and bottom surfaces of the gate layer 220 in the first direction, and the protective layer 241 is located between two adjacent first dielectric layers 212 ; the dielectric constant of the protective layer 241 is greater than the dielectric constant of the first dielectric layer 212 .

[0113] The protective layer 241 may include an hk material having a dielectric constant greater than that of the first dielectric layer 212, such as aluminum oxide. The protective layer 241 may cover the top and bottom surfaces of the gate layer 220 in the z direction. The protective layer 241 is located between two adjacent first dielectric layers 212 and in contact with the first dielectric layer 212 to increase the electrical isolation performance between the two adjacent gate layers 220, reduce the mutual leakage between the two adjacent gate layers 220, and improve the stability of the device. In some other embodiments, the protective layer 241 may cover the top and bottom surfaces of the gate layer 220 in the z direction, and also cover the side surfaces of the gate layer 220 parallel to the z direction. In some embodiments, the constituent materials of the protective layer 241 and the first blocking sublayer 2311 may be the same or different. Figure 6 The protective layer 241 and the first blocking sublayer 2311 shown in the example may both be aluminum oxide, and the protective layer 241 and the first blocking sublayer 2311 may not have a clear physical boundary.

[0114] According to some aspects of the embodiments of the present disclosure, Figure 7 A schematic diagram of a manufacturing method of a three-dimensional memory 200 is provided, combining Figure 7The production method may include:

[0115] Reference Figure 8a As shown, a stacked structure is formed, the stacked structure includes alternately stacked dielectric material layers 211 and sacrificial layers 213; a channel hole 23 is formed that penetrates the stacked structure along a first direction;

[0116] Reference Figure 8b As shown, a portion of the dielectric material layer 211 is etched along a second direction perpendicular to the first direction through the channel hole 23 to form an opening 14 between two adjacent sacrificial layers 213;

[0117] Reference Figure 8c As shown, a first stop layer 214 is formed at one end of the sacrificial layer 213 exposed from the sidewall of the channel hole 23;

[0118] Reference Figure 8d to Figure 8e As shown, a second stop layer 216 is formed in the opening 14;

[0119] Reference Figure 8f As shown, a barrier layer 231, a storage layer 232, a tunnel layer 233 and a channel layer 234 are sequentially formed on the first stop layer 214 and the second stop layer 216;

[0120] Reference Figure 8g to Figure 8h As shown, the sacrificial layer 213 and the first stop layer 214 are removed to form a first gap 217 between adjacent dielectric material layers 211; Figure 8i As shown, a gate layer 220 is formed in the first gap 217;

[0121] Reference Figure 8j to Figure 8k As shown, the dielectric material layer 211 and the second stop layer 216 are removed to form a second gap 218 between adjacent gate layers 220;

[0122] Reference Figure 8l As shown, the storage layer 232 is separated by the second gap 218 to form a plurality of storage sub-layers 2321; wherein the storage sub-layers 2321 correspond to the gate layer 220, and the storage sub-layers 2321 are electrically isolated from each other;

[0123] exist Figure 8l The first dielectric layer 212 is formed in the second gap 218 as shown, forming Figure 3 A three-dimensional memory 200 is shown.

[0124] Specifically, in some embodiments, Figure 8aThe stacked structure can be formed on a substrate or on a semiconductor layer. The back of the substrate or the semiconductor layer can be thinned, and a back wiring process can be performed on the back of the substrate or the semiconductor layer to lead out the electrical signal of the three-dimensional memory 200. Taking the substrate as an example, the substrate has two planes arranged opposite to each other in the z direction, namely the front side and the back side, and the stacked structure is formed on the front side of the substrate. The constituent materials of the substrate and the semiconductor layer may include but are not limited to: silicon-based semiconductor materials, germanium-based semiconductor materials or other semiconductor materials known in the field, and the substrate and the semiconductor layer can be doped with n-type or p-type.

[0125] Reference Figure 8a As shown, the penetration direction of the channel hole 23 can be the z direction or a direction with a certain angle with the z direction. The constituent materials of the dielectric material layer 211 can include but are not limited to: insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The constituent materials of the sacrificial layer 213 can include but are not limited to: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon, and other materials. Figure 8b As shown, the sacrificial layer 213 and the dielectric material layer 211 are made of different materials, which can improve the selectivity of the etching process when forming the opening 14. In this etching process, the dielectric material layer 211 has a relatively large etching rate, and the sacrificial layer 213 has a very small etching rate or is substantially not etched, thereby reducing over-etching of the sacrificial layer 213 while forming the opening 14. Exemplarily, the dielectric material layer 211 can be silicon oxide, silicon or aluminum oxide, and the sacrificial layer 213 can be silicon nitride. In the etching process for forming the opening 14, non-plasma gas etching or wet etching can be selected, and the channel hole 23 is used to remove part of the dielectric material layer 211 along the x direction, thereby reducing the size of the dielectric material layer 211 in the x direction. This x direction can include a positive x direction and a negative x direction.

[0126] The embodiment of the present disclosure takes one channel hole 23 as an example for explanation, and may include a plurality of channel holes 23 , without limiting the number and array arrangement of the channel holes 23 .

[0127] Reference Figure 8c As shown, the first stop layer 214 in the embodiment of the present disclosure covers the end of the sacrificial layer 213 exposed from the channel hole 23, and the first stop layer 214 may not cover the dielectric material layer 211. The method of forming the first stop layer 214 may include deposition, and during the deposition process, a process gas with affinity to the sacrificial layer 213 is selected to additionally form the first stop layer 214 on the sacrificial layer 213 by selective deposition. Alternatively, the sacrificial layer 213 may be oxidized or reduced so that a portion of the sacrificial layer 213 participates in the film forming reaction, thereby forming a portion of the sacrificial layer 213 into the first stop layer 214.

[0128] In some embodiments, reference Figure 8cAs shown, the method of forming the first stop layer 214 includes:

[0129] One end of the oxidized sacrificial layer 213 is exposed from the sidewall of the channel hole 23 , and a portion of the sacrificial layer 213 forms a first stop layer 214 .

[0130] Exemplarily, the constituent material of the sacrificial layer 213 may include silicon or silicon nitride, and an oxidant is introduced into the channel hole 23 to oxidize a portion of the sacrificial layer 213 into silicon oxide, wherein the silicon nitride may also be oxidized into silicon oxynitride. The dielectric material layer 211 in this embodiment is a material that is difficult to oxidize, such as silicon oxide, to prevent the dielectric layer from being oxidized. Exemplarily, the oxidant may include a gaseous oxidant such as oxygen, or a liquid oxidant such as hydrogen peroxide or nitric acid. Figure 8g As shown, the first stop layer 214 can be used as an etching stop layer when etching to remove the sacrificial layer 213, thereby reducing damage to the barrier layer 231 caused by etching, reducing the collapse of the stacked structure, and improving the yield.

[0131] In some embodiments, the method of forming the second stop layer 216 includes:

[0132] Reference Figure 8d As shown, a second stop material layer 215 is formed in the opening 14 and on the first stop layer 214; Figure 8e As shown, a portion of the second stop layer 216 on the first stop layer 214 is etched away to form the second stop layer 216 .

[0133] In this embodiment, the first formed second stop material layer 215 fills the opening 14 not covered by the first stop layer 214 and covers the first stop layer 214, and then the part of the second stop material layer 215 covering the first stop layer 214 is removed by etching, and the remaining second stop material layer 215 is used as the second stop layer 216 to fill the opening 14. The surface of the second stop layer 216 and the first stop layer 214 in the x direction can be flush, providing a better landing surface for the subsequent formation of the barrier layer 231, which is conducive to improving the morphological uniformity of the barrier layer 231 and other film layers. The materials of the second stop layer 216, the first stop layer 214, the dielectric material layer 211 and the sacrificial layer 213 can be different, and there is a large etching difference in different etching processes, so that when removing a certain film layer, other film layers are not damaged, the stacked structure is prevented from collapsing, and the manufacturing yield is improved. For example, the first stop layer 214 and the dielectric material layer 211 of the disclosed embodiment may be silicon oxide, the sacrificial layer 213 may be silicon nitride, and the second stop layer 216 may be single crystal silicon, polycrystalline silicon or amorphous silicon, and the crystal form of silicon is not limited here. Figure 8j As shown, the second stop layer 216 can be used as an etching stop layer when etching away the dielectric material layer 211, thereby reducing damage to the barrier layer 231 caused by etching, reducing the collapse of the stacked structure, and improving the yield.

[0134] In some embodiments, reference Figure 8f As shown, after the channel layer 234 is formed, the channel layer 234 does not fill the channel hole 23, and the remaining channel hole 23 space is filled with an insulating material (e.g., silicon oxide) to form a core 235 to support the channel pillar 230. The core 235 may have a gap to reduce stress concentration of the core 235 and reduce the bending of the memory.

[0135] In some embodiments, reference Figure 8f As shown, the method of forming the barrier layer 231 includes:

[0136] A first blocking sublayer 2311 and a second blocking sublayer 2312 are sequentially formed on the first stop layer 214 and the second stop layer 216 ; wherein the dielectric constant of the first blocking sublayer 2311 is greater than the dielectric constant of the second blocking sublayer 2312 .

[0137] The constituent material of the second blocking sublayer 2312 may include silicon oxide, and the constituent material of the first blocking sublayer 2311 may include hk materials, such as aluminum oxide. The first blocking sublayer 2311 may be used as an etching stop layer when etching and removing the first stop layer 214 and the second stop layer 216, thereby reducing the collapse of the stacked structure and improving the yield. In addition, the first blocking sublayer 2311 has a higher dielectric constant and can have a smaller film thickness under the premise of having the same insulation performance, thereby reducing the total thickness of the blocking layer 231, improving the integration density of the channel pillar 230, and improving the storage capacity.

[0138] Reference Figure 8g As shown, in the etching process for removing the sacrificial layer 213, the first stop layer 214 has a lower etching rate or is basically not etched compared to the sacrificial layer 213, and as the etching stop layer of the etching process, it prevents the barrier layer 231 and the second stop layer 216 from being etched and damaged during the etching process with a large amount of etching, and reduces the etching of the portion of the barrier layer 231 (or, the first barrier sublayer 2311) in contact with the second stop layer 216 to produce gaps, thereby reducing the collapse of the stacked structure and improving the manufacturing yield.

[0139] Reference Figure 8h As shown, when the first stop layer 214 is removed by etching, the thickness of the first stop layer 214 in the x direction is much smaller than the size of the sacrificial layer 213 in the x direction, the etching amount of the first stop layer 214 is small, the etching time is easier to control, and even the barrier layer 231 of a single film layer structure has a small risk of being damaged by over-etching. The embodiment of the present disclosure further provides a first barrier sublayer 2311, which can be used as an etching stop layer when removing the first stop layer 214, so as to avoid the collapse of the stacked structure due to over-etching of the barrier layer 231, thereby improving the yield.

[0140] exist Figure 8h The first gap 217 is filled with a conductive material to form a gate layer 220, which serves as a word line of the three-dimensional memory 200. The gate layer 220 may be a single-layer conductive structure filling the first gap 217, or may include a multi-layer structure of a conductive layer 222.

[0141] In some embodiments, reference Figure 8i As shown, the method of forming the gate layer 220 includes:

[0142] exist Figure 8h A connection layer 221 is formed on the inner wall of the first gap 217 , and a conductive layer 222 is formed in the first gap 217 including the connection layer 221 ; wherein the conductive layer 222 is surrounded by the connection layer 221 .

[0143] The constituent materials of the connection layer 221 may include, but are not limited to, metal nitrides or metal silicides. The constituent materials of the conductive layer 222 may include conductive materials such as tungsten, platinum, gold, silver, chromium, titanium, nickel, copper, aluminum or polysilicon. The connection layer 221 may surround and contact six surfaces outside the conductive layer 222, and the six surfaces may include the top and bottom surfaces in the z direction, and four side surfaces parallel to the z direction. Taking the conductive layer 222 as tungsten and the connection layer 221 as titanium nitride as an example, titanium nitride can reduce the surface tension between tungsten and the first dielectric layer 212 (silicon oxide), improve the adhesion, and titanium nitride has a lower resistance, while reducing the gap defects, it can also maintain the good conductivity of the gate layer 220. The process of forming the conductive layer 222 may include chemical deposition and physical deposition.

[0144] Reference Figure 8j As shown, when etching away the dielectric material layer 211, the second stop layer 216 can be used as an etching stop layer to reduce the damage to the barrier layer 231 during the etching process with a large amount of etching, reduce the collapse of the stacked structure, and improve the yield. Figure 8k As shown, when the second stop layer 216 is etched away to form the second gap 218, the etching amount of the second stop layer 216 is much smaller than the etching amount of the dielectric material layer 211, and the etching time is easier to control. Even the barrier layer 231 of a single film layer structure has a lower risk of being damaged by over-etching. The first barrier sublayer 2311 of the disclosed embodiment can also be used as an etching stop layer when removing the second stop layer 216, so as to avoid the collapse of the stacked structure due to over-etching of the barrier layer 231, thereby improving the yield.

[0145] In some embodiments, reference Figure 8l As shown, the storage layer 232 is separated by the second gap 218 to form a plurality of storage sub-layers 2321, including:

[0146] The blocking layer 231 and the storage layer 232 are etched so that the second gap 218 at least penetrates the blocking layer 231 and the storage layer 232 in the second direction (x direction) to form a storage sub-layer 2321 .

[0147] exist Figure 8k On the basis of the second gap 218, the barrier layer 231 and the storage layer 232 are etched along the x direction to increase the size of the second gap 218 in the x direction. The second gap 218 may only penetrate the barrier layer 231 and the storage layer 232, and stop at the surface of the tunnel layer 233 after the storage layer 232 is separated to form a storage sublayer 2321. Alternatively, after the second gap 218 penetrates the storage layer 232, it continues to extend toward the channel layer 234 and penetrates part or all of the tunnel layer 233. For example Figure 8l As shown, the second gap 218 penetrates the barrier layer 231, the storage layer 232 and the tunnel layer 233, and stops on the surface of the channel layer 234 near the tunnel layer 233. On the basis of penetrating the storage layer 232 and not damaging the channel layer 234, the thickness of the second gap 218 penetrating the tunnel layer 233 is not limited, which is conducive to expanding the etching process window.

[0148] exist Figure 8l The second gap 218 is filled with an insulating material to form a first dielectric layer 212, forming Figure 3 A three-dimensional memory 200 is shown.

[0149] In some embodiments, reference Figure 8k As shown, the second gap 218 exposes the first blocking sublayer 2311, and / or the second gap 218 penetrates at least a portion of the thickness of the first blocking sublayer 2311 in the second direction (x direction); Figure 9a As shown, the storage layer 232 is separated by the second gap 218 to form a plurality of storage sub-layers 2321, including:

[0150] A portion of the storage layer 232 is oxidized to form a second dielectric layer 2322 ; wherein the second dielectric layer 2322 divides the storage layer 232 into a plurality of storage sub-layers 2321 .

[0151] like Figure 9aAs shown, the second gap 218 exposes the first blocking sublayer 2311, and the second gap 218 does not penetrate the first blocking sublayer 2311. An oxidant is introduced into the second gap 218, and the oxidant can pass through the first blocking sublayer 2311 and the second blocking sublayer 2312 along the x direction to oxidize the storage layer 232, and oxidize a portion of the storage layer 232 into a second dielectric layer 2322. The storage layer 232 can be silicon nitride, and the second dielectric layer 2322 is silicon oxide or silicon oxynitride formed by oxidation of silicon nitride; wherein, a longer oxidation time can form silicon oxide, and a shorter oxidation time can form silicon oxynitride. In some embodiments, the second dielectric layer 2322 may include a mixed material of silicon oxide and silicon oxynitride. Due to the diffusion of the oxidant, the second dielectric layer 2322 may extend along the z direction, leaving the storage sublayer 2321 corresponding to the gate layer 220, and the junction between the second dielectric layer 2322 and the storage sublayer 2321 may be Figure 9a The straight line extending along the z direction shown may also be a curve or other irregular shapes. For example, the oxidant in the disclosed embodiment may include a gaseous oxidant such as oxygen, which is conducive to diffusion. During the oxidation process, pressure may be applied to allow the oxidant to pass through the barrier layer 231 to oxidize the storage layer 232. Figure 9a The first dielectric layer 212 is formed in the second gap 218 as shown, forming Figure 4 A three-dimensional memory 200 is shown.

[0152] In some embodiments, before oxidizing the storage layer 232, the second gap 218 that only exposes the first blocking sublayer 2311 may be etched along the x direction, so that the second gap 218 penetrates part of the first blocking sublayer 2311, or penetrates part of the second blocking sublayer 2312, or penetrates the second blocking sublayer 2312 completely and stops at the surface of the storage layer 232, thereby reducing the difficulty of oxidation. After the second gap 218 penetrates the second blocking sublayer 2312 and exposes the storage layer 232, a gaseous oxidant or a liquid oxidant such as hydrogen peroxide or nitric acid may be used to oxidize the storage layer 232. Figure 9b As shown in the example, the second gap 218 penetrates the first blocking sublayer 2311 and stops at the surface of the second blocking sublayer 2312. After the storage layer 232 is oxidized to form the storage sublayer 2321, the first dielectric layer 212 is formed in the second gap 218, forming a Figure 5 A three-dimensional memory 200 is shown.

[0153] In some embodiments, the barrier layer 231 may be a single-layer film structure, the second gap 218 may expose the barrier layer 231 and / or penetrate at least a portion of the thickness of the barrier layer 231, and the second gap 218 is used to oxidize a portion of the storage layer 232 along the x direction to form a storage sublayer 2321.

[0154] In some embodiments, reference Figure 9aAs shown, in the first direction, the second dielectric layer 2322 is located between two adjacent gate layers 220 .

[0155] In the z direction, the second dielectric layer 2322 is located between two adjacent gate layers 220, and the orthographic projection of the gate layer 220 in the z direction may not overlap with the orthographic projection of the second dielectric layer 2322 in the z direction. The orthographic projection of the second dielectric layer 2322 in the x direction falls between the orthographic projections of the two adjacent gate layers 220 in the x direction. The orthographic projection of the second dielectric layer 2322 in the x direction may not overlap with the orthographic projection of the gate layer 220 in the x direction or may have a small overlap. The size of the overlapping part in the z direction may account for 0 to 10% of the size of the orthographic projection of the entire gate layer 220 in the z direction, or less.

[0156] In some embodiments, in the first direction, the size of the storage sublayer 2321 is greater than or equal to the size of the gate layer 220. In some embodiments, the orthographic projection of the gate layer 220 in the second direction falls within the orthographic projection of the storage sublayer 2321 in the second direction.

[0157] While increasing the size of the storage sublayer 2321 to increase the electron capture performance and the amount of electron capture, the size of the storage sublayer 2321 corresponding to the gate layer 220 in the x direction is also increased, so that all parts of the gate layer 220 correspond to the storage sublayer 2321, thereby increasing the voltage load of the gate layer 220 and reducing the tip discharge between the gate layers 220. Figure 8l and Figure 9a For example, the size of the storage sublayer 2321 in the z direction is equal to the size of the gate layer 220 in the z direction, and the orthographic projection of the gate layer 220 in the x direction falls exactly within the orthographic projection of the storage sublayer 2321 in the x direction. In some other specific embodiments, the size of the storage sublayer 2321 in the z direction may be greater than the size of the gate layer 220 in the z direction.

[0158] In some embodiments, the manufacturing method further comprises:

[0159] exist Figure 9a Before forming the first dielectric layer 212, refer to Fig.9c As shown, a protection layer 241 is formed at least on the top and bottom surfaces of the gate layer 220; wherein the dielectric constant of the protection layer 241 is greater than the dielectric constant of the first dielectric layer 212; and the protection layer 241 is located between two adjacent first dielectric layers 212. Fig.9c The first dielectric layer 212 is formed in the second gap 218 as shown, forming Figure 6 A three-dimensional memory 200 is shown.

[0160] The protective layer 241 may include an hk material having a dielectric constant greater than that of the first dielectric layer 212, such as aluminum oxide. The protective layer 241 may cover the top and bottom surfaces of the gate layer 220 in the z direction. The protective layer 241 is located between two adjacent first dielectric layers 212 and in contact with the first dielectric layer 212 to increase the electrical isolation performance between the two adjacent gate layers 220, reduce the mutual leakage between the two adjacent gate layers 220, and improve the stability of the device. In some other embodiments, the protective layer 241 may cover the top and bottom surfaces of the gate layer 220 in the z direction, and also cover the side surfaces of the gate layer 220 parallel to the z direction.

[0161] In some embodiments, including:

[0162] Memory devices, including one or more such Figures 3 to 6 The three-dimensional memory 200 is shown; and a memory controller coupled to the memory device and controlling the memory device.

[0163] Fig.10 A block diagram of an exemplary system 1000 with a memory device is shown for some aspects of the disclosed embodiments. The system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Fig.10 As shown in , system 1000 may include a host 1008 and a memory system 1002, the memory system 1002 having one or more memory devices 1004 and a memory controller 1006. The host 1008 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1008 may be configured to send data to the memory device 1004 or receive data from the memory device 1004.

[0164] The memory device 1004 may be any memory disclosed in the present disclosure. As disclosed in detail below, the memory device 1004 (e.g., a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory)) may have reduced leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows the size of the drive transistor to be further reduced.

[0165] According to some embodiments, the memory controller 1006 is coupled to the memory device 1004 and the host 1008, and is configured to control the memory device 1004. The memory controller 1006 may manage data stored in the memory device 1004, and communicate with the host 1008.

[0166] In some embodiments, the memory controller 1006 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1006 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays. The memory controller 1006 can be configured to control the operation of the memory device 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions related to data stored or to be stored in the memory device 1004, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.

[0167] In some embodiments, the memory controller 1006 is further configured to process error correction codes (ECC) on data read from or written to the memory device 1004. The memory controller 1006 may also perform any other suitable functions, such as formatting the memory device 1004. The memory controller 1006 may communicate with an external device (e.g., the host 1008) according to a specific communication protocol. For example, the memory controller 1006 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0168] The memory controller 1006 and the one or more memory devices 1004 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1002 can be implemented and packaged into different types of terminal electronic products. Fig.11aIn one example shown in , the memory controller 1006 and the single memory device 1004 can be integrated into a memory card 1102. The memory card 1102 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1102 may also include a processor that connects the memory card 1102 to a host (e.g., Fig.10 The memory card connector 1104 is coupled to the host 1008 in FIG. Fig.11b In another example shown in , the memory controller 1006 and the plurality of memory devices 1004 may be integrated into an SSD 1106. The SSD 1106 may also include a processor that interfaces the SSD 1106 with a host (e.g., Fig.10 In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102. The embodiments of the present disclosure do not limit the packaging form and execution protocol of the memory controller and the memory device, and can be selected and optimized according to the host interface protocol and actual user needs.

[0169] In some embodiments, a memory device may include a memory array and a peripheral circuit. The memory array and the peripheral circuit may be arranged on the same wafer, that is, the memory array and the peripheral circuit are arranged on the same die to form a chip. The memory array and the peripheral circuit may be arranged on different wafers, that is, the memory array Die and the peripheral circuit Die are formed into a chip chip through hybrid bonding. The Die mentioned in the embodiment of the present disclosure is divided by the memory array. A Die may include or exclude peripheral circuits, and the memory array may include multiple Dies. A Die of the memory array includes at least one storage plane, and adjacent planes can be divided by cutting paths. Each plane may include multiple pages. The memory cells on each page share word lines, and each page can be used as the minimum unit of read and write operations. Each plane can be divided into multiple storage blocks, and each block can be used as the minimum unit of erase operation. A memory device may include one Die or multiple Dies. A memory device may include multiple memory arrays.

[0170] Fig.12 Schematic circuit diagram of an exemplary memory device 1200 including peripheral circuits illustrating some aspects of the disclosed embodiments. The memory device 1200 may be Fig.101. The memory device 1200 may include a memory array 1201 and a peripheral circuit 1202 coupled to the memory array 1201. The memory array 1201 may be a NAND flash memory array, in which memory cells 1206 are provided in the form of an array of NAND memory strings 1208, each of which may extend vertically above a substrate (not shown).

[0171] In some embodiments, each NAND memory string 1208 includes a plurality of memory cells 1206 coupled in series and stacked vertically. Each memory cell 1206 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 1206. Each memory cell 1206 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0172] In some embodiments, each memory cell 1206 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 1206 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0173] like Fig.12 As shown in , each NAND memory string 1208 may include a source select gate (SSG) 1210 at its source end and a drain select gate (DSG) 1212 at its drain end. The SSG 1210 and the DSG 1212 may be configured to activate a selected NAND memory string 1208 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 1208 in the same block 1204 are coupled by the same source line (SL) 1214 (e.g., a common SL).

[0174] According to some embodiments, all NAND memory strings 1208 in the same block 1204 have an array common source (ACS). According to some embodiments, the DSG 1212 of each NAND memory string 1208 is coupled to a corresponding bit line 1216, and data can be read from or written to the bit line 1216 via an output bus (not shown). In some embodiments, each NAND memory string 1208 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having the DSG 1212) or a deselect voltage (e.g., 0V) to the corresponding DSG 1212 via one or more DSG lines 1213 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having the SSG 1210) or a deselect voltage (e.g., 0V) to the corresponding SSG 1210 via one or more SSG lines 1215.

[0175] like Fig.12 As shown in , the NAND memory string 1208 can be organized into a plurality of blocks 1204, each of which can have a common source line 1214 (e.g., coupled to ground). In some embodiments, each block 1204 is a basic data unit for an erase operation, that is, all memory cells 1206 on the same block 1204 are erased at the same time. To erase the memory cells 1206 in the selected block 1204a, the source lines 1214 coupled to the selected block 1204a and the unselected blocks 1204b in the same plane as the selected block 1204a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0176] It should be understood that in some examples, erase operations can be performed at a half-block level, at a quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of a block. The memory cells 1206 of adjacent NAND memory strings 1208 can be coupled by word lines 1218, which select which row of memory cells 1206 are affected by read and programming operations. In some embodiments, each word line 1218 is coupled to a page 1220 of memory cells 1206, which is the basic unit of data for programming operations. The size of a page 1220 in bits can be related to the number of NAND memory strings 1208 coupled by the word line 1218 in a block 1204. Each word line 1218 can include a plurality of control gates (gate electrodes) at each memory cell 1206 in a corresponding page 1220 and a gate line coupling the control gates. Fig.12 The illustrated page 1220 may include a row of memory cells 1206 , or may include multiple rows of memory cells 1206 on the same layer that share a word line voltage.

[0177] In some embodiments, the physical device structure of NAND memory string 1208 may include Figures 3 to 6 A NAND memory string 1208 may include one or more channel pillars 230 , and a NAND string may also include a plurality of channel pillars 230 that are stacked and coupled.

[0178] Fig.12 The word line 1218 in may correspond to Figures 3 to 6 The gate layer 220 in the stack structure. The gate layer 220 at the top of the stack structure can be extended laterally as an upper selection gate line, the gate layer 220 at the bottom of the stack structure can be extended laterally as a lower selection gate line, and the gate layer 220 extending laterally between the upper selection gate line and the lower selection gate line can be used as a word line layer.

[0179] Return to reference Fig.12 , the peripheral circuit 1202 may be coupled to the memory array 1201 through the bit line 1216, the word line 1218, the source line 1214, the SSG line 1215, and the DSG line 1213. The peripheral circuit 1202 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 1201 by applying a voltage signal and / or a current signal to each target memory cell 1206 and sensing a voltage signal and / or a current signal from each target memory cell 1206 through the bit line 1216, the word line 1218, the source line 1214, the SSG line 1215, and the DSG line 1213. The peripheral circuit 1202 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. The memory array 1201 may include a plurality of arranged channel pillars 230, and the embodiments of the present disclosure are not limited to the arrangement manner and number.

[0180] In some embodiments, Fig.13 Some exemplary peripheral circuits are shown, including page buffer / sense amplifier 1304, column decoder / bit line driver 1306, row decoder / word line driver 1308, voltage generator 1310, control logic unit 1312, register 1314, interface 1316 and data bus 1318. It should be understood that in some examples, it may also include Fig.13 Additional peripheral circuits not shown.

[0181] The page buffer / sense amplifier 1304 may be configured to read data from the memory array 1201 and program (write) data to the memory array 1201 according to a control signal from the control logic unit 1312. In one example, the page buffer / sense amplifier 1304 may store a page of programming data (write data) to be programmed into one page 1220 of the memory array 1201. In another example, the page buffer / sense amplifier 1304 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 1206 coupled to the selected word line 1218. In yet another example, the page buffer / sense amplifier 1304 may also sense a low-power signal from the bit line 1216 representing a data bit stored in the memory cell 1206 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 1306 may be configured to be controlled by the control logic unit 1312 and select one or more NAND memory strings 1208 by applying a bit line voltage generated from the voltage generator 1310.

[0182] The row decoder / word line driver 1308 may be configured to be controlled by the control logic unit 1312 and select / deselect the block 1204 of the memory array 1201 and select / deselect the word line 1218 of the block 1204. The row decoder / word line driver 1308 may also be configured to drive the word line 1218 using the word line voltage generated from the voltage generator 1310. In some embodiments, the row decoder / word line driver 1308 may also select / deselect and drive the SSG line 1215 and the DSG line 1213. As described in detail below, the row decoder / word line driver 1308 is configured to perform an erase operation on the memory cell 1206 coupled to the selected word line(s) 1218. The voltage generator 1310 may be configured to be controlled by the control logic unit 1312 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 1201.

[0183] The control logic unit 1312 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 1314 may be coupled to the control logic unit 1312, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 1316 may be coupled to the control logic unit 1312, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 1312, and to buffer status information received from the control logic unit 1312 and relay them to the host. The interface 1316 may also be coupled to the column decoder / bit line driver 1306 via the data bus 1318, and act as a data I / O interface and a data buffer to buffer data and relay them to the storage array 1201 or relay or buffer data from the storage array 1201.

[0184] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: A stacked structure comprising alternately stacked gate layers and first dielectric layers; A channel column, penetrating the stacked structure along a first direction; Along a second direction perpendicular to the first direction, the channel column includes: a barrier layer, a storage layer, a tunneling layer and a channel layer arranged in sequence; wherein the storage layer includes a plurality of storage sublayers corresponding to the gate layer, and the storage sublayers are electrically isolated from each other.

2. The three-dimensional memory according to claim 1, characterized in that: The first dielectric layer at least penetrates the barrier layer and the storage layer along the second direction, and the storage layer is divided into a plurality of storage sub-layers by the first dielectric layer.

3. The three-dimensional memory according to claim 1, characterized in that: In the first direction, the storage layer includes a second dielectric layer located between two adjacent storage sublayers; in the second direction, the barrier layer is located between the first dielectric layer and the second dielectric layer.

4. The three-dimensional memory according to claim 3, characterized in that: The first dielectric layer penetrates at least a portion of the thickness of the barrier layer along the second direction.

5. The three-dimensional memory according to claim 4, characterized in that: The blocking layer includes a first blocking sublayer and a second blocking sublayer, wherein the second blocking sublayer is located between the first blocking sublayer and the second dielectric layer; wherein the dielectric constant of the first blocking sublayer is greater than the dielectric constant of the second blocking sublayer; and the first dielectric layer penetrates at least part of the thickness of the first blocking sublayer along the second direction.

6. The three-dimensional memory according to claim 3, characterized in that: In the first direction, the second dielectric layer is located between the two gate layers.

7. The three-dimensional memory according to claim 1, characterized in that: In the first direction, a size of the storage sublayer is greater than or equal to a size of the gate layer.

8. The three-dimensional memory according to claim 7, characterized in that: An orthographic projection of the gate layer in the second direction falls within an orthographic projection of the storage sublayer in the second direction.

9. The three-dimensional memory according to claim 1, characterized in that: The three-dimensional memory further comprises: A protection layer, wherein the protection layer at least covers the top surface and the bottom surface of the gate layer in the first direction, and the protection layer is located between two adjacent first dielectric layers; and the dielectric constant of the protection layer is greater than the dielectric constant of the first dielectric layer.

10. The three-dimensional memory according to claim 1, characterized in that: The gate layer comprises: A connecting layer and a conductive layer; wherein the connecting layer surrounds the conductive layer; and the connecting layer is located between two adjacent first dielectric layers.

11. A method for manufacturing a three-dimensional memory, characterized in that: include: forming a stacked structure, the stacked structure comprising alternately stacked dielectric material layers and sacrificial layers; forming a channel hole penetrating the stacked structure along a first direction; Etching a portion of the dielectric material layer along a second direction perpendicular to the first direction through the channel hole to form an opening between two adjacent sacrificial layers; forming a first stop layer at one end of the sacrificial layer exposed from the sidewall of the channel hole; forming a second stop layer in the opening; On the first stop layer and the second stop layer, a barrier layer, a storage layer, a tunnel layer and a channel layer are sequentially formed; removing the sacrificial layer and the first stop layer, forming a first gap between adjacent dielectric material layers, and forming a gate layer in the first gap; removing the dielectric material layer and the second stop layer to form a second gap between adjacent gate layers; The storage layer is separated by the second gap to form a plurality of storage sub-layers; wherein the storage sub-layers correspond to the gate layer and the storage sub-layers are electrically isolated from each other; A first dielectric layer is formed in the second gap.

12. The manufacturing method according to claim 11, characterized in that: The method of forming the first stop layer includes: An end of the sacrificial layer exposed from the sidewall of the channel hole is oxidized, and a portion of the sacrificial layer forms the first stop layer.

13. The manufacturing method according to claim 11, characterized in that: The method of forming the second stop layer includes: A second stop material layer is formed in the opening and on the first stop layer, and a portion of the second stop material layer on the first stop layer is etched away to form the second stop layer.

14. The manufacturing method according to claim 11, characterized in that: The step of isolating the storage layer through the second gap to form a plurality of storage sub-layers comprises: The barrier layer and the storage layer are etched so that the second gap at least penetrates the barrier layer and the storage layer in the second direction to form the storage sublayer.

15. The manufacturing method according to claim 11, characterized in that: The method of forming the barrier layer comprises: A first blocking sublayer and a second blocking sublayer are sequentially formed on the first stop layer and the second stop layer; wherein the dielectric constant of the first blocking sublayer is greater than the dielectric constant of the second blocking sublayer.

16. The manufacturing method according to claim 15, characterized in that: The second gap exposes the first barrier sublayer, and / or the second gap penetrates at least a portion of the thickness of the first barrier sublayer in the second direction; The step of isolating the storage layer through the second gap to form a plurality of storage sub-layers comprises: Part of the storage layer is oxidized to form a second dielectric layer; wherein the second dielectric layer divides the storage layer into a plurality of storage sub-layers.

17. The manufacturing method according to claim 16, characterized in that: In the first direction, the second dielectric layer is located between two adjacent gate layers.

18. The manufacturing method according to claim 11, characterized in that: In the first direction, a size of the storage sublayer is greater than or equal to a size of the gate layer.

19. The manufacturing method according to claim 18, characterized in that: An orthographic projection of the gate layer in the second direction falls within an orthographic projection of the storage sublayer in the second direction.

20. The manufacturing method according to claim 11, characterized in that: The method of forming the gate layer includes: A connection layer is formed on an inner wall of the first gap, and a conductive layer is formed in the first gap including the connection layer; wherein the conductive layer is surrounded by the connection layer.

21. The manufacturing method according to claim 11, characterized in that: The production method further comprises: Before forming the first dielectric layer, a protective layer is formed at least on the top surface and the bottom surface of the gate layer; wherein the dielectric constant of the protective layer is greater than the dielectric constant of the first dielectric layer; and the protective layer is located between two adjacent first dielectric layers.

22. A memory system, characterized in that: include: A memory device comprising one or more three-dimensional memories according to any one of claims 1 to 10; as well as A memory controller is coupled to the memory device and controls the memory device.

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