Memory device and method of forming the same

Abstract

The invention provides a memory device and a method of forming the same. The memory device is a three-dimensional bit cost scalable memory device (BiCS) including a stack of layers and a via electrode extending vertically through the stack of layers. The layer stack includes a conductivity controllable layer and an electrode layer. The electrode layer has a conductor portion and a partition portion separating the via electrode and the conductor portion of the electrode layer. At least one storage portion of the conductivity controllable layer is electrically connected in series between the via electrode and the conductor portion of the electrode layer. The via electrode comprises, for example, tungsten. The conductivity controllable layer includes, for example, a bi-directional threshold switching material. The conductor portion of the electrode layer contains, for example, carbon.

Description

Technical Field

[0001] The present disclosure relates to memory cells, including memory cells for integrated circuits. Background Art

[0002] Memory cells, such as those used in integrated circuits, benefit from optimized performance, such as reduced latency, increased bandwidth, and / or reduced energy consumption. They also benefit from optimized cost, such as increased density. For example, the continued slowdown in the scaling of dynamic random access memory (DRAM) has delayed performance and / or cost optimization. Summary of the Invention

[0003] A system of one or more computers can be configured to perform specific operations or actions by having software, firmware, hardware, or a combination thereof installed on the system. The running software, firmware, hardware, or a combination thereof causes the system to perform and / or control actions. One or more computer programs can be configured to perform specific operations or actions by containing instructions that, when executed by a data processing device, cause the device to perform the actions.

[0004] A first aspect includes a memory device comprising a layer stack and a via electrode extending vertically through the layer stack, wherein the layer stack optionally comprises a controllable conductivity layer and an electrode layer adjacent to the controllable conductivity layer, wherein the electrode layer optionally comprises a conductor portion and a separator portion, wherein the separator portion separates the via electrode from the conductor portion, and wherein at least one storage portion of the controllable conductivity layer is electrically connected in series between the via electrode and the conductor portion.

[0005] Some exemplary embodiments may optionally include one or more of the following features, alone or in combination. The layer stack has inner sidewalls defining a hole for accommodating a through-hole electrode. The conductivity-controllable layer includes an Ovonic Threshold Switch (OTS) material. The conductor portion may optionally include carbon (C) and a metal material. The conductor portion may optionally include a plurality of materials selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co) and ruthenium (Ru). The through-hole electrode may optionally include tungsten (W). The through-hole electrode may optionally include titanium nitride (TiN). The separator portion may optionally include a dielectric material. The through-hole electrode is one of a plurality of through-hole electrodes, the plurality of through-hole electrodes extending vertically through the layer stack; and the layer stack has a plurality of inner sidewalls defining a plurality of holes, the plurality of holes accommodating each of the plurality of through-hole electrodes. The conductivity-controllable layer is a conductivity-controllable layer among a plurality of conductivity-controllable layers; and the electrode layer is an electrode layer among a plurality of electrode layers, each conductivity-controllable layer of the plurality of conductivity-controllable layers being adjacent to an electrode layer among the plurality of electrode layers. The layer stack optionally includes a plurality of separator layers; at least one separator layer among the plurality of separator layers separates each conductivity-controllable layer of the plurality of conductivity-controllable layers from other conductivity-controllable layers among the plurality of conductivity-controllable layers; and at least one separator layer among the plurality of separator layers separates each electrode layer of the plurality of electrode layers from other electrode layers among the plurality of electrode layers. The conductor portion is a conductor portion among a plurality of conductor portions; the separator portion is a separator portion among a plurality of separator portions; each electrode layer of the plurality of electrode layers optionally includes a conductor portion among a plurality of conductor portions corresponding to a through-hole electrode among a plurality of through-hole electrodes, and a separator portion among a plurality of separator portions; the plurality of separator portions separate the plurality of through-hole electrodes from the plurality of conductor portions. The storage portion is a specific storage portion; corresponding to each through-hole electrode of the plurality of through-hole electrodes and each electrode layer of the plurality of electrode layers, at least one storage portion of the conductivity-controllable layer is adjacent to the corresponding electrode layer and electrically connected in series between the corresponding through-hole electrode and the corresponding conductor portion of the corresponding electrode layer; and the specific storage portion is a storage portion among the plurality of storage portions. Each conductor portion of the plurality of conductor portions can serve as an individual word line of the memory array; each through-hole electrode of the plurality of through-hole electrodes can serve as an individual bit line of the memory array; and each storage portion serves as non-volatile storage to store information of a portion of the memory array, the information being parsed into one or more bits of binary information accessed using word lines and bit lines, the word lines and bit lines having a storage portion electrically connected in series therebetween. The storage device is suitable for implementing non-volatile storage in a solid-state drive (SSD), implementing a storage-class memory (SCM), and / or implementing a memory compatible with a fast computing connection.

[0006] A second aspect includes a method for forming a memory device. The method comprises: forming a layer stack, wherein the layer stack comprises a controllable conductivity layer and an electrode layer adjacent to the controllable conductivity layer; forming a via electrode extending vertically through the layer stack, wherein the electrode layer optionally comprises a conductor portion and a separator portion, wherein the separator portion separates the via electrode from the conductor portion, and wherein at least one storage portion of the controllable conductivity layer is electrically connected in series between the via electrode and the conductor portion.

[0007] Some exemplary embodiments may optionally include one or more of the following features, alone or in combination. A method of forming a through-hole electrode may optionally include forming a hole through the layer stack, and the hole defines the size of the through-hole electrode that extends through the layer stack. The electrode layer may be formed by forming an undercut in the electrode layer so that the undercut opening surrounds the hole, and the undercut opening defines the volume of the separator. The electrode layer may be formed by forming a separator in the undercut opening. The conductivity-controllable layer may include a bidirectional threshold switch material, and the conductor portion may optionally include carbon (C).

[0008] The third aspect includes a processor and a memory, wherein the memory can store instructions executable by the processor, and when the processor executes the instructions, the processor performs an operation. The operation includes a method of forming a storage device.

[0009] The foregoing embodiments optionally comprise hardware, a method or process, or computer software on a computer-accessible medium.

[0010] Other aspects and advantages of the present disclosure will become apparent from the accompanying drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A 、 Figure 1B and Figure 1C A 3D diagram, a cross-sectional diagram, and a top view respectively illustrating various aspects of a plurality of memory cells of a 3D bit cost scalable memory;

[0012] Figure 2 A schematic diagram illustrating various aspects of a plurality of memory cells of a three-dimensional bit-cost scalable memory is shown;

[0013] Figure 3 a three-dimensional diagram illustrating various aspects of a memory array of a three-dimensional bit-cost scalable memory;

[0014] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 A time series graph illustrating an example of manufacturing a three-dimensional bit cost scalable memory; and

[0015] Figure 9 A flow chart illustrating a technique for fabricating one or more regions of a three-dimensional bit-cost scalable memory is shown.

[0016] Description of Reference Numerals

[0017] 110,410: Separator layer

[0018] 120,420: Conductivity controllable layer

[0019] 130: Electrode conductor part

[0020] 140: Separator

[0021] 150,850: Through-hole electrodes

[0022] 199,299: brackets

[0023] 250, 251, 350: bit lines

[0024] 260,261,268,269: Word plane

[0025] 280: Storage unit

[0026] 290,291: Source line selector connector

[0027] 320: OTS layer

[0028] 321: Source line connector

[0029] 370: Bit line selector connector

[0030] 391: Source line

[0031] 392: Source Line Selector

[0032] 398: Contact element

[0033] 430,530: Electrode conductive layer

[0034] 510: Completed separator layer

[0035] 520: Completed conductivity controllable layer

[0036] 550: Holes

[0037] 630: Completed electrode conductor part

[0038] 640: Electrode separation side etch opening

[0039] 740: Completed partition

[0040] 904,905,906,907,908: Steps

[0041] AA, BB: hatching DETAILED DESCRIPTION

[0042] Reference Figures 1A-1C and Figure 2-9 Provides a detailed description of three-dimensional bit-cost scalable memory technology.

[0043] One or more flowcharts are described herein. Processors programmed with computer programs, dedicated logic hardware (including field programmable integrated circuits), and various combinations thereof can be used to implement and / or guide the processing steps described by the flowcharts. The computer program is stored in a memory accessible to a computer system and executed by the processor. Various actions can be combined, performed simultaneously, and / or performed in a different order without affecting the processing achieved. In some cases, the rearrangement of multiple actions can achieve the same effect only if certain other changes are made. In addition, for clarity, some of the flowcharts herein omit certain actions that are not necessary for understanding the disclosed technology. Various additional actions can be performed before, after, and / or between the actions.

[0044] Examples of selected acronyms, mnemonics, and abbreviations used in the narrative are as follows.

[0045]

[0046]

[0047] [The concept of scalable memory with three-dimensional bit cost]

[0048] The three-dimensional bit-cost scalable memory described herein includes a structure for forming nonvolatile memory cells. The memory cells are capable of storing information, for example, each memory cell storing one or more bits of information. The memory cells are formed at the intersection of vertical bit lines and horizontal word planes, and information storage is provided at the intersection. Each memory cell is formed by a pair of active layers. A spacer layer separates the multiple memory cells in the vertical dimension.

[0049] The bit plane is formed by thin film layers deposited on a flat wafer surface. The vertical bit lines are perpendicular to the flat wafer surface.

[0050] Integrated circuit fabrication techniques, such as those based on planar processing of silicon wafers, can be used to fabricate electronic devices that include one or more of the three-dimensional bit-cost scalable memories described herein.

[0051] Some of the 3D bit-cost scalable memories described herein can achieve access latencies competitive with DRAM (e.g., faster than 3D NAND-type memories) and densities competitive with 3D NAND-type memories (e.g., higher density than DRAM). Compared to other memory manufacturing technologies, some of the 3D bit-cost scalable memories described herein can reduce the cost of memory manufacturing.

[0052] In the description herein and in the accompanying drawings, like numbered elements correspond to like elements, substantially like elements, and / or examples thereof. For example, Figure 1A The through-hole electrode 150 and Figure 1B The through-hole electrode 150 is the same. For example, Figure 5 The completed separation layer 510 and Figure 6 The completed separation layer 510 is the same.

[0053] In the drawings, unless otherwise specified, elements labeled with the same pattern correspond to elements composed of the same or substantially the same type of material, such as the same or substantially similar chemical composition and / or structure. Figure 4 The conductivity controllable layer 420 and Figure 5 The patterns of the completed controllable conductivity layer 520 are the same, which means that the materials of the controllable conductivity layer 420 and the completed controllable conductivity layer 520 are substantially similar, such as OTS material.

[0054] Figures 1A to 1C Various aspects of a memory cell of a three-dimensional bit-cost scalable memory are shown. Figure 1A A three-dimensional diagram illustrating a portion of a three-dimensional bit-cost scalable memory is shown. Figure 1A In FIG. 1 , there are six examples of through-hole electrodes 150 . Figure 1A , there are five examples of separator layers 110, four examples of controllable conductivity layers 120, and four examples of electrode layers, each of which includes an electrode conductor portion 130 and a separator portion 140. An example of the separator portion 140 is located at each intersection of the through-hole electrode 150 and the electrode conductor portion 130.

[0055] Figure 1B A cross-sectional view of a portion of a three-dimensional bit-cost scalable memory is shown. Figure 1B Corresponding to Figure 1CThe top and bottom layers of the stack are instances of the separator layer 110. Individual instances of the controllable conductivity layer 120 are adjacent to corresponding layers comprising instances of the electrode conductor portion 130 and the separator portion 140. Each instance of the separator portion 140 surrounds a portion of an instance of the through-hole electrode 150. Instances of the separator layer 110 form the top and bottom layers, and other instances of the separator layer 110 are formed between the controllable conductivity layer 120 and the layer formed by the combination of the electrode conductor portion 130 and the separator portion 140. Bracket 199 represents a three-layer stack formed by (1) to (3) that can include any number of repetitions: (1) the controllable conductivity layer 120, (2) the electrode layer formed by the combination of the electrode conductor portion 130 and the separator portion 140, and (3) the separator layer 110. Information storage can be provided separately. For example, the multiple storage parts of the example of the controllable conductivity layer 120 can provide information storage separately. The multiple storage parts of the example of the controllable conductivity layer 120 are electrically connected in series between the example of the through-hole electrode 150 and the electrode conductor part 130.

[0056] Figure 1C A top view of a portion of a three-dimensional bit-cost scalable memory is shown. Figure 1C Corresponding to Figure 1B An example of the through-hole electrode 150 surrounded by an example of the partition portion 140 is provided in an example of the electrode conductor portion 130 .

[0057] Figure 2 Schematic diagram illustrating various aspects of a plurality of memory cells of a three-dimensional bit-cost scalable memory. For clarity, Figure 2 Two bit lines are shown (bit line 250 and bit line 251 are related). Bit line 250 is coupled to a plurality of memory cells in parallel. Memory cell 280 is used as an example of a memory cell. Bit line 250 is coupled to a source line selector (not shown) via source line selector connector (To SLS) 290. Bit line 251 is coupled to a source line selector (not shown) via source line selector connector 291. Any number of memory cells can be implemented, as shown in bracket 299. Conceptually, bracket 299 corresponds to Figure 1B Brackets 199.

[0058] For example, by Figure 1B The memory cell 280 can be realized by a stack of two layers formed by (1) and (2): (1) the controllable conductivity layer 120, and (2) the electrode layer formed by combining the electrode conductor portion 130 and the separator portion 140. As a specific example, the memory cell 280 can be realized by a portion of the example of the controllable conductivity layer 120 electrically connected in series between the through-hole electrode 150 and the example of the electrode conductor portion 130.

[0059] A word plane is associated with each memory cell. The word planes are shown as word planes 260, 261, 268, and 269. Each word plane corresponds to Figure 1B Each word plane is associated with a plurality of bit lines. For example, word plane 260 couples a plurality of memory cells to bit lines 250 and 251. Bit lines 250 and 251 correspond to Figure 1B The through-hole electrode 150 is provided.

[0060] Bracket 299 represents a three-layer stack formed by (1) to (3) which may include any number of repetitions: (1) a conductivity-controlled layer 120, (2) an electrode layer formed by combining an electrode conductor portion 130 and a separator portion 140, and (3) a separator layer 110.

[0061] Figure 3 A three-dimensional diagram illustrating various aspects of a memory array for a three-dimensional bit cost scalable memory. Bit lines 350 are Figure 1B The through-hole electrode 150 and Figure 2 The bit line selector connector 370 is an example implementation of multiple connectors for multiple bit lines 350. The OTS layer 320 is Figure 1B The source line selector 392 is an example of a source line selector, which is coupled to the Figure 2 Source line selector connector 290 is shown. Source line 391 is coupled to source line selector 392. OTS and source line connector 321 are examples of multiple connectors that connect to other components, such as a driver (not shown). Contact element 398 is an example of a contact element that is interposed between source line (SL) 391 and other components, such as a ground source (not shown).

[0062] [Exemplary Fabrication of 3D Bit-Cost Scalable Memory]

[0063] Figure 4-8 A time series diagram illustrating an example of manufacturing a three-dimensional bit cost scalable memory. The time series progresses monotonically in time, starting from Figure 4 , ending at Figure 8 Each figure is a cross-section.

[0064] Figure 4 The first graph in the time series graph is shown. A manufacturing process performs thin film deposition of three alternating planar material layers. Two of the three alternating planar material layers form a pair of active layers. One of the three alternating planar material layers is a separator layer. Controllable conductivity layer 420 represents the first layer of a pair of active layers. Electrode conductive layer 430 represents the second layer of a pair of active layers. Separator layer 410 represents a separator layer. Separator layers separate each pair of active layers from the other pairs of active layers.

[0065] Thin film deposition begins with the fabrication process depositing a first (e.g., base) layer as a spacer layer 410, for example, on top of a substrate, such as a silicon base wafer. Thin film deposition continues with the fabrication process depositing a second layer as a controllable conductivity layer 420. Controllable conductivity layer 420 is thus adjacent to and coplanar with spacer layer 410. Thin film deposition continues with the fabrication process depositing a third layer as an electrode conductive layer 430. Controllable conductivity layer 430 is thus adjacent to and coplanar with controllable conductivity layer 420.

[0066] The thin film deposition continues, with the fabrication process depositing more examples of the spacer layer 410, the conductivity-controllable layer 420, and the electrode conductive layer 430, until a predetermined number of layers are deposited. In various examples of three-dimensional bit-cost scalable memory, the number of layers may be various, such as 300 layers (e.g., 100 pairs of active layers and 100 spacer layers) or 3,000 layers.

[0067] After the thin film is deposited, the fabrication process equipment performs additional processing on the material layer to form multiple three-dimensional bit-cost scalable memory cells (such as Figure 4-8 shown).

[0068] In some examples of fabricating a 3D bit-cost scalable memory, the first spacer layer 410 is omitted, and the first controllable conductivity layer 420 is deposited directly on the substrate. As shown, the last layer deposited is spacer layer 410. Alternatively, the last layer deposited can be controllable conductivity layer 420 or electrode conductive layer 430.

[0069] In various manufacturing examples, the materials used and / or their thicknesses may be: (a) the same for all examples of the spacer layers 410, (b) the same for all examples of the spacer layers 410 except for the first example of the spacer layer 410, (c) the same for all examples of the spacer layers 410 except for the last example of the spacer layer 410, or (d) the same for all examples of the spacer layers 410 except for the first example of the spacer layer 410 and the last example of the spacer layer 410.

[0070] Please refer to Figure 9 Step 904 (depositing multiple thin films) and its related paragraphs to obtain and Figure 4 Supplementary description.

[0071] Figure 5 The second graph in the time series graph is shown. The manufacturing process equipment etches to form a plurality of parallel holes, the holes being orthogonal to the planar material layer. The plurality of holes extend through the plurality of layers. Each hole establishes a corresponding inner sidewall extending through the plurality of layers. Hole 550 (for through-hole electrode 850) represents a hole. The etching of hole 550 causes the hole 550 to be formed. Figure 4The separator layer 410, the controllable conductivity layer 420 and the electrode conductive layer 430 are transformed into the following Figure 5 The completed separator layer 510, the completed conductivity-controllable layer 520, and the electrode conductive layer 530 are shown. In some exemplary embodiments, the holes extend through all layers except the first separator layer 410. In some exemplary embodiments, the holes extend through all layers including the first separator layer 410.

[0072] Please refer to Figure 9 Step 905 (etching hole openings) and its related paragraphs to obtain and Figure 5 Supplementary description.

[0073] Figure 6 The third graph in the time series diagram is shown. Manufacturing processing equipment etches to form undercut openings in the examples of the electrode conductive layer 530, forming examples of completed electrode conductor portions 630 and corresponding examples of electrode separation undercut openings 640. Each example of the electrode conductive layer 530 has an example of an electrode separation undercut opening 640 corresponding to an example of a hole 550. At this stage of manufacturing, the examples of holes 550 and the examples of electrode separation undercut openings 640 are conceptual. They are conceptual; for each example of a hole 550, its adjacent examples of electrode separation undercut openings 640 and the corresponding example of a hole 550 together form a single three-dimensional aperture. In the figures, the junction between the examples of holes 550 and the examples of electrode separation undercut openings 640 is indicated by a dashed line.

[0074] In a specific example, in the case of circular holes 550 , each electrode separation undercut opening 640 is exemplified by the additional removal of an annular volume of material from the electrode conductive layer 530 to form the completed electrode conductor portion 630 .

[0075] The etching of the side-etch opening does not affect the examples of the hole 550 , the completed separation layer 510 , and the completed conductivity-controllable layer 520 .

[0076] Please refer to Figure 9 Step 906 (etching side etch openings) and its related paragraphs to obtain and Figure 6 Supplementary description.

[0077] Figure 7 The fourth figure in the time series diagram is shown. The manufacturing process equipment deposits the separation material in the example of the electrode separation side etch opening 640 and the hole 550, and then etches back the separation material to form the completed separation portion 740. Thus, after the separation material is deposited, the corresponding inner sidewalls (e.g., as shown in FIG. 5 ) created by the hole opening etching are formed. Figure 5 shown and Figure 5 Related descriptions) are effectively restored.

[0078] Depositing the separator material does not affect the completed electrode conductor portion 630 , the hole 550 , the completed separator layer 510 , and the completed conductivity-controllable layer 520 .

[0079] Please refer to Figure 9 Step 907 (deposition and etch back) and its related paragraphs to obtain and Figure 7 Supplementary description.

[0080] Figure 7 The fifth graph in the time series diagram illustrates an example of a fabrication process performing deposition of a via electrode material (eg, via metal deposition) to (completely) fill the hole 550 , followed by CMP to form a via electrode 850 .

[0081] Depositing the via electrode material does not affect the examples of the completed separation layer 510 , the completed conductivity-controllable layer 520 , the completed electrode conductor portion 630 , and the completed separation portion 740 .

[0082] thereby, Figure 8 A completed portion of a three-dimensional bit-cost scalable memory is shown. Figure 4-8 Mark the manufacturing Figures 1A-1C An example of a 3D bit-cost scalable memory is shown. Figure 8 The examples of the completed separation layer 510, the completed conductivity controllable layer 520, the completed electrode conductor portion 630, the completed separation portion 740, and the through-hole electrode 850 correspond to the examples of the first embodiment. Figures 1A-1C The separator layer 110, the conductivity controllable layer 120, the electrode conductor part 130, the separator part 140, and the through-hole electrode 150 are included.

[0083] Please refer to Figure 9 Step 908 (depositing vias and performing CMP) and its related paragraphs to obtain and Figure 8 Supplementary description.

[0084] [Exemplary Manufacturing Process for 3D Bit-Cost Scalable Memory]

[0085] A device comprising a three-dimensional bit cost scalable memory is manufactured, for example, from a wafer, such as a semiconductor (e.g., silicon) wafer. The wafer has an upper surface, and the upper surface of the wafer is processed across the entire upper surface to make it suitable for manufacturing. Manufacturing is performed in a semiconductor fabrication facility. The processing steps form one or more regions of the three-dimensional bit cost scalable memory element and optionally form other regions. The other regions optionally include circuitry that uses the three-dimensional bit cost scalable memory element as a storage device, such as one or more processors, interfaces, and / or circuits that are interoperable with the memory. The other regions optionally include circuitry that uses the three-dimensional bit cost scalable memory device in a system and / or components of the system itself.

[0086] Figure 9 A flow chart illustrating a technique for fabricating one or more areas of a three-dimensional bit cost scalable memory device, such as the three-dimensional bit cost scalable memory device shown in any of the aforementioned figures, is provided.

[0087] The operations include depositing and etching materials to form a three-dimensional, bit-cost scalable memory. For example, one or more masks (e.g., photomasks) may be used to guide the etching. The etching may optionally include an intermediate step of depositing a layer of photosensitive material, which is then selectively exposed to electromagnetic radiation (e.g., ultraviolet light) through a photomask to selectively remove (or retain) the photosensitive material layer. Different photomasks are used for the different operations depicted in the figures. For clarity, the detailed description of the photomasks will be omitted from the following description related to the figures.

[0088] The manufacturing process begins by depositing a plurality of planar thin film layers (step 904: depositing a plurality of thin films), wherein a set of planar thin film layers includes three interlaced planar thin film layers, such as Figure 4 The separator layer 410, the controllable conductivity layer 420 and the electrode conductive layer 430 are formed. The multiple thin film layers are staggered so that a separator layer is formed after a pair of active layers are formed. The separator layer can separate a pair of active layers formed subsequently, and so on until the target number of layers is formed.

[0089] The first deposition (e.g., first spacer layer 410) at least substantially covers the entire upper surface of the wafer that will become the vertical three-dimensional bit-cost scalable memory element. The second deposition (e.g., conductivity-controllable layer 420 adjacent to spacer layer 410) at least substantially covers the entire upper surface of the first deposition. The third deposition (e.g., electrode conductive layer 430 adjacent to conductivity-controllable layer 420) at least substantially covers the entire upper surface of the second deposition, and so on. The spacer layers (corresponding to the first deposition, the fourth deposition, and so on) serve to separate (e.g., electrically and / or thermally isolate) a pair of active layers from other pairs of active layers. Multiple spacer layers (e.g., spacer layer 410) can optionally be composed of the same material, for example, a specific dielectric such as silicon nitride or silicon oxide. The pairs of active layers (corresponding to the second and third depositions, the fifth and sixth depositions, and so on) serve to form a portion of the active circuitry of the three-dimensional bit-cost scalable memory element. The first layer of the pair of active layers (e.g., conductivity-controllable layer 420) comprises a conductivity-controllable material, such as a specific OTS material. The second layer in the pair of active layers (e.g., electrode conductive layer 430) includes a conductive material, such as a material containing carbon (C). Deposition is continued until the target number of layers is deposited, for example, a total of 3*8, 3*32, 3*64, and 3*1024 layers (corresponding to 8, 32, 64, and 1024 pairs of active layers) are formed.

[0090] Thin film deposition was performed using CVD.

[0091] Next, a manufacturing process equipment is used to form a plurality of holes, which are used for subsequent material deposition to form (deep) through-hole electrodes (step 905: etching hole openings), for example Figure 5 An example of a hole 550 is shown. The hole is used for subsequent deposition of central electrode material. The hole can be formed by etching, for example, using RIE techniques. In some exemplary embodiments, an etch stop layer can be used to determine the depth of the hole etching, for example to prevent excessive etching depth.

[0092] Next, the manufacturing process equipment forms the conductor portion (the conductor portion of the electrode conductive layer), for example Figure 6 The completed electrode conductor portion 630 is shown. An undercut opening is etched in each electrode conductive layer (step 906: etching undercut openings), for example Figure 6 The electrodes are shown separated by undercut openings 640 to form the conductor portions.

[0093] The side-etch openings can be etched using wet or dry etching techniques. One example of an etching technique is O2 plasma etching. Another example of an etching technique is N2 plasma etching. The extension of the side-etch openings can be controlled by controlling the etching time.

[0094] Next, a manufacturing process is performed to form a partition (a partition of the electrode conductive layer), for example Figure 7The completed partition 740 is shown. The partition is formed by material deposition and subsequent etching (step 907: deposition and etch back). The material deposition fills the undercut openings and holes with the partition material. Next, the partition material is etched away (e.g., etch back) to re-form the initially formed holes, such as the holes (e.g., holes) formed in step 905 (etch hole openings). Figure 7 The completed partition portion 740 is shown).

[0095] The material deposition may be performed by ALD technology. In some exemplary embodiments, the material deposition may be performed by RIE technology.

[0096] Next, the fabrication process forms a (deep) via electrode. The via electrode is formed by material deposition followed by polishing (step 908: via deposition and CMP). Material deposition fills the hole initially formed in step 905 (hole etch) and subsequently re-formed in step 907 (deposition and etchback) with the via electrode material. Polishing removes material, for example, to expose the topmost spacer layer.

[0097] Material deposition can be performed using CVD technology, and polishing can be performed using CMP technology.

[0098] This completes the process of manufacturing a three-dimensional bit-cost scalable memory element.

[0099] In some manufacturing processes, additional processing steps may be performed Figure 9 Before or after, and / or with any one or more of the actions shown Figure 9 Any one or more of the illustrated actions may be performed in whole or in part in parallel. For example, additional processing steps may be performed in circuitry associated with using the three-dimensional bit-cost scalable memory element as a memory device, using the memory device in a system, and / or forming one or more components of the system.

[0100] [Materials for 3D Bit-Cost Scalable Memory]

[0101] Suitable materials for (deep) via electrodes include one or more conductive materials, such as tungsten (W) and titanium nitride (TiN), which can be used alone or in any combination or as a material basis in combination with one or more other materials.

[0102] Suitable materials for the conductor portion of the electrode layer include one or more conductive materials, such as carbon (C), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co), and ruthenium (Ru). These materials can be used alone or in any combination, or as a basis for a material formulated in combination with one or more other materials. Some conductor portions include carbon (C) and metal materials, such as tungsten (W), titanium (Ti), tantalum (Ta), cobalt (C), and ruthenium (Ru). o ) and ruthenium (Ru).

[0103] Suitable materials for the conductivity-controllable material include arsenic (As), selenium (Se), silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), and indium (In). These materials can be used alone, in any combination, or as a basis for a material formulated with one or more other materials. For example, one or more OTS elements are made of chalcogenides including (i) As, Se, and Ge (e.g., AsSeGe), (ii) AsSeGe and Si (e.g., AsSeGeSi), (iii) AsSeGeSi and In (e.g., AsSeGeSiIn), and (iv) AsSeGeIn.

[0104] Suitable materials for the spacer layer and / or the spacer portion of the electrode layer include one or more dielectric materials, such as silicon nitride or silicon oxide.

[0105] [Three-dimensional bit-cost scalable storage device and system]

[0106] Some devices (e.g., integrated circuits, one or more chips in a system-on-a-chip, and / or packaged chips) include one or more arrays of three-dimensional bit-cost scalable memory cells (as described elsewhere herein) and additional circuitry to implement a memory device that can be used as a standalone device and / or as a component in a system. The additional circuitry provides interface and control functions that enable the three-dimensional array of bit-cost scalable memory cells to be organized in various ways into one or more planes, each plane containing one or more blocks, and each block containing one or more pages.

[0107] The additional circuitry may include various hardware circuit blocks, such as bit line circuits, sense amplifiers, page caches / buffers, interface circuits, word line decoders / drivers, controllers, and / or bias circuits (eg, voltage and / or current sources).

[0108] In some exemplary embodiments, the additional circuitry enables the three-dimensional bit-cost scalable memory cell array to replace and / or augment DRAM and / or SCM in a system, such as in a DIMM or SODIMM package. In some exemplary embodiments, the additional circuitry enables the three-dimensional bit-cost scalable memory cell array to be coupled to CPUs and / or GPUs via a high-performance communication technology such as CXL. In some exemplary embodiments, the additional circuitry enables the three-dimensional bit-cost scalable memory cell array to be used in one or more locations in the memory and / or storage hierarchy, such as in an SSD and / or in a DRAM-like device.

[0109] In some exemplary embodiments, the additional circuitry enables the three-dimensional bit-cost scalable memory cell array to serve as a replacement and / or augmentation for various non-volatile memory elements in a system, such as packaged in and / or operated as an NVDIMM.

[0110] [Additional information on scalable memory with 3D bit cost]

[0111] Figures 1A-1C and Figure 2-9 Various aspects of an exemplary three-dimensional bit cost scalable memory technology are disclosed that provides non-volatile information storage by using a conductivity controllable layer composed, for example, of OTS materials.

[0112] Although the present invention has been disclosed with reference to the preferred embodiments and examples above, it should be understood that these examples are intended to be illustrative rather than restrictive. It is expected that those skilled in the art will readily be able to arrive at various modifications and combinations that fall within the spirit of the present invention and the scope of the appended claims.

Claims

1. A storage device, comprising: A stack comprising a controllable conductivity layer and an electrode layer adjacent to the controllable conductivity layer; and a via electrode extending vertically through the layer stack, The electrode layer includes a conductor part and a separation part, the separation part separates the through-hole electrode and the conductor part, and at least one storage part of the conductivity-controllable layer is electrically connected in series between the through-hole electrode and the conductor part, and the conductivity-controllable layer includes a bidirectional threshold switch (Ovonic Threshold Switch, OTS) material. 2 . The memory device according to claim 1 , wherein the layer stack has an inner sidewall, the inner sidewall defining a hole for accommodating the through-hole electrode.

3. The memory device according to claim 1, wherein the conductor portion comprises carbon (C) and a metal material.

4. The memory device of claim 1, wherein the conductor portion comprises a plurality of materials selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co) and ruthenium (Ru). 5 . The memory device according to claim 1 , wherein the via electrode comprises tungsten (W). 6 . The memory device according to claim 1 , wherein the via electrode comprises titanium nitride (TiN).

7. The storage device according to claim 1, wherein the through-hole electrode is a through-hole electrode among a plurality of through-hole electrodes, the plurality of through-hole electrodes vertically extending through the layer stack, the layer stack having a plurality of inner side walls defining a plurality of holes, the holes accommodating each through-hole electrode of the plurality of through-hole electrodes.

8. The storage device according to claim 7, wherein the conductivity-controllable layer is a conductivity-controllable layer among a plurality of the conductivity-controllable layers, the electrode layer is an electrode layer among a plurality of the electrode layers, and each of the plurality of the conductivity-controllable layers is respectively adjacent to one of the plurality of the electrode layers.

9. A method of forming a storage device, comprising: forming a layer stack, wherein the layer stack comprises a controllable conductivity layer and an electrode layer adjacent to the controllable conductivity layer; and forming a via electrode extending vertically through the layer stack, The electrode layer includes a conductor part and a separator part, the separator part separates the through-hole electrode and the conductor part, and at least one storage part of the conductivity-controllable layer is electrically connected in series between the through-hole electrode and the conductor part, the conductivity-controllable layer includes a bidirectional threshold switch (Ovonic Threshold Switch; OTS) material, and the conductor part includes carbon (C).

10. The method of claim 9, wherein forming the via electrode comprises forming a hole through the layer stack, the hole defining a dimension of the via electrode extending through the layer stack, The electrode layer is formed by forming an undercut in the electrode layer so that the undercut surrounds the hole, and the undercut defines the volume of the separation portion.

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