Display substrate and display device

Abstract

The invention provides a display substrate and a display device, and belongs to the technical field of display, and the display substrate comprises a substrate, a plurality of pixel units located on the substrate and arranged in an array, and color film layers located on the sides, away from the substrate, of the pixel units; the pixel unit comprises a plurality of pixel driving circuits and a plurality of light-emitting devices which are arranged on the substrate; one light-emitting device is electrically connected with one pixel driving circuit to form a sub-pixel; the color film layer comprises a plurality of color blocks, and one color block corresponds to one light-emitting device; the contour shape of the orthographic projection of the pixel openings of at least part of the light-emitting devices on the substrate is circular; and / or, the contour of the orthographic projection of the pixel opening of at least part of the light-emitting device on the substrate comprises a symmetrical pattern formed by alternately enclosing a plurality of arc-shaped parts and straight edges, and the corresponding angles of at least two arc-shaped parts are the same.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display device. Background Art

[0002] With the rapid development of the display industry, organic light emitting diode display (OLED), as the most commonly used display device, has received great attention and development in the field of display technology.

[0003] As an important component of the display device, the display substrate has common pixel arrangements such as Real RGB (traditional pixel arrangement), Pentile (pixel arrangement), Delta (delta) and other pixel arrangements, each of which has its own advantages and disadvantages. Among them, Real RGB has the best display effect. In the traditional real RGB pixel structure, the pixel driving circuit and the light-emitting device (red light-emitting device R, green light-emitting device G or blue light-emitting device B) are arranged one by one, while the diffraction pattern of the COE (CF on EN, forming a color film layer on the thin-film encapsulated organic electroluminescent device) product based on realRGB is often a cross structure, such as Figure 1 As shown, it is a schematic diagram of the diffraction pattern of a real RGB+COE product. It can be clearly seen that there is a color separation phenomenon therein, which is not accepted by users. Summary of the invention

[0004] The present disclosure aims to at least solve the technical problems existing in the prior art and provide a display substrate and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a display substrate, comprising a base substrate, a plurality of pixel units arranged in an array on the base substrate, and a color filter layer located on a side of the pixel unit away from the base substrate;

[0006] The pixel unit includes a plurality of pixel driving circuits and a plurality of light-emitting devices arranged on the substrate; one light-emitting device is electrically connected to one pixel driving circuit to form a sub-pixel; the color filter layer includes a plurality of color block blocks, and one color block is arranged corresponding to one light-emitting device;

[0007] The contour of the orthographic projection of at least part of the pixel openings of the light-emitting device on the substrate is circular; and / or, the contour of the orthographic projection of at least part of the pixel openings of the light-emitting device on the substrate includes a symmetrical figure alternately surrounded by multiple arc parts and straight edges, and the angles corresponding to at least two arc parts are the same.

[0008] In some embodiments, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first sub-pixel includes a first light-emitting device; the second sub-pixel includes a second light-emitting device; the third sub-pixel includes a third light-emitting device and a fourth light-emitting device;

[0009] For the plurality of pixel units arranged in an array, the first light emitting devices and the second light emitting devices are alternately arranged along a column direction to form a plurality of columns of first light emitting device groups; the third light emitting devices and the fourth light emitting devices are alternately arranged along a column direction to form a plurality of columns of second light emitting device groups.

[0010] In some embodiments, the outline shapes of the orthographic projections of the pixel openings of the first light-emitting device, the second light-emitting device, the third light-emitting device, and the fourth light-emitting device on the substrate are all circular.

[0011] In some embodiments, for one of the pixel units, the aperture ratio of the first sub-pixel is A, the aperture ratio of the second sub-pixel is B, and the aperture ratio of the third sub-pixel is C; A:B:C is one of 1:(1.7~2.2)(1.4~2).

[0012] In some embodiments, an aperture ratio of the third light emitting device is the same as an aperture ratio of the fourth light emitting device.

[0013] In some embodiments, the aperture ratio of the pixel unit ranges from 10% to 55%.

[0014] In some embodiments, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first sub-pixel includes a first light-emitting device; the second sub-pixel includes a second light-emitting device and a fifth light-emitting device; the third sub-pixel includes a third light-emitting device and a fourth light-emitting device;

[0015] For the plurality of pixel units arranged in an array, the first light emitting devices and the second sub-pixels are alternately arranged along a column direction to form a plurality of columns of first light emitting device groups; the third light emitting devices and the fourth light emitting devices are alternately arranged along a column direction to form a plurality of columns of second light emitting device groups;

[0016] An angle formed between an extension line of a line connecting the center point of the second light emitting device and the center point of the fifth light emitting device and an extension line of a line connecting the center point of the third light emitting device and the center point of the fourth light emitting device is in a range of 0° to 90°.

[0017] In some embodiments, the outline shapes of the orthographic projections of the pixel openings of the first light-emitting device, the second light-emitting device, the third light-emitting device, the fourth light-emitting device, and the fifth light-emitting device on the substrate are all circular.

[0018] In some embodiments, the display substrate further comprises a first conductive layer disposed on a side of the pixel driving circuit away from the base substrate and a pixel defining layer disposed on a side of the first conductive layer away from the base substrate;

[0019] The light emitting device comprises a pixel opening penetrating the pixel defining layer, a first electrode formed on the pixel defining layer close to the pixel driving circuit, a light emitting layer at least located in the pixel opening, and a second electrode;

[0020] The first conductive layer includes a first electrode of each of the light-emitting devices;

[0021] For the third sub-pixel, the first electrode of the third light emitting device is electrically connected to the first electrode of the fourth light emitting device.

[0022] In some embodiments, the first electrode of the third light emitting device and the first electrode of the fourth light emitting device are connected into an integral structure.

[0023] In some embodiments, the first electrode of the third light emitting device and the first electrode of the fourth light emitting device are disconnected;

[0024] For the third sub-pixel, the pixel driving circuit includes a driving transistor and a first connecting electrode electrically connected to the driving transistor; the first connecting electrode includes a first main body, a first branch portion and a second branch portion electrically connected to the first main body respectively; the first branch portion is electrically connected to the first electrode of the third light-emitting device, and the second branch portion is electrically connected to the first electrode of the fourth light-emitting device.

[0025] In some embodiments, for the second sub-pixel, the first electrode of the second light emitting device and the first electrode of the fifth light emitting device are electrically connected.

[0026] In some embodiments, the first electrode of the second light emitting device and the first electrode of the fifth light emitting device are connected as an integral structure.

[0027] In some embodiments, the first electrode of the second light emitting device and the first electrode of the fifth light emitting device are disconnected;

[0028] For the second sub-pixel, the pixel driving circuit includes a driving transistor and a second connecting electrode electrically connected to the driving transistor; the second connecting electrode includes a second main body, a third branch portion and a fourth branch portion electrically connected to the second main body respectively; the third branch portion is electrically connected to the first electrode of the second light-emitting device, and the fourth branch portion is electrically connected to the first electrode of the fifth light-emitting device.

[0029] In some embodiments, the plurality of pixel units include a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are alternately arranged along a row direction and a column direction respectively;

[0030] The first pixel unit and the second pixel unit each include a first sub-pixel, a second sub-pixel and a third sub-pixel; the first sub-pixel includes a first light-emitting device, the second sub-pixel includes a second light-emitting device, and the third sub-pixel includes a third light-emitting device;

[0031] For the first pixel unit, the first light emitting device and the second light emitting device are located in the same column, and are located in an adjacent column to the third light emitting device;

[0032] For the second pixel unit, the first light emitting device and the second light emitting device are located in the same row, and are located in an adjacent row to the third light emitting device;

[0033] The line connecting the center point of the first light-emitting device in the first pixel unit and the center point of the second light-emitting device is a first line segment, and the line connecting the center point of the first light-emitting device in the second pixel unit and the center point of the second light-emitting device is a second line segment; the extension direction of the first line segment is perpendicular to the extension direction of the second line segment.

[0034] In some embodiments, the outline shapes of the orthographic projections of the pixel openings of the first light-emitting device and the pixel openings of the second light-emitting device on the substrate are both circular;

[0035] The outline shape of the orthographic projection of the pixel opening of the third light emitting device on the base substrate is an ellipse.

[0036] In some embodiments, for the first pixel unit, an extension direction of the first line segment and an extension direction of a short axis corresponding to an outline of a pixel opening of the third light-emitting device are perpendicular to each other;

[0037] For the second pixel unit, an extension direction of the second line segment and an extension direction of a short axis corresponding to an outline of a pixel opening of the third light-emitting device are perpendicular to each other.

[0038] In some embodiments, the display substrate further comprises a semiconductor layer disposed on the base substrate, a second conductive layer disposed on a side of the semiconductor layer away from the base substrate, a third conductive layer disposed on a side of the second conductive layer away from the base substrate, and a fourth conductive layer disposed on a side of the second conductive layer close to the third conductive layer;

[0039] The pixel driving circuit at least includes a plurality of thin film transistors and a storage capacitor;

[0040] The active layer of each of the thin film transistors is located on the semiconductor layer;

[0041] At least a portion of the gate electrode of the thin film transistor and the first electrode plate of the storage capacitor are located in the second conductive layer;

[0042] The second electrode plate of the storage capacitor is located on the third conductive layer;

[0043] At least part of the control signal lines of the thin film transistors are located in the fourth conductive layer.

[0044] In some embodiments, the outline shape of the orthographic projection of at least part of the first electrode of the light-emitting device on the base substrate is circular.

[0045] In some embodiments, the ratio of the size of the pixel opening of each of the light-emitting devices along the column direction to the size along the row direction is in a range of 1:1 to 1:3.

[0046] In some embodiments, the sub-pixel includes a plurality of light emitting devices;

[0047] The distance between the light emitting devices in different sub-pixels is greater than the distance between the light emitting devices in the sub-pixel having a plurality of light emitting devices.

[0048] In some embodiments, the light-emitting layer of each of the light-emitting devices is located on a side of the pixel defining layer away from the first electrode; and the orthographic projections of the light-emitting layers of different light-emitting devices on the substrate at least partially overlap.

[0049] In some embodiments, the outline of the orthographic projection of the light-emitting layer of at least part of the light-emitting device on the substrate is circular; or, the outline of the orthographic projection of the light-emitting layer of at least part of the light-emitting device on the substrate is a symmetrical figure surrounded by multiple arc parts and straight edges alternating, and the angles corresponding to at least two arc parts are the same.

[0050] In some embodiments, the display substrate further includes an isolation column; the isolation column is located on a side of the pixel defining layer close to the light emitting layer.

[0051] In some embodiments, for a plurality of pixel units arranged in an array, an isolation column is disposed corresponding to every 2 to 3 rows of pixel units and / or every 3 to 5 columns of pixel units.

[0052] In some embodiments, the orthographic projection of the color resist block on the base substrate covers the orthographic projection of the light emitting device corresponding to the color resist block on the base substrate.

[0053] In some embodiments, a distance between an edge of a projection of the color resist block on the substrate and an edge of a projection of a light emitting device corresponding to the color resist block on the substrate is in a range of 1.5 μm to 10.5 μm.

[0054] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes a display substrate as described in any one of the above-mentioned first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is a schematic diagram of the diffraction pattern of existing real RGB+COE products;

[0056] Figure 2a A schematic diagram of the main components of a display substrate based on real RGB+COE provided in an embodiment of the present disclosure;

[0057] Figure 2b A top view of an exemplary color filter layer provided in an embodiment of the present disclosure;

[0058] Figure 3 A schematic diagram of a pixel arrangement provided in an embodiment of the present disclosure;

[0059] Figure 4 Based on Figure 3 Schematic diagram of the diffraction image of the product of pixel arrangement + COE shown;

[0060] Figure 5 A schematic diagram of another pixel arrangement provided in an embodiment of the present disclosure;

[0061] Figure 6 A schematic diagram of another pixel arrangement provided in an embodiment of the present disclosure;

[0062] Figure 7 A film layer layout of a light-emitting device provided in an embodiment of the present disclosure;

[0063] Figure 8 A film layer layout of another light-emitting device provided in an embodiment of the present disclosure;

[0064] Fig. 9 A schematic diagram of another pixel arrangement provided in an embodiment of the present disclosure;

[0065] Fig.10 Based on Fig. 9 Schematic diagram of the diffraction image of the product of pixel arrangement + COE shown;

[0066] Fig.11 A circuit diagram of a 7T1C pixel driving circuit provided in an embodiment of the present disclosure;

[0067] Fig.12 A partial structural layout of an exemplary display substrate provided in an embodiment of the present disclosure;

[0068] Fig.13 A layout of a semiconductor layer provided in an embodiment of the present disclosure;

[0069] Fig.14 A layout of a second conductive layer provided in an embodiment of the present disclosure;

[0070] Fig.15 A layout of a third conductive layer provided in an embodiment of the present disclosure;

[0071] Fig.16 A layout of a fourth conductive layer provided in an embodiment of the present disclosure;

[0072] Fig.17 A layout of a fifth conductive layer provided in an embodiment of the present disclosure;

[0073] Figure 18a to Figure 18d for Figure 13 to Figure 17 The layout of the pixel driving circuit preparation process shown;

[0074] Fig.19 A layout of a pixel unit provided in an embodiment of the present disclosure;

[0075] Fig. 20 A layout of a semiconductor layer provided in an embodiment of the present disclosure;

[0076] Fig.21 A layout of a second conductive layer provided in an embodiment of the present disclosure;

[0077] Fig. 22 A layout of a third conductive layer provided in an embodiment of the present disclosure;

[0078] Fig.23 A layout of a fourth conductive layer provided in an embodiment of the present disclosure;

[0079] Figure 24a to Figure 24d for Figure 20 to Figure 23 The layout of the pixel driving circuit preparation process shown;

[0080] Fig.25 Another layout of a pixel unit provided in an embodiment of the present disclosure.

[0081] The reference numerals are as follows: 1, substrate; 21, pixel driving circuit; 22, sub-pixel; 23, color filter layer; 231, red color block; 232, green color block; 233, blue color block; 234, black matrix; TFE, encapsulation layer; Cathod, cathode; R-EL, red light-emitting layer; G-EL, green light-emitting layer; B-EL, blue light-emitting layer; PDL, pixel defining layer; 22-R, red sub-pixel; 22-G, green sub-pixel; 22-B, blue sub-pixel; R, first light-emitting device (red light-emitting device); G1, second light-emitting device ( Green light emitting device); G2, the fifth light emitting device (green light emitting device); B1, the third light emitting device (blue light emitting device); B2, the fourth light emitting device (blue light emitting device); L1, the first light emitting device group; L2, the second light emitting device group; B1-Anode, the first electrode of the blue light emitting device B1; B2-Anode, the first electrode of the blue light emitting device B2; PLN2, the second planarization layer; 01, the first conductive layer; 3, the first connecting electrode; 31, the first main body; 32, the first branch portion; 33, the second branch portion; 2-1, the first pixel unit; 2 -2, second pixel unit; t1, first line segment; t2, second line segment; 06, semiconductor layer; 02, second conductive layer; 03, third conductive layer; 04, fourth conductive layer; 05, fifth conductive layer; GI1, first insulating layer; GI2, second insulating layer; ILD, third insulating layer (interlayer insulating layer); T1, first reset transistor; T2, threshold compensation transistor; T3, drive transistor; T4, data writing transistor; T5, first light emission control transistor; T6, second light emission control transistor; T7, second reset transistor; Cst, storage capacitor; CC1 , the first plate of the storage capacitor; CC2, the second plate of the storage capacitor; T1a, the active layer of the first reset transistor; T2a, the active layer of the threshold compensation transistor; T3a, the active layer of the drive transistor; T4a, the active layer of the data write transistor; T5a, the active layer of the first light emission control transistor; T6a, the active layer of the second light emission control transistor; T7a, the active layer of the second reset transistor; T1c, the gate of the first reset transistor; T2c, the gate of the threshold compensation transistor; T4c, the gate of the data write transistor; T7c, the gate of the second reset transistor. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0083] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0084] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0085] It should be noted here that the row direction and column direction involved in the embodiments of the present disclosure only represent two different directions, and the two are not limited to being perpendicular to each other. In the drawings of the embodiments of the present disclosure, the row direction and the column direction are perpendicular to each other for illustration only, but it does not constitute a limitation to the embodiments of the present disclosure.

[0086] In addition, the descriptions of "same" and "equal" in the embodiments of the present disclosure do not mean that two objects are completely equal in size or shape. They are allowed to be roughly the same or roughly equal within a certain error range.

[0087] The transistor involved in the embodiments of the present disclosure may be a thin film transistor, a field effect transistor or other devices with the same or similar characteristics. Since the source and drain of the transistor are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode and the other is called the second electrode; the gate of the transistor is called the control electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first electrode is the drain of the P-type transistor, and the second electrode is the source of the P-type transistor. The N-type is the opposite (the first electrode is the source of the N-type transistor, and the second electrode is the drain of the N-type transistor). The N-type transistor is turned on when a high-level signal is applied to its control electrode, and is turned off when a low-level signal is applied to its control electrode; the P-type transistor is turned on when a low-level signal is applied to its control electrode, and is turned off when a high-level signal is applied to its control electrode. In the embodiments of the present disclosure, the transistor is a P-type transistor as an example for exemplary description.

[0088] In the related art, the Real RGB pixel structure has the best display effect among the pixel arrangement methods of the traditional display substrate. However, due to the large number of pixels and the limitations of various process factors, the resolution of the product is relatively low. Therefore, the Real RGB pixel structure is often used in display products with relatively low pixel density units (Pixels Per Inch, PPI), and is not suitable for mobile phone products. For example, the Real RGB pixel structure is mainly used in display products with relatively low PPI, such as notebook computers (NB) and car-mounted products.

[0089] That is to say, for products with relatively low PPI, such as NB and automotive products, in order to meet the image quality requirements, their pixel arrangement can only use the real RGB pixel structure. However, the diffraction patterns of COE (CF onEN, forming a color film layer on the thin-film encapsulated organic electroluminescent device) NB or automotive products currently in mass production on the market based on real RGB are often cross structures, such as Figure 1 As shown, it is a schematic diagram of the diffraction pattern of an automotive product based on real RGB+COE. It can be clearly seen that the color separation phenomenon exists therein, thus affecting the display quality.

[0090] In order to solve the above technical problems, the embodiments of the present disclosure provide a display substrate, which can significantly improve the color separation phenomenon produced by COE products based on real RGB and improve the display quality of the products.

[0091] Figure 2a A schematic diagram of the main components of a display substrate based on real RGB+COE provided in an embodiment of the present disclosure is shown in FIG. Figure 2aAs shown, the display substrate includes a base substrate 1, a plurality of pixel units arranged in an array on the base substrate 1, and a color filter layer 23 located on a side of the pixel unit away from the base substrate.

[0092] A packaging layer TFE is provided on one side of the color filter layer 23 close to the sub-pixel 22.

[0093] The pixel unit includes a plurality of pixel driving circuits 21 and a plurality of light-emitting devices arranged on a substrate; a light-emitting device is electrically connected to a pixel driving circuit 21 to form a sub-pixel 22. A light-emitting device is electrically connected to a pixel driving circuit 21, and different light-emitting devices can be electrically connected to the same pixel driving circuit 21. For example, a pixel driving circuit 21 can be configured to simultaneously drive a plurality of light-emitting devices in a sub-pixel. Exemplarily, a plurality of sub-pixels 22 adopt a RealRGB pixel arrangement. A pixel driving circuit 21 is configured to drive a sub-pixel 22. Exemplarily, the pixel driving circuit 21 includes at least a plurality of thin film transistors TFT. The sub-pixel 22 includes a first electrode (e.g., an anode), a second electrode (e.g., a cathode Cathod) and a light-emitting layer (e.g., a red light-emitting layer R-EL, or a green light-emitting layer G-EL, or a blue light-emitting layer B-EL) corresponding to each light-emitting device.

[0094] The sub-pixel 22 includes at least one light-emitting device; the color filter layer 23 includes a plurality of color blocks, and one color block is arranged corresponding to one light-emitting device. Figure 2b A top view of an exemplary color filter layer provided in an embodiment of the present disclosure, such as Figure 2b As shown, the color filter layer 23 may adopt COE (CF on EN, forming a color filter layer on a thin film encapsulated organic electroluminescent device). Specifically, the color filter layer 23 includes a plurality of color blocks, such as a red block 231, a green block 232, and a blue block 233; the plurality of color blocks are arranged in one-to-one correspondence with the light-emitting devices in the plurality of sub-pixels 22, for example, a red block 231 is arranged in correspondence with a red light-emitting device R, a green block 232 is arranged in correspondence with a green light-emitting device G, and a blue block 233 is arranged in correspondence with a blue light-emitting device B. Exemplarily, the red block 231 is used to filter the red light entering therein so as to allow the three primary colors of light for color display to pass through, for example, the red block 231 can only pass red light, the green block 232 can only pass green light, and the blue block 233 can only pass blue light, thereby achieving full-color display. The black matrix 234 is disposed between any adjacent color resist blocks to shield light and has the function of absorbing light of all visible bands; the black matrix separates each color resist block to prevent cross-coloring between different color resist blocks and affect the display effect.

[0095] The sub-pixel 22 includes at least one light-emitting device; the outline shape of the orthographic projection of the pixel opening of at least part of the light-emitting devices on the substrate is circular.

[0096] And / or, the outline of the orthographic projection of the pixel opening of at least part of the light-emitting device on the substrate includes a symmetrical figure surrounded by a plurality of arc parts and straight edges alternately, and the angles corresponding to at least two arc parts are the same. For example, it may include an ellipse, a rounded rectangle, various rounded polygons, etc.

[0097] The diffraction image of the product based on real RGB+COE in the embodiment of the present disclosure is approximately circular, thereby improving the color separation phenomenon of the product and enhancing the display effect.

[0098] It should be noted that the pixel opening of the light emitting device may be understood as an opening on the pixel defining layer PDL for defining the light emitting layer of the light emitting device.

[0099] In addition, considering other product performance, such as standby time and life, the disclosed embodiment further improves the pixel structure of the display substrate. It should be noted that there are many factors that affect the standby time and life of the product, so the pixel arrangement design needs to meet many constraints, and adopting a reasonable pixel arrangement is a way to optimize the efficiency and life of the display product.

[0100] Before describing the specific pixel structure of the present disclosure, a plurality of sub-pixels 22 are first described. The plurality of sub-pixels 22 specifically include a red sub-pixel 22-R, a green sub-pixel 22-G, and a blue sub-pixel 22-B. The present disclosure embodiment is described by taking the first sub-pixel as a red sub-pixel 22-R, the second sub-pixel as a green sub-pixel 22-G, and the third sub-pixel as a blue sub-pixel 22-B as an example. The red sub-pixel 22-R includes at least one red light-emitting device, the green sub-pixel 22-G includes at least one green light-emitting device, and the blue sub-pixel 22-B includes at least one blue light-emitting device.

[0101] The following embodiments describe different pixel structures in detail.

[0102] In some embodiments, Figure 3 A schematic diagram of a pixel arrangement provided in an embodiment of the present disclosure is shown in FIG. Figure 3As shown, the plurality of sub-pixels 22 include a red sub-pixel 22-R, a green sub-pixel 22-G, and a blue sub-pixel 22-B; the red sub-pixel 22-R includes a red light-emitting device R; the green sub-pixel 22-G includes a green light-emitting device G1; and the blue sub-pixel 22-B includes a blue light-emitting device B1 and a blue light-emitting device B2. For the plurality of pixel units arranged in an array, the red light-emitting devices R and the green light-emitting devices G1 are alternately arranged along the column direction to form a plurality of columns of first light-emitting device groups L1; the blue light-emitting devices B1 and the blue light-emitting devices B2 are alternately arranged along the column direction to form a plurality of columns of second light-emitting device groups L2.

[0103] For example, Figure 3 The pixel arrangement shown in the figure, for a pixel unit, includes four light-emitting areas, and three pixel driving circuits 21 can be used, that is, the red light-emitting device R uses the first pixel driving circuit 21, the green light-emitting device G1 uses the second pixel driving circuit 21, and the blue light-emitting device B1 and the blue light-emitting device B2 jointly use the third pixel driving circuit 21. When lit, the two display areas of the blue light-emitting device are lit at the same time.

[0104] Furthermore, the outline shapes of the orthographic projections of the pixel openings of the red light emitting device R, the green light emitting device G1, the blue light emitting device B1, and the blue light emitting device B2 on the base substrate 1 are all circular.

[0105] Figure 4 Based on Figure 3 Schematic diagram of the diffraction image of the product of pixel arrangement + COE shown in FIG. Figure 4 As shown, the embodiment of the present disclosure adopts Figure 3 The pixel arrangement shown sets the pixel opening of the light-emitting device to a circular shape, thereby circularizing the diffraction pattern, that is, improving the color separation phenomenon; at the same time, it also maximizes the pixel opening of the sub-pixel 22, which can increase the brightness and reduce the risk of screen burn-in for a long time, thereby extending the product life.

[0106] In some embodiments, for a pixel unit, the aperture ratio of the red sub-pixel 22-R is A, the aperture ratio of the green sub-pixel 22-G is B, and the aperture ratio of the blue sub-pixel 22-B is C; wherein A:B:C is one of 1:(1.7~2.2):(1.4~2).

[0107] It should be noted that the aperture ratio of the sub-pixel 22 is the ratio between the sum of the areas of the pixel openings of each light-emitting device in the sub-pixel and the overall area occupied by the pixel unit. The overall area occupied by the pixel unit includes not only the area of ​​the pixel opening defined by the pixel defining layer PDL, but also the projected area of ​​the retaining wall between adjacent light-emitting devices.

[0108] For example, the aperture ratio A of the red sub-pixel 22-R is the ratio of the sum of the areas of the pixel openings of each light-emitting device in the red sub-pixel 22-R to the overall area occupied by the pixel unit; for example, the aperture ratio B of the green sub-pixel 22-G is the ratio of the sum of the areas of the pixel openings of each light-emitting device in the green sub-pixel 22-B to the overall area occupied by the pixel unit; for example, the aperture ratio C of the blue sub-pixel 22-B is the ratio of the sum of the areas of the pixel openings of each light-emitting device in the blue sub-pixel 22-R to the overall area occupied by the pixel unit. A:B:C represents the aperture ratios between the red sub-pixel 22-R, the green sub-pixel 22-G, and the blue sub-pixel 22-B.

[0109] Exemplarily, the aperture ratio among the red sub-pixel 22 -R, the green sub-pixel 22 -G, and the blue sub-pixel 22 -B is one of 1:(1.7-2.2):(1.4-2).

[0110] Taking the example that the red sub-pixel 22-R includes a red light-emitting device R, the green sub-pixel 22-G includes a green light-emitting device G1, and the blue sub-pixel 22-B includes a blue light-emitting device B1 and a blue light-emitting device B2, the opening ratio between the red sub-pixel 22-R (red light-emitting device R), the green sub-pixel 22-G (green light-emitting device G1), and the blue sub-pixel 22-B (blue light-emitting device B1+B2) is one of 1:1.7:1.4, 1:2:1.8, and 1:2.2:2.

[0111] This embodiment maximizes the pixel opening of the sub-pixels 22 by reasonably optimizing the opening ratio between the sub-pixels 22, thereby improving the brightness and reducing the risk of screen burn-in over a long period of time, thereby extending the product life.

[0112] Of course, the above opening ratio can also be adjusted according to actual product applications, and the embodiments of the present disclosure do not specifically limit it.

[0113] In some embodiments, the aperture ratio of the pixel unit is in the range of 10% to 55%. It should be noted that the aperture ratio of the pixel unit is the ratio between the sum of the areas of the pixel openings of each light-emitting device in the pixel unit and the overall area occupied by the pixel unit. The overall area occupied by the pixel unit includes not only the area of ​​the pixel opening defined by the pixel defining layer PDL, but also the projected area of ​​the retaining wall between adjacent light-emitting devices.

[0114] Exemplarily, the aperture ratios of different sub-pixels in a pixel unit can be determined according to the aperture ratio range of the actual pixel unit and the aperture ratio of each sub-pixel. For example, the aperture ratio of the red sub-pixel 22-R, the green sub-pixel 22-G, and the blue sub-pixel 22-B is 1:1.7:1.4, and the aperture ratio of the pixel unit is 41%, then the aperture ratio of the red sub-pixel 22-R is 10%, the aperture ratio of the green sub-pixel 22-G is 17%, and the aperture ratio of the blue sub-pixel 22-B is 14%.

[0115] In some embodiments, the aperture ratio of the blue light-emitting device B1 is the same as the aperture ratio of the blue light-emitting device B2. The aperture ratio of the blue light-emitting device B1 is the ratio between the area of ​​the pixel opening of the blue light-emitting device B1 and the overall area occupied by one pixel unit. The aperture ratio of the blue light-emitting device B2 is the ratio between the area of ​​the pixel opening of the blue light-emitting device B2 and the overall area occupied by one pixel unit. For example, if the aperture ratio of the blue sub-pixel 22-B is 14%, then the aperture ratios of the blue light-emitting device B1 and the blue light-emitting device B2 are both 7%.

[0116] This embodiment maximizes the pixel opening of the sub-pixel 22 by reasonably optimizing the aperture ratio of each sub-pixel 22, thereby improving brightness and reducing the risk of screen burn-in over a long period of time, thereby extending the life of the product.

[0117] In some embodiments, Figure 5 A schematic diagram of another pixel arrangement provided in an embodiment of the present disclosure, Figure 6 A schematic diagram of another pixel arrangement provided in an embodiment of the present disclosure is shown in FIG. Figure 5 and Figure 6 As shown, the plurality of sub-pixels 22 include a red sub-pixel 22-R, a green sub-pixel 22-G, and a blue sub-pixel 22-B; the red sub-pixel 22-R includes a red light-emitting device R; the green sub-pixel 22-G includes a green light-emitting device G1 and a green light-emitting device G2; and the blue sub-pixel 22-B includes a blue light-emitting device B1 and a blue light-emitting device B2. For the plurality of pixel units arranged in an array, the red light-emitting devices R and the green sub-pixels 22-G are alternately arranged along the column direction to form a plurality of columns of first light-emitting device groups L1; the blue light-emitting devices B1 and the blue light-emitting devices B2 are alternately arranged along the column direction to form a plurality of columns of second light-emitting device groups L2.

[0118] The angle between the extended line of the line connecting the center points of the green light emitting device G1 and the green light emitting device G2 and the extended line of the line connecting the center points of the blue light emitting device B1 and the blue light emitting device B2 is in the range of 0° to 90°.

[0119] Exemplarily, for a pixel unit including five light-emitting areas, three pixel driving circuits 21 can be used, that is, the red light-emitting device R uses the first pixel driving circuit 21, the green light-emitting device G1 and the green light-emitting device G2 use the second pixel driving circuit 21, and the blue light-emitting device B1 and the blue light-emitting device B2 jointly use the third pixel driving circuit 21. When lit, the two display areas of the green light-emitting device are lit at the same time, and the two display areas of the blue light-emitting device are lit at the same time.

[0120] For example, Figure 5 As shown, the angle between the extension line of the line connecting the center point of the green light-emitting device G1 and the center point of the green light-emitting device G2 and the extension line of the line connecting the center point of the blue light-emitting device B1 and the center point of the blue light-emitting device B2 is 0°, that is, the extension line of the line connecting the center point of the green light-emitting device G1 and the center point of the green light-emitting device G2 and the extension line of the line connecting the center point of the blue light-emitting device B1 and the center point of the blue light-emitting device B2 are parallel to each other.

[0121] For example, Figure 6 As shown, the angle between the extension line of the line connecting the center point of the green light emitting device G1 and the center point of the green light emitting device G2 and the extension line of the line connecting the center point of the blue light emitting device B1 and the center point of the blue light emitting device B2 is 45°.

[0122] Furthermore, the outline shapes of the orthographic projections of the pixel openings of the red light-emitting device R, the green light-emitting device G1, the blue light-emitting device B1, the blue light-emitting device B2, and the green light-emitting device G2 on the base substrate 1 are all circular.

[0123] The present disclosure embodiment adopts Figure 5 or Figure 6 The pixel arrangement shown in the figure sets the pixel opening of the light-emitting device to a circular shape, thereby realizing the circularization of the diffraction pattern, that is, improving the color separation phenomenon; at the same time, the pixel opening of the sub-pixel 22 is maximized, which can improve the brightness and reduce the risk of screen burn-in for a long time, thereby extending the life of the product. In addition, for the green sub-pixel 22-G and the blue sub-pixel 22-B, the green sub-pixel 22-G includes two green light-emitting devices, and the blue sub-pixel 22-B includes two blue light-emitting devices. Therefore, this embodiment improves the aperture ratio of the green light-emitting device and the aperture ratio of the blue light-emitting device, thereby improving the brightness and reducing the risk of screen burn-in for a long time, thereby extending the life of the product.

[0124] Taking the example that the red sub-pixel 22-R includes a red light-emitting device R, the green sub-pixel 22-G includes a green light-emitting device G1 and a green light-emitting device G2, and the blue sub-pixel 22-B includes a blue light-emitting device B1 and a blue light-emitting device B2, the aperture ratio between the red sub-pixel 22-R, the green sub-pixel 22-G and the blue sub-pixel 22-B is one of 1:(1.7-2.2):(1.4-2). Exemplarily, the aperture ratio between the red sub-pixel 22-R, the green sub-pixel 22-G and the blue sub-pixel 22-B is one of 1:1.7:1.4, 1:2:1.8, and 1:2.2:2.

[0125] This embodiment maximizes the pixel opening of the sub-pixels 22 by reasonably optimizing the opening ratio between the sub-pixels 22, thereby improving the brightness and reducing the risk of screen burn-in over a long period of time, thereby extending the product life.

[0126] In some embodiments, the aperture ratio of the pixel unit ranges from 10% to 55%.

[0127] Exemplarily, the aperture ratios of different sub-pixels in a pixel unit can be determined according to the aperture ratio range of the actual pixel unit and the aperture ratio of each sub-pixel. For example, the aperture ratio of the red sub-pixel 22-R, the green sub-pixel 22-G, and the blue sub-pixel 22-B is 1:2:1.8, and the aperture ratio of the pixel unit is 48%. Then, the aperture ratio of the red sub-pixel 22-R is 10%, the aperture ratio of the green sub-pixel 22-G is 20%, and the aperture ratio of the blue sub-pixel 22-B is 18%.

[0128] In some embodiments, the aperture ratio of the green light emitting device G1 is the same as the aperture ratio of the green light emitting device G2. The aperture ratio of the green light emitting device G1 is the ratio between the area of ​​the pixel opening of the green light emitting device G1 and the overall area occupied by one pixel unit. The aperture ratio of the green light emitting device G2 is the ratio between the area of ​​the pixel opening of the green light emitting device G2 and the overall area occupied by one pixel unit.

[0129] For example, the aperture ratio of the green sub-pixel 22 -G is 18%, and the aperture ratios of the green light emitting device G1 and the green light emitting device G2 are both 9%.

[0130] This embodiment maximizes the pixel opening of the sub-pixel 22 by reasonably optimizing the aperture ratio of each sub-pixel 22, thereby improving brightness and reducing the risk of screen burn-in over a long period of time, thereby extending the life of the product.

[0131] In the case where a sub-pixel 22 includes multiple light-emitting devices, one pixel driving circuit 21 is configured to drive the multiple light-emitting devices in one sub-pixel 22. Specifically, anodes of the light-emitting devices in one sub-pixel 22 are electrically connected to the same pixel driving circuit 21.

[0132] In some embodiments, for Figure 3 , Figure 5 or Figure 6 In the pixel arrangement shown, the display substrate further includes a first conductive layer 01 disposed on the side of the pixel driving circuit 21 away from the base substrate 1 and a pixel defining layer PDL disposed on the side of the first conductive layer 01 away from the base substrate 1; the light-emitting device includes a pixel opening penetrating the pixel defining layer PDL, and a first electrode formed on the pixel defining layer PDL near the pixel driving circuit 21, a light-emitting layer at least located in the pixel opening, and a second electrode. The first conductive layer 01 includes the first electrode of each light-emitting device, and for the blue sub-pixel 22-B, the first electrode B1-Anode of the blue light-emitting device B1 is electrically connected to the first electrode B2-Anode of the blue light-emitting device B2.

[0133] Exemplarily, the electrical connection between the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 can be direct connection or indirect electrical connection via connecting electrodes, which can be specifically set according to the actual pixel arrangement and the wiring layout of each light-emitting device.

[0134] For example, Figure 7 A film layer layout of a light-emitting device provided in an embodiment of the present disclosure, such as Figure 7 As shown, the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 are connected as an integral structure and are arranged on the side of the second planarization layer PLN2 close to the pixel defining layer PDL. The first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 are arranged in the same layer, that is, located in the first conductive layer 01, and can be formed by a single patterning process. At this time, the hollow portion of the mask corresponding to the first electrode of the blue light-emitting device is a closed pattern. Here, although the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 are connected as an integral structure, a retaining wall of the pixel defining layer PDL is arranged above the connection position of the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 to limit the blue light-emitting layers B-EL of different blue light-emitting devices.

[0135] For example, Figure 8 Another film layer layout of a light emitting device provided in the embodiment of the present disclosure, such as Figure 8As shown, the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 are disconnected; for the blue sub-pixel 22-B, the pixel driving circuit 21 includes a driving transistor and a first connecting electrode 3 electrically connected to the driving transistor; the first connecting electrode 3 includes a first main body 31 (see Fig.12 ), a first branch portion 32 and a second branch portion 33 electrically connected to the first main body portion 31 respectively; the first branch portion 32 is electrically connected to the first electrode B1-Anode of the blue light-emitting device B1, and the second branch portion 33 is electrically connected to the first electrode B2-Anode of the blue light-emitting device B2. The first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 are arranged in the same layer, that is, located in the first conductive layer 01, and can be formed by a single patterning process. At this time, the hollowed-out portion of the mask corresponding to the first electrode of the blue light-emitting device is two closed patterns. In addition, a retaining wall of the pixel defining layer PDL is provided at the disconnection position of the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2, so as to define the blue light-emitting layers B-EL of different blue light-emitting devices.

[0136] In some embodiments, in combination with the above embodiments, for Figure 5 or Figure 6 In the pixel arrangement shown, for the blue sub-pixel 22-B, the first electrode B1-Anode of the blue light-emitting device B1 and the first electrode B2-Anode of the blue light-emitting device B2 are electrically connected, and for the green sub-pixel 22-G, the first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 are electrically connected.

[0137] Exemplarily, the first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 may be electrically connected directly or indirectly via connecting electrodes, which may be specifically set according to the actual pixel arrangement and the wiring layout of each light-emitting device.

[0138] The first electrode of the green light emitting device G1 and the first electrode of the green light emitting device G2 are connected as an integral structure. Figure 7The first electrode B1-Anode and the first electrode B2-Anode shown in are connected as an integrated structure. The first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 are arranged in the same layer, that is, located in the first conductive layer 01, and can be formed by a single patterning process. At this time, the hollow portion of the mask corresponding to the first electrode of the green light-emitting device is a closed pattern. Here, although the first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 are connected as an integrated structure, a retaining wall of the pixel defining layer PDL is provided above the connection position of the first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 to define the light-emitting layers of different green light-emitting devices.

[0139] The first electrode of the green light emitting device G1 and the first electrode of the green light emitting device G2 are disconnected; Figure 8 The disconnection settings of the first electrode B1-Anode and the first electrode B2-Anode shown in are similar. For the green sub-pixel 22-G, the pixel driving circuit 21 includes a driving transistor and a second connecting electrode electrically connected to the driving transistor; the second connecting electrode includes a second main body, a third branch and a fourth branch electrically connected to the second main body respectively; the third branch is electrically connected to the first electrode of the green light-emitting device G1, and the fourth branch is electrically connected to the first electrode of the green light-emitting device G2. The first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 are arranged in the same layer, that is, located in the first conductive layer 01, and can be formed by a single patterning process. At this time, the hollowed-out portion of the mask corresponding to the first electrode of the green light-emitting device is two closed patterns. In addition, the disconnection position of the first electrode of the green light-emitting device G1 and the first electrode of the green light-emitting device G2 is provided with a retaining wall of the pixel defining layer PDL to define the light-emitting layers of different green light-emitting devices.

[0140] In some embodiments, Fig. 9 A schematic diagram of another pixel arrangement provided in an embodiment of the present disclosure is shown in FIG. Fig. 9As shown, the plurality of pixel units include a first pixel unit 2-1 and a second pixel unit 2-2, and the first pixel unit 2-1 and the second pixel unit 2-2 are alternately arranged along the row direction and the column direction respectively; the first pixel unit 2-1 and the second pixel unit 2-2 each include a red sub-pixel 22-R, a green sub-pixel 22-G and a blue sub-pixel 22-B; the red sub-pixel 22-R includes a red light-emitting device R, the green sub-pixel 22-G includes a green light-emitting device G1, and the blue sub-pixel 22-B includes a blue light-emitting device B1; for the first pixel unit 2-1, the red light-emitting device R and the green light-emitting device G1 are arranged alternately along the row direction and the column direction respectively; the first pixel unit 2-1 and the second pixel unit 2-2 each include a red sub-pixel 22-R, a green sub-pixel 22-G and a blue sub-pixel 22-B; the red sub-pixel 22-R includes a red light-emitting device R, the green sub-pixel 22-G includes a green light-emitting device G1, and the blue sub-pixel 22-B includes a blue light-emitting device B1 The red light emitting device G1 is located in the same column and is located in an adjacent column to the blue light emitting device B1; for the second pixel unit 2-2, the red light emitting device R and the green light emitting device G1 are located in the same row and are located in an adjacent row to the blue light emitting device B1; the line connecting the center point of the red light emitting device R in the first pixel unit 2-1 and the center point of the green light emitting device G1 is the first line segment t1, and the line connecting the center point of the red light emitting device R in the second pixel unit 2-2 and the center point of the green light emitting device G1 is the second line segment t2; the extension direction of the first line segment t1 and the extension direction of the second line segment t2 are perpendicular to each other.

[0141] For example, Fig. 9 The pixel arrangement shown, for a pixel unit, includes three light-emitting areas, and three pixel driving circuits 21 can be used, that is, the red light-emitting device R uses the first pixel driving circuit 21, the green light-emitting device G1 uses the second pixel driving circuit 21, and the blue light-emitting device B1 uses the third pixel driving circuit 21.

[0142] Furthermore, the outline shapes of the orthographic projections of the pixel openings of the red light-emitting device R and the green light-emitting device G1 on the base substrate 1 are both circular; the outline shapes of the orthographic projections of the pixel openings of the blue light-emitting device B1 on the base substrate 1 are both elliptical.

[0143] Fig.10 Based on Fig. 9 Schematic diagram of the diffraction image of the product of pixel arrangement + COE shown in FIG. Fig.10 As shown, this embodiment adopts Fig. 9 The pixel arrangement shown sets the pixel openings of the red light-emitting device R and the green light-emitting device G1 to a circle, and sets the pixel opening of the blue light-emitting device B1 to an ellipse, which can also achieve circularization of the diffraction pattern, that is, improve the color separation phenomenon; at the same time, it also maximizes the pixel opening of the sub-pixel 22, which can improve the brightness and reduce the risk of screen burn-in for a long time, thereby extending the product life.

[0144] Further, taking the case where the outline shapes of the orthographic projections of the pixel openings of the red light-emitting device R and the green light-emitting device G1 on the substrate 1 are both circular, and the outline shapes of the orthographic projections of the pixel openings of the blue light-emitting device B1 on the substrate 1 are both elliptical, as an example, Fig. 9 As shown, for the first pixel unit 2-1, the extension direction of the first line segment t1 is perpendicular to the extension direction of the short axis corresponding to the outline of the pixel opening of the blue light-emitting device B1; for the second pixel unit 2-2, the extension direction of the second line segment t2 is perpendicular to the extension direction of the short axis corresponding to the outline of the pixel opening of the blue light-emitting device B1.

[0145] The orthogonal design of adjacent pixel units in this embodiment can improve the uniformity of light-emitting device distribution. Combined with the design of maximizing pixel opening, it can improve product color deviation and further improve color separation.

[0146] In some embodiments, for one pixel unit, the opening ratio among the red sub-pixel 22 -R, the green sub-pixel 22 -G, and the blue sub-pixel 22 -B is one of 1:(1.7-2.2):(1.4-2).

[0147] Taking the case where the red sub-pixel 22-R includes a red light-emitting device R, the green sub-pixel 22-G includes a green light-emitting device G1, and the blue sub-pixel 22-B includes a blue light-emitting device B1, and the contour shapes of the orthographic projections of the pixel openings of the red light-emitting device R and the green light-emitting device G1 on the substrate 1 are both circular; and the contour shapes of the orthographic projections of the pixel openings of the blue light-emitting device B1 on the substrate 1 are both elliptical as examples, the opening ratio between the red sub-pixel 22-R (red light-emitting device R), the green sub-pixel 22-G (green light-emitting device G1) and the blue sub-pixel 22-B (blue light-emitting device B1) is one of 1:1.7:1.4, 1:2:1.8, and 1:2.2:2.

[0148] This embodiment maximizes the pixel opening of the sub-pixels 22 by reasonably optimizing the opening ratio between the sub-pixels 22, thereby improving the brightness and reducing the risk of screen burn-in over a long period of time, thereby extending the product life.

[0149] Of course, the above opening ratio can also be adjusted according to actual product applications, and the embodiments of the present disclosure do not specifically limit it.

[0150] In some embodiments, the aperture ratio of the pixel unit ranges from 10% to 55%.

[0151] This embodiment maximizes the pixel opening of the sub-pixel 22 by reasonably optimizing the aperture ratio of each sub-pixel 22, thereby improving brightness and reducing the risk of screen burn-in over a long period of time, thereby extending the life of the product.

[0152] In some embodiments, each sub-pixel 22 in the embodiments of the present disclosure may be driven by a pixel driving circuit 21 with the same structure.

[0153] It should be noted that the pixel driving circuit 21 provided in the embodiment of the present disclosure may adopt Fig.11 The case of 7T1C (7 transistors and 1 capacitor) is shown in Fig.11 It is only for illustrative purposes and will not limit the technical solution of the present disclosure. The pixel driving circuit 21 can also adopt a structure with other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiments of the present disclosure are not limited to this.

[0154] Fig.12 A partial structural layout of an exemplary display substrate provided in an embodiment of the present disclosure, such as Fig.12 As shown, the display substrate further includes a semiconductor layer 06 disposed on the base substrate 1, a second conductive layer 02 disposed on the side of the semiconductor layer 06 away from the base substrate 1, a third conductive layer 03 disposed on the side of the second conductive layer 02 away from the base substrate 1, and a fourth conductive layer 04 disposed on the side of the second conductive layer 02 close to the third conductive layer 03. The pixel driving circuit 21 at least includes a plurality of thin film transistors TFT and a storage capacitor Cst; the active layer of each thin film transistor TFT is located on the semiconductor layer 06; the gate of at least some thin film transistors TFT and the first electrode plate of the storage capacitor Cst are located on the second conductive layer 02; the second electrode plate of the storage capacitor Cst is located on the third conductive layer 03; and the control signal lines of at least some thin film transistors TFT are located on the fourth conductive layer 04.

[0155] like Fig.12 As shown, a buffer layer is arranged on the base substrate 1; a semiconductor layer 06 is arranged on the side of the buffer layer away from the base substrate 1; a first insulating layer (also known as a gate insulating layer) is arranged on the side of the semiconductor layer 06 away from the buffer layer; a second conductive layer 02 is arranged on the side of the first insulating layer away from the semiconductor layer 06; a second insulating layer is arranged on the side of the second conductive layer 02 away from the first insulating layer; a third conductive layer 03 is arranged on the side of the second insulating layer away from the second insulating layer; a third conductive layer 03 is arranged on the side of the third conductive layer 03 away from the second insulating layer; a fourth conductive layer 04 is arranged on the side of the third insulating layer away from the third conductive layer 03; a passivation layer PVX is arranged on the side of the fourth conductive layer 04 away from the third insulating layer; a first planarization layer PLN1 is arranged on the side of the passivation layer PVX away from the fourth conductive layer 04; a connecting electrode (for example, a first connecting electrode 3 and / or a second connecting electrode) is arranged on the side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 is arranged on the side of the connecting electrode away from the first planarization layer PLN1.

[0156] Taking the 7T1C pixel driving circuit 21 as an example, the pixel driving circuit 21 includes 7 thin film transistors TFT and 1 storage capacitor Cst. Fig.11 As shown, it specifically includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, a storage capacitor Cst, a first electrode CC1, and a second electrode CC2.

[0157] The source of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the drain of the data writing transistor T4 is configured to be electrically connected to the data line Vd to receive the data signal, and the gate T4c of the data writing transistor T4 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the first plate CC1 of the storage capacitor Cst is electrically connected to the first power supply voltage terminal VDD, and the second plate CC2 of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3; the source of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3. The drain of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate T2c of the threshold compensation transistor T2 is configured to be electrically connected to the second scanning signal line Ga2 to receive the compensation control signal; the source of the first reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the drain of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate T1c of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Reset1 to receive the first sub-reset control signal; the source of the second reset transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal, the drain of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device OLED, and the gate T7c of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Reset2 to receive the second sub-reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage terminal VDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode D1 of the light-emitting device OLED, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal; the second electrode of the light-emitting device OLED is electrically connected to the second power supply voltage terminal VSS.

[0158] A possible implementation method, taking the 7T1C pixel driving circuit 21 as an example, Fig.13The layout of the semiconductor layer 06 provided in the embodiment of the present disclosure, Fig.14 The layout of the second conductive layer 02 provided in the embodiment of the present disclosure, Fig.15 The layout of the third conductive layer 03 provided in the embodiment of the present disclosure, Fig.16 The layout of the fourth conductive layer 04 provided in the embodiment of the present disclosure, Fig.17 This is the layout of the fifth conductive layer 05 provided in the embodiment of the present disclosure.

[0159] like Fig.13 As shown, the active layer T1a of the first reset transistor T1, the active layer T2a of the threshold compensation transistor T2, the active layer T3a of the driving transistor T3, the active layer T4a of the data writing transistor T4, the active layer T5a of the first light emission control transistor T5, the active layer T6a of the second light emission control transistor T6, and the active layer T7a of the second reset transistor T7 are all located in the semiconductor layer 06.

[0160] like Fig.14 As shown, the gate T1c of the first reset transistor T1, the gate T2c of the threshold compensation transistor T2, the gate T4c of the data writing transistor T4, the gate T7c of the second reset transistor T7, the first electrode CC1 of the storage capacitor Cst, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are all located in the second conductive layer 02. Among them, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are an integrated structure (such as Fig.14 EM in ).

[0161] like Fig.15 As shown, the gate of the driving transistor T3, the second plate CC2 of the storage capacitor Cst, the signal line drawn from the first reset power supply terminal Vinit1 and electrically connected to the source of the first reset transistor T1, and the signal line drawn from the second reset power supply terminal Vinit2 and electrically connected to the source of the second reset transistor T7 are all located in the third conductive layer 03. Among them, the gate of the driving transistor T3 and the second plate CC2 of the storage capacitor Cst are an integrated structure (such as Fig.15 in CC2).

[0162] like Fig.16As shown, the first scanning signal line Ga1 (the control signal line of the data writing transistor T4), the second scanning signal line Ga2 (the control signal line of the threshold compensation transistor T2), the first reset control signal line Reset1 (the control signal line of the first reset transistor T1) and the second reset control signal line Reset2 (the control signal line of the second reset transistor T7) are all located in the fourth conductive layer 04. Among them, the first scanning signal line Ga1 and the second scanning signal line Ga2 are connected as an integrated structure (such as Fig.16 of Ga).

[0163] like Fig.17 As shown, the data line Vd is located in the fifth conductive layer 05 , and the signal line drawn from the first power supply voltage terminal VDD and electrically connected to the first electrode CC1 of the storage capacitor Cst and the source of the first light emitting control transistor T5 are both located in the fifth conductive layer 05 .

[0164] For example, Figure 18a to Figure 18d for Figure 13 to Figure 17 The layout of the pixel driving circuit 21 preparation process shown in FIG. Fig.18a As shown, a semiconductor layer 06 is formed; Fig.18b As shown, a second conductive layer 02 is formed on the semiconductor layer 06; Fig.18c As shown, a third conductive layer 03 and a fourth conductive layer 04 are sequentially formed on the second conductive layer 02; Fig.18d As shown, a fifth conductive layer 05 is formed on the fourth conductive layer 04 .

[0165] The pixel driving circuit 21 in the above example can be applied to Figure 3 , Figure 5 or Figure 6 The pixel arrangement shown. Fig.19 A layout of a pixel unit provided in an embodiment of the present disclosure, such as Fig.19 As shown, the specific Fig.18d The pixel driving circuit 21 shown is applied to Figure 3 The pixel arrangement shown.

[0166] Another possible implementation method, taking the 7T1C pixel driving circuit 21 as an example, Fig. 20 The layout of the semiconductor layer 06 provided in the embodiment of the present disclosure, Fig.21 The layout of the second conductive layer 02 provided in the embodiment of the present disclosure, Fig. 22 The layout of the third conductive layer 03 provided in the embodiment of the present disclosure, Fig.23 This is the layout of the fourth conductive layer 04 provided in the embodiment of the present disclosure.

[0167] like Fig. 20As shown, the active layer T1a of the first reset transistor T1, the active layer T2a of the threshold compensation transistor T2, the active layer T3a of the driving transistor T3, the active layer T4a of the data writing transistor T4, the active layer T5a of the first light emission control transistor T5, the active layer T6a of the second light emission control transistor T6, and the active layer T7a of the second reset transistor T7 are all located in the semiconductor layer 06.

[0168] like Fig.21 As shown, the gate T1c of the first reset transistor T1, the gate T2c of the threshold compensation transistor T2, the gate T4c of the data writing transistor T4, the gate T7c of the second reset transistor T7, the first electrode CC1 of the storage capacitor Cst, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are all located in the second conductive layer 02. Among them, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are an integrated structure (such as Fig.21 EM in ).

[0169] Exemplarily, the gate T1c of the first reset transistor T1 and the first reset control signal line Reset1 (the control signal line of the first reset transistor T1) are an integrated structure (eg Fig.21 The gate T2c of the threshold compensation transistor T2 and the second scanning signal line Ga2 (the control signal line of the threshold compensation transistor T2) are integrated (such as Fig.21 The gate T4c of the data writing transistor T4 is integrated with the first scanning signal line Ga1 (the control signal line of the data writing transistor T4) (eg Fig.21 The gate T7c of the second reset transistor T7 and the second reset control signal line Reset2 (the control signal line of the second reset transistor T7) are an integrated structure (such as Fig.21 T7c in FIG. 1). Compared with the structure in which the signal line and the gate are layered, this embodiment can save a layer of Mask process, improve process efficiency, and save process cost.

[0170] like Fig. 22 As shown, the gate of the driving transistor T3, the second plate CC2 of the storage capacitor Cst, the signal line drawn from the first reset power supply terminal Vinit1 and electrically connected to the source of the first reset transistor T1, and the signal line drawn from the second reset power supply terminal Vinit2 and electrically connected to the source of the second reset transistor T7 are all located in the third conductive layer 03. Among them, the gate of the driving transistor T3 and the second plate CC2 of the storage capacitor Cst are an integrated structure (such as Fig. 22The signal line drawn from the first reset power supply terminal Vinit1 and electrically connected to the source of the first reset transistor T1 and the signal line drawn from the second reset power supply terminal Vinit2 and electrically connected to the source of the second reset transistor T7 are an integrated structure (such as Fig. 22 in Vinit).

[0171] like Fig.23 As shown, the data line Vd is located in the fifth conductive layer 05, and the signal line (that is, the source of the first light-emitting control transistor T5) led out from the first power supply voltage terminal VDD and electrically connected to the first electrode CC1 of the storage capacitor Cst and the source of the first light-emitting control transistor T5 is also located in the fifth conductive layer 05.

[0172] For example, Figure 24a to Figure 24d for Figure 20 to Figure 23 The layout of the pixel driving circuit 21 preparation process shown in FIG. Fig.24a As shown, a semiconductor layer 06 is formed; Figure 24b As shown, a second conductive layer 02 is formed on the semiconductor layer 06; Fig.24c As shown, a third conductive layer 03 is formed on the second conductive layer 02; Fig.24d As shown, a fourth conductive layer 04 is formed on the third conductive layer 03 .

[0173] The pixel driving circuit 21 in the above example can be applied to Fig. 9 The pixel arrangement shown. Fig.25 Another pixel unit layout provided in the embodiment of the present disclosure is as follows: Fig.25 As shown, the specific Fig.24d The pixel driving circuit 21 shown is applied to Fig. 9 The pixel arrangement shown.

[0174] In some embodiments, in combination with the above embodiments, the contour shape of the orthographic projection of the first electrode of at least part of the light-emitting device on the base substrate 1 is circular.

[0175] Exemplarily, for the first electrode of each light-emitting device, the shape of its orthographic projection on the base substrate 1 can be circular, thereby improving the wiring arrangement of the real RGB pixel structure.

[0176] In some embodiments, in combination with the above embodiments, the ratio of the size of the pixel opening of each light emitting device along the column direction to the size along the row direction is in a range of 1:1 to 1:3.

[0177] Exemplarily, the ratio of the size of the pixel opening of the light emitting device in the column direction to the size in the row direction is 1:1, and it can be determined that the contour shape of the orthographic projection of the pixel opening of the light emitting device on the substrate 1 is a circle.

[0178] Exemplarily, the contour of the orthographic projection of the pixel opening of the light-emitting device on the substrate 1 includes a symmetrical figure surrounded by a plurality of arc portions and straight edges alternately, and the angles corresponding to at least two arc portions are the same. The ratio of the size of the pixel opening of the light-emitting device along the column direction to the size along the row direction is any one of 1:1 to 1:3, excluding 1:1, and it can be determined that the contour shape of the orthographic projection of the pixel opening of the light-emitting device on the substrate 1 is an ellipse, and at this time, the ratio of the size of the pixel opening of the light-emitting device along the column direction to the size along the row direction is also the ratio of the short axis to the long axis of the ellipse.

[0179] In some embodiments, the sub-pixel 22 includes a plurality of light-emitting devices; the distance between the light-emitting devices in different sub-pixels 22 is greater than the distance between the light-emitting devices in the sub-pixel 22 having the plurality of light-emitting devices.

[0180] For example, Figure 3 As shown, the blue sub-pixel 22-B includes two blue light-emitting devices B1 and B2, for example, the distance between the red light-emitting device R and the green light-emitting device G1 is greater than the distance between the blue light-emitting device B1 and the blue light-emitting device B2. Here, the distance between the red light-emitting device R and the green light-emitting device G1 can be understood as the distance between the geometric center of the pixel opening of the red light-emitting device R and the geometric center of the pixel opening of the green light-emitting device G1. The distance between the blue light-emitting device B1 and the blue light-emitting device B2 can be understood as the distance between the geometric center of the pixel opening of the blue light-emitting device B1 and the geometric center of the pixel opening of the blue light-emitting device B2. The reason why the blue sub-pixel 22-B is divided into two circular blue light-emitting devices in the embodiment of the present disclosure is that the area of ​​the pixel opening of the blue sub-pixel 22-B is large. After it is divided into two, the pixel opening of the blue light-emitting device B1 (or B2) is not much different from the pixel opening of the red light-emitting device R or the pixel opening of the green light-emitting device G1. Therefore, the four light-emitting devices can be closely distributed, thereby achieving a larger aperture ratio.

[0181] Similarly, if Figure 5 or Figure 6 As shown, for the green sub-pixel 22-G, the green sub-pixel 22-G includes two green light-emitting devices G1 and G2, for example, the distance between the red light-emitting device R and the green light-emitting device G1 is greater than the distance between the green light-emitting device G1 and the green light-emitting device G2. Here, the green sub-pixel 22-G is divided into two circular green light-emitting devices because the pixel opening area of ​​the green sub-pixel 22-G is large. After it is divided into two, the pixel opening of the green light-emitting device G1 (or G2) is not much different from the pixel opening of the red light-emitting device R or the pixel opening of the blue light-emitting device B1. Therefore, the four light-emitting devices can be closely distributed, thereby achieving a larger aperture ratio.

[0182] In some embodiments, the light-emitting layer of each light-emitting device is located on a side of the pixel defining layer PDL away from the first electrode; and the orthographic projections of the light-emitting layers of different light-emitting devices on the substrate at least partially overlap.

[0183] In some embodiments, the contour of the orthographic projection of the light-emitting layer of at least part of the light-emitting device on the substrate is circular; or, the contour of the orthographic projection of the light-emitting layer of at least part of the light-emitting device on the substrate includes a symmetrical figure surrounded by multiple arc parts and straight edges alternately, and the angles corresponding to at least two arc parts are the same. For example, it can include an ellipse, a rounded rectangle, various rounded polygons, etc., so that the diffraction image of the product is approximately circular, thereby improving the color separation phenomenon of the product and enhancing the display effect.

[0184] In some embodiments, the display substrate further includes an isolation column; the isolation column is located on a side of the pixel defining layer close to the light emitting layer, and supports a high-precision metal mask (Fine Metal Mask, FMM) to prevent damage.

[0185] In some embodiments, for a plurality of pixel units arranged in an array, an isolation column is disposed correspondingly for every 2 to 3 rows of pixel units and / or every 3 to 5 columns of pixel units.

[0186] Exemplarily, for a plurality of pixel units arranged in an array, one isolation column is provided corresponding to every 3×4 pixel units, which ensures the supporting strength and saves materials.

[0187] In some embodiments, the orthographic projection of the color block on the base substrate covers the orthographic projection of the light emitting device corresponding to the color block on the base substrate.

[0188] In some embodiments, the distance between the edge of the projection of the color resist block on the substrate and the edge of the projection of the light emitting device corresponding to the color resist block on the substrate is in the range of 1.5 μm to 10.5 μm.

[0189] In addition, the embodiment of the present disclosure further provides a display device, which includes the display substrate of any one of the above embodiments. The display device can be, for example, a tablet computer, a display, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device are understood by those of ordinary skill in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0190] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, a plurality of pixel units arranged in an array on the base substrate, and a color filter layer located on a side of the pixel unit away from the base substrate; The pixel unit includes a plurality of pixel driving circuits and a plurality of light-emitting devices arranged on the substrate; one light-emitting device is electrically connected to one pixel driving circuit to form a sub-pixel; the color filter layer includes a plurality of color block blocks, and one color block is arranged corresponding to one light-emitting device; The contour of the orthographic projection of at least part of the pixel openings of the light-emitting device on the substrate is circular; and / or, the contour of the orthographic projection of at least part of the pixel openings of the light-emitting device on the substrate includes a symmetrical figure alternately surrounded by multiple arc parts and straight edges, and the angles corresponding to at least two arc parts are the same.

2. The display substrate according to claim 1, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel; the first sub-pixel includes a first light-emitting device; the second sub-pixel includes a second light-emitting device; the third sub-pixel includes a third light-emitting device and a fourth light-emitting device; For the plurality of pixel units arranged in an array, the first light emitting devices and the second light emitting devices are alternately arranged along a column direction to form a plurality of columns of first light emitting device groups; the third light emitting devices and the fourth light emitting devices are alternately arranged along a column direction to form a plurality of columns of second light emitting device groups.

3. The display substrate according to claim 2, wherein: The outline shapes of the orthographic projections of the pixel openings of the first light-emitting device, the second light-emitting device, the third light-emitting device, and the fourth light-emitting device on the base substrate are all circular.

4. The display substrate according to claim 2, wherein: For one of the pixel units, the aperture ratio of the first sub-pixel is A, the aperture ratio of the second sub-pixel is B, and the aperture ratio of the third sub-pixel is C; A:B:C is one of 1:(1.7-2.2)(1.4-2).

5. The display substrate according to claim 4, wherein: The aperture ratio of the third light emitting device is the same as the aperture ratio of the fourth light emitting device.

6. The display substrate according to claim 1, wherein: The aperture ratio of the pixel unit ranges from 10% to 55%.

7. The display substrate according to claim 1, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel; the first sub-pixel includes a first light-emitting device; the second sub-pixel includes a second light-emitting device and a fifth light-emitting device; the third sub-pixel includes a third light-emitting device and a fourth light-emitting device; For the plurality of pixel units arranged in an array, the first light emitting devices and the second sub-pixels are alternately arranged along a column direction to form a plurality of columns of first light emitting device groups; the third light emitting devices and the fourth light emitting devices are alternately arranged along a column direction to form a plurality of columns of second light emitting device groups; An angle formed between an extension line of a line connecting the center point of the second light emitting device and the center point of the fifth light emitting device and an extension line of a line connecting the center point of the third light emitting device and the center point of the fourth light emitting device is in a range of 0° to 90°.

8. The display substrate according to claim 7, wherein: The outline shapes of the orthographic projections of the pixel openings of the first light-emitting device, the second light-emitting device, the third light-emitting device, the fourth light-emitting device, and the fifth light-emitting device on the substrate are all circular.

9. The display substrate according to claim 2 or 7, wherein: The display substrate further comprises a first conductive layer disposed on a side of the pixel driving circuit away from the base substrate and a pixel defining layer disposed on a side of the first conductive layer away from the base substrate; The light emitting device comprises a pixel opening penetrating the pixel defining layer, a first electrode formed on the pixel defining layer close to the pixel driving circuit, a light emitting layer at least located in the pixel opening, and a second electrode; The first conductive layer includes a first electrode of each of the light-emitting devices; For the third sub-pixel, the first electrode of the third light emitting device is electrically connected to the first electrode of the fourth light emitting device.

10. The display substrate according to claim 9, wherein: The first electrode of the third light emitting device and the first electrode of the fourth light emitting device are connected into an integrated structure.

11. The display substrate according to claim 9, wherein: The first electrode of the third light emitting device and the first electrode of the fourth light emitting device are disconnected; For the third sub-pixel, the pixel driving circuit includes a driving transistor and a first connecting electrode electrically connected to the driving transistor; the first connecting electrode includes a first main body, a first branch portion and a second branch portion electrically connected to the first main body respectively; the first branch portion is electrically connected to the first electrode of the third light-emitting device, and the second branch portion is electrically connected to the first electrode of the fourth light-emitting device.

12. The display substrate according to claim 9, wherein: For the second sub-pixel, the first electrode of the second light emitting device is electrically connected to the first electrode of the fifth light emitting device.

13. The display substrate according to claim 12, wherein: The first electrode of the second light emitting device and the first electrode of the fifth light emitting device are connected into an integrated structure.

14. The display substrate according to claim 12, wherein: The first electrode of the second light emitting device and the first electrode of the fifth light emitting device are disconnected; For the second sub-pixel, the pixel driving circuit includes a driving transistor and a second connecting electrode electrically connected to the driving transistor; the second connecting electrode includes a second main body, a third branch portion and a fourth branch portion electrically connected to the second main body respectively; the third branch portion is electrically connected to the first electrode of the second light-emitting device, and the fourth branch portion is electrically connected to the first electrode of the fifth light-emitting device.

15. The display substrate according to claim 1, wherein: The plurality of pixel units include a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are alternately arranged along a row direction and a column direction respectively; The first pixel unit and the second pixel unit each include a first sub-pixel, a second sub-pixel and a third sub-pixel; the first sub-pixel includes a first light-emitting device, the second sub-pixel includes a second light-emitting device, and the third sub-pixel includes a third light-emitting device; For the first pixel unit, the first light emitting device and the second light emitting device are located in the same column, and are located in an adjacent column to the third light emitting device; For the second pixel unit, the first light emitting device and the second light emitting device are located in the same row, and are located in an adjacent row to the third light emitting device; The line connecting the center point of the first light-emitting device in the first pixel unit and the center point of the second light-emitting device is a first line segment, and the line connecting the center point of the first light-emitting device in the second pixel unit and the center point of the second light-emitting device is a second line segment; the extension direction of the first line segment is perpendicular to the extension direction of the second line segment.

16. The display substrate according to claim 15, wherein: The outline shapes of the orthographic projections of the pixel openings of the first light-emitting device and the pixel openings of the second light-emitting device on the base substrate are both circular; The outline shape of the orthographic projection of the pixel opening of the third light emitting device on the base substrate is an ellipse.

17. The display substrate according to claim 16, wherein: For the first pixel unit, an extension direction of the first line segment and an extension direction of a short axis corresponding to an outline of a pixel opening of the third light-emitting device are perpendicular to each other; For the second pixel unit, an extension direction of the second line segment and an extension direction of a short axis corresponding to an outline of a pixel opening of the third light-emitting device are perpendicular to each other.

18. The display substrate according to any one of claims 1 to 8, wherein: The display substrate further comprises a semiconductor layer disposed on the base substrate, a second conductive layer disposed on a side of the semiconductor layer away from the base substrate, a third conductive layer disposed on a side of the second conductive layer away from the base substrate, and a fourth conductive layer disposed on a side of the second conductive layer close to the third conductive layer; The pixel driving circuit at least includes a plurality of thin film transistors and a storage capacitor; The active layer of each of the thin film transistors is located on the semiconductor layer; At least a portion of the gate electrode of the thin film transistor and the first electrode plate of the storage capacitor are located in the second conductive layer; The second electrode plate of the storage capacitor is located on the third conductive layer; At least part of the control signal lines of the thin film transistors are located in the fourth conductive layer.

19. The display substrate according to any one of claims 1 to 8, wherein: The outline shape of the orthographic projection of at least part of the first electrodes of the light-emitting device on the base substrate is circular.

20. The display substrate according to any one of claims 1 to 8, wherein: The ratio of the size of the pixel opening of each light emitting device along the column direction to the size along the row direction is in the range of 1:1 to 1:

3.

21. The display substrate according to any one of claims 1 to 8, wherein: The sub-pixel includes a plurality of light-emitting devices; The distance between the light emitting devices in different sub-pixels is greater than the distance between the light emitting devices in the sub-pixel having a plurality of light emitting devices.

22. The display substrate according to claim 9, wherein: The light-emitting layer of each of the light-emitting devices is located on a side of the pixel defining layer away from the first electrode; and the orthographic projections of the light-emitting layers of different light-emitting devices on the base substrate at least partially overlap.

23. The display substrate according to claim 22, wherein: The outline of the orthographic projection of the light-emitting layer of at least part of the light-emitting device on the substrate is circular; or, the outline of the orthographic projection of the light-emitting layer of at least part of the light-emitting device on the substrate is a symmetrical figure surrounded by multiple arc parts and straight edges alternating, and the angles corresponding to at least two arc parts are the same.

24. The display substrate according to any one of claims 1 to 8, wherein: The display substrate further includes an isolation column; the isolation column is located on a side of the pixel defining layer close to the light emitting layer.

25. The display substrate according to claim 23, wherein: For a plurality of pixel units arranged in an array, an isolation column is correspondingly provided for every 2 to 3 rows of pixel units and / or every 3 to 5 columns of pixel units.

26. The display substrate according to any one of claims 1 to 8, wherein: The orthographic projection of the color resist block on the base substrate covers the orthographic projection of the light emitting device corresponding to the color resist block on the base substrate.

27. The display substrate according to claim 26, wherein: The distance between the contour edge of the projection of the color resist block on the base substrate and the contour edge of the projection of the light emitting device corresponding to the color resist block on the base substrate is in the range of 1.5 μm to 10.5 μm.

28. A display device, wherein: The invention comprises the display substrate according to any one of claims 1 to 27.

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