Pixel circuit and driving method thereof, display panel and display device

Abstract

The invention discloses a pixel circuit and a driving method thereof, a display panel and a display device, and belongs to the technical field of display. In the pixel circuit, a data write-in circuit (01) can control connection and disconnection between a data end (Vdt) and a first node (N1). The reset circuit (02) can control the connection and disconnection between the first initial power supply end (Vinit1) and the second node (N2), the connection and disconnection between the second initial power supply end (Vinit2) and the light-emitting element (L1), and the connection and disconnection between the first reference power supply end (Vref1) and the first node (N1). The potential adjusting circuit (03) can control the on-off of the driving power supply end (VDD) and the third node (N3), control the on-off of the second node (N2) and the fourth node (N4), and adjust the potentials of the first node (N1), the second node (N2) and the third node (N3) through the coupling effect. The light-emitting control circuit (04) can control connection and disconnection between the second reference power supply end (Vref2) and the first node (N1) and control connection and disconnection between the fourth node (N4) and the light-emitting element (L1). The driving circuit (05) can transmit a driving signal to the fourth node (N4) based on the potential of the second node (N2) and a driving power supply signal so as to drive the light-emitting element (L1) to emit light. Therefore, reliable compensation of the threshold voltage of the driving transistor in the driving circuit (05) can be realized, and a good display effect is ensured.

Description

Pixel circuit and driving method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] A display panel generally includes a substrate and a plurality of pixels located on the substrate. Each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0003] In the related art, a pixel circuit generally includes a light-emitting control circuit and a light-emitting drive circuit. The light-emitting control circuit includes multiple control transistors, and the light-emitting drive circuit includes a drive transistor. In addition, the multiple control transistors are respectively coupled to multiple signal terminals (such as a gate signal terminal and a data terminal), and are also coupled to the gate of the drive transistor to control the potential of the gate of the drive transistor. The first electrode of the drive transistor is used to receive a drive power signal, and the second electrode of the drive transistor is coupled to the light-emitting element to transmit a drive signal to the light-emitting element based on the gate potential and the drive power signal, thereby driving the light-emitting element to emit light.

[0004] However, due to factors such as process and materials, the uniformity and stability of semiconductor characteristics such as the threshold voltage or mobility of the driving transistor are poor, resulting in an inability to reliably generate a driving signal to drive the light-emitting element to emit light, resulting in poor display effect of the display panel.

[0005] Summary of the Invention

[0006] Provided are a pixel circuit and a driving method thereof, a display panel, and a display device. The technical solution is as follows:

[0007] In one aspect, a pixel circuit is provided, comprising:

[0008] a data writing circuit, coupled to the gate signal terminal, the data terminal and the first node respectively, and configured to control the connection and disconnection between the data terminal and the first node based on a gate driving signal provided by the gate signal terminal;

[0009] a reset circuit, coupled to a reset signal terminal, a scan signal terminal, a first reference power terminal, a first initial power terminal, a second initial power terminal, the first node, the second node, and the light-emitting element, respectively, and configured to control the connection and disconnection between the first initial power terminal and the second node based on a reset signal provided by the reset signal terminal, and to control the connection and disconnection between the first reference power terminal and the first node, and to control the connection and disconnection between the second initial power terminal and the light-emitting element based on a scan signal provided by the scan signal terminal;

[0010] a potential adjustment circuit, coupled to the first compensation terminal, the second compensation terminal, the driving power supply terminal, the first node, the second node, the third node, and the fourth node, respectively, and configured to control the connection and disconnection between the driving power supply terminal and the third node based on a first compensation signal provided by the first compensation terminal, control the connection and disconnection between the second node and the fourth node based on a second compensation signal provided by the second compensation terminal, and adjust the potentials of the first node, the second node, and the third node through coupling;

[0011] a light-emitting control circuit, coupled to a light-emitting control terminal, a second reference power terminal, the first node, the fourth node, and the light-emitting element, respectively, and configured to control the connection and disconnection between the second reference power terminal and the first node, and the connection and disconnection between the fourth node and the light-emitting element, based on a light-emitting control signal provided by the light-emitting control terminal, wherein the potential of the second reference power signal provided by the second reference power terminal is lower than the potential of the first reference power signal provided by the first reference power terminal;

[0012] The driving circuit is coupled to the second node, the driving power supply terminal and the fourth node respectively, and is used to transmit a driving signal to the fourth node based on the potential of the second node and the driving power supply signal.

[0013] Optionally, the reset circuit includes:

[0014] a first reset sub-circuit, coupled to the reset signal terminal, the first initial power terminal, and the second node, respectively, and configured to control the connection and disconnection between the first initial power terminal and the second node based on the reset signal;

[0015] a second reset sub-circuit, coupled to the scan signal terminal, the first reference power terminal, and the first node, respectively, and configured to control the connection and disconnection between the first reference power terminal and the first node based on the scan signal;

[0016] The third reset subcircuit is coupled to the scan signal terminal, the second initial power terminal and the light emitting element respectively, and is used to control the on and off of the second initial power terminal and the light emitting element based on the scan signal.

[0017] Optionally, the first reset sub-circuit includes: a first transistor; the second reset sub-circuit includes: a second transistor; the third reset sub-circuit includes: a third transistor;

[0018] The gate of the first transistor is coupled to the reset signal terminal, the first electrode of the first transistor is coupled to the first initial power supply terminal, and the second electrode of the first transistor is coupled to the second node;

[0019] The gate of the second transistor is coupled to the scan signal terminal, the first electrode of the second transistor is coupled to the first reference power terminal, and the second electrode of the second transistor is coupled to the first node;

[0020] A gate of the third transistor is coupled to the scan signal terminal, a first electrode of the third transistor is coupled to the second initial power terminal, and a second electrode of the third transistor is coupled to the light emitting element.

[0021] Optionally, the potential regulating circuit includes:

[0022] a switch sub-circuit, coupled to the first compensation terminal, the driving power terminal, and the third node, respectively, and configured to control the connection and disconnection between the driving power terminal and the third node based on the first compensation signal;

[0023] a compensation sub-circuit, coupled to the second compensation terminal, the second node, and the fourth node, respectively, and configured to control connection and disconnection between the second node and the fourth node based on the second compensation signal;

[0024] The regulating subcircuit is coupled to the first node, the second node and the third node respectively, and is used to regulate the potentials of the first node, the second node and the third node through coupling.

[0025] Optionally, the switch subcircuit includes: a fourth transistor; the compensation subcircuit includes: a fifth transistor; the regulation subcircuit includes: a first capacitor and a second capacitor;

[0026] The gate of the fourth transistor is coupled to the first compensation terminal, the first electrode of the fourth transistor is coupled to the driving power supply terminal, and the second electrode of the fourth transistor is coupled to the third node;

[0027] The gate of the fifth transistor is coupled to the second compensation terminal, the first electrode of the fifth transistor is coupled to the fourth node, and the second electrode of the fifth transistor is coupled to the second node;

[0028] The first capacitor is connected in series between the first node and the third node;

[0029] The second capacitor is connected in series between the third node and the second node.

[0030] Optionally, the light emitting control circuit includes:

[0031] a first light-emitting control subcircuit, coupled to the light-emitting control terminal, the second reference power terminal, and the first node, respectively, and configured to control the connection and disconnection between the second reference power terminal and the first node based on the light-emitting control signal;

[0032] The second light-emitting control subcircuit is coupled to the light-emitting control terminal, the fourth node and the light-emitting element respectively, and is used to control the on-off of the fourth node and the light-emitting element based on the light-emitting control signal.

[0033] Optionally, the first light emitting control subcircuit includes: a sixth transistor; the second light emitting control subcircuit includes: a seventh transistor;

[0034] The gate of the sixth transistor is coupled to the light emitting control terminal, the first electrode of the sixth transistor is coupled to the second reference power supply terminal, and the second electrode of the sixth transistor is coupled to the first node;

[0035] A gate of the seventh transistor is coupled to the light emitting control terminal, a first electrode of the seventh transistor is coupled to the fourth node, and a second electrode of the seventh transistor is coupled to the light emitting element.

[0036] Optionally, the pixel circuit further includes:

[0037] an anti-leakage circuit, coupled to the first compensation terminal, the second node, and the fifth node, respectively, and configured to control connection and disconnection between the second node and the fifth node based on the first compensation signal;

[0038] The potential regulating circuit is further coupled to the fifth node, and the driving circuit is coupled to the second node via the fifth node.

[0039] Optionally, the anti-leakage circuit includes: an eighth transistor;

[0040] A gate of the eighth transistor is coupled to the first compensation terminal, a first electrode of the eighth transistor is coupled to the fifth node, and a second electrode of the eighth transistor is coupled to the second node.

[0041] Optionally, in the reset circuit, the materials of the transistor that controls the on / off connection between the first initial power supply terminal and the second node, and the materials of the transistor that controls the on / off connection between the fourth node and the second node in the potential adjustment circuit both include: low-temperature polysilicon material; the material of the transistor in the anti-leakage circuit includes: oxide material.

[0042] Optionally, the data writing circuit includes: a ninth transistor; the driving circuit includes: a tenth transistor;

[0043] The gate of the ninth transistor is coupled to the gate signal terminal, the first electrode of the ninth transistor is coupled to the driving power supply terminal, and the second electrode of the ninth transistor is coupled to the first node;

[0044] A gate of the tenth transistor is coupled to the second node, a first electrode of the tenth transistor is coupled to the driving power supply terminal, and a second electrode of the tenth transistor is coupled to the fourth node.

[0045] In another aspect, a method for driving a pixel circuit is provided, which is applied to the pixel circuit according to the above aspect, and the method includes:

[0046] In the first stage, the reset circuit controls the first initial power supply terminal to be conductively connected to the second node based on a reset signal provided by the reset signal terminal, controls the first reference power supply terminal to be conductively connected to the first node based on a scan signal provided by the scan signal terminal, and controls the second initial power supply terminal to be conductively connected to the light-emitting element, and the potential adjustment circuit controls the driving power supply terminal to be conductively connected to the third node based on a first compensation signal provided by the first compensation terminal;

[0047] In the second stage, the reset circuit controls the first reference power supply terminal to be electrically conductive with the first node, and controls the second initial power supply terminal to be electrically conductive with the light-emitting element, based on the scan signal; the potential adjustment circuit controls the driving power supply terminal to be electrically conductive with the third node, based on the first compensation signal, and controls the second node to be electrically conductive with the fourth node, based on the second compensation signal provided by the second compensation terminal;

[0048] In the third stage, the data writing circuit controls the data terminal to be connected to the first node based on the gate driving signal provided by the gate signal terminal, and the potential adjustment circuit controls the driving power terminal to be connected to the third node based on the first compensation signal, and controls the second node to be connected to the fourth node based on the second compensation signal;

[0049] In the fourth stage, the light control circuit controls the second reference power supply terminal to be electrically connected to the first node, and controls the fourth node to be electrically connected to the light-emitting element based on the light control signal provided by the light control terminal. The driving circuit transmits a driving signal to the fourth node based on the potential of the second node and the driving power signal provided by the driving power supply terminal, so as to drive the light-emitting element to emit light.

[0050] In the fifth stage, the reset circuit controls the first reference power supply terminal to be conductively connected to the first node, and controls the second initial power supply terminal to be conductively connected to the light-emitting element based on the scan signal;

[0051] The potential of the second reference power signal provided by the second reference power terminal is lower than the potential of the first reference power signal provided by the first reference power terminal;

[0052] Furthermore, the first stage, the second stage, the third stage, the fourth stage and the fifth stage are executed sequentially; and in each stage, the potential regulating circuit regulates the potentials of the first node, the second node and the third node through coupling.

[0053] Optionally, the pixel circuit further includes: an anti-leakage circuit; the method further includes: during the first stage to the third stage, the anti-leakage circuit controlling the second node and the fifth node to be conductive based on the first compensation signal;

[0054] The potential regulating circuit is further coupled to the fifth node, and the driving circuit is coupled to the second node via the fifth node.

[0055] In yet another aspect, a display panel is provided, comprising: a substrate, and a plurality of pixels located on one side of the substrate;

[0056] The pixel includes: a light-emitting element, and the pixel circuit as described in the above aspect, wherein the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0057] In another aspect, a display device is provided, comprising: a signal providing circuit, and the display panel according to the above-mentioned further aspect;

[0058] The signal providing circuit is coupled to a plurality of signal terminals coupled to the pixel circuit in the display panel, and is used to provide signals to the plurality of signal terminals to control the pixel circuit to drive the coupled light-emitting element to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0060] FIG1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0061] FIG2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0062] FIG3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0063] FIG4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0065] FIG6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0066] FIG7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0067] FIG8 is a flow chart of a driving method for a pixel circuit provided by an embodiment of the present disclosure;

[0068] FIG9 is a signal timing diagram based on the pixel circuit shown in FIG6 provided by an embodiment of the present disclosure;

[0069] FIG10 is a signal timing diagram based on the pixel circuit shown in FIG7 provided by an embodiment of the present disclosure;

[0070] FIG11 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0071] FIG12 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0073] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode, and the drain is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the control electrode, which can also be referred to as the gate, the signal input end is designated as the source electrode, and the signal output end is designated as the drain electrode. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two state variables and do not imply that the first potential or the second potential has a specific value throughout the text.

[0074] Organic light-emitting diode (OLED) displays are currently a hot topic in display research. Compared to liquid crystal displays (LCDs), OLED displays offer advantages such as low energy consumption, low cost, self-luminescence, wide viewing angles, and fast response times. OLED displays typically use pixel circuits to drive the OLED light. Furthermore, with the advancement of display technology, the application scope of OLED displays has gradually expanded from small and medium-sized watches, mobile phones, and tablets to large-scale personal computers (PCs) and monitors. Large-scale displays are characterized by their high pixel count (PPI), or resolution. Furthermore, because large-scale displays are used in a wide variety of scenarios, their refresh rate requirements also vary significantly. For example, for text reading or power-saving mode, the required refresh rate is generally below 10 Hz; for web browsing and video viewing, the required refresh rate is generally between 48 Hz and 60 Hz; and for gaming, the required refresh rate can reach 120 Hz to 144 Hz, or even 240 Hz or higher. Therefore, the display needs to have good display effects at refresh rates ranging from a few Hz to several hundred Hz.

[0075] At present, common pixel circuits are all 7T1C (i.e., including 7 transistors and 1 capacitor) structures, and data writing and compensation threshold voltage Vth are completed simultaneously by the same device in the pixel circuit. As a result, Vth cannot be reliably compensated in a short time (such as high frame rate). At the same time, the impact of the unevenness of the driving transistor characteristics in the pixel circuit on data writing is also amplified, resulting in a significant decrease in the display quality of the display. Therefore, it is urgent to find other compensation methods to improve the accuracy of data writing and compensation time, thereby improving the display quality of the display.

[0076] The disclosed embodiments provide a novel pixel circuit that can drive a light-emitting element to emit light by separating data writing and Vth compensation. This allows Vth compensation to be unconstrained by the data writing time, resulting in better compensation in a shorter time (e.g., at high resolution and high frame rate). Furthermore, the disclosed embodiments provide a pixel circuit that can flexibly adjust the gate potential of the drive transistor, reliably resetting the drive transistor to its off state at low frame rates, ensuring better display stability at low frame rates.

[0077] FIG1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in FIG1 , the pixel circuit includes: a data writing circuit 01 , a reset circuit 02 , a potential adjustment circuit 03 , a light emitting control circuit 04 , and a driving circuit 05 .

[0078] The data writing circuit 01 is coupled to the gate signal terminal Sn, the data terminal Vdt and the first node N1 respectively and is used to control the connection between the data terminal Vdt and the first node N1 based on the gate driving signal provided by the gate signal terminal Sn.

[0079] For example, the data writing circuit 01 can control the data terminal Vdt to be connected to the first node N1 when the potential of the gate driving signal provided by the gate signal terminal Sn is a first potential, so that the data signal provided by the data terminal Vdt can be transmitted to the first node N1 to charge the first node N1. Furthermore, the data writing circuit 01 can control the data terminal Vdt to be disconnected from the first node N1 when the potential of the gate driving signal provided by the gate signal terminal Sn is a second potential.

[0080] Optionally, in the embodiment of the present disclosure, the first potential may be an effective potential, the second potential may be an ineffective potential, and the first potential may be a low potential relative to the second potential. Of course, in some other embodiments, the first potential may be a high potential relative to the second potential.

[0081] The reset circuit 02 is coupled to the reset signal terminal Re, the scan signal terminal Scan, the first reference power terminal Vref1, the first initial power terminal Vinit1, the second initial power terminal Vinit2, the first node N1, the second node N2, and the light-emitting element L1. The reset circuit 02 is configured to control the connection between the first initial power terminal Vinit1 and the second node N2 based on a reset signal provided by the reset signal terminal Re, and to control the connection between the first reference power terminal Vref1 and the first node N1, and to control the connection between the second initial power terminal Vinit2 and the light-emitting element L1 based on a scan signal provided by the scan signal terminal Scan.

[0082] For example, when the potential of the reset signal provided by the reset signal terminal Re is a first potential, the reset circuit 02 can control the first initial power supply terminal Vinit1 to be conductive with the second node N2, so that the first initial power supply signal provided by the first initial power supply terminal Vinit1 can be transmitted to the second node N2, thereby resetting the second node N2. Furthermore, when the potential of the reset signal provided by the reset signal terminal Re is a second potential, the reset circuit 02 can control the first initial power supply terminal Vinit1 to be decoupled from the second node N2.

[0083] Similarly, when the potential of the scan signal provided by the scan signal terminal Scan is the first potential, the reset circuit 02 can control the first reference power terminal Vref1 to be conductively connected to the first node N1, so that the first reference power signal provided by the first reference power terminal Vref1 can be transmitted to the first node N1, thereby resetting the first node N1. The reset circuit 02 can also control the second initial power terminal Vinit2 to be conductively connected to the light-emitting element L1, so that the second initial power signal provided by the second initial power terminal Vinit2 can be transmitted to the light-emitting element L1, thereby resetting the light-emitting element L1. Furthermore, when the potential of the scan signal provided by the scan signal terminal Scan is the first potential, the reset circuit 02 can control the first reference power terminal Vref1 to be decoupled from the first node N1, and the second initial power terminal Vinit2 to be decoupled from the light-emitting element L1.

[0084] The potential adjustment circuit 03 is coupled to the first compensation terminal AZ1, the second compensation terminal AZ2, the driving power supply terminal VDD, the first node N1, the second node N2, the third node N3, and the fourth node N4, respectively. The potential adjustment circuit 03 is configured to control the connection between the driving power supply terminal VDD and the third node N3 based on a first compensation signal provided by the first compensation terminal AZ1, and to control the connection between the second node N2 and the fourth node N4 based on a second compensation signal provided by the second compensation terminal AZ2. Furthermore, through coupling, the potentials of the first node N1, the second node N2, and the third node N3 are adjusted.

[0085] For example, when the potential of the first compensation signal provided by the first compensation terminal AZ1 is at a first potential, the potential adjustment circuit 03 can control the driving power supply terminal VDD to be conductive with the third node N3, so that the driving power signal provided by the driving power supply terminal VDD can be transmitted to the third node N3 to charge the third node N3. Furthermore, when the potential of the first compensation signal provided by the first compensation terminal AZ1 is at a second potential, the potential adjustment circuit 03 can control the driving power supply terminal VDD to be decoupled from the third node N3.

[0086] Similarly, the potential adjustment circuit 03 can control the second node N2 and the fourth node N4 to be conductive when the potential of the second compensation signal provided by the second compensation terminal AZ2 is the first potential, so that the potentials of the second node N2 and the fourth node N4 affect each other. That is, the potential of one node is adjusted according to the potential of the other node. Furthermore, the potential adjustment circuit 03 can control the second node N2 to be decoupled from the fourth node N4 when the potential of the second compensation signal provided by the second compensation terminal AZ2 is the second potential.

[0087] The light-emitting control circuit 04 is coupled to the light-emitting control terminal EM, the second reference power terminal Vref2, the first node N1, the fourth node N4, and the light-emitting element L1. The light-emitting control circuit 04 is configured to control the connection between the second reference power terminal Vref2 and the first node N1, and the connection between the fourth node N4 and the light-emitting element L1, based on a light-emitting control signal provided by the light-emitting control terminal EM.

[0088] For example, when the potential of the light-emitting control signal provided by the light-emitting control terminal EM is a first potential, the light-emitting control circuit 04 can control the second reference power supply terminal Vref2 to be electrically connected to the first node N1, so that the potential of the second reference power supply signal provided by the second reference power supply terminal Vref2 is transmitted to the first node N1, resetting the first node N1. The light-emitting control circuit 04 can also control the fourth node N4 to be electrically connected to the light-emitting element L1, so that the potential of the fourth node N4 can be transmitted to the light-emitting element L1, driving the light-emitting element L1 to reliably emit light. Furthermore, when the potential of the light-emitting control signal provided by the light-emitting control terminal EM is a second potential, the light-emitting control circuit 04 can control the second reference power supply terminal Vref2 to be disconnected from the first node N1, and the fourth node N4 to be disconnected from the light-emitting element L1.

[0089] The driving circuit 05 is coupled to the second node N2, the driving power supply terminal VDD, and the fourth node N4, respectively. The driving circuit 05 is configured to transmit a driving signal (e.g., a driving current) to the fourth node N4 based on the potential of the second node N2 and the driving power supply signal. When the light-emitting control circuit 04 controls the fourth node N4 and the light-emitting element L1 to be conductive, the driving signal transmitted to the fourth node N4 can be further transmitted to the light-emitting element L1, thereby driving the light-emitting element L1 to emit light.

[0090] Optionally, as shown in FIG1 , both the reset circuit 02 and the drive circuit 05 can be coupled to the first electrode of the light-emitting element L1. Furthermore, the second electrode of the light-emitting element L1 can also be coupled to the pull-down power supply terminal VSS. The light-emitting element L1 can emit light in response to the potential difference between the first electrode and the second electrode. Furthermore, one of the first electrode and the second electrode of the light-emitting element L1 can be an anode, and the other can be a cathode. In the structure shown in FIG1 , the first electrode of the light-emitting element L1 serves as an anode, and the second electrode serves as a cathode.

[0091] Combined with the working principles of each of the above circuits, it can be seen that in the embodiment of the present disclosure, the data write circuit 01 can write a data signal to the first node N1 based on the gate drive signal, and the potential adjustment circuit 03 can write a driving power signal to the third node N3 based on the compensation signal, control the on and off of the second node N2 and the fourth node N4, and adjust the potentials of the first node N1, the second node N2 and the third node N3 through coupling, so that the threshold voltage Vth of the driving transistor in the driving circuit 05 can be reliably written to the second node N2, thereby making the subsequent driving signal generated by the driving circuit 05 independent of the threshold voltage Vth, thereby achieving compensation for the threshold voltage Vth. Combined with Figure 1, it can be seen that in the pixel circuit recorded in the embodiment of the present disclosure, the circuit for performing data writing and the circuit for performing threshold voltage Vth compensation can be independent of each other, that is, data writing and threshold voltage Vth compensation can be performed by different circuits. On this basis, the signals provided by each signal terminal can be flexibly set to reliably separate the actions of data writing and threshold voltage compensation. Furthermore, the compensation time for the threshold voltage Vth is no longer limited by the data writing time, and a better compensation effect can be achieved in a shorter time, ensuring a better display effect.

[0092] In addition, in the embodiment of the present disclosure, the potential of the second reference power signal provided by the second reference power terminal Vref2 may be lower than the potential of the first reference power signal provided by the first reference power terminal Vref1 .

[0093] For example, the potential Vref10 of the first reference power signal may be approximately 5V to 7V; and the potential Vref20 of the second reference power signal may be approximately 2V to 4V.

[0094] It should be noted that during the display process, the light-emitting element L1 and the driving transistor included in the driving circuit 05 need to be reset at a higher frequency to compensate for the brightness difference caused by device aging during the light-emitting process of the light-emitting element L1. In addition, this reset action also needs to be performed at a low frame rate. Accordingly, the refresh of a frame is usually divided into a refresh frame stage and a hold frame stage, which are executed in sequence. In the refresh frame stage, data signals can be written, and the threshold voltage Vth can be compensated and the light-emitting element L1 can be driven to emit light. In the hold frame stage, only the light-emitting element L1 and the driving transistor can be reset.

[0095] In this manner, on the basis of setting the potential Vref10 of the first reference power signal provided by the first reference power terminal Vref1 to be greater than the potential Vref20 of the second reference power signal provided by the second reference power terminal Vref2, during the hold frame phase, the light-emitting control terminal EM is set high (i.e., the potential of the light-emitting control signal is controlled to be an invalid potential) and the scan signal terminal Scan is set low (i.e., the potential of the scan signal is controlled to be an effective potential). The light-emitting control circuit 04 controls the fourth node N4 to be disconnected from the light-emitting element L1 and the second reference power terminal Vref2 to be disconnected from the first node N1. The reset circuit 02 controls the first reference power terminal Vref1 to be conductive with the first node N1 and controls the second initial power terminal Vinit2 to be conductive with the light-emitting element L1. Furthermore, of the first reference power supply terminal Vref1 and the second reference power supply terminal Vref2, the first reference power supply terminal Vref1, which provides a sufficiently high potential, can transmit a first reference power supply signal Vref10 to the first node N1. The potential adjustment circuit O3 then raises the potential of the second node N2, ensuring that the driving transistor can be reliably turned off and resetting the driving transistor to its off state. Furthermore, the second initial power supply terminal Vinit2 can transmit a second initial power supply signal to the light-emitting element L1, reliably resetting the light-emitting element L1. This control method ensures good display stability of the light-emitting element at low frame rates.

[0096] Afterwards, when the light-emitting element L1 needs to begin emitting light normally, the light-emission control terminal EM can be set low (i.e., the potential of the light-emission control signal is controlled to be an effective potential), and the scan signal terminal Scan can be set high (i.e., the potential of the scan signal is controlled to be an inactive potential). The light-emission control circuit 04 controls the second reference power supply terminal Vref2 to be conductively connected to the first node N1, and controls the fourth node N4 to be conductively connected to the light-emitting element L1. The reset circuit 02 controls the first reference power supply terminal Vref1 to be disconnected from the first node N1, and controls the second initial power supply terminal Vinit2 to be disconnected from the light-emitting element L1. Furthermore, the second reference power supply terminal Vref2, which provides the lower potential between the first reference power supply terminal Vref1 and the second reference power supply terminal Vref2, can transmit the second reference power supply signal to the first node N1, thereby restoring the potential of the first node N1 to the potential of the second reference power supply signal Vref20. In addition, since only the potential of the first node N1 changes, according to the law of conservation of charge, under the control of the potential adjustment circuit 03, the potential of the second node N2 can be quickly restored to the normal luminous potential, ensuring that the driving circuit 05 can reliably drive the light-emitting element L1 to emit light based on the potential of the second node N2.

[0097] In summary, the embodiment of the present disclosure provides a pixel circuit, in which the data writing circuit can control the on-off connection between the data terminal and the first node based on the gate drive signal. The reset circuit can control the on-off connection between the initial power supply terminal and the second node and the light-emitting element based on the reset signal and the scan signal, and control the on-off connection between the reference power supply terminal and the first node. The potential adjustment circuit can control the on-off connection between the driving power supply terminal and the third node based on the compensation signal, and control the on-off connection between the second node and the fourth node, and can adjust the potential of the first node, the second node and the third node through coupling. The light-emitting control circuit can control the on-off connection between the reference power supply terminal and the first node based on the light-emitting control signal, and control the on-off connection between the fourth node and the light-emitting element. The driving circuit can transmit a driving signal to the fourth node based on the potential of the second node and the driving power signal to drive the light-emitting element to emit light. In this way, by flexibly setting the signals provided by each signal terminal, reliable compensation for the threshold voltage of the driving transistor in the driving circuit can be achieved, ensuring a better display effect.

[0098] In addition, because data is written directly to the second node under the coupling effect of the potential adjustment circuit, without having to go through the drive circuit to write to the second node, data writing and threshold voltage compensation can be achieved through different paths and different circuits. This allows data writing and threshold voltage compensation to be separated from each other and not affect each other, ensuring effective compensation of the threshold voltage and further ensuring a better display effect. Furthermore, based on the flexible setting of the reference power supply signals provided by the first reference power supply terminal and the second reference power supply terminal, a reference power supply signal with a larger potential can be written to the gate of the drive transistor in the drive circuit while maintaining the frame, ensuring reliable off-state reset of the drive transistor, thereby ensuring better display stability, especially ensuring better display stability at low frame rates.

[0099] FIG2 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure. As shown in FIG2 , the reset circuit 02 may include: a first reset sub-circuit 021 , a second reset sub-circuit 022 , and a third reset sub-circuit 023 .

[0100] The first reset sub-circuit 021 can be coupled to the reset signal terminal Re, the first initial power terminal Vinit1 and the second node N2 respectively. The first reset sub-circuit 021 can be used to control the connection between the first initial power terminal Vinit1 and the second node N2 based on the reset signal.

[0101] For example, the first reset sub-circuit 021 can control the first initial power supply terminal Vinit1 to be connected to the second node N2 when the potential of the reset signal is the first potential, and can control the first initial power supply terminal Vinit1 to be disconnected from the second node N when the potential of the reset signal is the second potential.

[0102] The second reset sub-circuit 022 can be coupled to the scan signal terminal Scan, the first reference power terminal Vref1 and the first node N1 respectively. The second reset sub-circuit 022 can be used to control the connection between the first reference power terminal Vref1 and the first node N1 based on the scan signal.

[0103] For example, the second reset subcircuit 022 can control the first reference power supply terminal Vref1 to be connected to the first node N1 when the potential of the scan signal is the first potential, and can control the first reference power supply terminal Vref1 to be disconnected from the first node N1 when the potential of the scan signal is the second potential.

[0104] The third reset sub-circuit 023 can be coupled to the scan signal terminal Scan, the second initial power terminal Vinit2, and the light-emitting element L1, respectively. The third reset sub-circuit 023 can be used to control the connection between the second initial power terminal Vinit2 and the light-emitting element L1 based on the scan signal. Alternatively, as described in the above embodiment, the third reset sub-circuit 023 can be coupled to the anode of the light-emitting element L1 to control the connection between the second initial power terminal Vinit2 and the anode of the light-emitting element L1.

[0105] For example, the third reset subcircuit 023 can control the second initial power supply terminal Vinit2 to be connected to the light-emitting element L1 when the potential of the scan signal is the first potential, and can control the second initial power supply terminal Vinit2 to be disconnected from the light-emitting element L1 when the potential of the scan signal is the second potential.

[0106] FIG3 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG3 , the potential adjustment circuit 03 may include: a switch sub-circuit 031 , a compensation sub-circuit 032 , and an adjustment sub-circuit 033 .

[0107] The switch sub-circuit 031 can be coupled to the first compensation terminal AZ1, the driving power terminal VDD and the third node N3 respectively. The switch sub-circuit 031 can be used to control the connection between the driving power terminal VDD and the third node N3 based on the first compensation signal.

[0108] For example, the switch sub-circuit 031 can control the driving power supply terminal VDD and the third node N3 to be connected when the potential of the first compensation signal is the first potential, and can control the driving power supply terminal VDD and the third node N3 to be disconnected when the potential of the first compensation signal is the second potential.

[0109] The compensation sub-circuit 032 can be coupled to the second compensation terminal AZ2, the second node N2, and the fourth node N4, respectively. The compensation sub-circuit 032 can be used to control the connection between the second node N2 and the fourth node N4 based on the second compensation signal.

[0110] For example, the compensation sub-circuit 032 can control the second node N2 and the fourth node N4 to be conductive when the potential of the second compensation signal is the first potential, and can control the second node N2 and the fourth node N4 to be decoupled when the potential of the second compensation signal is the second potential.

[0111] The regulating sub-circuit 033 can be coupled to the first node N1, the second node N2 and the third node N3 respectively. The regulating sub-circuit 033 can be used to regulate the potentials of the first node N1, the second node N2 and the third node N3 through coupling.

[0112] FIG4 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG4 , the light emitting control circuit 04 may include: a first light emitting control sub-circuit 041 and a second light emitting control sub-circuit 042 .

[0113] The first light control subcircuit 041 can be coupled to the light control terminal EM, the second reference power terminal Vref2 and the first node N1 respectively. The first light control subcircuit 041 can be used to control the connection between the second reference power terminal Vref2 and the first node N1 based on the light control signal.

[0114] For example, the first light-emitting control subcircuit 041 can control the second reference power supply terminal Vref2 to be connected to the first node N1 when the potential of the light-emitting control signal is the first potential, and can control the second reference power supply terminal Vref2 to be disconnected from the first node N1 when the potential of the light-emitting control signal is the second potential.

[0115] The second light-emission control subcircuit 042 can be coupled to the light-emission control terminal EM, the fourth node N4, and the light-emitting element L1, respectively. The second light-emission control subcircuit 042 can be used to control the connection between the fourth node N4 and the light-emitting element L1 based on the light-emission control signal. Optionally, as described in the above embodiment, the second light-emission control subcircuit 042 can be coupled to the anode of the light-emitting element L1 and control the connection between the fourth node N4 and the anode of the light-emitting element L1.

[0116] For example, the second light-emitting control subcircuit 042 can control the fourth node N4 and the light-emitting element L1 to be turned on when the potential of the light-emitting control signal is the first potential, and can control the fourth node N4 and the light-emitting element L1 to be disconnected when the potential of the light-emitting control signal is the second potential.

[0117] FIG5 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG5 , the pixel circuit described in the embodiment of the present disclosure may further include: an anti-leakage circuit 06 .

[0118] The leakage prevention circuit 06 can be coupled to the first compensation terminal AZ1, the second node N2 and the fifth node N5 respectively. The leakage prevention circuit 06 can be used to control the connection and disconnection of the second node N2 and the fifth node N5 based on the first compensation signal.

[0119] For example, the leakage protection circuit 06 can control the second node N2 and the fifth node N5 to be conductive when the potential of the first compensation signal is the first potential, and can control the second node N2 and the fifth node N5 to be decoupled when the potential of the first compensation signal is the second potential.

[0120] Based on this, referring to FIG. 5 , it can be seen that the potential adjustment circuit 03 can also be coupled to the fifth node N5. For example, the compensation sub-circuit 032 and the adjustment sub-circuit 033 in the potential adjustment circuit 03 can be coupled to the fifth node N5. Furthermore, the drive circuit 05 can be coupled to the second node N2 via the fifth node N5. In other words, the drive circuit 05 can be indirectly coupled to the second node N2 via the leakage prevention circuit 06.

[0121] Furthermore, the potential adjustment circuit 03 can control the fourth node N4 to be electrically connected to the second node N2 when the potential of the second compensation signal is the first potential. Based on this, when the leakage prevention circuit 06 controls the second node N2 to be electrically connected to the fifth node N5, the fourth node N4 can be indirectly electrically connected to the fifth node N5. Similarly, when the leakage prevention circuit 06 controls the second node N2 to be electrically connected to the fifth node N5, the first initial power supply terminal Vinit1 can be indirectly electrically connected to the fifth node N5. The potential adjustment circuit 03 can control the fourth node N4 to be decoupled from the fifth node N5 when the potential of the second compensation signal is the second potential. Furthermore, the potential adjustment circuit 03 can adjust the potentials of the first node N1, the third node N3, and the fifth node N5.

[0122] Based on the above embodiments, it can be seen that by providing the leakage prevention circuit 06, the driving circuit 05 can be indirectly coupled to the second node N2, and the first initial power supply terminal Vinit1 and the fourth node N4 can be indirectly connected to and disconnected from the fifth node N5 via the second node N2. In this way, the potential of the fifth node N5 (e.g., the gate of the driving transistor) can be prevented from leaking, that is, the potential stability of the fifth node N5 is improved.

[0123] Taking the structure shown in Figure 4 as an example, Figure 6 shows a schematic diagram of a circuit structure of a pixel circuit. Taking the structure shown in Figure 5 as an example, Figure 7 shows a schematic diagram of a circuit structure of another pixel circuit.

[0124] 6 and 7 , it can be seen that in the embodiment of the present disclosure, the first reset sub-circuit 021 may include: a first transistor T1 , the second reset sub-circuit 022 may include: a second transistor T2 , and the third reset sub-circuit 023 may include: a third transistor T3 .

[0125] A gate of the first transistor T1 may be coupled to the reset signal terminal Re, a first electrode of the first transistor T1 may be coupled to the first initial power terminal Vinit1 , and a second electrode of the first transistor T1 may be coupled to the second node N2 .

[0126] A gate of the second transistor T2 may be coupled to the scan signal terminal Scan, a first electrode of the second transistor T2 may be coupled to the first reference power terminal Vref1 , and a second electrode of the second transistor T2 may be coupled to the first node N1 .

[0127] The gate of the third transistor T3 can be coupled to the scan signal terminal Scan, the first electrode of the third transistor T3 can be coupled to the second initial power supply terminal Vinit2, and the second electrode of the third transistor T3 can be coupled to the light-emitting element L1. Optionally, as described in the above embodiment, the second electrode of the third transistor T3 can be coupled to the anode of the light-emitting element L1.

[0128] Optionally, referring to FIG6 and FIG7 , it can be seen that the switch sub-circuit 031 may include a fourth transistor T4 , the compensation sub-circuit 032 may include a fifth transistor T5 , and the regulation sub-circuit 033 may include a first capacitor C1 and a second capacitor C2 .

[0129] A gate of the fourth transistor T4 may be coupled to the first compensation terminal AZ1 , a first electrode of the fourth transistor T4 may be coupled to the driving power supply terminal VDD, and a second electrode of the fourth transistor T4 may be coupled to the third node N3 .

[0130] A gate of the fifth transistor T5 may be coupled to the second compensation terminal AZ2 , a first electrode of the fifth transistor T5 may be coupled to the fourth node N4 , and a second electrode of the fifth transistor T5 may be coupled to the second node N2 .

[0131] The first capacitor C1 may be connected in series between the first node N1 and the third node N3. The first capacitor C1 may also be referred to as a node potential storage capacitor Cst.

[0132] The second capacitor C2 may be connected in series between the third node N3 and the second node N2. The second capacitor C2 may also be referred to as a threshold voltage storage capacitor Cvth.

[0133] Among them, when the first reference power supply terminal Vref1 transmits a first reference power supply signal with a relatively large potential to the first node N1 through the second transistor T2, the potential of the third node N3 can be synchronously raised through the node potential storage capacitor Cst, and the gate potential of the driving transistor (i.e., the tenth transistor T10) can be increased through the threshold voltage storage capacitor Cvth, thereby ensuring reliable off-state resetting of the driving transistor and improving the display stability of the display panel at low frame rates.

[0134] Optionally, referring to FIG6 and FIG7 , it can be seen that the first light emitting control subcircuit 041 may include a sixth transistor T6 , and the second light emitting control subcircuit 042 may include a seventh transistor T7 .

[0135] A gate of the sixth transistor T6 may be coupled to the light emitting control terminal EM, a first electrode of the sixth transistor T6 may be coupled to the second reference power supply terminal Vref2 , and a second electrode of the sixth transistor T6 may be coupled to the first node N1 .

[0136] The gate of the seventh transistor T7 can be coupled to the light emitting control terminal EM, the first electrode of the seventh transistor T7 can be coupled to the fourth node N4, and the second electrode of the seventh transistor T7 can be coupled to the light emitting element L1. Optionally, as described in the above embodiment, the second electrode of the seventh transistor T7 can be coupled to the anode of the light emitting element L1.

[0137] Optionally, referring to FIG6 and FIG7 , it can be seen that the data writing circuit 01 may include a ninth transistor T9 , and the driving circuit 05 may include a tenth transistor T10 (ie, a driving transistor).

[0138] A gate of the ninth transistor T9 may be coupled to the gate signal terminal Sn, a first electrode of the ninth transistor T9 may be coupled to the driving power supply terminal VDD, and a second electrode of the ninth transistor T9 may be coupled to the first node N1.

[0139] A gate of the tenth transistor T10 may be coupled to the second node N2 , a first electrode of the tenth transistor T10 may be coupled to the driving power supply terminal VDD, and a second electrode of the tenth transistor T10 may be coupled to the fourth node N4 .

[0140] Optionally, referring to FIG. 7 , it can be seen that the leakage protection circuit 06 may include: an eighth transistor T8 .

[0141] A gate of the eighth transistor T8 may be coupled to the first compensation terminal AZ1 , a first electrode of the eighth transistor T8 may be coupled to the fifth node N5 , and a second electrode of the eighth transistor T8 may be coupled to the second node N2 .

[0142] Comparing FIG6 and FIG7 , it can be seen that, without the leakage protection circuit 06, the other end of the second capacitor C2 and the gate of the tenth transistor T10 can both be directly coupled to the second node N2. When the leakage protection circuit 06 is included, the other end of the second capacitor C2 and the gate of the tenth transistor T10 can both be indirectly coupled to the second node N2 via the eighth transistor T8.

[0143] Optionally, in the embodiment of the present disclosure, on the basis of setting up the anti-leakage circuit 06, in the reset circuit 02, the materials of the transistor that controls the on-off connection between the first initial power supply terminal Vinit1 and the second node N2 (i.e., the first transistor T1), and the transistor that controls the on-off connection between the fourth node N4 and the second node N2 in the potential adjustment circuit 03 (i.e., the fifth transistor T5) can both include: low temperature polysilicon (LTPS) material. The material of the transistor in the anti-leakage circuit 06 (i.e., the eighth transistor T8) can include: oxide material. In addition, like the eighth transistor T8, the material of the fourth transistor T4 coupled to the first compensation terminal AZ1 can also include oxide material. It should be noted that the materials of the transistors here all refer to the materials of the active layers included in the transistors.

[0144] Optionally, with continued reference to FIG7 , it can be seen that the first transistor T1 and the fifth transistor T5 made of LTPO material can both be P-type transistors; the eighth transistor T8 and the fourth transistor T4 made of oxide material can both be N-type transistors. In addition, all transistors except the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 can be P-type transistors. And, with continued reference to FIG6 , it can be seen that each transistor in the pixel circuit shown therein can be a P-type transistor. The material of the P-type transistor can be the LTPS material described in the above embodiment. That is, the pixel circuit shown in FIG6 can be a circuit with an LTPS structure. The pixel circuit shown in FIG7 can be a circuit with an LTPO structure. For a P-type transistor, the first potential can be a low potential; the second potential can be a high potential. For an N-type transistor, the first potential can be a high potential; the second potential can be a low potential.

[0145] Since N-type transistors made of oxide materials have better leakage protection capabilities than P-type transistors made of LTPS materials, in conjunction with Figure 7, by setting the first transistor T1 and the fifth transistor T5 to be P-type transistors made of LTPS materials, an N-type transistor made of oxide material (i.e., the eighth transistor T8) is added. This can reliably prevent leakage of the potential of the second node N2 without setting the first transistor T1 and the fifth transistor T5 to be N-type transistors made of oxide materials, thereby simplifying the process.

[0146] In summary, the embodiment of the present disclosure provides a pixel circuit, in which the data writing circuit can control the on-off connection between the data terminal and the first node based on the gate drive signal. The reset circuit can control the on-off connection between the initial power supply terminal and the second node and the light-emitting element based on the reset signal and the scan signal, and control the on-off connection between the reference power supply terminal and the first node. The potential adjustment circuit can control the on-off connection between the driving power supply terminal and the third node based on the compensation signal, and control the on-off connection between the second node and the fourth node, and can adjust the potential of the first node, the second node and the third node through coupling. The light-emitting control circuit can control the on-off connection between the reference power supply terminal and the first node based on the light-emitting control signal, and control the on-off connection between the fourth node and the light-emitting element. The driving circuit can transmit a driving signal to the fourth node based on the potential of the second node and the driving power signal to drive the light-emitting element to emit light. In this way, by flexibly setting the signals provided by each signal terminal, reliable compensation for the threshold voltage of the driving transistor in the driving circuit can be achieved, ensuring a better display effect.

[0147] In addition, because data is written directly to the second node under the coupling effect of the potential adjustment circuit, without having to go through the drive circuit to write to the second node, data writing and threshold voltage compensation can be achieved through different paths and different circuits. This allows data writing and threshold voltage compensation to be separated from each other and not affect each other, ensuring effective compensation of the threshold voltage and further ensuring a better display effect. Furthermore, based on the flexible setting of the reference power supply signals provided by the first reference power supply terminal and the second reference power supply terminal, a reference power supply signal with a larger potential can be written to the gate of the drive transistor in the drive circuit while maintaining the frame, ensuring reliable off-state reset of the drive transistor, thereby ensuring better display stability, especially ensuring better display stability at low frame rates.

[0148] FIG8 is a driving method of a pixel circuit provided by an embodiment of the present disclosure, which can be applied to any pixel circuit shown in FIG1 to FIG7. As shown in FIG8, the driving method includes:

[0149] Step 801, in the first stage, the reset circuit controls the first initial power supply terminal to be turned on with the second node based on the reset signal provided by the reset signal terminal, controls the first reference power supply terminal to be turned on with the first node based on the scan signal provided by the scan signal terminal, and controls the second initial power supply terminal to be turned on with the light-emitting element, and the potential adjustment circuit controls the driving power supply terminal to be turned on with the third node based on the first compensation signal provided by the first compensation terminal.

[0150] Step 802, in the second stage, the reset circuit controls the first reference power supply terminal to be turned on with the first node based on the scan signal, and controls the second initial power supply terminal to be turned on with the light-emitting element; the potential adjustment circuit controls the driving power supply terminal to be turned on with the third node based on the first compensation signal, and controls the second node to be turned on with the fourth node based on the second compensation signal provided by the second compensation terminal.

[0151] Step 803, the third stage, the data writing circuit controls the data terminal to be connected to the first node based on the gate driving signal provided by the gate signal terminal, the potential adjustment circuit controls the driving power supply terminal to be connected to the third node based on the first compensation signal, and controls the second node to be connected to the fourth node based on the second compensation signal.

[0152] Step 804, the fourth stage, the light-emitting control circuit controls the second reference power supply terminal to be connected to the first node based on the light-emitting control signal provided by the light-emitting control terminal, and controls the fourth node to be connected to the light-emitting element. The driving circuit transmits a driving signal to the fourth node based on the potential of the second node and the driving power signal provided by the driving power supply terminal to drive the light-emitting element to emit light.

[0153] Step 805 , the fifth stage: the reset circuit controls the first reference power terminal to be conductive with the first node and controls the second initial power terminal to be conductive with the light emitting element based on the scan signal.

[0154] The potential of the second reference power signal provided by the second reference power terminal is lower than the potential of the first reference power signal provided by the first reference power terminal. Furthermore, the first, second, third, fourth, and fifth stages are performed sequentially. Furthermore, in each stage, the potential adjustment circuit adjusts the potentials of the first, second, and third nodes through coupling.

[0155] It should be noted that the first to fourth stages may be the refresh frame stages described in the above embodiment; and the fifth stage may be the hold frame stage described in the above embodiment.

[0156] Continuing with reference to Figures 5 and 7 , it can be seen that in one embodiment of the present disclosure, the pixel circuit may further include: an anti-leakage circuit 06. Based on this, the method described in this embodiment of the present disclosure may further include: during the first to third stages, the anti-leakage circuit controlling the second node and the fifth node to be conductive based on the first compensation signal. Furthermore, referring to Figures 5 and 7 , it can be seen that, in addition to including the anti-leakage circuit 06, the potential adjustment circuit 03 may further be coupled to the fifth node N5, and the drive circuit 05 may be coupled to the second node N2 via the fifth node N5.

[0157] Optionally, based on the structures shown in Figures 6 and 7, Figures 9 and 10 respectively illustrate the operating timing diagrams of the two pixel circuits, including two phases: a refresh frame and a hold frame. It can be seen from Figures 9 and 10 that the refresh frame can include four phases: a first phase t1, a second phase t2, a third phase t3, and a fourth phase t4. The hold frame can include a fifth phase t5.

[0158] First, in the first phase t1:

[0159] For the structures shown in Figures 6 and 7 , the reset signal provided by the reset signal terminal Re and the scan signal provided by the scan signal terminal Scan are both low; the second compensation signal provided by the second compensation terminal AZ2, the gate drive signal provided by the gate signal terminal Sn, and the light control signal provided by the light control terminal EM are all high. Furthermore, for the structure shown in Figure 6 , the first compensation signal provided by the first compensation terminal AZ1 is low; for the structure shown in Figure 7 , the first compensation signal provided by the first compensation terminal AZ1 is high. That is, for the structure shown in Figure 6 , the reset signal terminal Re, the scan signal terminal Scan, and the first compensation terminal AZ1 can all be set low, while the second compensation terminal AZ2, the gate signal terminal Sn, and the light control terminal EM can all be set high. For the structure shown in Figure 7 , the reset signal terminal Re and the scan signal terminal Scan can all be set low, while the second compensation terminal AZ2, the gate signal terminal Sn, the light control terminal EM, and the first compensation terminal AZ1 can all be set high. Accordingly, in the structures shown in FIG6 and FIG7, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on; while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are all turned off. In the structure shown in FIG7, the eighth transistor T8 is turned on.

[0160] Furthermore, in the structures shown in Figures 6 and 7, the first initial power signal provided by the first initial power terminal Vinit1 can be transmitted to the second node N2 via the turned-on first transistor T1. The first reference power signal provided by the first reference power terminal Vref1 can be transmitted to the first node N1 via the turned-on second transistor T2. The second initial power signal provided by the second initial power terminal Vinit2 can be transmitted to the anode of the light-emitting element L1 via the turned-on third transistor T3. The driving power signal provided by the driving power terminal VDD can be transmitted to the third node N3 via the turned-on fourth transistor T4. Furthermore, in the structure shown in Figure 7, the first initial power signal transmitted to the second node N2 can continue to be transmitted to the fifth node N5 via the turned-on eighth transistor T8.

[0161] For example, assuming the potential of the first initial power signal is Vinit10, the potential of the second initial power signal is Vinit20, the potential of the first reference power signal is Vref10, and the potential of the driving power signal is Vdd, it can be seen that in the first phase t1, the potential of the first node N1 can be controlled to be Vref10, the potential of the second node N2 and the potential of the fifth node N5 can both be controlled to be Vinit10, the potential of the third node N3 can be controlled to be Vdd, and the potential of the anode of the light-emitting element L1 can be controlled to be Vinit20. This resets the first node N1, the second node N2, the fifth node N5, and the anode of the light-emitting element L1, turning on the tenth transistor T10. That is, in the first phase t1, the potentials across the first capacitor C1 can be Vref10 and Vdd, and the potentials across the second capacitor C2 can be Vdd and Vinit10. The first phase t1 can also be referred to as a reset phase.

[0162] Then, in the second phase:

[0163] For the structures shown in Figures 6 and 7, the potential of the second compensation signal provided by the second compensation terminal AZ2 and the potential of the scan signal provided by the scan signal terminal Scan are both low; the potential of the reset signal provided by the reset signal terminal Re, the potential of the gate drive signal provided by the gate signal terminal Sn, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM are all high. Furthermore, for the structure shown in Figure 6, the potential of the first compensation signal provided by the first compensation terminal AZ1 is low; for the structure shown in Figure 7, the potential of the first compensation signal provided by the first compensation terminal AZ1 is high. That is, for the structure shown in Figure 6, the first compensation terminal AZ1, the second compensation terminal AZ2, and the scan signal terminal Scan can all be set low, while the reset signal terminal Re, the gate signal terminal Sn, and the light-emitting control terminal EM can all be set high. For the structure shown in Figure 7, the second compensation terminal AZ2 and the scan signal terminal Scan can all be set low, while the first compensation terminal AZ1, the reset signal terminal Re, the gate signal terminal Sn, and the light-emitting control terminal EM can all be set high. Accordingly, in the structures shown in Figures 6 and 7, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned on, while the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are all turned off. Furthermore, in the structure shown in Figure 7, the eighth transistor T8 is turned on. Furthermore, under the coupling effect of the second capacitor C2, the second node N2 can maintain the first initial power supply signal of the first stage, and the tenth transistor T10 is turned on.

[0164] Furthermore, in the structures shown in Figures 6 and 7, the first reference power supply signal provided by the first reference power supply terminal Vref1 can continue to be transmitted to the first node N1 via the turned-on second transistor T2. The second initial power supply signal provided by the second initial power supply terminal Vinit2 can continue to be transmitted to the anode of the light-emitting element L1 via the turned-on third transistor T3. The driving power supply signal provided by the driving power supply terminal VDD can continue to be transmitted to the third node N3 via the turned-on fourth transistor T4. Furthermore, the fourth node N4 can be connected to the second node N2, and the second node N2 can remain connected to the fifth node N5. The driving power supply signal provided by the driving power supply terminal VDD can be transmitted to the second node N2 via the turned-on tenth transistor T10 and the fifth transistor T5 (i.e., the T10-T5 path), so that the potential of the second node N2 is related to the driving power supply signal and the threshold voltage Vth of the tenth transistor T10 (i.e., the driving transistor). Furthermore, in the structure shown in Figure 7, the potential transmitted to the second node N2 can continue to be transmitted to the fifth node N5 via the turned-on eighth transistor T8.

[0165] For example, assuming that the potential of the first initial power signal is Vinit10, the potential of the second initial power signal is Vinit20, the potential of the first reference power signal is Vref10, and the potential of the driving power signal is Vdd, it can be seen that in the second phase t2, the potential of the first node N1 can be controlled to be Vref10, the potential of the second node N2 and the potential of the fifth node N5 can be controlled to be Vdd+Vth, the potential of the third node N3 can be controlled to be Vdd, and the potential of the anode of the light-emitting element L1 can be controlled to be Vinit20. In other words, in the second phase t2, the potentials across the first capacitor C1 can be Vref10 and Vdd, and the potentials across the second capacitor C2 can be Vdd and Vdd+Vth. The second phase t2 can also be called the compensation phase.

[0166] Then, in the third stage t3:

[0167] For the structures shown in Figures 6 and 7, the potential of the second compensation signal provided by the second compensation terminal AZ2 and the potential of the gate drive signal provided by the gate signal terminal Sn are both low; the potential of the reset signal provided by the reset signal terminal Re, the potential of the scan signal provided by the scan signal terminal Scan, and the potential of the light-emission control signal provided by the light-emission control terminal EM are all high. Furthermore, for the structure shown in Figure 6, the potential of the first compensation signal provided by the first compensation terminal AZ1 is low; for the structure shown in Figure 7, the potential of the first compensation signal provided by the first compensation terminal AZ1 is high. That is, for the structure shown in Figure 6, the first compensation terminal AZ1, the second compensation terminal AZ2, and the gate signal terminal Sn can all be set low, while the reset signal terminal Re, the scan signal terminal Scan, and the light-emission control terminal EM can all be set high. For the structure shown in Figure 7, the second compensation terminal AZ2 and the gate signal terminal Sn can all be set low, while the first compensation terminal AZ1, the reset signal terminal Re, the scan signal terminal Scan, and the light-emission control terminal EM can all be set high. 6 and 7 , the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are all turned on, while the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are all turned off. Furthermore, in the structure shown in FIG7 , the eighth transistor T8 is turned on.

[0168] Furthermore, in the structures shown in Figures 6 and 7, the driving power signal provided by the driving power supply terminal VDD can continue to be transmitted to the third node N3 via the turned-on fourth transistor T4. The fourth node N4 can remain connected to the second node N2, and the second node N2 can remain connected to the fifth node N5. The driving power signal provided by the driving power supply terminal VDD can continue to be transmitted to the second node N2 via the turned-on tenth transistor T10 and the fifth transistor T5 (i.e., the T10-T5 path). Furthermore, in the structure shown in Figure 7, the potential transmitted to the second node N2 can continue to be transmitted to the fifth node N5 via the turned-on eighth transistor T8. And, the data signal provided by the data terminal Vdt can be transmitted to the first node N1 via the turned-on ninth transistor T9.

[0169] For example, assuming that the potential of the first initial power signal is Vinit10, the potential of the second initial power signal is Vinit20, the potential of the first reference power signal is Vref10, the potential of the drive power signal is Vdd, and assuming that the potential of the data signal is Vdt0, then in the third stage t3, the potential of the first node N1 can be Vdt0. The potential of the third node N3 can be maintained at Vdd. The potential of the second node N2 and the potential of the fifth node N5 can both be maintained at Vdd+Vth. That is, in the third stage t3, the potentials across the first capacitor C1 can be Vdt0 and Vdd. The potentials across the second capacitor C2 can be Vdd and Vdd+Vth. The third stage t3 can also be called a data writing stage.

[0170] Finally, in the fourth stage t4:

[0171] For the structures shown in Figures 6 and 7 , the potential of the light-emission control signal provided by the light-emission control terminal EM is low, while the potential of the second compensation signal provided by the second compensation terminal AZ2, the potential of the gate drive signal provided by the gate signal terminal Sn, the potential of the reset signal provided by the reset signal terminal Re, and the potential of the scan signal provided by the scan signal terminal Scan are all high. Furthermore, for the structure shown in Figure 6 , the potential of the first compensation signal provided by the first compensation terminal AZ1 is high; for the structure shown in Figure 7 , the potential of the first compensation signal provided by the first compensation terminal AZ1 is low. That is, for the structure shown in Figure 6 , the light-emission control terminal EM can be set low, while the first compensation terminal AZ1, the second compensation terminal AZ2, the gate signal terminal Sn, the reset signal terminal Re, and the scan signal terminal Scan can be set high. For the structure shown in Figure 7 , the light-emission control terminal EM and the first compensation terminal AZ1 can be set low, while the second compensation terminal AZ2, the gate signal terminal Sn, the reset signal terminal Re, and the scan signal terminal Scan can be set high. Accordingly, in the structures shown in Figures 6 and 7, the sixth transistor T6 and the seventh transistor T7 are both turned on; while the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are all turned off. Furthermore, in the structure shown in Figure 7, the eighth transistor T8 is turned off. Furthermore, under the bootstrap effect of the second capacitor C2, the tenth transistor T10 remains on.

[0172] Furthermore, in the structures shown in FIG6 and FIG7 , the second reference power signal provided by the second reference power terminal Vref2 can be transmitted to the first node N1 via the turned-on sixth transistor T6 .

[0173] For example, assuming that the potential of the first initial power signal is Vinit10, the potential of the second initial power signal is Vinit20, the potential of the first reference power signal is Vref10, the potential of the driving power signal is Vdd, and the potential of the data signal is Vdt0, and assuming that the potential of the second reference power signal is Vref20, then in the fourth stage t4, the potentials across the first capacitor C1 can be Vref20 and Vdd + Vref20 - Vdt. The potential of the gate of the driving transistor can be Vdd + Vref20 - Vdt + Vth. A path can be formed between the driving power terminal VDD and the pull-down power terminal VSS. The tenth transistor T10 can transmit a driving signal to the fourth node N4 based on the potential of the second node N2 and the driving power signal provided by the driving power terminal VDD. This driving signal can continue to be transmitted to the anode of the light-emitting element L1 via the turned-on seventh transistor T7. The light-emitting element L1 can emit light due to the voltage difference between the driving signal and the pull-down power signal provided by the pull-down power terminal VSS. The fourth stage t4 can also be referred to as the light-emitting stage. The formula for generating a driving signal (eg, driving current I0) by combining the driving transistor (ie, the tenth transistor T10) is: I0=1 / 2μ n C ox (W / L)*(Vgs-Vth) 2 It can be seen that: in the second stage t2, the threshold voltage Vth of the driving transistor is written into the second node N2, so that in the fourth stage t4, based on the gate-source voltage difference Vgs=Vg-Vs=(Vdd+Vref20-Vdt+Vth)-Vdd=Vref20-Vdt+Vth of the driving transistor, the driving current I0 generated by the driving transistor can meet the following conditions: I0=1 / 2μ n C ox (W / L)*(Vref20-Vdt+Vth-Vth)=1 / 2μ n C ox (W / L)*(Vdt0-Vref0) is independent of the threshold voltage Vth, thus achieving compensation for the threshold voltage Vth. n is the carrier mobility of the driving transistor, C ox is the capacitance of the gate insulating layer of the driving transistor, and W / L is the width-to-length ratio of the driving transistor, both of which are constants determined in the display panel manufacturing process.

[0174] Continuing to refer to Figures 9 and 10, it can be seen that within the hold frame:

[0175] For the structures shown in Figures 6 and 7, the potential of the scan signal provided by the scan signal terminal Scan is low, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM is high. Furthermore, the potential of the reset signal provided by the reset signal terminal Re, the potential of the second compensation signal provided by the second compensation terminal AZ2, and the potential of the gate drive signal provided by the gate signal terminal Sn are all high. Furthermore, for the structure shown in Figure 6, the potential of the first compensation signal provided by the first compensation terminal AZ1 is high; for the structure shown in Figure 7, the potential of the first compensation signal provided by the first compensation terminal AZ1 is low. That is, for the structure shown in Figure 6, the scan signal terminal Scan can be set low, and all other signal terminals can be set high. For the structure shown in Figure 7, the scan signal terminal Scan and the first compensation terminal AZ1 can be set low, and all other signal terminals can be set high. Accordingly, in the structures shown in Figures 6 and 7, the second transistor T2 and the third transistor T3 can both be turned on, while all other transistors except the second transistor T2 and the third transistor T3 are turned off.

[0176] Furthermore, the first reference power signal provided by the first reference power terminal Vref1 can be transmitted to the first node N1 via the turned-on second transistor T2, causing the potential of the first node N1 to rise from the second reference power signal in the previous light-emitting stage t4 to the first reference power signal, i.e., from the smaller potential Vref20 of the second reference power signal to the larger potential Vref10 of the first reference power signal. Under the regulation of the first capacitor C1 and the second capacitor C2, the potential of the gate of the driving transistor T10 (e.g., the second node N2 shown in FIG6 or the fifth node N5 shown in FIG7 ) can be further increased by approximately Vref10-Vref20. If the potential Vref10 of the first reference power signal is sufficiently high, the tenth transistor T10 (i.e., the driving transistor) can be reliably turned off regardless of the displayed image, thereby resetting the driving transistor to its off state. Furthermore, the second initial power signal provided by the second initial power terminal Vinit2 can be transmitted to the anode of the light-emitting element L1 via the turned-on third transistor T3, thereby resetting the light-emitting element L1.

[0177] That is, in the disclosed embodiment, the threshold voltage Vth of the anode of the light-emitting element L1 and the driving transistor can be reset during the frame hold phase, causing the gate-source voltage difference Vgs of the driving transistor to rapidly drop to approximately equal Vth. Because the fifth transistor T5 included in the compensation sub-circuit 032 is turned off, the gate potential of the driving transistor is not affected. The brightness of the display panel can remain unchanged until the light-emitting element L1 resumes emitting light. This allows for better low-frame-rate display in a low-frequency refresh state.

[0178] Afterwards, when the light-emitting element L1 needs to be turned on again to emit light normally, the light-emitting control terminal EM can be set low and the scan control terminal Scan can be set high, so that the second transistor T2 and the third transistor T3 are both turned off, while the sixth transistor T6 and the seventh transistor T7 are both turned on. Furthermore, the second reference power supply signal provided by the second reference power supply terminal Vref2 can be transmitted to the first node N1 via the turned-on second transistor T2, so that the potential of the first node N1 is restored from the larger potential Vref10 of the first reference power supply signal to the lower potential Vref20 of the second reference power supply signal. Furthermore, the fourth node N4 is connected to the anode of the light-emitting element L1, thereby reliably driving the light-emitting element L1 to emit light again. Furthermore, since only the potential of the first node N1 jumps from the hold frame to the stage where the light-emitting element L1 emits light again, and no charge is charged or discharged in other devices and capacitors, according to the law of charge conservation, after entering normal light emission, the gate potential of the driving transistor can quickly return to the voltage during normal light emission, further ensuring that the light-emitting element L1 can be reliably driven to emit light.

[0179] In summary, the embodiments of the present disclosure provide a method for driving a pixel circuit. In this method, the data writing circuit can control the on-off connection between the data terminal and the first node based on the gate driving signal. The reset circuit can control the on-off connection between the initial power terminal and the second node and the light-emitting element based on the reset signal and the scan signal, and control the on-off connection between the reference power terminal and the first node. The potential adjustment circuit can control the on-off connection between the driving power terminal and the third node based on the compensation signal, and control the on-off connection between the second node and the fourth node, and can adjust the potential of the first node, the second node and the third node through coupling. The light-emitting control circuit can control the on-off connection between the reference power terminal and the first node based on the light-emitting control signal, and control the on-off connection between the fourth node and the light-emitting element. The driving circuit can transmit a driving signal to the fourth node based on the potential of the second node and the driving power signal to drive the light-emitting element to emit light. In this way, by flexibly setting the signals provided by each signal terminal, reliable compensation for the threshold voltage of the driving transistor in the driving circuit can be achieved, ensuring a better display effect.

[0180] In addition, because data is written directly to the second node under the coupling effect of the potential adjustment circuit, without having to go through the drive circuit to write to the second node, data writing and threshold voltage compensation can be achieved through different paths and different circuits. This allows data writing and threshold voltage compensation to be separated from each other and not affect each other, ensuring effective compensation of the threshold voltage and further ensuring a better display effect. Furthermore, based on the flexible setting of the reference power supply signals provided by the first reference power supply terminal and the second reference power supply terminal, a reference power supply signal with a larger potential can be written to the gate of the drive transistor in the drive circuit while maintaining the frame, ensuring reliable off-state reset of the drive transistor, thereby ensuring better display stability, especially ensuring better display stability at low frame rates.

[0181] FIG11 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG11 , the display panel includes: a substrate 10 and a plurality of pixels 20 located on one side of the substrate 10 .

[0182] The pixel 20 may include: a light emitting element L1 and a pixel circuit 00 as shown in any one of Figures 1 to 7. The pixel circuit 00 may be coupled to the light emitting element L1 and used to drive the light emitting element L1 to emit light.

[0183] FIG12 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG12 , the display device includes: a signal providing circuit 000 and a display panel 100 as shown in FIG11 .

[0184] 11 , the signal providing circuit 000 can be coupled to multiple signal terminals coupled to the pixel circuit 00 in the display panel 100 and used to provide signals to the multiple signal terminals to control the pixel circuit 00 to drive the coupled light-emitting element L1 to emit light. Optionally, as described in the above embodiment, the multiple signal terminals here may include: a gate signal terminal Sn, a scan signal terminal Scan, a light-emitting control terminal EM, a first compensation terminal AZ1, a second compensation terminal AZ2, and a reset terminal Re. Taking the gate signal terminal Sn as an example, the signal providing circuit 000 that provides the gate drive signal thereto may be a gate drive circuit.

[0185] Optionally, the display device described in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0186] It should be noted that the terms used in the embodiments of the present disclosure are intended only to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the same meaning as those commonly understood by persons of ordinary skill in the art to which the present disclosure belongs.

[0187] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0188] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0189] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0190] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0191] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising: A data writing circuit is coupled to the gate signal terminal, the data terminal and the first node respectively, and is used to control the connection and disconnection between the data terminal and the first node based on the gate driving signal provided by the gate signal terminal; a reset circuit, coupled to a reset signal terminal, a scan signal terminal, a first reference power terminal, a first initial power terminal, a second initial power terminal, the first node, the second node and the light-emitting element, respectively, and used to control the on-off of the first initial power terminal and the second node based on a reset signal provided by the reset signal terminal, and to control the on-off of the first reference power terminal and the first node based on a scan signal provided by the scan signal terminal, and to control the on-off of the second initial power terminal and the light-emitting element; A potential regulating circuit is coupled to the first compensation terminal, the second compensation terminal, the driving power terminal, the first node, the second node, the third node and the fourth node respectively, and is used to control the connection and disconnection between the driving power terminal and the third node based on the first compensation terminal providing a first compensation signal, and to control the connection and disconnection between the second node and the fourth node based on the second compensation signal provided by the second compensation terminal, and to regulate the potentials of the first node, the second node and the third node through coupling; a light emitting control circuit, coupled to a light emitting control terminal, a second reference power terminal, the first node, the fourth node and the light emitting element, respectively, and used to control the on-off connection between the second reference power terminal and the first node, and control the on-off connection between the fourth node and the light emitting element based on a light emitting control signal provided by the light emitting control terminal, wherein the potential of the second reference power signal provided by the second reference power terminal is less than the potential of the first reference power signal provided by the first reference power terminal; The driving circuit is coupled to the second node, the driving power supply terminal and the fourth node respectively, and is used to transmit a driving signal to the fourth node based on the potential of the second node and the driving power supply signal.

2. The pixel circuit according to claim 1, wherein: The reset circuit comprises: a first reset subcircuit, coupled to the reset signal terminal, the first initial power terminal and the second node respectively, and used to control the connection and disconnection between the first initial power terminal and the second node based on the reset signal; The second reset subcircuit is respectively connected to the scan signal terminal, the first reference power terminal and the first A node is coupled and used to control the connection and disconnection between the first reference power supply terminal and the first node based on the scanning signal; The third reset subcircuit is coupled to the scan signal terminal, the second initial power terminal and the light emitting element respectively, and is used to control the on and off of the second initial power terminal and the light emitting element based on the scan signal.

3. The pixel circuit according to claim 2, wherein: The first reset subcircuit includes: a first transistor; the second reset subcircuit includes: a second transistor; the third reset subcircuit includes: a third transistor; The gate of the first transistor is coupled to the reset signal terminal, the first electrode of the first transistor is coupled to the first initial power supply terminal, and the second electrode of the first transistor is coupled to the second node; The gate of the second transistor is coupled to the scan signal terminal, the first electrode of the second transistor is coupled to the first reference power terminal, and the second electrode of the second transistor is coupled to the first node; A gate of the third transistor is coupled to the scan signal terminal, a first electrode of the third transistor is coupled to the second initial power terminal, and a second electrode of the third transistor is coupled to the light emitting element.

4. The pixel circuit according to any one of claims 1 to 3, wherein: The potential regulating circuit comprises: a switch subcircuit, coupled to the first compensation terminal, the driving power terminal and the third node respectively, and used to control the connection and disconnection of the driving power terminal and the third node based on the first compensation signal; a compensation subcircuit, coupled to the second compensation terminal, the second node and the fourth node respectively, and used to control the connection and disconnection of the second node and the fourth node based on the second compensation signal; The regulating subcircuit is coupled to the first node, the second node and the third node respectively, and is used to regulate the potentials of the first node, the second node and the third node through coupling.

5. The pixel circuit according to claim 4, wherein: The switch subcircuit includes: a fourth transistor; the compensation subcircuit includes: a fifth transistor; the regulation subcircuit includes: a first capacitor and a second capacitor; The gate of the fourth transistor is coupled to the first compensation terminal, and the first electrode of the fourth transistor coupled to the driving power supply terminal, and the second electrode of the fourth transistor is coupled to the third node; The gate of the fifth transistor is coupled to the second compensation terminal, the first electrode of the fifth transistor is coupled to the fourth node, and the second electrode of the fifth transistor is coupled to the second node; The first capacitor is connected in series between the first node and the third node; The second capacitor is connected in series between the third node and the second node.

6. The pixel circuit according to any one of claims 1 to 5, wherein: The light emitting control circuit comprises: a first light-emitting control subcircuit, coupled to the light-emitting control terminal, the second reference power terminal and the first node respectively, and used for controlling the on-off of the second reference power terminal and the first node based on the light-emitting control signal; The second light-emitting control subcircuit is coupled to the light-emitting control terminal, the fourth node and the light-emitting element respectively, and is used to control the on-off of the fourth node and the light-emitting element based on the light-emitting control signal.

7. The pixel circuit according to claim 6, wherein: The first light emitting control subcircuit includes: a sixth transistor; the second light emitting control subcircuit includes: a seventh transistor; The gate of the sixth transistor is coupled to the light emitting control terminal, the first electrode of the sixth transistor is coupled to the second reference power supply terminal, and the second electrode of the sixth transistor is coupled to the first node; A gate of the seventh transistor is coupled to the light emitting control terminal, a first electrode of the seventh transistor is coupled to the fourth node, and a second electrode of the seventh transistor is coupled to the light emitting element.

8. The pixel circuit according to any one of claims 1 to 7, wherein: The pixel circuit further includes: an anti-leakage circuit, coupled to the first compensation terminal, the second node and the fifth node respectively, and used to control the connection and disconnection of the second node and the fifth node based on the first compensation signal; The potential regulating circuit is also coupled to the fifth node, and the driving circuit is coupled to the second node via the fifth node.

9. The pixel circuit according to claim 8, wherein: The anti-leakage circuit comprises: an eighth transistor; The gate of the eighth transistor is coupled to the first compensation terminal, and the first electrode of the eighth transistor The first electrode of the eighth transistor is coupled to the fifth node, and the second electrode of the eighth transistor is coupled to the second node.

10. The pixel circuit according to claim 8, wherein: In the reset circuit, the materials of the transistor that controls the connection and disconnection between the first initial power supply terminal and the second node, and the materials of the transistor that controls the connection and disconnection between the fourth node and the second node in the potential adjustment circuit both include: low-temperature polysilicon material; the material of the transistor in the anti-leakage circuit includes: oxide material.

11. The pixel circuit according to any one of claims 1 to 10, wherein: The data writing circuit comprises: a ninth transistor; the driving circuit comprises: a tenth transistor; The gate of the ninth transistor is coupled to the gate signal terminal, the first electrode of the ninth transistor is coupled to the driving power supply terminal, and the second electrode of the ninth transistor is coupled to the first node; The gate of the tenth transistor is coupled to the second node, the first electrode of the tenth transistor is coupled to the driving power supply terminal, and the second electrode of the tenth transistor is coupled to the fourth node.

12. A method for driving a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 11, the method comprising: In the first stage, the reset circuit controls the first initial power supply terminal to be connected to the second node based on the reset signal provided by the reset signal terminal, controls the first reference power supply terminal to be connected to the first node based on the scan signal provided by the scan signal terminal, and controls the second initial power supply terminal to be connected to the light-emitting element, and the potential adjustment circuit controls the driving power supply terminal to be connected to the third node based on the first compensation signal provided by the first compensation terminal; In the second stage, the reset circuit controls the first reference power supply terminal to be conductive with the first node based on the scan signal, and controls the second initial power supply terminal to be conductive with the light-emitting element, and the potential adjustment circuit controls the driving power supply terminal to be conductive with the third node based on the first compensation signal, and controls the second node to be conductive with the fourth node based on the second compensation signal provided by the second compensation terminal; In the third stage, the data writing circuit controls the data terminal to be connected to the first node based on the gate driving signal provided by the gate signal terminal, and the potential adjustment circuit controls the driving power supply terminal to be connected to the third node based on the first compensation signal, and controls the second node to be connected to the fourth node based on the second compensation signal; In the fourth stage, the light emitting control circuit controls the second reference power supply terminal to be connected to the first node, and controls the fourth node to be connected to the light emitting element based on the light emitting control signal provided by the light emitting control terminal. The driving circuit transmits a driving signal to the fourth node based on the potential of the second node and the driving power signal provided by the driving power terminal, so as to drive the light-emitting element to emit light; In the fifth stage, the reset circuit controls the first reference power supply terminal to be conductive with the first node, and controls the second initial power supply terminal to be conductive with the light emitting element based on the scan signal; Wherein, the potential of the second reference power signal provided by the second reference power terminal is smaller than the potential of the first reference power signal provided by the first reference power terminal; Furthermore, the first stage, the second stage, the third stage, the fourth stage and the fifth stage are performed sequentially; and in each stage, the potential regulating circuit regulates the potentials of the first node, the second node and the third node through coupling.

13. The method according to claim 12, wherein: The pixel circuit further includes: an anti-leakage circuit; the method further includes: in the first stage to the third stage, the anti-leakage circuit controls the second node and the fifth node to be turned on based on the first compensation signal; The potential regulating circuit is also coupled to the fifth node, and the driving circuit is coupled to the second node via the fifth node.

14. A display panel, comprising: A substrate, and a plurality of pixels located on one side of the substrate; The pixel comprises: a light-emitting element, and a pixel circuit as claimed in any one of claims 1 to 11, wherein the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

15. A display device, comprising: A signal providing circuit, and a display panel as claimed in claim 14; The signal providing circuit is coupled to a plurality of signal terminals coupled to the pixel circuit in the display panel, and is used to provide signals to the plurality of signal terminals to control the pixel circuit to drive the coupled light-emitting element to emit light.

Images