Dormancy awakening method and system for multi-core heterogeneous product

Abstract

The invention discloses a sleep wake-up method and system for a multi-core heterogeneous product, and the method comprises the steps: enabling a main core to query the number of sleep locks recorded by all heterogeneous cores through inter-core communication after the sleep of the system is triggered, and judging whether to carry out the sleep operation or not according to the number of sleep locks; when the dormancy operation is carried out, the main core sends a dormancy starting notice to all heterogeneous cores; after the main core completes task freezing, the dormancy willingness of each sub-core is checked; the main core performs dormancy on the sub-core needing dormancy, takes over the wakeup interruption of the sub-core needing dormancy, records the wakeup interruption number, updates the clock and power supply resources of the sub-core needing dormancy, and cuts off the power supply of the sub-core needing dormancy; and the main core completes own dormancy action, determines final clock and power supply configuration of the system, provides basic working conditions for the wake-up source, and then the system enters dormancy. According to the method, a solution is provided for resource and event dispute processing and adaptive switching of a dormancy scene when the multi-core heterogeneous chip enters the dormancy state.

Description

Technical Field

[0001] The present invention relates to the field of multi-core heterogeneous technology, and in particular to a sleep and wake-up method, system, electronic device and storage medium for a multi-core heterogeneous product. Background Art

[0002] For the hibernation and wakeup scenarios of multi-core heterogeneous chip products, the existing technical solutions are mostly to treat other heterogeneous cores except the main core in hibernation as the main core's devices for hibernation. Under this solution, other heterogeneous cores will not run the hibernation framework, and the interaction between cores only involves the triggering of hibernation and wakeup, and does not involve interrupt and resource allocation processing. When hibernating, other heterogeneous cores suspend the processor after a simple task freeze and interrupt setting, and usually do not lose power. When waking up, the heterogeneous core exits the suspended state and resumes operation or restarts directly. The problem with this solution is that when multiple heterogeneous cores are hibernated as a whole, there will be disputes over clock and power resource allocation, wakeup event reception, and hibernation intention. In addition, the specific product form of the chip application requires different hibernation scenarios. There are requirements such as only specific cores falling into hibernation, hibernating again after waking up, and switching hibernation scenarios. A strategy is needed to handle resource and event disputes in multi-core heterogeneous hibernation and wakeup, and enable the chip to adapt to changes in product hibernation scenarios. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a sleep wakeup method, system, electronic device and storage medium for multi-core heterogeneous products, providing a solution for resource and event dispute handling when multi-core heterogeneous chips enter sleep mode, as well as adaptive switching of sleep scenarios.

[0004] On the one hand, the sleep and wake-up method of a multi-core heterogeneous product according to an embodiment of the present invention is applied to a sleep and wake-up system of a multi-core heterogeneous product, wherein the sleep and wake-up system of the multi-core heterogeneous product comprises a framework core layer, an action interaction module and a resource management module, wherein the framework core layer comprises a plurality of heterogeneous cores, wherein one of the heterogeneous cores is a main core, and the remaining heterogeneous cores are sub-cores, each of the sub-cores has a corresponding state machine and a wake-up source, and the action interaction module is used to manage the state of the state machine; the resource management module is used to manage the clock and power supply resources of the system, and allocates corresponding clock and power supply resources to each of the sub-cores and each of the wake-up sources; the sleep and wake-up method comprises:

[0005] After the system hibernation is triggered, the main core queries the number of hibernation locks recorded by all the heterogeneous cores through inter-core communication, and determines whether to perform a hibernation operation according to the number of hibernation locks;

[0006] When performing the sleep operation, the main core sends a sleep start notification to all the heterogeneous cores;

[0007] After the main core completes task freezing, checking the sleep willingness of each sub-core;

[0008] The main core puts the sub-core that needs to sleep to sleep into sleep mode, takes over the wake-up interrupt of the sub-core that needs to sleep into sleep mode, records the wake-up interrupt number, updates the clock and power supply resources of the sub-core that needs to sleep into sleep mode, and cuts off the power supply of the sub-core that has already sleep mode;

[0009] After the main core completes its own sleep action and determines the final clock and power supply configuration of the system and provides basic working conditions for the wake-up source, the system enters sleep.

[0010] According to some embodiments of the present invention, when performing the sleep operation, the step of the main core sending a sleep start notification to all the heterogeneous cores includes:

[0011] The action interaction module registers an event notification mechanism on the main core to trigger the same event notification of the sub-core in the callback of the main core;

[0012] When performing the sleep operation, the main core sends a sleep start notification to itself, and triggers the same notification action of the sub-core through the event notification mechanism.

[0013] According to some embodiments of the present invention, after the main core completes task freezing, after the step of checking the sleep willingness of each of the sub-cores, the method further includes:

[0014] If the sub-core needs to keep running in this round of dormancy, the action interaction module switches the state machine of the sub-core to keep running, and the main core retains the clock and power supply resources of the sub-core that needs to keep running;

[0015] The main core adds a first identifier to a system core device required by the sub-core to keep running, and does not put the system core device with the first identifier to sleep.

[0016] According to some embodiments of the present invention, after the steps of the main core putting the sub-core that needs to sleep to sleep into sleep mode, taking over the wake-up interrupt of the sub-core that needs to sleep into sleep mode, recording the wake-up interrupt number, updating the dependent resources of the sub-core that needs to sleep into sleep mode, and cutting off the power supply of the sub-core that has already sleep mode, the method further includes:

[0017] When all the sub-cores that need to sleep have successfully done so, the main core continues the subsequent sleep action;

[0018] When the sub-core that needs to sleep fails to sleep, the main core interrupts the sleep and performs process rollback.

[0019] According to some embodiments of the present invention, the step of taking over the wake-up interrupt of the sub-core that needs to sleep and recording the wake-up interrupt number includes:

[0020] The main core uniformly applies for a processing function for all the wake-up interrupt numbers, and takes over the wake-up interrupt of the dormant sub-core through the processing function.

[0021] According to some embodiments of the present invention, each of the heterogeneous cores has a first count value of a corresponding number of wake-up events, and the main core has a second count value representing the occurrence of other core events; the sleep wake-up method further includes:

[0022] When an interrupt is triggered, the system hardware pulls up the main core, the main core restores the system clock and power supply, and wakes up until the system is in the resume_early state, and then performs a first-level sleep again judgment;

[0023] If the first count value and the second count value do not change, the main core further determines whether there is an event being processed, and if no event is being processed, the system enters sleep again;

[0024] If the first count value and / or the second count value changes, the main core continues to wake up the system and selectively wakes up the corresponding sub-core according to the wake-up interrupt.

[0025] According to some embodiments of the present invention, the sleep awakening method further includes:

[0026] When the main core selectively wakes up the corresponding sub-core according to the wake-up interrupt, a second-level re-sleep judgment is performed to query the first count value;

[0027] If the first count value does not change, the system enters sleep mode again;

[0028] If the first count value changes, the main core continues to wake up the system, completes the wake-up action, and sends a sleep end notification to all heterogeneous cores.

[0029] On the other hand, according to an embodiment of the present invention, the hibernation and wake-up system of a multi-core heterogeneous product includes a framework core layer, an action interaction module and a resource management module. The framework core layer includes multiple heterogeneous cores, one of which is a main core, and the remaining heterogeneous cores are sub-cores. Each sub-core has a corresponding state machine and a wake-up source. The action interaction module is used to manage the state of the state machine; the resource management module is used to manage the clock and power supply resources of the system, and allocates corresponding clock and power supply resources to each sub-core and each wake-up source. The hibernation and wake-up system of the multi-core heterogeneous product is used to implement the hibernation and wake-up method of the multi-core heterogeneous product described in the above-mentioned embodiment.

[0030] On the other hand, an electronic device according to an embodiment of the present invention includes:

[0031] A memory for storing program instructions;

[0032] The processor is used to call the program instructions stored in the memory and execute the sleep and wake-up method of the multi-core heterogeneous product of the above-mentioned embodiment according to the obtained program instructions.

[0033] On the other hand, according to a storage medium of an embodiment of the present invention, the storage medium stores computer executable instructions, and the computer executable instructions are used to enable a computer to execute the sleep and wake-up method of a multi-core heterogeneous product described in the above-mentioned embodiment.

[0034] The hibernation and awakening method, system, electronic device and storage medium of a multi-core heterogeneous product according to an embodiment of the present invention have at least the following beneficial effects: it solves the problem of how to coordinate the orderly hibernation and awakening recovery of each core when the multi-core heterogeneous product is hibernated and awakened as a whole, and provides management of hibernation scene resources, and realizes adaptive switching in each hibernation scene. Using this framework, multiple heterogeneous cores are independent individuals in the hibernation and awakening process, and can handle wake-up events separately and decide whether the system should hibernate.

[0035] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 A schematic diagram of the structure of a sleep and wake-up system for a multi-core heterogeneous product according to an embodiment of the present invention;

[0038] Figure 2 A flowchart of the steps of the sleep and wake-up method of a multi-core heterogeneous product according to an embodiment of the present invention;

[0039] Figure 3 A flowchart of some steps of a method for waking up a multi-core heterogeneous product from sleep according to another embodiment of the present invention;

[0040] Figure 4 A schematic diagram of resource management of a resource management module according to an embodiment of the present invention;

[0041] Figure 5 The figure is a schematic diagram of the action flow of the action interaction module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0043] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0044] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0045] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] For the hibernation and wakeup scenarios of multi-core heterogeneous chip products, the existing technical solutions are mostly to treat other heterogeneous cores except the main core in hibernation as the main core's devices for hibernation. Under this solution, other heterogeneous cores will not run the hibernation framework, and the interaction between cores only involves the triggering of hibernation and wakeup, and does not involve interrupt and resource allocation processing. When hibernating, other heterogeneous cores suspend the processor after a simple task freeze and interrupt setting, and usually do not lose power. When waking up, the heterogeneous core exits the suspended state and resumes operation or restarts directly. The problem with this solution is that when multiple heterogeneous cores are hibernated as a whole, there will be disputes over clock and power resource allocation, wakeup event reception, and hibernation intention. In addition, the specific product form of the chip application requires different hibernation scenarios. There are requirements such as only specific cores falling into hibernation, hibernating again after waking up, and switching hibernation scenarios. A strategy is needed to handle resource and event disputes in multi-core heterogeneous hibernation and wakeup, and enable the chip to adapt to changes in product hibernation scenarios.

[0047] To this end, the embodiment of the present invention provides a method, system, electronic device and storage medium for hibernation and awakening of a multi-core heterogeneous product. Through the hibernation and awakening software interactive framework of a multi-core heterogeneous chip product, the problem of how to coordinate the orderly hibernation and awakening recovery of each core when the multi-core heterogeneous product is hibernated and awakened as a whole is solved, and hibernation scene resources are managed to achieve adaptive switching in each hibernation scene. Using this framework, multiple heterogeneous cores are independent individuals in the hibernation and awakening process, and can handle wake-up events separately and decide whether the system is hibernated.

[0048] The following describes in detail the sleep and wake-up method, system, electronic device and storage medium for a multi-core heterogeneous product according to an embodiment of the present invention in conjunction with the accompanying drawings.

[0049] It should be noted that the present invention is a software strategy, and its development requirements are based on a DSP HIFI4, ARMM33, RISCV C906 three-core heterogeneous chip (it can also be applied to other multi-core heterogeneous products), and the three heterogeneous cores of the chip all run the Freertos operating system. In the early development work, a general sleep and wake-up framework including task freezing, device sleep, platform sleep and wake-up event management components has been implemented on the rtos system running heterogeneous cores with reference to the Linux sleep and wake-up framework. In addition, there is a module for transmitting data between cores in the chip hardware design, and inter-core communication has been realized based on this module.

[0050] On the basis of the existing general sleep and wake-up framework, heterogeneous cores can be woken up from sleep individually. However, when multiple heterogeneous cores are in sleep mode as a whole, disputes may arise in the resource configuration of clock and power supply, reception of wake-up events, and willingness to sleep. In addition, the specific product forms of chip applications require different sleep scenarios, such as only specific cores falling into sleep mode, sleeping again after being woken up, and switching sleep scenarios. A strategy is needed to handle resource and event disputes in multi-core heterogeneous sleep and wake-up, and enable the chip to adapt to changes in product sleep scenarios. Based on the above requirements, the present invention implements a multi-core heterogeneous sleep and wake-up interaction framework, which mainly provides solutions for resource and event dispute handling when multi-core heterogeneous chips enter sleep mode, as well as adaptive switching of sleep scenarios. Its logic implementation is mainly located in the platform sleep component, which can be reused by different platforms.

[0051] like Figure 1 As shown, on the one hand, an embodiment of the present invention proposes a sleep and wake-up system for a multi-core heterogeneous product, wherein the sleep and wake-up system includes a framework core layer, an action interaction module and a resource management module. The framework core layer includes multiple heterogeneous cores, one of which is a main core, and the remaining heterogeneous cores are sub-cores. Each sub-core has a corresponding state machine and a wake-up source. The action interaction module is used to manage the state of the state machine; the resource management module is used to manage the clock and power supply resources of the system, and allocates corresponding clock and power supply resources to each sub-core and each wake-up source.

[0052] Among them, the system designates one core among multiple processors (heterogeneous cores) as the sleep main core, and other processors as sub-cores. The main core is responsible for triggering the sleep or query action specified by the sub-core, managing the allocation information of wake-up interrupts and wake-up resources, and is responsible for completing the configuration and recovery of the sleep scene clock and power supply. The sub-core is responsible for responding to the main core action request and feedback the action result, as well as completing the resource application.

[0053] The sleep interaction logic of the system is implemented in the platform callback of the sleep module (the platform can be understood as a specific operating environment, such as an operating system on software, or different chips on hardware; callback refers to a custom function registered by the developer, which is called at a specified location; the platform callback is a custom function implemented by the developer to adapt to different operating environments, containing the function implementation for a specific platform. The specific interaction logic here may have different application requirements for different cores, and this logic is implemented in the platform callback). As the sleep wake-up process progresses, the main core completes the sleep wake-up action triggering of the sub-core and the wake-up event information query work, and performs two-level re-sleep arbitration based on the queried information. During the entire interaction process, the system's clock and power supply resource dependency information is updated based on whether the wake-up source is enabled or not, and the system clock and power supply status are configured before the system finally falls into sleep, and the sleep scene is flexibly switched.

[0054] The framework core layer is responsible for organizing the work of the action interaction module and the resource management module, and provides an interface for reporting events being processed to the device driver. The action interaction module maintains the state machine for all sub-cores on the main core. The module creates two tasks, which are responsible for action triggering and action result checking respectively. The state machine of the sub-core is changed according to the triggered action and result. The state machine is mainly used to confirm the sleep and wake-up phase status of the sub-core and whether the sleep of the core needs to be skipped. The resource management module lists the clock and power supply resources of the system and abstracts them into specific objects. The wake-up source and the sub-core are regarded as a combination of specified resources in the framework. When the wake-up source is enabled or the sub-core needs to keep running, its bound resources are selected, and the main core configures the selected resources before sleep. After the wake-up source is enabled in other cores, its interrupt number will be recorded in the main core, and its dependent resources will be updated at the same time. After the other cores are in sleep, the main core will temporarily receive the interrupt.

[0055] Each heterogeneous core is an independent sleep subject in the interactive framework. A complete sleep framework will include wakeup sources and event counts. When the event count increases, it means that the system needs to wake up. In the present invention, the wakeup source and event count are not completely managed by one core. The wakeup source is registered in any core, and the core where it is located maintains the wakeup source status and event count information separately, and processes the wakeup event. The wakeup interrupt and count information will be queried by the main core at a specific time to arbitrate whether the entire system needs to be woken up.

[0056] When the system is in hibernation, each core is autonomous, completes its own scene saving and hibernation actions, and maintains counts to determine whether it is in hibernation. The main core updates the system's clock and power resource dependency information based on whether the wake-up source is enabled or not, and finally completes resource configuration, and the system as a whole goes into hibernation. When waking up, the main core wakes up first, and selectively wakes up the sub-cores based on the wake-up interrupt. After the sub-cores process the event, they go back into hibernation based on the new resource combination, or wake up all sub-cores to allow the system as a whole to exit hibernation.

[0057] On the other hand, based on the above-mentioned sleep and wake-up system for multi-core heterogeneous products, the present invention also proposes a sleep and wake-up method for multi-core heterogeneous products, such as Figure 2 As shown, the method comprises the following steps:

[0058] Step S100: After the system hibernation is triggered, the main core queries the number of hibernation locks recorded by all heterogeneous cores through inter-core communication, and determines whether to perform the hibernation operation according to the number of hibernation locks;

[0059] Specifically, after the system hibernation is triggered, the main core queries the number of wakelocks (sleep locks requested by the application, when they are held, the system refuses to hibernate) recorded by each core through inter-core communication. If the total number is not 0, hibernation is refused. If the number of sleep locks is 0, subsequent hibernation operations are performed.

[0060] Step S200: When performing a sleep operation, the main core sends a sleep start notification to all heterogeneous cores;

[0061] Specifically, the action interaction module will register an event notification mechanism (notifier, used for sleep action phase notification in the sleep module) on the main core to trigger the same event notification of the sub-core in the callback of the main core. When performing a sleep operation, the main core sends a sleep start notification to itself and triggers the same notification action of the sub-core through the event notification mechanism.

[0062] Step S300: After the main core completes task freezing, it checks the sleep willingness of each sub-core;

[0063] Specifically, when performing a sleep operation, the main core first freezes its own tasks, and then checks the sleep willingness of each sub-core. Before sleep, the sub-core sleep willingness is checked. If the sub-core needs to keep running in this round of sleep, the action interaction module switches the state machine of the sub-core to keep running (KEEP_AWAK) and retains the dependent resources required by the sub-core. In addition, the first identifier (COMMON) is added to the system core devices of the syscore layer (such as GPIO, CCMU device drivers, etc.). When a sub-core keeps running, the COMMON device is not put into sleep and its running resources are retained. The sleep willingness judgment method can be customized. In this framework, it is judged with the help of soft wake-up sources.

[0064] Step S400: the main core puts the sub-core that needs to sleep to sleep into sleep mode, takes over the wake-up interrupt of the sub-core that needs to sleep into sleep mode, records the wake-up interrupt number, updates the clock and power supply resources of the sub-core that needs to sleep into sleep mode, and cuts off the power supply of the sub-core that has already sleep mode;

[0065] Specifically, after the main core puts the sub-core to sleep, it will record the wake-up interrupt number of each sub-core, and then the main core will uniformly apply for a processing function for all wake-up interrupt numbers, and take over the wake-up interrupt of the sleeping sub-core through the processing function. The processing function only contains three actions: the main core interrupt controller disables this interrupt, increases the "subcnt" count value that marks the occurrence of the wake-up event of the other core, and records which sub-core needs to be awakened to handle the interrupt. Since the dependent resources required by the sub-core will change when it is in sleep state, it is necessary to update its dependent resources and cut off its power supply to put it into sleep state. After the sub-core is in sleep state, the sleep result will be fed back to the main core. If the main core receives the sleep success result of all sub-cores within the specified event, it will continue the subsequent sleep, otherwise the sleep interruption will be interrupted and the process will roll back.

[0066] Step S500: After the main core completes its own sleep action and determines the final clock and power supply configuration of the system and provides basic working conditions for the wake-up source, the system enters sleep.

[0067] Specifically, after the main core completes the hibernation of the sub-core, it needs to perform the hibernation action of the core. Before the main core enters the low-power state, the final system clock and power supply configuration are performed according to the current clock (clk) and power supply (power) selection to provide basic working conditions for the wake-up source, and then the system falls into hibernation.

[0068] Further, in some embodiments of the present invention, each heterogeneous core has a first count value of a corresponding wake-up event number, and the main core has a second count value representing the occurrence of other core events; the sleep wake-up method further includes the following steps:

[0069] Step S600: When the interrupt is triggered, the system hardware pulls up the main core, the main core restores the system clock and power supply, and wakes up until the system is in the resume_early state, and then performs a first-level sleep again judgment;

[0070] Step S700: If the first count value and the second count value have not changed, the main core further determines whether there is an event being processed. If no event is being processed, the system enters sleep mode again.

[0071] Step S800: if the first count value and / or the second count value changes, the main core continues to wake up the system and selectively wakes up the corresponding sub-core according to the wake-up interrupt;

[0072] Step S900: when the main core selectively wakes up the corresponding sub-core according to the wake-up interrupt, a second-level sleep-again judgment is performed to query the first count values ​​of all sub-cores;

[0073] Step S1000: If the first count value does not change, the system enters sleep mode again;

[0074] Step S1100: If the first count value changes, the main core continues to wake up the system, completes the wake-up action, and sends a sleep end notification to all heterogeneous cores.

[0075] Specifically, the multi-core heterogeneous sleep and wake-up framework of the embodiment of the present invention relies on the traditional sleep module to add multi-level re-sleep jump judgment to the traditional sleep framework, and the action logic is embedded in the sleep and wake-up process of the sleep module through platform callback.

[0076] The following key mechanisms exist in the action process, and hierarchical awakening is achieved based on the following mechanisms:

[0077] (1) First-level re-hibernation judgment: The judgment basis for re-hibernation is that the two wake-up count values ​​have not changed, namely "cnt" (first count value) marking the number of wake-up events completed by the core in the hibernation module and "subcnt" (second count value) added in the framework to mark the occurrence of other core events (referring to the wake-up events of the wake-up source not registered by the core). These count values ​​will be recorded and saved as snapshots when hibernation is triggered or hibernation is repeated. At this time, only the main core and the sub-cores that remain running in the previous round of hibernation are online. After the main core completes the wake-up to the resume_early part of the system (one of the device wake-up callbacks defined by the Linux hibernation module, indicating an early device recovery action, at this time only some necessary devices have completed the wake-up or are preparing for the subsequent wake-up of most devices), first determine whether any count value has changed. If so, directly wake up the system. Otherwise, further determine whether there is an event being processed. Wait until no event is being processed or any count value changes. If there is no event being processed and no count changes, the system updates the clock and power supply configuration and enters hibernation again. In order to avoid waking up too many unnecessary devices and increasing the wake-up time, the wake-up source on the main core that needs to sleep again should ensure that it has the ability to handle the wake-up event after resume_early completes the wake-up.

[0078] (2) Second-level re-sleep judgment: The basis for re-sleep judgment is that the "cnt" in the sleep module of each core, which marks the number of wake-up events that the core has completed, has not changed. The main core continues to query the count value on each core until the cnt on any core changes, then wakes up the system. Or if it is determined that no events are being processed on all cores and cnt has not changed, the system updates the clock and power supply configuration and enters sleep again.

[0079] (3) Judgment of keeping the sub-core running: In this framework, a soft type is added to the wake-up source, that is, software-initiated wake-up. A negative number in a specified range that is not covered by the architecture interrupt number is used as the wake-up interrupt number, and the interrupt number is used to distinguish it from the normal wake-up source. Bind this type of wake-up source to the inter-core communication device and the clock and power resources required for the core to keep running. In the sleep process, the non-wake-up interrupt of the interrupt controller will be disabled. When the soft wake-up source of a sub-core is enabled, the main core will enable the interrupt reception of the inter-core communication device separately after the non-wake-up interrupt is disabled, and use it as an interrupt that can actually wake up the system. The main core reserves or configures the required running resources for the sub-core. The sub-core keeps running after the system falls into a sleep scenario and triggers system wake-up by calling the software wake-up interface.

[0080] The first level of sleep again involves the update of the sleep scene within the main core, and the second level of sleep again involves the update of the sleep scene within the entire system. Each time the second level of sleep again, the sub-core will re-judge whether to keep running.

[0081] like Figure 4As shown, in some embodiments of the present invention, the resource management module is responsible for providing clock and power supply resources for selection by each core. The scope of resources involved is limited to system-level resources. For clock, the configuration action only involves the PLL switch, the clock source selection of the system low-frequency and high-frequency clock sources, and the sleep frequency configuration of the main core. For power supply, the configuration action only involves DCDC, LDO switch, and SWITCH control related to a whole power supply. The frequency of the sub-core and the module working clock are configured by the sub-core and the module itself in the sleep wake-up process.

[0082] In addition, the resource management module is also responsible for recording all wake-up interrupts on the main core. The wake-up source is a component of the sleep module. Each core can independently register and enable or disable the wake-up source, and maintain event count information related to the wake-up source. The interrupt numbers that can be used to wake up the system on hardware are limited. The resource management module binds clock and power resources to all interrupt numbers. When the wake-up source of each core is enabled, its interrupt number is passed to the main core, and converted into the hardware interrupt number of the main core and recorded. The record is cleared when the wake-up source is disabled. At the same time as recording and clearing, the clock and power resources bound to the wake-up interrupt are selected and cleared together.

[0083] After the other cores are in sleep mode, the main core obtains the wake-up interrupt number recorded by the resource management module and uniformly applies for the processing function. Before the sub-core wakes up, it receives the wake-up interrupt of the other core and records the information. Before the main core falls into sleep mode, it completes the system resource configuration according to the final clock and power supply resource selection.

[0084] like Figure 4 As shown in the figure, there are two types of resource objects abstracted by the resource management module:

[0085] (1) Specifically refers to the object CLK_A or POWER_A: indicates that the resource object needs to be enabled in this round of dormancy;

[0086] (2) Clock source description relationship CLK_A_FROM_SRC_B: Indicates that clock source B needs to be set for clock A in this round of sleep.

[0087] The role of the resource management module in the framework is similar to that of a restaurant, which provides a resource menu. Each core acts as a customer to select resources and place an order, and the main core completes the configuration and presents a table of food. This approach can refine the granularity of sleep scene adjustment, so that the sleep scene can be flexibly adjusted after the framework is developed, and is no longer a fixed combination of resource configurations defined in advance.

[0088] like Figure 5 As shown, in some embodiments of the present invention, when the framework core layer of the main core is initialized, a sub-core object is registered for each sub-core. The object stores the sub-core state machine, as well as two queues and two tasks that interact with the sub-core actions:

[0089] (1) Sub-core action triggering Task: responsible for triggering sub-core actions and switching state machines through the system inter-core communication module after receiving a signal;

[0090] (2) Sub-core action result detection Task: responsible for detecting the action result and switching the state machine;

[0091] (3) Action trigger signal receiving queue: The signal is actively sent by the framework core layer, and the quilt core action trigger task waits;

[0092] (4) Action result signal receiving queue: The signal is sent by the sub-core action result detection Task and is waited for by the framework core layer.

[0093] The sub-core object maintains its own state machine to represent the action state of the sub-core. The state machine contains 6 states:

[0094] (1) NORMAL: normal operation;

[0095] (2) SUSPENDING: Sleeping;

[0096] (3)SUSPENDED: in sleep mode;

[0097] (4) RESUMING: waking up;

[0098] (5) ERROR: No response;

[0099] (6) KEEP_AWAKE: The core needs to be kept running in this round of hibernation

[0100] State machine switching instructions:

[0101] The sub-core is in the "NORMAL" state when it is operating normally. After the system starts to sleep, if the sub-core needs to keep running in this round of sleep after responding to the sleep trigger request, its state machine is "KEEP_AWAKE", otherwise it switches to "SUSPENDING", and is switched to the "SUSPENDED" state after the sleep action is successful, until the sub-core responds to the wake-up trigger request and is switched to "RESUMING". After the wake-up is completed, it returns to the "NORMAL" state. If the sub-core does not respond to the action request of the main core, its state machine is switched to "ERROR", and an attempt is made to reset and restart the core. The response status of the sub-core can be monitored through the heartbeat packet or request timeout mechanism. The unresponsive sub-core is marked as offline by the main core and is no longer managed.

[0102] In addition, the message passing between cores depends on the inter-core communication device. After the device is in sleep mode, the action results of the two requests of sleep and wake-up are transmitted through the shared register that is not powered off after sleep mode.

[0103] The sleep and wake-up method and system for multi-core heterogeneous products according to the embodiments of the present invention solve the problem of how to coordinate the orderly sleep and wake-up recovery of each core when the multi-core heterogeneous chip is woken up from sleep as a whole, and provide a method for managing sleep scene resources and adaptively switching in each sleep scene. Using this framework, multiple heterogeneous cores are independent individuals in the sleep and wake-up process, each managing its own sleep and wake-up and processing wake-up events, reporting event counts and resource information at specified times, and voting to decide whether the system should wake up or sleep again. The wake-up process can selectively wake up specified cores to achieve hierarchical wake-up. In addition, the framework abstracts the clock and power supply resources, and each wake-up source is bound to the heterogeneous core and the clock and power resources required by each core. The sleep scene resource combination can be flexibly defined, and the sleep scene can be adjusted in real time according to the resource changes after the wake-up event is processed.

[0104] The dormancy awakening method and system for a multi-core heterogeneous product according to an embodiment of the present invention has the following features:

[0105] (1) Action framework logic and multi-level re-sleep mechanism: After a wake-up interrupt is generated, the system can execute only part of the wake-up action and selectively wake up the sub-core to reduce power consumption and save wake-up time, enter a low-power critical state waiting for event processing, and use a multi-level re-sleep mechanism to update the sleep scenarios within different scopes.

[0106] (2) The resource management module refines the granularity of sleep scene adjustment: By abstracting the clock and power supply objects, a limited number of wake-up interrupts can be selected and bound, so that the sleep scene that needs to be entered can be flexibly adjusted by enabling or disabling the wake-up source, providing more refined sleep power consumption adjustment.

[0107] (3) Each heterogeneous core is an independent sleep entity: Each core runs the same sleep module, autonomously manages its own sleep and wakeup, maintains the wakeup source and counting information in the sleep module, and handles wakeup events. The device driver's wakeup source-related processing does not need to pay attention to multi-core heterogeneity and can be regarded as a single core to implement action logic, which simplifies the overall sleep and wakeup interaction logic of the multi-core heterogeneous system. At the same time, the driver code is adaptable to single-core and multi-heterogeneous core systems.

[0108] (4) Each core can participate in determining whether the system can sleep. When adjusting the sleep scenario, for example, when it involves whether the core itself needs to sleep, it only needs to enable the wake-up source according to the actual scenario. Through the multi-level sleep mechanism, each core has the opportunity to adjust the scenario it wants to enter and then put the system into sleep again.

[0109] On the other hand, an embodiment of the present invention further provides an electronic device, including:

[0110] A memory for storing program instructions;

[0111] The processor is used to call the program instructions stored in the memory and execute the above-mentioned sleep and wake-up method of the multi-core heterogeneous product according to the obtained program instructions.

[0112] The processor may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0113] The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other applications. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory, and the processor calls and executes the dormancy wake-up method of the multi-core heterogeneous product in the embodiments of this application; the memory and the processor can be connected through a bus or the like.

[0114] On the other hand, an embodiment of the present invention further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the sleep and wake-up method of the multi-core heterogeneous product is implemented.

[0115] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0116] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0117] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0118] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0119] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0120] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0121] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0122] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A dormancy awakening method for a multi-core heterogeneous product, characterized in that: A sleep and wake-up system applied to a multi-core heterogeneous product, the sleep and wake-up system of the multi-core heterogeneous product comprising a framework core layer, an action interaction module and a resource management module, the framework core layer comprising a plurality of heterogeneous cores, one of which is a main core, and the remaining heterogeneous cores are sub-cores, each of which has a corresponding state machine and a wake-up source, and the action interaction module is used to manage the state of the state machine; The resource management module is used to manage the clock and power supply resources of the system, and allocate corresponding clock and power supply resources to each sub-core and each wake-up source; The sleep awakening method comprises: After the system hibernation is triggered, the main core queries the number of hibernation locks recorded by all the heterogeneous cores through inter-core communication, and determines whether to perform a hibernation operation according to the number of hibernation locks; When performing the sleep operation, the main core sends a sleep start notification to all the heterogeneous cores; After the main core completes task freezing, checking the sleep willingness of each sub-core; The main core puts the sub-core that needs to sleep to sleep into sleep mode, takes over the wake-up interrupt of the sub-core that needs to sleep into sleep mode, records the wake-up interrupt number, updates the clock and power supply resources of the sub-core that needs to sleep into sleep mode, and cuts off the power supply of the sub-core that has already sleep mode; After the main core completes its own sleep action and determines the final clock and power supply configuration of the system and provides basic working conditions for the wake-up source, the system enters sleep.

2. The method for awakening a multi-core heterogeneous product from sleep mode according to claim 1, characterized in that: The step of the main core sending a sleep start notification to all the heterogeneous cores when the sleep operation is performed includes: The action interaction module registers an event notification mechanism on the main core to trigger the same event notification of the sub-core in the callback of the main core; When performing the sleep operation, the main core sends a sleep start notification to itself, and triggers the same notification action of the sub-core through the event notification mechanism.

3. The method for awakening a multi-core heterogeneous product from sleep mode according to claim 1, characterized in that: After the main core completes task freezing, after the step of checking the sleep willingness of each sub-core, the method further includes: If the sub-core needs to keep running in this round of dormancy, the action interaction module switches the state machine of the sub-core to keep running, and the main core retains the clock and power supply resources of the sub-core that needs to keep running; The main core adds a first identifier to a system core device required by the sub-core to keep running, and does not put the system core device with the first identifier to sleep.

4. The method for awakening a multi-core heterogeneous product from sleep mode according to claim 1, characterized in that: After the steps of the main core putting the sub-core that needs to sleep to sleep into sleep mode, taking over the wake-up interrupt of the sub-core that needs to sleep into sleep mode, recording the wake-up interrupt number, updating the dependent resources of the sub-core that needs to sleep into sleep mode, and cutting off the power supply of the sub-core that has already sleep mode, the process further includes: When all the sub-cores that need to sleep have successfully done so, the main core continues the subsequent sleep action; When the sub-core that needs to sleep fails to sleep, the main core interrupts the sleep and performs process rollback.

5. The method for awakening a multi-core heterogeneous product from sleep mode according to claim 1, characterized in that: The step of taking over the wake-up interrupt of the sub-core that needs to sleep and recording the wake-up interrupt number includes: The main core uniformly applies for a processing function for all the wake-up interrupt numbers, and takes over the wake-up interrupt of the dormant sub-core through the processing function.

6. The method for awakening a multi-core heterogeneous product from sleep mode according to claim 1, characterized in that: Each of the heterogeneous cores has a first count value of the corresponding number of wake-up events, and the main core has a second count value representing the occurrence of other core events; The sleep awakening method further includes: When an interrupt is triggered, the system hardware pulls up the main core, the main core restores the system clock and power supply, and wakes up until the system is in the resume_early state, and then performs a first-level sleep again judgment; If the first count value and the second count value do not change, the main core further determines whether there is an event being processed, and if no event is being processed, the system enters sleep again; If the first count value and / or the second count value changes, the main core continues to wake up the system and selectively wakes up the corresponding sub-core according to the wake-up interrupt.

7. The method for awakening a multi-core heterogeneous product from sleep mode according to claim 6, characterized in that: The sleep awakening method further includes: When the main core selectively wakes up the corresponding sub-core according to the wake-up interrupt, a second-level re-sleep judgment is performed to query the first count value; If the first count value does not change, the system enters sleep mode again; If the first count value changes, the main core continues to wake up the system, completes the wake-up action, and sends a sleep end notification to all heterogeneous cores.

8. A dormancy wake-up system for multi-core heterogeneous products, characterized in that: It includes a framework core layer, an action interaction module and a resource management module, wherein the framework core layer includes a plurality of heterogeneous cores, one of which is a main core, and the other heterogeneous cores are sub-cores, each of which has a corresponding state machine and a wake-up source, and the action interaction module is used to manage the state of the state machine; The resource management module is used to manage the clock and power supply resources of the system, and allocate corresponding clock and power supply resources to each sub-core and each wake-up source; the sleep and wake-up system is used to execute the sleep and wake-up method for multi-core heterogeneous products as described in any one of claims 1-7.

9. An electronic device, characterized in that: include: A memory for storing program instructions; The processor is used to call the program instructions stored in the memory, and execute the sleep and wake-up method of the multi-core heterogeneous product according to any one of claims 1 to 7 according to the obtained program instructions.

10. A storage medium, characterized in that: The storage medium stores computer executable instructions, and the computer executable instructions are used to enable a computer to execute the sleep and wake-up method for a multi-core heterogeneous product according to any one of claims 1 to 7.

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