Test stimulus code optimization method, device, equipment and medium

Abstract

This invention discloses a method, apparatus, device, and medium for optimizing test stimulus code. Relating to the field of chip verification technology, the method includes: obtaining constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment; identifying and sorting the target constraint expressions to be optimized based on the included constraint quantities; traversing each target constraint expression according to the sorting result and progressively determining the target value range of the target constrained random variable in each target constraint expression; recoding the target value range of each target constrained random variable according to a set data width unit based on the data width of each target constrained random variable; and adding the recoding result to the test stimulus code. By progressively narrowing the target value range of the target constrained random variable and recoding it sequentially, the size of the constraint solving problem input to the solving engine is reduced, thereby improving the performance of the constraint solver.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a method, apparatus, device, and medium for optimizing test stimulus code. Background Technology

[0002] Software simulation tools can be used to simulate the behavior of electronic systems and circuits, and to simulate the logic behavior of circuits, including signal transmission, logic operations and timing control, in order to verify whether the functions and timing constraints of chip circuits are correct.

[0003] As problem size and complexity increase, the performance of constraint solvers based on the SAT (Boolean Satisfiability) engine deteriorates due to the expansion of the search space. Existing techniques, improving the SAT algorithm can enhance the performance of constraint solvers based on the SAT engine. While this directly improves the solver's computational efficiency and ability to handle complex problems, it also increases the complexity of the algorithm implementation, risks over-optimization for specific problem types, and a decrease in the solver's generalization ability when dealing with new or unforeseen problems. Summary of the Invention

[0004] This invention provides an optimization method, apparatus, device, and medium for test stimulus code to solve the problem of performance degradation of constraint solvers based on the SAT solver engine due to the large scale of constraint problems in large-scale constraint scenarios.

[0005] According to one aspect of the present invention, a method for optimizing test incentive code is provided, comprising:

[0006] Obtain constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment. Each constraint expression contains a constrained random variable and a constraint quantity used to constrain the range of values ​​of the constrained random variable. The constraint quantity can be a constant or other random variable. Based on the constraint quantity contained in the constraint expression, identify the target constraint expression to be optimized in each constraint expression and sort the target constraint expressions. Traverse each target constraint expression according to the sorting result, and gradually determine the target range of values ​​of the target constrained random variable in each target constraint expression during the traversal process. The target range of values ​​contains only constants. Based on the data width of each target constrained random variable, recode the target range of values ​​of each target constrained random variable according to the set data width unit, and add the recoding result to the test stimulus code.

[0007] According to another aspect of the present invention, an optimization apparatus for test stimulus code is also provided, comprising:

[0008] The constraint expression acquisition module is used to acquire constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment; the target constraint expression sorting module is used to identify the target constraint expressions to be optimized from each constraint expression according to the constraint quantities contained in the constraint expressions, and sort the target constraint expressions; the target value range determination module is used to traverse each target constraint expression according to the sorting results, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process; the target value range recoding module is used to recode the target value range of each target constrained random variable according to the data width of each target constrained random variable and according to the set data width unit, and add the recoding result to the test stimulus code.

[0009] According to another aspect of the present invention, an electronic device is also provided, the electronic device comprising:

[0010] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the optimization method of test stimulus code according to any embodiment of the present invention.

[0011] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the method for optimizing test stimulus code according to any embodiment of the present invention.

[0012] According to another aspect of the present invention, a computer program product is also provided, including computer instructions that, when executed by a processor, implement the steps of the method as described in any embodiment of the present invention.

[0013] The technical solution of this invention obtains constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment, identifies and sorts the target constraint expressions to be optimized based on the included constraint quantities, iterates through each target constraint expression according to the sorting result, and progressively determines the target value range of the target constrained random variable in each target constraint expression. Based on the data width of each target constrained random variable, the target value range of each target constrained random variable is recoded according to a set data width unit, and the recoding result is added to the test stimulus code. By progressively narrowing the target value range of the target constrained random variable and recoding it, the test stimulus code is optimized, the size of the constraint solving problem input to the solving engine is reduced, and the performance of the constraint solver is improved.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a method for optimizing test incentive code according to Embodiment 1 of the present invention;

[0017] Figure 2 This is an example diagram of an abstract syntax tree applicable to embodiments of the present invention;

[0018] Figure 3 This is a schematic diagram of the structure of an optimization device for test stimulus code according to Embodiment 2 of the present invention;

[0019] Figure 4 This is a schematic diagram of the structure of an electronic device that implements the optimization method for test incentive code according to embodiments of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Example 1

[0023] Figure 1 This is a flowchart of a test stimulus code optimization method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where the size of the constraint solution problem input to the solver engine is reduced during the chip verification stage. This method can be executed by a test stimulus code optimization device, which can be implemented in hardware and / or software and is generally configured in an electronic device. Figure 1 As shown, the method includes:

[0024] S110. Obtain the constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment.

[0025] In this embodiment of the invention, test stimulus code can be specifically understood as code used to simulate input conditions for chip or circuit design. This code is used to generate signals in a simulation environment to verify the correctness of the design. Test stimuli can include the generation of clock, reset, data input, and control signals. The same scope can be specifically understood as the context range that variables or functions can access in a programming language. In SystemVerilog, the scope can be local (e.g., variables defined inside a function or module) or global (e.g., variables defined outside a module). Variables within the same scope can access each other, while variables from different scopes need to interact through specific methods (e.g., parameter passing or global variables). Constraint expressions can be specifically understood in SystemVerilog as defining the legal value range of variables, used for generating random variables to ensure that the generated test data meets specific conditions. Constraint expressions can be simple conditional statements or complex combinations of logical statements used to control the generation process of random variables.

[0026] S120. Based on the constraint quantities contained in the constraint expressions, identify the target constraint expressions to be optimized in each constraint expression, and sort the target constraint expressions.

[0027] In this embodiment of the invention, the constraint quantity can be specifically understood as a quantity used in the constraint expression to restrict the value of the random variable; it can be a constant or other random variable. The constraint expression can be specifically understood as a logical expression used to restrict the value of the random variable; it can be an expression containing relational operators (such as <, <=, ==, >=, or >), logical operators (such as &&, ||, or !), set membership operators (such as inside), and distribution operators (such as dist). Through these expressions, complex relationships and conditions between random variables can be defined.

[0028] In this embodiment of the invention, the constraint expression to be optimized can be specifically understood as the expression involving the existence of a number of uncertain solutions for a certain random variable (e.g., 3≤x≤5; 10≤y≤20; x≤z≤y, where z has a number of uncertain solutions), and the expression involving at least two expressions restricting the range of values ​​for a certain random variable (e.g., 2≤z≤10; 3≤z≤6). The purpose of optimization is to find a solution that satisfies all constraints by adjusting the constraint expressions to narrow the range of values ​​for the random variable and reduce the size of the constraint problem. The sorting of constraint expressions can be understood as defining a processing priority among multiple constraints. The processing priority of constraints can be determined based on the dependencies between constraints, the complexity of the constraints, and the test coverage. That is, if some constraints depend on the results of other constraints, then the dependent constraints should be given higher priority; constraints that improve test coverage should be satisfied first; more complex constraints require more computational resources, so they can be given higher priority to reduce solution time. In SystemVerilog, the solve-before constraint can be used to specify the solution order of random variables. For example, `solve xbefore y;` means to solve the random variable x before solving the random variable y. When the range of values ​​of the random variable y depends on the random variable x, this can affect the order in which the random variables are solved. By first determining the range of values ​​of the dependent random variable x, the range of values ​​of the target random variable y can be narrowed, making it easier to satisfy the constraints of the variables.

[0029] S130. According to the sorting results, traverse each target constraint expression and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process.

[0030] Specifically, after assigning priorities and sorting each objective constraint expression, each expression is traversed from highest to lowest priority. For each random variable, its possible value range is determined step by step by applying the constraint expression. For example, if multiple constraint expressions restrict the value range of the same random variable, redundant constraints can be removed and similar constraints can be merged to simplify the value range of the random variable and reduce the scale of the constraint solution problem, while ensuring that there are no conflicts between constraints. Removing redundant constraints can include: if two constraints restrict the same variable range and these ranges overlap, then only the stricter constraint can be retained; if some constraints will never be satisfied or are irrelevant to the possible value range of the variable, these constraints should be deleted. Merging similar constraints can include: if two constraints cover the same range, or if the merged constraint can accurately cover all overlapping parts and will not introduce new, unnecessary restrictions, they can be merged into one constraint; if multiple constraints are only effective under the same conditions, they can be merged into one condition constraint.

[0031] S140. Based on the data width of each target constrained random variable, recode the target value range of each target constrained random variable according to the set data width unit, and add the recoding result to the test stimulus code.

[0032] In this embodiment of the invention, data width can be specifically understood as the number of bits used when storing or transmitting data. In programming languages, such as SystemVerilog, data types have explicit bit widths (e.g., int, bit, and logic have bit widths of 32 bits, 1 bit, and 1 bit, respectively). Recoding can be specifically understood as the process of converting data from one encoding format to another. According to specific rules or algorithms, input data is mapped to different output data, and the wide-bit representation of the original data is mapped to a new narrow-bit representation to reduce the number of bits required to represent the data, thus compressing the data. Based on the target value range of each constrained random variable, the encoding strategy is optimized to minimize the required number of bits. For example, Huffman coding or other variable-length coding techniques can be used to assign shorter codes to random variables while satisfying constraints. After recoding, the recoding result is added to the test stimulus code to optimize the test stimulus code.

[0033] The technical solution of this invention obtains constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment, identifies and sorts the target constraint expressions to be optimized based on the included constraint quantities, iterates through each target constraint expression according to the sorting result, and progressively determines the target value range of the target constrained random variable in each target constraint expression. Based on the data width of each target constrained random variable, the target value range of each target constrained random variable is recoded according to a set data width unit, and the recoding result is added to the test stimulus code. By progressively narrowing the target value range of the target constrained random variable and recoding it, the test stimulus code is optimized, the size of the constraint solving problem input to the solving engine is reduced, and the performance of the constraint solver is improved.

[0034] Optionally, in this embodiment of the invention, identifying the target constraint expression to be optimized from each constraint expression based on the constraint quantities contained in the constraint expressions may include:

[0035] Initialize the first and second type constraint variable lists; extract one constraint expression from each constraint expression and use it as the current constraint expression; if all constraint variables in the current constraint expression are constants, then the current constraint expression is determined as a first type target constraint expression belonging to univariate constraints, and the constrained random variables in the current constraint expression are added to the first type constraint variable list; if the constraint variables in the current constraint expression are constants and random variables from the first type constraint variable list, or both are any random variables from the first type constraint variable list, then the current constraint expression is determined as a second type target constraint expression belonging to multivariate association constraints, and the constrained random variables in the current constraint expression are added to the first type constraint variable list. The constrained random variable is added to the second type of constraint variable list. If the constraint quantity in the current constraint expression is a constant and a random variable in the second type of constraint variable list, a random variable in the first type of constraint variable list and a random variable in the second type of constraint variable list, or both are random variables in the second type of constraint variable list, then the current constraint expression is determined as a second type of target constraint expression belonging to multivariate association constraints, and the constrained random variable in the current constraint expression is added to the second type of constraint variable list. The operation of obtaining a constraint expression in each constraint expression is repeated until no new first type or second type target constraint expression can be determined.

[0036] In the embodiments of the present invention, the first type of constrained variable list can be specifically understood as: the constrained random variables in the first type of target constraint expression, that is, the set composed of the constrained random variables in the single-variable constraint expression. Among them, single-variable constraint means that the constraint quantities in the current constraint expression are all constants. For example, var inside{[constant1:constant2]} or var>constant1; var<constant2, where var represents a variable and constant represents a constant. In SystemVerilog, inside is a set membership operator, which is used to constrain the value range of a random variable. When a random variable is constrained to be inside a specific set, it must satisfy at least one element in the set. var inside{[constant1:constant2]} means that the value range of var is constant1≤var≤constant2.

[0037] The second type of constrained variable list can be specifically understood as: the constrained random variables in the second type of target constraint expression, that is, the set composed of the constrained random variables in the multi-variable association constraint expression. Among them, multi-variable association constraint means that the constraint quantities in the current constraint expression are any one of constants and the random variables in the first type of constrained variable list, all the random variables in the first type of constrained variable list, constants and the random variables in the second type of constrained variable list, the random variables in the first type of constrained variable list and the random variables in the second type of constrained variable list, or all the random variables in the second type of constrained variable list. For example, var1 inside{[var2:var3]}; where the constraints involved in var2 and var3 are constants and single-variable constraints, all single-variable constraints, constants and multi-variable association constraints, single-variable constraints and multi-variable association constraints, or all multi-variable association constraints, and the range of var1 is jointly determined by var2 and var3. In addition, it can also include a third type of constraint, that is, the range of variables cannot be further simplified and determined by sorting or other means through other constraints, or it can be understood as a constraint other than single-variable constraint and multi-variable association constraint.

[0038] Specifically, the first and second types of constraint variable lists are initialized to empty. One constraint expression is retrieved from each constraint expression. If the constraint quantity determines it to be a univariate constraint expression, and the constrained random variable is not in the first type of constraint variable list, the constrained random variable in the expression is added to the first type of constraint variable list. If the constraint quantity determines it to be a multivariate correlation constraint expression, and the constrained random variable is not in the second type of constraint variable list, the constrained random variable in the expression is added to the second type of constraint variable list. This process of retrieving one constraint expression from each constraint expression is repeated until no new first or second type target constraint expression can be determined in this round of execution. The remaining undetermined constraint expressions are then classified as third type target constraint expressions. Thus, the first type of target constraint expression is identified based on the constraint quantity, followed by the second type, and the third type expression can also be determined.

[0039] Optionally, in this embodiment of the invention, sorting the target constraint expressions may include:

[0040] The first type of objective constraint expressions are randomly sorted to obtain the first sorting result; the second type of objective constraint expressions are sorted according to the dependency relationship between the random variables in the constraint quantities to obtain the second sorting result; the second sorting result is appended to the first sorting result to obtain the final sorting result.

[0041] Specifically, since the first type of objective constraint expressions only contain constrained random variables and the constraint quantities are all constants, the order of the objective constraint expressions does not affect the solution of other variables. Because the range of variables in the third type of constraints cannot be determined regardless of their order, the final gate-level descriptions are all the same. That is, no sorting is needed for the first and third types of constraints; only the second type of constraints need to be sorted. Therefore, the first type of objective constraint expressions are randomly sorted to obtain the first sorting result; the second type of objective constraint expressions are sorted according to the dependencies between the random variables in the constraint quantities, i.e., according to the identification order of the objective constraint expressions to be optimized, or according to the order in which the constrained random variables in the expressions are added to the list of second-type constraint variables, to obtain the second sorting result; the third type of objective constraint expressions can also be randomly sorted to obtain the third sorting result; thus, the second sorting result is appended to the first sorting result, and the third sorting result is appended to the second sorting result to obtain the final sorting result.

[0042] Optionally, in this embodiment of the invention, sorting the expressions of each second type of objective constraint according to the dependency relationship between the random variables in the constraint quantities to obtain a second sorting result may include:

[0043] In each sorting round, the current second-type target constraint expression in each unsorted second-type target constraint expression is retrieved sequentially, and random variables in each current constraint quantity are extracted from the current second-type target constraint expression. If all random variables in the current constraint quantities are located in the dependent item set, the current second-type target constraint expression is added to the sorting queue, and the process of retrieving the current second-type target constraint expressions in each second-type target constraint expression is returned. The dependent item set is initialized and stored with the constrained random variables in each first-type target constraint expression. If at least one current constraint quantity is not located in the dependent item set, the process of retrieving the current second-type target constraint expressions in each second-type target constraint expression is returned directly. After completing the processing of the current sorting round, the constrained random variables in each newly added second-type target constraint expression in the sorting queue are added to the dependent item set. In the new sorting round, the process of retrieving the current second-type target constraint expressions in each second-type target constraint expression is repeated until all second-type target constraint expressions are added to the sorting queue, resulting in the second sorting result.

[0044] Specifically, the dependent set refers to the set defined by the value of another variable that the constrained random variable used in the constraint expression depends on. This dependency is usually reflected in the constraints of random variables, where the set of legal values ​​for one variable is determined by the current value of another variable. In this embodiment of the invention, the dependent set stores the constrained random variables in the constraint expressions that have been sorted. Since the constraint quantities in the first type of target constraint expression are constants, the order of the target constraint expressions does not affect the solution of other variables. The dependent set is initialized with the constrained random variables in each of the first type of target constraint expressions, serving as the dependency of the constrained random variables in the second type of target constraint expression.

[0045] In each round of sorting the second type of target constraint expressions, the current second type of target constraint expression is obtained sequentially, and each current constraint quantity is extracted. If all currently processed constraint quantities are located in the dependent set, that is, the constraint quantities that the constrained random variables depend on are all derived from the sorted constraint expressions, the current second type of target constraint expression is added to the sorting queue, and the current operation is returned. If at least one current constraint quantity is not located in the dependent set, the current second type of target constraint expression is not sorted, and the current operation is returned directly. After completing the sorting operation of the second type of target constraint expressions in this round, the constrained random variables in each newly added second type of target constraint expression in the sorting queue are added to the dependent set, and a new sorting round is started. The operation of obtaining the current second type of target constraint expression is re-executed in the remaining second type of target constraint expressions that have not participated in the sorting, until all second type of target constraint expressions are added to the sorting queue, and the second sorting result is obtained, realizing the sorting of the second type of target constraint expressions according to the dependency relationship between random variables.

[0046] Optionally, in this embodiment of the invention, traversing each target constraint expression according to the sorting result, and progressively determining the target value range of the target constrained random variable in each target constraint expression during the traversal process, may include:

[0047] Set an initial value range for each objective constrained random variable; traverse each objective constraint expression sequentially according to the sorting result, and update the value range of each objective constrained random variable according to the constraint content in each objective constraint expression; after completing the traversal of all objective constraint expressions, obtain the objective value range of each objective constrained random variable.

[0048] Specifically, in the process of progressively determining the target value range of the constrained random variables in each objective constraint expression, an initial value range is first set for each constrained random variable, for example, [-inf:inf], meaning the variable's value range is unrestricted, extending from negative infinity to positive infinity, covering all possible value ranges of the random variable. Subsequently, during the sequential traversal of each objective constraint expression according to the sorting results, the target value range of the constrained random variable is determined based on the constraint content in each objective constraint expression and updated sequentially to the preset initial value range. After completing the traversal of all objective constraint expressions, the final target value range of each constrained random variable is obtained. Sort the constraint expressions according to the dependency order of the random variables and optimize the value range of the random variables, which can significantly improve the efficiency and success rate of constraint solving. This method reduces the workload of the solver in finding solutions that satisfy all constraints, avoids invalid randomization attempts, enhances the quality of testing, and improves test coverage. Furthermore, it helps improve the verifiability of the design, ensures the rational use of resources, and makes the test data more representative, thereby covering more test scenarios.

[0049] Optionally, in this embodiment of the invention, traversing each target constraint expression sequentially according to the sorting result, and updating the value range of each target constrained random variable according to the constraint content in each target constraint expression, may include:

[0050] When traversing to the current second type of target constraint expression, obtain the current target constrained random variable contained in the second type of target constraint expression, and at least one target random variable used to constrain the value range of the current target constrained random variable; if the target random variable constrains the upper boundary of the current target constrained random variable, then obtain the maximum value of the target random variable in the already updated value range of the target random variable, and use the maximum value to update the upper boundary of the current target constrained random variable; if the target random variable constrains the lower boundary of the current target constrained random variable, then obtain the minimum value of the target random variable in the already updated value range of the target random variable, and use the minimum value to update the lower boundary of the current target constrained random variable.

[0051] Specifically, when iterating through each target constraint expression and updating the range of values ​​for the target constrained random variable, since the constraint quantity of the second type of target constraint expression contains at least one random variable (the optional combination of constraint quantity is constant and first type of constraint random variable, both are first type of constraint random variables, constant and second type of constraint random variable, first type of constraint random variable and second type of constraint random variable, or both are second type of constraint random variables), the current target constrained random variable contained in the second type of target constraint expression is obtained, as well as at least one target random variable used to constrain the range of values ​​for the current target constrained random variable. When the target random variable constrains the upper boundary of the current target constrained random variable, the maximum value of the target random variable is obtained in the already updated range of values ​​for the target random variable, and the upper boundary of the current target constrained random variable is updated. For example, in the case of var1 inside{[3:var2]}; var2inside{[var2_min:var2_max]}, this case can be transformed into var1 inside{[3:var2_max]}. When the target random variable constrains the lower boundary of the current target constrained random variable, the minimum value of the target random variable is obtained within the already updated range of values, and the lower boundary of the current target constrained random variable is updated. For example, in the case of `var1 inside{[var2:3]}; var2 inside{[var2_min:var2_max]}`, this can be transformed into `var1 inside{[var2_min:3]}`, converting the range of random variable values ​​into a form containing only constant constraints. This improves the determinism and predictability of the simulation because it provides clear value boundaries, making the results easier to reproduce. This constraint method simplifies the solution process, speeds up the solution, and reduces the dependencies between random variables, thereby reducing the complexity of the problem.

[0052] Optionally, in this embodiment of the invention, the data width unit is 1 bit. Recoding the target value range of each constrained random variable according to the set data width unit can include:

[0053] Calculate the number of extreme value bits for each constrained random variable based on the target value range and data width of each constrained random variable; recode the target value range of each constrained random variable based on the data width range of 0 bits in the extreme value bits of each constrained random variable.

[0054] Specifically, calculating the number of extreme bits for a constrained random variable involves determining the minimum and maximum values ​​of the variable, and then calculating the bit width of these two values. The number of extreme bits refers to the minimum number of bits required to represent the maximum and minimum values ​​of the random variable. For each constraint expression that has been sorted and optimized for its value range, the target value range of each constrained random variable is limited by recoding based on the data width range of the 0 bits in the extreme bit count for each constrained random variable. For example:

[0055] rand int rand_var;

[0056] constraint c_rand_var{

[0057] rand_var inside{4:15};}

[0058] Here, `rand_var` is an `int` type variable with 32 bits. The minimum value of `rand_var` is 4, which is represented as 100 in binary and requires 3 bits to represent. The maximum value is 15, which is represented as 1111 in binary and requires 4 bits to represent. Therefore, in this example, `rand_var` can be recoded as:

[0059] rand_var[31:4]==28'b0; rand_var[3:0]inside{[4:15]};

[0060] By recoding the random variable to limit its bit count by limiting the number of extreme bits, we can optimize the allocation of storage resources, ensure that no bits are wasted, reduce the size of the constraint solving problem, reduce power consumption, and improve the efficiency of verification.

[0061] Specific application scenarios

[0062] Figure 2 This is an example diagram of an abstract syntax tree applicable to embodiments of the present invention. An AST (Abstract Syntax Tree) is a tree-like representation of source code, showcasing the syntactic structure of a programming language in a tree-like structure. In a compiler or interpreter, source code is first parsed into an AST. This process ignores formatting details (such as spaces and parentheses) and focuses on its syntactic structure. ASTs facilitate program analysis, optimization, and execution.

[0063] For example, consider a piece of System Verilog code regarding random variables and constraints:

[0064] rand bit[31:0]x;

[0065] constraint c1{x<10;x! =5;x>=2;}

[0066] The code contains two key pieces of information: the definition of the random variable x and the set c1 consisting of constraint expressions. These two are called the expression-level constraint description. At this point, the constraints are only in string form; they need to be converted into an abstract syntax tree. Taking x < 10 as an example, the corresponding structure is as follows: Figure 2 As shown:

[0067] x<10 can be viewed as an expression tree. The root node is of type Boolean operation, meaning that if the expression is true, the overall expression is true, otherwise it is false.

[0068] If the expression evaluates to false, it means the constraint cannot be satisfied, i.e., the solution fails. The root node has only one child node, and its type is binary operation, with the operator being less than. Since it's a binary operation, it must have two child nodes: child node 1 is a reference to the random variable, i.e., the variable itself; child node 2 is a constant node. Both of these nodes are leaf nodes.

[0069] Similarly, each constraint in the constraint set can be transformed into a similar expression tree, with the root node of each expression tree being a Boolean operation. Combining the root nodes of each expression using a logical AND (&&) operation yields only one root node, which is the root node of the abstract syntax tree. This root node is also a Boolean operation; a return value of 1 indicates that the value of the random variable satisfies all constraints, while a return value of 0 indicates that at least one constraint cannot be satisfied. During the construction of the abstract syntax tree, each constraint can be modified based on the type of expression operation.

[0070] Test stimulus code, without code optimization, often involves a large constraint-solving problem. For example, when the test stimulus code is:

[0071] rand bit[31:0]x,y,z,u,v,w;

[0072] constraint c1{

[0073] x inside{[0:50]}; z inside{[20:40]}; y inside{[x:z]};

[0074] u inside{[y:y+20]}; v inside{[z-10:u]};

[0075] x+y>=w;}

[0076] The code above is analyzed using abstract syntax trees (ASTs). These three inputs are transformed into three ASTs. The leaf nodes of these three ASTs share the same reference variables: x, y, and z. The array of ASTs forms the input to this algorithm.

[0077] If this set of constraints is directly input into the SAT engine without optimization, the number of bits to be randomized is 192, meaning there are at most 2^192 possibilities, resulting in a very large computational load. Therefore, minimizing the number of bits to be randomized input into the SAT engine can significantly accelerate the solution process. The constraint optimization process based on abstract syntax trees can be specifically described as follows:

[0078] 1. Constraint Classification and Sorting

[0079] Constraint solvers are generally used to generate random stimuli that conform to specific rules. In the field of chip verification, random simulation is an indispensable part. Random stimuli are generally used to verify whether the output of a chip design circuit meets the designer's expectations under specific random inputs. In SystemVerilog syntax, the variables modified by the rand and randc keywords are random variables (stimuli) that need to satisfy specific constraints. As mentioned above, these variables serve as inputs to the chip design circuit. Based on the output of the chip design circuit or its sub-circuits, it is determined whether the circuit design being verified meets expectations.

[0080] Traditional constraint solvers, in scenarios without solve-before constraints, do not prioritize constraints; each constraint has the same weight and is solved simultaneously. This means that regardless of the order in which constraints are analyzed, the final gate circuits input to the SAT engine are the same. However, the range of some variables can deduce the range of others; therefore, the order in which constraints are analyzed is a crucial factor for code optimization. In constraint programming, solve-before constraints can be used to specify the order in which variables are solved, ensuring that dependent variables are processed and determined first, thus optimizing the search process and adjusting probability distributions. Solve-before constraints cannot be used for randc type variables (used to declare periodic random variables) because they are always solved first. Therefore, this specific application scenario only discusses random variables modified by the rand keyword and their associated constraints; random variables modified by the randc keyword are not within the scope of this specific application scenario.

[0081] At this stage, the input is the array of abstract syntax trees obtained previously. After constraint classification, three arrays are obtained, namely three classifications: single-variable constraints, multi-variable association constraints, and other constraints. The input for the sorting stage is the array composed of the second type of abstract syntax trees, that is, multi-variable association constraints. The output result is the array composed of the sorted second type of abstract syntax trees, which is sorted according to the solution priority.

[0082] 1.1 Traverse all constraints and classify them into three categories

[0083] The first type of constraint is a single-variable constraint, which contains only one random variable (var) and the rest are constants (constant). For example, var inside{[constant1:constant2]}; that is, constant1≤var≤constant2 or var>constant1; var<constant2. Single-variable constraints are the most common. The second type of constraint is a multi-variable association constraint, which contains multiple random variables. For each random variable, either all the constraints it involves are of the first type, or its range can be determined by other random variables. For example, var1 inside{[var2:var3]}, that is, var2≤var1≤var3; the constraints involved by var2 and var3 are all of the first type, and the range of var1 is determined jointly by var2 and var3. The third type of constraint is other constraints, and the range of variables cannot be further simplified or determined by sorting or other means, such as var1 + var2 < var3. This operation can reduce the complexity of the subsequent sorting. For the above example, the first type of constraints are: x inside{[0:50]}; z inside{[20:40]}; the second type of constraints are: y inside{[x:z]}; u inside{[y:y + 20]}; v inside{[z - 10:u]}; the third type of constraint is: x + y >= w.

[0084] 1.2 Constraint sorting

[0085] After constraint classification, it is necessary to sort the constraints belonging to different categories because the range of some variables is determined by the range of other variables, that is, there is a dependency relationship between variables. For the first type and the third type of constraints, no sorting is required. The first type of constraint contains only single variables, and the order does not affect the solution of other variables. Sorting the third type of constraint is meaningless. No matter how it is sorted, the range of variables therein cannot be determined, resulting in the same description at the gate circuit level in the end.

[0086] Therefore, only the second type of constraints need to be sorted. The sorting algorithm is similar to topological sorting, constructing a directed acyclic graph (DAG). It is worth noting that this DAG is for random variables, not constraints. First, random variables whose range can be determined solely by the first type of constraints are placed at the top, denoted as sv0; then, random variables whose range can only be determined by variables in sv0 are placed, denoted as sv1, and constraints containing at least sv1 (i.e., containing a constant and sv1, sv0 and sv1, or only sv1) are denoted as sc1; and so on, until constraints containing at least sv2 are obtained, denoted as sc2, up to scN.

[0087] After sorting the second type of constraints, they are then sorted in the order of first, second, and third type constraints to obtain the final constraint sort. For the example above, the second type of constraints are sorted as follows:

[0088] sc0:y inside{[x:z]};

[0089] sc1:u inside{[y:y+20]};

[0090] sc2:v inside{[z-10:u]};

[0091] 2. Range analysis of random variables

[0092] After obtaining the sorting of constraints, analysis is performed based on the sorted constraints. By traversing the constraints involved in each variable, the range of random variables is continuously narrowed, thereby determining the value range of each variable and obtaining a result in the form of var inside{[min:max]}.

[0093] First, set an initial range for all variables: [-inf:inf], which is from negative infinity to positive infinity. To obtain the final range of variables, iterate through all constraints, starting with the first type of constraint. During the constraint iteration, continuously update the range of the variables. After completing the first type of constraints, iterate through the second type of constraints. When encountering constraints of the form var1inside{[var2:var3]} during the iteration of the second type of constraints, they can be transformed into the form var1 inside{[var2_min:var3_max]}, where var2_min refers to the minimum value that var2 can take, and var3_max refers to the maximum value that var3 can take. After completing the iteration of the second type of constraints, the range analysis of the random variables is complete; there is no need to iterate through the third type of constraints.

[0094] The input for this stage is the array of abstract syntax trees (ASTs) formed by the first type of univariate constraints and the second type of multivariate association constraints obtained in the previous stage. In this stage, the algorithm prioritizes analyzing the first type of constraints to obtain the ranges of some random variables. Then, based on these ranges, it iterates through and analyzes the second type of constraints. Since the array of second type constraints is sorted, it can inevitably obtain the ranges of random variables contained only by the first and second types of constraints. That is, the output is an array consisting of the random variables contained only by the first and second types of constraints and their ranges. In other words, the original range of the random variables contained only by the first and second types of constraints is [-inf:inf]. After this stage, it can be narrowed down to [a:b], where -inf <= a <= b <= inf. This range does not represent the final value range of the variable, but rather the search range for the next solution stage (logic synthesis and SAT solving). A smaller range means less search space and faster solution speed.

[0095] 3. Recoding the range of random variables

[0096] After obtaining the ranges of all variables, these ranges are recoded and displayed in the constraints to reduce the size when converting to gate circuits in the next step. For example:

[0097] rand int a;a inside{[0:20]};

[0098] a can be recoded as:

[0099] a[31:5]==27'b0;a[4:0]inside{[0:20]};

[0100] That is, bits 5 to 31 (27 bits in total) of 'a' are set to zero, the value of 'a' is in the range of 0 to 20, and the operation is performed only on bits 0 to 4 of 'a'. This operation greatly reduces the size of the gate circuit generated.

[0101] The input to this stage is an array of random variables and their ranges that are only included in the first and second types of constraints, obtained from the previous stage, and an array of abstract syntax trees (ASTs) composed of the first and second types of constraints. The operation in this stage involves directly modifying the ASTs of the first and second types of constraints, using the recoded random variables to construct new subtrees of the ASTs, and replacing the corresponding nodes in the original ASTs, resulting in a new AST array. This new AST array is the output of this stage.

[0102] In the subsequent constraint solving phase, the logical synthesis phase, the abstract syntax tree is transformed into a gate-level netlist through logical synthesis, and then into Conjunctive Normal Form (CNF) as input to the Sat solver. The optimized abstract syntax tree corresponds to a gate-level netlist with fewer nodes, resulting in a CNF with fewer clauses. The Sat solver can be understood as a search algorithm; fewer clauses mean a smaller search space, which means finding the answer that satisfies all constraints faster, thus accelerating constraint solving. For example:

[0103] rand int a,b,c;

[0104] constraint c1{

[0105] a inside{[0:20]};

[0106] b inside{[0:100]};

[0107] c = a % b;

[0108] Without optimization, the above example would require 32x32 operations for 'c'. After optimization using the incentive code optimization method provided by this invention, the above example becomes:

[0109] rand int a,b,c;

[0110] constraint c1{

[0111] a[31:5]==0; b[31:7]==0;

[0112] a[4:0]inside{[0:20]};

[0113] b[6:0]inside{[0:100]};

[0114] c = a[4:0]%b[6:0];}

[0115] After optimization, c only needs to perform 5 x 7 operations, resulting in a speedup of approximately 30 times. Compared to the speedup effect, the overhead of the optimization algorithm itself is negligible.

[0116] The optimization method for the incentive code provided by this invention can greatly reduce the size of the input SAT solver engine for constraint solving problems, and enable the rapid generation of random variables that satisfy specific constraints and are uniformly distributed, thereby improving the performance of the constraint solver.

[0117] Example 2

[0118] Figure 3 This is a schematic diagram of a test stimulus code optimization device provided in Embodiment 2 of the present invention. Figure 3 As shown, the device includes: a constraint expression acquisition module 310, a target constraint expression sorting module 320, a target value range determination module 330, and a target value range recoding module 340.

[0119] The constraint expression acquisition module 310 is used to acquire constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment;

[0120] The target constraint expression sorting module 320 is used to identify the target constraint expressions to be optimized in each constraint expression according to the constraint quantities contained in the constraint expressions, and sort the target constraint expressions.

[0121] The target value range determination module 330 is used to traverse each target constraint expression according to the sorting result, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process.

[0122] The target value range recoding module 340 is used to recode the target value range of each target constrained random variable according to the data width of each target constrained random variable and according to the set data width unit, and add the recoding result to the test stimulus code.

[0123] The technical solution of this invention obtains constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment, identifies and sorts the target constraint expressions to be optimized based on the included constraint quantities, iterates through each target constraint expression according to the sorting result, and progressively determines the target value range of the target constrained random variable in each target constraint expression. Based on the data width of each target constrained random variable, the target value range of each target constrained random variable is recoded according to a set data width unit, and the recoding result is added to the test stimulus code. By progressively narrowing the target value range of the target constrained random variable and recoding it, the test stimulus code is optimized, the size of the constraint solving problem input to the solving engine is reduced, and the performance of the constraint solver is improved.

[0124] In this embodiment of the invention, the target constraint expression sorting module 320 is specifically used for:

[0125] Initialize the first and second type constraint variable lists; extract one constraint expression from each constraint expression and use it as the current constraint expression; if all constraint variables in the current constraint expression are constants, then the current constraint expression is determined as a first type target constraint expression belonging to univariate constraints, and the constrained random variables in the current constraint expression are added to the first type constraint variable list; if the constraint variables in the current constraint expression are constants and random variables from the first type constraint variable list, or both are any random variables from the first type constraint variable list, then the current constraint expression is determined as a second type target constraint expression belonging to multivariate association constraints, and the constrained random variables in the current constraint expression are added to the first type constraint variable list. The constrained random variable is added to the second type of constraint variable list. If the constraint quantity in the current constraint expression is a constant and a random variable in the second type of constraint variable list, a random variable in the first type of constraint variable list and a random variable in the second type of constraint variable list, or both are random variables in the second type of constraint variable list, then the current constraint expression is determined as a second type of target constraint expression belonging to multivariate association constraints, and the constrained random variable in the current constraint expression is added to the second type of constraint variable list. The operation of obtaining a constraint expression in each constraint expression is repeated until no new first type or second type target constraint expression can be determined.

[0126] Optionally, the target constraint expression sorting module 320 includes:

[0127] The first sorting result acquisition submodule is used to randomly sort the first type of target constraint expressions to obtain the first sorting result;

[0128] The second sorting result acquisition submodule is used to sort each second type of objective constraint expression according to the dependency relationship between random variables in the constraint quantity to obtain the second sorting result;

[0129] The final sorting result acquisition module is used to append the second sorting result to the first sorting result to obtain the final sorting result.

[0130] Optionally, the submodule for obtaining the second sorting result includes:

[0131] The current second type of objective constraint expression acquisition unit is used to sequentially acquire the current second type of objective constraint expression in each sorting round, and extract the random variables in each current constraint quantity in the current second type of objective constraint expression;

[0132] The current second type of objective constraint expression sorting unit is used to add the current second type of objective constraint expression to the sorting queue if all random variables in the current constraint quantities are located in the dependent term set, and then add the expression to the sorting queue and return to perform the operation of sequentially retrieving the current second type of objective constraint expression from each second type of objective constraint expression;

[0133] The operation execution return unit is used to directly return to the operation of sequentially obtaining the current second type target constraint expression in each second type target constraint expression if at least one current constraint quantity is not in the dependent item set;

[0134] The dependent item set update unit is used to add the constrained random variables in each of the second type of target constraint expressions newly added to the sorting queue to the dependent item set after the processing of the current sorting round is completed.

[0135] The second sorting result acquisition unit is used to re-execute the operation of sequentially obtaining the current second type of target constraint expression in each second type of target constraint expression in a new sorting round, until all second type of target constraint expressions are added to the sorting queue to obtain the second sorting result.

[0136] In this embodiment of the invention, the target value range determination module 330 is specifically used for:

[0137] Set an initial value range for each objective constrained random variable; traverse each objective constraint expression sequentially according to the sorting result, and update the value range of each objective constrained random variable according to the constraint content in each objective constraint expression; after completing the traversal of all objective constraint expressions, obtain the objective value range of each objective constrained random variable.

[0138] Optionally, the target value range determination module 330 includes:

[0139] The current second type of target constraint expression traversal submodule is used to obtain the current target constrained random variable contained in the second type of target constraint expression when traversing to the current second type of target constraint expression, as well as at least one target random variable used to constrain the value range of the current target constrained random variable;

[0140] The upper boundary update submodule is used to obtain the maximum value of the target random variable within the range of values ​​of the currently updated target random variable if the target random variable constrains the upper boundary of the current target constrained random variable, and then use the maximum value to update the upper boundary of the current target constrained random variable.

[0141] The lower boundary update submodule is used to obtain the minimum value of the target random variable within the range of values ​​of the currently updated target random variable if the target random variable constrains the lower boundary of the current target constrained random variable, and then use the minimum value to update the lower boundary of the current target constrained random variable.

[0142] In this embodiment of the invention, the target value range recoding module 340 is specifically used for:

[0143] Calculate the number of extreme bits for each constrained random variable based on the target range of each value and the data width.

[0144] The target value range of each constrained random variable is recoded based on the data width range of 0 bits in the extreme value bits of each constrained random variable.

[0145] The test stimulus code optimization apparatus provided in this embodiment of the invention can execute the test stimulus code optimization method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0146] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0147] Example 3

[0148] Figure 4 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0149] like Figure 4As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0150] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0151] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as optimization methods for testing stimulus code.

[0152] In other words: Obtain constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment; each constraint expression contains a constrained random variable and a constraint quantity used to constrain the range of values ​​of the constrained random variable, where the constraint quantity is a constant or other random variable; based on the constraint quantity contained in the constraint expressions, identify the target constraint expressions to be optimized in each constraint expression and sort them; traverse each target constraint expression according to the sorting result, and gradually determine the target range of values ​​for the target constrained random variable in each target constraint expression during the traversal process, where the target range of values ​​only contains constants; recode the target range of values ​​for each target constrained random variable according to the set data width unit, and add the recoding result to the test stimulus code.

[0153] In some embodiments, the method for optimizing the test stimulus code may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the method for optimizing the test stimulus code described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the method for optimizing the test stimulus code by any other suitable means (e.g., by means of firmware).

[0154] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0155] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0156] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0157] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0158] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0159] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0160] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0161] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for optimizing test incentive code, characterized in that, include: Obtain the constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment; each constraint expression contains a constrained random variable and a constraint quantity used to constrain the range of values ​​of the constrained random variable, the constraint quantity being a constant or other random variable; Based on the constraint quantities contained in the constraint expressions, the target constraint expressions to be optimized are identified in each constraint expression, and the target constraint expressions are sorted. According to the sorting results, each target constraint expression is traversed, and the target value range of the target constrained random variable in each target constraint expression is determined step by step during the traversal. The target value range only contains constants. Based on the data width of each target constrained random variable, the target value range of each target constrained random variable is recoded according to the set data width unit, and the recoding result is added to the test stimulus code.

2. The method according to claim 1, characterized in that, Based on the constraint quantities contained in the constraint expressions, the target constraint expressions to be optimized are identified in each constraint expression, including: Initialize the list of first-class constraint variables and the list of second-class constraint variables; Select one constraint expression from among the various constraint expressions and use it as the current constraint expression; If all the constraint quantities in the current constraint expression are constants, then the current constraint expression is determined to be a first-class target constraint expression belonging to single-variable constraints, and the constrained random variable in the current constraint expression is added to the first-class constraint variable list. If the constraint quantity in the current constraint expression is a constant and a random variable in the first type of constraint variable list, or both are random variables in the first type of constraint variable list, then the current constraint expression is determined to be a second type of target constraint expression belonging to multivariate association constraints, and the constrained random variable in the current constraint expression is added to the second type of constraint variable list. If the constraint quantity in the current constraint expression is a constant and a random variable in the second type of constraint variable list, a random variable in the first type of constraint variable list and a random variable in the second type of constraint variable list, or both are random variables in the second type of constraint variable list, then the current constraint expression is determined to be a second type of target constraint expression belonging to multivariate association constraints, and the constrained random variable in the current constraint expression is added to the second type of constraint variable list. Repeat the process of obtaining one constraint expression at a time from each constraint expression until no new first-type or second-type target constraint expression can be determined.

3. The method according to claim 2, characterized in that, The expression of each objective constraint is sorted, including: The first type of objective constraint expressions are randomly sorted to obtain the first sorting result; The second sorting result is obtained by sorting the expressions of each type of objective constraint according to the dependency relationship between the random variables in the constraint quantities; The second sorting result is appended to the first sorting result to obtain the final sorting result.

4. The method according to claim 3, characterized in that, The expressions for each type II objective constraint are sorted according to the dependencies between the random variables in the constraint quantities to obtain the second sorting result, which includes: In each sorting round, the current second type of objective constraint expression in each second type of objective constraint expression to be sorted is obtained sequentially, and the random variables in each current constraint quantity are extracted from the current second type of objective constraint expression; If all random variables in the current constraint quantities are located in the dependent term set, then the current second type of objective constraint expression is added to the sorting queue, and the operation of retrieving the current second type of objective constraint expression from each second type of objective constraint expression is returned. Among them, the set of dependent items is initialized to store the constrained random variables in each first type of target constraint expression; If at least one current constraint is not in the set of dependent items, return directly to execute the operation of retrieving the current second type of target constraint expression in each second type of target constraint expression in turn; After completing the processing of the current sorting round, the constrained random variables in each of the newly added second-type target constraint expressions in the sorting queue are added to the dependent item set; In the new sorting round, the operation of retrieving the current second-type objective constraint expression from each second-type objective constraint expression is re-executed until all second-type objective constraint expressions are added to the sorting queue, thus obtaining the second sorting result.

5. The method according to claim 1, characterized in that, According to the sorting results, each objective constraint expression is traversed, and during the traversal, the range of objective values ​​for the constrained random variable in each objective constraint expression is determined step by step, including: Set initial value ranges for the constrained random variables of each objective; Iterate through each target constraint expression according to the sorting results, and update the range of values ​​for each target constrained random variable according to the constraint content in each target constraint expression. After traversing all the target constraint expressions, the target value range of each target constrained random variable is obtained.

6. The method according to claim 5, characterized in that, Iterate through each objective constraint expression according to the sorting result, and update the value range of each objective constrained random variable according to the constraint content in each objective constraint expression, including: When traversing to the current second type of target constraint expression, obtain the current target constrained random variable contained in the second type of target constraint expression, as well as at least one target random variable used to constrain the range of values ​​of the current target constrained random variable; If the target random variable constrains the upper boundary of the current target constrained random variable, then within the range of values ​​of the already updated target random variable, the maximum value of the target random variable is obtained, and the maximum value is used to update the upper boundary of the current target constrained random variable. If the target random variable constrains the lower boundary of the current target constrained random variable, then within the range of values ​​of the already updated target random variable, the minimum value of the target random variable is obtained, and the lower boundary of the current target constrained random variable is updated using the minimum value.

7. The method according to claim 1, characterized in that, The data width unit is 1 bit; Based on the data width of each constrained random variable, the target value range of each constrained random variable is recoded according to the set data width unit, including: Calculate the number of extreme bits for each constrained random variable based on the target range of each value and the data width. The target value range of each constrained random variable is recoded based on the data width range of 0 bits in the extreme value bits of each constrained random variable.

8. An optimization apparatus for test stimulus code, characterized in that, include: The constraint expression acquisition module is used to obtain constraint expressions belonging to the same scope from the test stimulus code to be input into the chip verification environment; The target constraint expression sorting module is used to identify the target constraint expressions to be optimized in each constraint expression based on the constraint quantities contained in the constraint expressions, and to sort the target constraint expressions. The target value range determination module is used to traverse each target constraint expression according to the sorting results, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process. The target value range recoding module is used to recode the target value range of each target constrained random variable according to the set data width unit, based on the data width of each target constrained random variable, and add the recoding result to the test stimulus code.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to said at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the optimization method of the test stimulus code according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the method for optimizing the test stimulus code according to any one of claims 1-7.

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