Accelerator construction method based on logic gate neural network
By building an accelerator based on logic gate neural network, using computational graph scheduling and timing optimization technology, the problem of high computational complexity of logic gate neural network is solved, and the calculation effect with low power consumption and high efficiency is achieved. It is suitable for logic gate neural networks. accelerator design.
Patent Information
- Application Number
- CN202411253750.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2024-12-24
AI Technical Summary
The prior art is difficult to effectively accelerate the calculation of logic gate neural networks, resulting in high computational complexity, high power consumption during training and inference, and lack of dedicated accelerator design for logic gate neural networks.
By building an accelerator based on logic gate neural network, using computational graph scheduling and timing optimization techniques, a directed acyclic graph DAG is established, registers and Wallace tree adders are used, and the logic is optimized by combining the gated clock handshake protocol and FIFO parallel architecture. The operation pipeline of gate neural network reduces hardware resource overhead.
It realizes low power consumption, high efficiency and low latency calculations, significantly reduces hardware resource overhead and operating costs, and improves the accuracy and speed of binary data processing and image recognition.
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Figure CN119180300A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of neural network accelerators, and in particular relates to a method for constructing an accelerator based on a logic gate neural network. Background Art
[0002] As the application scenarios of neural networks continue to expand, neural network models need to process more detailed and complex data. In order to meet these ever-increasing performance requirements, the scale of the network has also shown a growing trend. However, this has also brought a series of challenges, including increased computational complexity of training and inference, and increased storage and transmission costs of large-scale model parameters. Bottlenecks such as computing efficiency and power consumption have put forward requirements for more efficient hardware implementations to accelerate the training and inference of large-scale neural networks. Therefore, dedicated neural network accelerators have emerged that can perform computing tasks with higher energy efficiency, reduce power consumption and operating costs, which is of great economic significance for large-scale neural network applications.
[0003] At present, in the field of neural network algorithms, a large part of the research is mainly focused on traditional neural network models, such as CNN, RNN, SNN and other neural network algorithms. These traditional neural network models mainly use numerical operations when calculating, which makes them inefficient when processing logical reasoning and binary data. The logic gate neural network uses the most basic logic gates such as AND, OR and NOT as the basic neurons of the neural network, such as Figure 1 As shown, it is more efficient when performing binary or logical reasoning tasks.
[0004] Since the operation of basic logic gates is easier to understand, the interpretability of neural network models can be improved. Compared with traditional neural networks, logic gate neural networks are sparser, which helps to reduce the connections between neurons and reduce the complexity of model calculations. In addition, compared with BNN, the scale of this neural network is not limited by the algorithm itself. There is no loss of accuracy when converting from a training model to an inference model, and when reasoning on the same data set, the logic gate neural network requires fewer operations. Therefore, there is an urgent need to design an accelerator designed for logic gate neural networks. Summary of the invention
[0005] In view of the above problems, the present invention proposes a method for constructing an accelerator based on a logic gate neural network.
[0006] The technical solution of the present invention is as follows:
[0007] A method for constructing an accelerator based on a logic gate neural network specifically comprises the following steps:
[0008] 1) According to the number of input neurons of the logic gate neural network, the number of layers of the intermediate neural network and the number of neurons in each layer of the neural network are determined, and the directed acyclic graph DAG of the logic gate neural network information is established according to the control logic between the operators of the logic gate neural network;
[0009] 2) Reasonably schedule the logic gate neural network by using the computational graph scheduling method, compile and generate the target code based on the scheduled DAG, and optimize its timing; wherein the scheduling includes the following specific steps:
[0010] 2-1) Mark the in-degree value of neurons in the logic gate neural network;
[0011] 2-2) Traverse the entire DAG, find nodes with in-degree 0, save these nodes in the first layer, and store the list of nodes with in-degree equal to 0;
[0012] 2-3) Traverse the list of nodes with in-degree equal to _0. If the node has a child node, the in-degree of the child node is reduced by 1; if the in-degree of the child node is equal to 0, the child node is stored in the current layer;
[0013] 2-4) Repeat steps 2-1) to 2-3) until there are no child nodes in the current layer and the scheduling ends;
[0014] 2-5) Improve circuit timing by inserting registers. For nodes that need to insert registers across pipeline stages, record the current longest pipeline stage of the node. If the pipeline stage of the child node is less than the current longest pipeline stage of the node, obtain data from the current register chain; otherwise, insert a new register to extend the register chain of the node;
[0015] 3) Use a pipeline based on the gated clock handshake protocol to complete the construction of the accelerator.
[0016] Furthermore, in step 1), an adjacency list and an inverse adjacency list data structure are used to store the logic gate neural network information, thereby speeding up the compilation speed.
[0017] Furthermore, in step 1), constant folding (CF), constant propagation (CP), dead code elimination (DCE), and mobile elimination (ME) are used to process the logic gate neural network information to reduce the scale of the logic gate neural network.
[0018] Furthermore, in step 2-5), a Wallace tree adder is used to further optimize the timing. If the number of input data of the current Wallace tree unit tree is not greater than 2, the Wallace tree unit tree is not generated; if the number of input data is greater than 2, a Wallace tree unit tree is generated.
[0019] Furthermore, the pipeline is divided every n layers in the Wallace tree unit tree, and registers are inserted.
[0020] Furthermore, step 3) adopts a FIFO parallel architecture, the FIFO can be parameterized and configured, and adopts an AXI crossbar bus architecture.
[0021] The beneficial effects of the present invention are as follows:
[0022] The present invention can reduce the size of exchange files, reduce hardware resource overhead, and save costs. Experimental results show that the accelerator constructed by the present invention has the characteristics of low power consumption, high efficiency, low latency, etc. It has high accuracy and fast speed in processing binary data and simple image recognition. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Schematic diagram of existing logic gate neural network model;
[0024] Figure 2 Schematic diagram of a logic gate neural network DAG according to a specific embodiment of the present invention;
[0025] Figure 3 A schematic diagram of the steps for reducing the scale of a logic gate neural network in a specific embodiment of the present invention;
[0026] Figure 4 Data flow scheduling flow chart in a specific embodiment of the present invention;
[0027] Figure 5 A flowchart of designing the number of Wallace tree units in a specific embodiment of the present invention;
[0028] Figure 6 The hardware description language corresponding to the 16 operators in the specific embodiment of the present invention;
[0029] Figure 7 Schematic diagram of the accelerator FPGA system of the present invention in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] The method for constructing an accelerator based on a logic gate neural network of the present invention comprises the following steps:
[0032] Step 1: According to the number of input neurons of the logic gate neural network, determine the number of layers of the intermediate neural network and the number of neurons in each layer of the neural network. According to the control logic between the operators of the logic gate neural network, establish the directed acyclic graph DAG of the logic gate neural network. The specific steps are as follows:
[0033] 1) If Figure 2 As shown, according to the number of input neurons of the logic gate neural network, the number of layers of the intermediate neural network and the number of neurons in each layer of the neural network are determined. According to the control logic between the operators of the logic gate neural network, a static graph of the logic gate neural network information is established. The static graph is essentially a directed acyclic graph DAG.
[0034] 2) Use adjacency list and inverse adjacency list data structures to save neural network information and speed up compilation.
[0035] 3) If Figure 3 As shown in the figure, based on the directed acyclic graph, constant folding, constant propagation, dead code elimination, move elimination and other optimization techniques are used to optimize the logic gate neural network information, which greatly reduces the scale of the logic gate neural network, including:
[0036] 3-1) Constant folding: Calculate a known constant expression and fold it into a constant. Among the 16 logical operations of the logic gate neural network, the outputs of the two operations, True and False, are always constants. By traversing the entire logic gate neural network, find the neurons whose logical expressions are constant expressions, calculate and store the results of the constant expressions in advance;
[0037] 3-2) Constant propagation: The constant result after constant folding is brought into the child nodes that have data dependency relationship with it.
[0038] 3-3) Dead code elimination: Use the inverse adjacency list to traverse the logic gate neural network in reverse order from the last middle layer of the logic gate neural network. If the parent node exists in the inverse adjacency list of the current neuron, the parent node of the neuron is a valid neuron. Finally, the neurons that have not been traversed are invalid neurons. The compiler will delete these neuron nodes and disconnect these neurons from their parent nodes, that is, update the inverse adjacency list of these neurons and the adjacency list of their parent nodes.
[0039] 3-4) Move elimination: This is an optimization specifically for neuron operations. If the neuron operation is the constant operation True and False, then the adjacency list of the effective parent node of the neuron will be updated, that is, its child nodes will be added to the adjacency list of its effective parent node. At the same time, the inverse adjacency list of the child node of the neuron will also be updated, that is, the nodes in its child nodes related to the neuron will be replaced with its parent node, and finally the node will be deleted.
[0040] Step 2: Figure 4 As shown in the figure, the reasonable scheduling of the logic gate neural network is achieved by using the calculation graph scheduling method, the target code is generated based on the scheduled DAG compilation, and its timing is optimized; the specific steps are as follows:
[0041] 1) Mark the in-degree value of neurons in the logic gate neural network;
[0042] 2) Traverse the entire DAG, find nodes with in-degree 0, save these nodes in the first layer, and store the list of nodes with in-degree equal to 0;
[0043] 3) Traverse the list of nodes with in-degree equal to _0. If the node has a child node, the in-degree of the child node is reduced by 1; if the in-degree of the child node is equal to 0, the child node is stored in the current layer;
[0044] 4) Repeat the above 1)-3) process until there is no child node in the current layer and the scheduling ends;
[0045] 5) Improve circuit timing by inserting registers. For nodes that need to insert registers across pipeline stages, record the longest pipeline stage of the node. If the pipeline stage of the child node is less than the longest pipeline stage of the node, obtain data from the current register chain; otherwise, insert a new register to extend the register chain of the node.
[0046] 6) Use Wallace tree adder to optimize timing, such as Figure 5 As shown, if the number of input data of the current Wallace tree unit tree is not greater than 2, there is no need to use the Wallace tree algorithm for calculation, so the Wallace tree unit tree will not be generated. If the number of input data is greater than 2, a Wallace tree unit tree is generated, and the specific algorithm is described as follows: First, use the input data to update the current layer input cur_in of the Wallace tree unit tree, and calculate the data length of cur_in; if the input data length is greater than 2, calculate the number of full adders csa_num included in this layer, and generate the corresponding number of full adders, and assign the output results of the full adders to sum(j) and cout(k); if the number of input data len in this layer cannot be completely divided by 3, then the remaining data and sum and the carry result from the previous unit tree are merged as the input data of the next layer of the unit tree. Repeat the above process until len is no more than 2, complete the Wallace tree unit tree design, and divide the pipeline every n layers in the Wallace tree unit tree, and insert registers;
[0047] 7) If Figure 6As shown, 16 operators are mapped one by one to specific hardware languages, and the output layer is generated using the hardware description language to complete the summation of the output results of the last intermediate layer and output the calculation results; that is, the module keyword is used to declare the functional module, and its input and output ports are declared in the module, including clock signals and reset signals. The input of the module is a set of binary data, and the input port bit width is equal to the length of the binary data. The output of the module is the summation result of num Wallace tree adders.
[0048] Step 3: Use a pipeline based on the gated clock handshake protocol to complete the accelerator. Figure 7 As shown, a FIFO parallel architecture is adopted, the FIFO can be parameterized and configured, and an AXI crossbar bus architecture is adopted. Specifically, in the hardware system, the PC host receives the original data set and performs binary data processing on the original data set, which specifically includes:
[0049] 1. PC host: responsible for further data processing of the num summation results output by the Wallace tree of the accelerator.
[0050] 2. JTAG interface: There are usually 4 signal lines: TCK is used to provide the clock signal; TMS is used to select the working mode of the JTAG interface. The interface has two working modes: programming mode and debugging mode; TDI and TDO are used to transmit data.
[0051] 3. JTAG2AXI module: As the host of the AXI bus, create and run AXI read and write transactions through TCL console commands. The parameters of the JTAG2AXI module are configured as follows: use the AXI4 bus protocol and support all data burst transfer types of the bus; the address bit width is configured to 32 bits; the data bit width is configured to 64 bits.
[0052] 4. AXI4 protocol: defines five independent transaction channels, namely: read address channel, read data channel, write address channel, write data channel, write response channel. The AXI4 bus uses the above channels to complete the data transmission between the master component and the slave component.
[0053] 5. FIFO design: uses the FPGA's BRAM resources and is a synchronous FIFO.
[0054] 6. Data processing module: It consists of three parts: input control module, output control module and data calculation unit. The input control module is located between in_FIFO and the calculation unit. It receives control signals from in_FIFO and the calculation unit, and inputs the image data from in_FIFO into the calculation unit when the calculation unit allows it. The output control module is located between out_FIFO and the calculation unit. This module receives control signals from out_FIFO and the calculation unit, and sends the output data of the calculation unit to out_FIFO. In addition, it can also block the pipeline of the calculation unit when necessary.
[0055] 7. Handshake protocol: In order to better control the logic of the pipeline design, a handshake protocol based on VALID / READY is adopted. The VALID / READY handshake protocol is implemented in a gated clock manner: if there is valid data in the current register group that can be output to the next-level register group, the VALID signal line it outputs is pulled high; if it can receive valid data from the previous-level register group, its READY signal line is pulled high; in addition, each register group includes a gated clock signal. If the VALID of the current register group and the READY handshake of the next-level register group are successful, the gated clock clk_en of the next-level register is high.
[0056] The following verifies the usage and performance of the accelerator FPGA based on the logic gate neural network of the present invention in different application scenarios.
[0057] When the three tasks of the logic gate neural network model corresponding to the MONK dataset are run on a single-core CPU with a frequency of 2.5GHz, the number of operations required to be executed are 144, 72, and 72 respectively; while when these three tasks are run on FPGA, the number of operations required to be executed are 108, 69, and 52 respectively. For Task 1 and Task 3, the number of operations executed on FPGA is about 25% less than that on CPU, which saves nearly 25% of the operating cost.
[0058] Table 1 Performance comparison between the logic gate neural network accelerator FPGA and single-core CPU of the present invention corresponding to the MONK data set
[0059] MONK CPU FPGA(ours) operand 144|72|72 108|69|52 Average inference time 18ns 1.63ns|1.62ns|1.61ns
[0060] Comparison of neural network model inference accelerator performance corresponding to the Adult dataset
[0061] As shown in Table 2, when processing a data point in the Adult data set, compared with Petersen F et al. running the logic gate neural network on a single-core CPU with a frequency of 2.5 GHz, the number of operations performed by the FPGA design of the present invention is reduced by 9.84%, and the speed of the inference accelerator is 3 times that of the CPU.
[0062] Table 2 Comparison of logic gate neural network accelerator performance and CPU corresponding to the Adult dataset
[0063] Adult CPU FPGA(ours) operand 1280 1154 Average inference time 5.1 1.70
[0064] Comparison of neural network model inference accelerator performance corresponding to the Breast Carcer dataset
[0065] Table 3 lists the performance indicators of the AI accelerator corresponding to the Breast Cancer dataset and the logic gate neural network FPGA of the present invention running on the CPU. To process a data point in the Breast Cancer dataset, the number of operations required to be executed on the FPGA of the present invention is 11.56% less than that on a single-core CPU with a frequency of 2.5GHz. And the speed of the accelerator FPGA of the present invention is 1.7 times the CPU reasoning speed.
[0066] Table 3 Comparison of logic gate neural network accelerator performance and CPU corresponding to the Breast Cancer dataset
[0067] Breast Cancer CPU FPGA(ours) operand 640 566 Average inference time 2.8 1.68
[0068] Comparison of performance of neural network model inference accelerators corresponding to the MNIST dataset
[0069] In order to further prove that the accelerator of the present invention also has good performance in image recognition, Table 6 is the comparison data of the accelerator corresponding to the small-scale logic gate neural network of the MNIST data set with the CPU and GPU, and Table 5.17 is the comparison data of the accelerator corresponding to the normal-scale logic gate neural network with the CPU and GPU.
[0070] Table 4 Comparison of performance of logic gate neural network accelerator and CPU corresponding to MNIST dataset
[0071] MNIST CPU FPGA(ours) operand 640 566 Average inference time 2.8 1.68
[0072] In summary, the network model corresponding to the MONK data set is reduced by about 30% by the present invention; the network model corresponding to the Adult and Breast Carcer data sets is reduced by about 20%; the small-scale network model corresponding to the MNIST data set is reduced by about 25%; and the large-scale network model corresponding to the MNIST data set is reduced by about 35%. The average inference time of the accelerator is less than that of a 2.5GHZ single-core CPU, and it has a higher throughput.
[0073] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.
Claims
1. A method for constructing an accelerator based on a logic gate neural network, comprising the following steps: 1) According to the number of input neurons of the logic gate neural network, the number of layers of the intermediate neural network and the number of neurons in each layer of the neural network are determined, and the directed acyclic graph DAG of the logic gate neural network information is established according to the control logic between the operators of the logic gate neural network; 2) Reasonably schedule the logic gate neural network by using the computational graph scheduling method, compile and generate the target code based on the scheduled DAG, and optimize its timing; wherein the scheduling includes the following specific steps: 2-1) Mark the in-degree value of neurons in the logic gate neural network; 2-2) Traverse the entire DAG, find nodes with in-degree 0, save these nodes in the first layer, and store the list of nodes with in-degree equal to 0; 2-3) Traverse the list of nodes with in-degree equal to _0. If the node has a child node, the in-degree of the child node is reduced by 1; if the in-degree of the child node is equal to 0, the child node is stored in the current layer; 2-4) Repeat steps 2-1) to 2-3) until there are no child nodes in the current layer and the scheduling ends; 2-5) Improve circuit timing by inserting registers. For nodes that need to insert registers across pipeline stages, record the current longest pipeline stage of the node. If the pipeline stage of the child node is less than the current longest pipeline stage of the node, obtain data from the current register chain; otherwise, insert a new register to extend the register chain of the node; 3) Use a pipeline based on the gated clock handshake protocol to complete the construction of the accelerator.
2. The accelerator construction method according to claim 1, characterized in that: In step 1), the adjacency list and inverse adjacency list data structures are used to store the logic gate neural network information.
3. The accelerator construction method according to claim 1, characterized in that: In step 1), constant folding, constant propagation, dead code elimination and move elimination are used to process the logic gate neural network information.
4. The accelerator construction method according to claim 1, characterized in that: In step 2-5), a Wallace tree adder is used to optimize the timing. If the number of input data of the current Wallace tree unit tree is not greater than 2, the Wallace tree unit tree is not generated; if the number of input data is greater than 2, a Wallace tree unit tree is generated.
5. The accelerator construction method according to claim 4, characterized in that: The pipeline is divided every n levels in the Wallace tree unit tree, and registers are inserted.
6. The accelerator construction method according to claim 1, characterized in that: In step 2), the output layer is generated using a hardware description language, the output results of the last intermediate layer are summed up, and the calculation results are output.
7. The accelerator construction method according to claim 1, characterized in that: Step 3) adopts a FIFO parallel architecture, the FIFO can be parameterized and configured, and adopts an AXI crossbar bus architecture.
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