A refresh circuit and method based on composite dielectric gate three-transistor memory

Abstract

The application discloses a refresh circuit and method based on a composite medium gate three-transistor memory. The refresh circuit comprises a sampling switch, a reset circuit, an inverter chain with a positive feedback loop, an output switch and a delay timer; a readout end of the memory is connected with an input end of the inverter chain through the sampling switch; the reset circuit is located between the sampling switch and the inverter chain and is connected with the input end of the inverter chain; an output end of the inverter chain is connected with a write-in end of the memory through the output switch; and an output end of the delay timer is connected with the inverter chain and the output switch respectively. The refresh circuit of the application utilizes the original readout and write-in structure of the memory to complete the "sensing storage value" and "rewriting" operations in the refresh process, thereby avoiding extra area consumption.

Description

TECHNICAL FIELD

[0001] The application relates to a refresh circuit based on a composite dielectric gate three-transistor memory and belongs to the integrated circuit field. BACKGROUND

[0002] In view of the problems of a memory device in the storage field, such as a capacitor limit and short data retention time, a Chinese invention patent with the application number CN202411088060.3 proposes a composite dielectric gate three-transistor memory, which is characterized in that writing and reading are separated, reading operation cannot damage the storage content, a transistor is used to store electric charges to avoid a large capacitor, the area of a single memory is small, but the data retention time can reach seconds, which is better than most DRAM type devices.

[0003] Common DRAM type memory devices are volatile, and the electric charges stored in the capacitors are mainly leaked in the form of transistor sub-threshold leakage current, PN junction reverse bias leakage current and the like, causing data loss, and the storage unit must be refreshed periodically to supplement the electric charges. The traditional 1T1C DRAM refreshes data by reading, although the data retention time of different DRAM units differs greatly, but considering the need to meet the worst case, the array is usually refreshed at a period of microseconds or milliseconds, which brings a large power consumption overhead. Moreover, read and write operations cannot be performed during the refresh period, and the working speed of the memory is also affected. For the 2T1C type DRAM unit, since the electric charges of the capacitor will not be disturbed by reading, the data does not need to be recovered after reading, and the refresh operation cannot be performed by using the existing circuit. The existing 2T1C DRAM scheme tends to improve the data retention time, and prolongs the data retention time to several hundred microseconds to several hundred seconds by developing new materials to make transistors with ultra-low leakage current, building 3D large capacitors in the area of the memory device and the like, which can be equivalent to a "non-volatile" device in high-speed access applications, so as to reduce the refresh frequency or cancel the refresh step. However, the non-volatility of the DRAM has not changed in essence, and the refresh circuit is still necessary for the DRAM in the application scenario requiring long-time storage. SUMMARY

[0004] In order to solve the problem that the multi-transistor structure memory cannot store data for a long time, the application provides a refresh circuit and method based on a composite dielectric gate three-transistor memory, so as to realize high-speed and stable refresh of the composite dielectric gate three-transistor memory, and the area overhead is very small.

[0005] The technical scheme of the refresh circuit of the application is as follows:

[0006] A refresh circuit based on composite dielectric gate three transistor memory is connected with the composite dielectric gate three transistor memory, and the refresh circuit comprises a sampling switch S1, a reset circuit, an inverter chain with positive feedback loop, an output switch S2 and a delay timer; the readout end of the composite dielectric gate three transistor memory is connected with the input end of the inverter chain with positive feedback loop through the sampling switch S1; the reset circuit is located between the sampling switch S1 and the inverter chain with positive feedback loop, and is connected with the input end of the inverter chain with positive feedback loop; the output end of the inverter chain with positive feedback loop is connected with the write-in end of the composite dielectric gate three transistor memory through the output switch S2; the output end of the delay timer is connected with the inverter chain with positive feedback loop and the output switch S2 respectively.

[0007] Further, the composite dielectric gate three transistor memory comprises an electronic write-in tube, an electronic readout tube and three series capacitors; the write-in end of the composite dielectric gate three transistor memory is the write-in source end of the electronic write-in tube, and the readout end of the composite dielectric gate three transistor memory is the readout drain end of the electronic readout tube.

[0008] Further, the inverter chain with positive feedback loop comprises a feedforward circuit formed by cascading three-stage inverters and a feedback switch S3; each inverter of the feedforward circuit comprises a pair of P-type doped MOSFET and N-type doped MOSFET, the gates of which are connected as an input end, and the drains of which are connected as an output end; one end of the feedback switch S3 is connected with the input end of the first-stage inverter of the inverter chain, and the other end is connected with the output end of the second-stage inverter of the inverter chain.

[0009] Further, the width-length ratio of the pair of P-type doped MOSFET and N-type doped MOSFET of each inverter of the feedforward circuit increases gradually.

[0010] Further, the feedback switch S3 adopts N-type MOSFET, the source end of which is connected with the output end of the second-stage inverter of the inverter chain with positive feedback loop, the drain end of which is connected with the input end of the first-stage inverter of the inverter chain with positive feedback loop, and the gate end of which is connected with the delay timer.

[0011] Further, the sampling switch S1 and the output switch S2 both adopt N-type MOSFET; the source end of the sampling switch S1 is connected with the readout end of the composite dielectric gate three transistor, the drain end of which is connected with the input end of the inverter chain with positive feedback loop, and the gate end of which is connected with an external voltage control signal; the source end of the output switch S2 is connected with the output end of the inverter chain with positive feedback loop, the drain end of which is connected with the write-in end of the composite dielectric gate three transistor, and the gate end of which is connected with the delay timer.

[0012] The application also provides a working method of a refresh circuit based on a composite dielectric gate three-transistor memory, wherein the refresh circuit is provided with two external connection voltages, a positive voltage VP and a negative voltage VN, and a ground voltage GND, and an external voltage control signal Vrf is provided in the circuit, and the external voltage control signal Vrf generates a delay signal Vrf_dly through a delay device; the composite dielectric gate three-transistor memory comprises an electronic write tube and an electronic read tube, and the voltage of the external port of the composite dielectric gate three-transistor memory is changed during refreshing: in a storage stage, the gate voltage of the electronic write tube is connected to the negative voltage VN, the source and drain of the electronic read tube are connected to the ground voltage GND, and the electronic write tube and the electronic read tube are both closed; in a refreshing stage, the drain of the electronic read tube is connected to the ground voltage VN, the source of the electronic read tube is left floating, the storage value is sensed to the readout end of the composite dielectric gate three-transistor memory, then the voltage of the readout end of the memory is sampled by the refresh circuit, then the sampled value is latched, enhanced and outputted by the inverter chain in the refresh circuit, and finally the gate of the electronic write tube is connected to the positive voltage VP, so that the electronic write tube is opened, and the voltage outputted by the refresh circuit is written into the composite dielectric gate three-transistor memory again.

[0013] The application also provides a storage chip based on a composite dielectric gate three-transistor device, which comprises a composite dielectric gate three-transistor memory array, the above-mentioned refresh circuit, a write word line driver, a write bit line driver, a read word line driver and a read bit line driver; the write word line driver drives a write word line WWL which is connected to the gates of the electronic write tubes of the same row of memory in the memory array, the write bit line driver drives a write bit line WBL which is connected to the sources of the electronic write tubes of the same column of memory in the memory array, the read word line driver drives a read word line RWL which is connected to the sources of the electronic read tubes of the same row of memory in the memory array, and the read bit line driver drives a read bit line RBL which is connected to the drains of the electronic read tubes of the same column of memory in the memory array; one refresh circuit is shared by each column of memory, the sampling switch S1 of the refresh circuit is connected to the read bit line RBL shared by one column of memory, and the output switch S2 is connected to the write bit line WBL shared by one column of memory.

[0014] The working principle / process of the application is as follows:

[0015] The circuit of the application has two working stages, including a reset stage and a refreshing stage.

[0016] In the reset stage, the external voltage control signal Vrf=VN, and the delay signal Vrf_dly thereof is also equal to VN. At this time, the sampling switch S1 and the output switch S2 of the refresh circuit are disconnected, and the refresh circuit is completely isolated from the memory. In the sampling circuit, the reset circuit is opened, and the voltage at the input end of the inverter chain is reset to 0V. The feedback switch S3 of the inverter chain is disconnected, and thus no positive feedback loop is formed.

[0017] During the refresh stage, the external voltage control signal Vrf=VP, Vrf_dly=VP, the sampling switch S1 and the output switch S2 of the refresh circuit are closed, and the refresh circuit is connected with the storage unit. During the refresh, the drain end (the memory readout area) of the electron readout tube T2 of the storage unit is changed from being connected with GND to being floating, and the source end is changed from being connected with GND to being connected with a negative voltage VN. When the stored voltage is VN, the voltage of the storage node SN is kept at VN, the electron readout tube T2 is turned off, and the voltage of the drain end (the memory readout area) of T2 is still floating near GND, and the floating GND is maintained by the parasitic capacitance of the drain end metal line; when the stored voltage is GND, the voltage of the storage node SN is reduced to GND-△V due to the leakage, and as long as GND-△V>VN+Vth, wherein Vth≈0.7V, T2 is turned on, and the drain end (the memory readout area) of T2 outputs the negative voltage VN. The voltage of the memory readout area is transmitted to the input end of the inverter chain through the sampling switch S1. As described above, the initial voltage of the input end of the inverter chain is GND, so when the voltage of the memory readout area is floating GND, the voltage of the input end of the inverter chain is also floating GND; when the voltage of the memory readout area is VN, the voltage of the input end of the inverter chain is VN. The output voltage of the second stage of the inverter chain is fed back to the input end of the first stage through the feedback switch S3, and the voltage of the input end of the inverter chain is latched. After latching, the output voltage of the third stage of the inverter chain is stably equal to the inverted voltage of the voltage of the input end of the inverter chain. The output voltage of the inverter chain is transmitted to the write-in area of the memory through the output switch S2. The electron write-in tube T1 of the memory is turned on, and the voltage of the write-in area driven by the refresh circuit is stored in the storage node SN again, and the refresh is completed.

[0018] Compared with the prior art, the application has the following beneficial effects:

[0019] (1) The refresh circuit of the application uses the original readout and write-in structure of the memory to complete the "sensing storage value" and "rewriting" operations in the refresh process, avoiding additional area overhead. According to the characteristics that the memory stores low voltage without loss and stores high voltage with loss, a larger fault tolerance range is set for the sensing of high voltage, ensuring the correctness of the refresh logic. The inverter chain with positive feedback in the refresh circuit can quickly latch and enhance the sensed storage value, realizing fast refresh.

[0020] (2) The reset circuit is arranged in the circuit to pre-charge the internal nodes. The metal line of the memory readout area has a certain parasitic capacitance, which can temporarily maintain the floating voltage before the refresh circuit latches the sampled value, realizing the distinction of binary voltage and ensuring the accuracy of sampling. The sampled voltage is quickly latched as a strong driving voltage by the positive feedback of the inverter chain, preventing the circuit from being driven by the floating voltage, and eliminating the influence of noise and leakage current in the circuit on the result.

[0021] (3) Since the last stage of the inverter chain needs to drive a certain load capacitance, the width-length ratio of the NMOS and PMOS pair of each stage of inverter needs to be increased step by step, so as to gradually improve the current driving capability. This can further speed up the speed of establishing positive feedback of the inverter chain, thereby enhancing the loop stability.

[0022] In summary, the circuit structure of the present application is simple, effectively utilizes part of the structure in the memory to save area, and is not easily disturbed by circuit noise and leakage current in the process of sensing the storage value and sampling and latching. The present application can realize high-speed and high-tolerance refresh for the composite dielectric gate three-transistor memory, and has good application prospects in the storage field. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The figure is a refresh circuit schematic diagram based on the composite dielectric gate three-transistor memory in the present embodiment.

[0024] Figure 2 The figure is a refresh circuit schematic diagram based on the composite dielectric gate three-transistor memory array. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings.

[0026] Example 1

[0027] Figure 1 The figure is a refresh circuit schematic diagram based on the composite dielectric gate three-transistor memory in the present embodiment, which includes a sampling switch 2, a reset circuit 3, an inverter chain 4 with positive feedback loop, an output switch 5 and a delay timer 6. The refresh circuit is connected with the composite dielectric gate three-transistor memory 1 (referred to as memory 1 for short). The specific structure of the memory 1 is described in the Chinese invention patent with the application number CN202411088060.3. Figure 1 And 2 The signal writing area and the readout area in the memory 1 are both N-type MOSFET transistors. The readout area is connected with one end of the sampling switch 2, and the writing area is connected with one end of the output switch 5. The other end of the sampling switch 2 is connected with the input end of the inverter chain 4 with positive feedback loop. The reset circuit 3 is connected between the sampling switch 2 and the inverter chain 4, and is also connected with the input end of the inverter chain 4 with positive feedback loop. The output end of the inverter chain 4 with positive feedback loop is connected with the other end of the output switch 5. The output of the delay timer 6 is connected with the inverter chain 4 and the output switch 5 respectively, for generating the delay signal Vrf_dly of the external voltage control signal Vrf. The delay time needs to be greater than the time of sampling the voltage at the readout end of the three-transistor memory of the refresh circuit.

[0028] The memory 1 comprises two N-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) and three capacitors. The two N-type MOSFETs are an electron writing tube T1 and an electron reading tube T2 respectively; the three capacitors are connected in series, and from top to bottom, they are capacitor C1, capacitor C2 and capacitor C3. The internal connection relationship of the device is as follows: the node connected with the lower plate of the capacitor C1 and the upper plate of the capacitor C2 is called node RN (Read node), and the node connected with the lower plate of the capacitor C2 and the upper plate of the capacitor C3 is called node SN (Storage node). According to the voltage division relationship of the capacitors, the voltage of the node RN is approximately equal to the voltage of the node SN. The drain of the electron writing tube T1 is connected with the node SN, and the gate of the electron reading tube T2 is connected with the node RN. The memory 1 has six external ports: the first port is the source of the electron writing tube T1; the second port is the gate of the electron writing tube T1; the third port is the source of the electron reading tube T2; the fourth port is the drain of the electron reading tube T2; the fifth port is the upper plate of the capacitor C1, connected with GND; and the sixth port is the lower plate of the capacitor C3, connected with negative voltage VN. In the writing mode of the memory, the first port transmits GND or negative voltage VN, the second port transmits positive voltage VP, the electron writing tube T1 is turned on, and the voltage transmitted by the first port is transmitted to the storage node SN. In the holding mode of the memory, the second port transmits negative voltage VN, the third and fourth ports transmit GND, and the electron writing tube T1 and the electron reading tube T2 are both in the off state, at this time, the voltage of the storage node SN gradually changes in the direction of the negative voltage VN. In the reading mode of the memory, the third port transmits negative voltage VN, and according to the different storage voltages, the electron reading tube T2 will produce obviously different drain currents, so as to read the stored data.

[0029] The writing end of the memory 1 is the writing source end of the electron writing tube T1, and the reading end is the reading drain end of the electron reading tube T2. In the writing stage, the voltage is applied to the writing source end of the electron writing tube T1, and the electrons are written into or extracted from the node SN; in the reading stage, the reading current of the electron reading tube T2 changes according to the amount of collected electrons.

[0030] The inverter chain 4 with positive feedback loop comprises a feed-forward circuit formed by cascading three-stage inverters and a feedback network formed by switches. The upper power supply rail of the inverters is GND and the lower power supply rail is negative voltage VN. Each inverter of the feed-forward circuit comprises a pair of P-type doped MOSFET (PMOS) and N-type doped MOSFET (NMOS), the source of the PMOS is connected to 0 potential, the source of the NMOS is connected to negative voltage VN, the gates of the two are connected as input terminal, and the drains are connected as output terminal. The three-stage inverters are cascaded in sequence according to the output terminal of the previous inverter connected to the input terminal of the next inverter to form the inverter chain. The width-length ratio of the PMOS is usually 2.5 times of the NMOS, i.e. the ratio of hole mobility to electron mobility. The width-length ratio of the NMOS and PMOS pair of each inverter needs to be increased step by step to gradually improve the current driving capability. The feedback network is formed by a feedback switch S3, one end of the feedback switch S3 is connected to the input terminal of the first stage of the inverter chain, and the other end is connected to the output terminal of the second stage of the inverter chain.

[0031] The sampling switch 2 comprises a switch S1, and the output switch 5 comprises a switch S2. In the embodiment, the switches S1, S2 and S3 are all formed by N-type MOSFET. The source of the NMOS switch S1 is connected to the drain of the memory electron read tube T2, the drain of the S1 is connected to the input terminal of the inverter chain 4 with positive feedback loop, and the gate of the S1 is connected to the external voltage control signal Vrf. The output of the delay timer 6 is connected to the gate of the feedback switch S3 and the gate of the switch 2 respectively. The source of the switch S2 is connected to the output terminal of the inverter chain 4, the drain is connected to the source of the memory electron write tube T1, and the gate is connected to the voltage control signal Vrf_dly. The source of the feedback switch S3 is connected to the output terminal of the second-stage inverter of the inverter chain 4, the drain is connected to the input terminal of the first-stage inverter of the inverter chain 4, and the gate is connected to the voltage control signal Vrf_dly.

[0032] The reset circuit 3 is formed by P-type MOSFET, the source is connected to GND, the drain is connected to the input terminal of the inverter chain 4 with positive feedback loop, and the gate is connected to the external voltage control signal Vrf.

[0033] The voltage of the external port of the memory during the refresh of the circuit in the embodiment needs to be changed in coordination: in the storage stage, the voltage of the external port controls to close the electron read tube and the electron write tube of the memory; in the refresh stage, first, the voltage of the external port controls to open the electron read tube of the memory, and the storage value is sensed to the memory read terminal, then the voltage of the memory read terminal is sampled by the refresh circuit, then the inverter chain in the refresh circuit latches, enhances and outputs the sampling value, and finally the voltage of the refresh circuit output is written into the memory by the voltage of the external port controlling to open the electron write tube of the memory. The specific working process is described as follows.

[0034] There are two external connection voltages in the circuit: positive voltage VP needs to satisfy the relationship VP-GND≥Vth (Vth≈0.7V), and the embodiment takes VP=3V; negative voltage VN needs to have a clear distinction from GND, which is conducive to data storage, and the embodiment takes VN=-3V. GND is the ground voltage 0V. The inverter chain 4 is powered by GND and VN=-3V, and the delay 6 is powered by VP=3V and VN=-3V. There is an external voltage control signal Vrf in the circuit, which is VP=3V or VN=-3V.

[0035] The sampling switch 2 and the reset circuit 3 in the circuit are controlled by the voltage control signal Vrf, and the feedback switch S3 and the output switch 5 of the inverter chain 4 are controlled by the voltage signal Vrf_dly, the purpose is to lock and output after the voltage sampled by the refresh circuit is stable.

[0036] When the refresh circuit is in the reset phase, the voltage control signal Vrf=Vrf_dly=-3V is the lowest global voltage. The sampling switch 2 is NMOS, the gate is connected to Vrf, and the sampling switch 2 is off; the reset circuit 3 is PMOS, the gate is connected to Vrf, and the source is connected to GND, the reset circuit is on, and GND is transmitted to the drain of the PMOS, that is, the input of the inverter chain 4; the feedback switch S3 of the inverter chain 4 is NMOS, the gate is connected to Vrf_dly, and S3 is off, so the positive feedback loop in the inverter chain 4 is not established; the output switch 5 is NMOS, the gate is connected to Vrf_dly, and the output switch 5 is off. When reset, the refresh circuit is not connected with the memory 1, and the internal nodes of the refresh circuit are provided with stable level by the reset circuit 3, so as to ensure that the initial state of the refresh circuit in the refresh phase is determined. When the refresh circuit is reset, the memory 1 can perform write and read operations, or keep storage.

[0037] Before refreshing, the memory 1 is in the holding phase, the gate of the electronic write tube T1 of the memory 1 is connected to the negative voltage VN=-3V, and the source and drain of the electronic read tube T2 are connected to GND.

[0038] When the refresh circuit is in the refresh phase, the first step is to change the source of the electronic read tube T2 of the memory 1 from GND to-3V, and change the drain from GND to floating. If the voltage stored in the memory 1 is-3V, which tends to remain at-3V, the gate-source voltage of the electronic read tube T2 is 0V, T2 is off, and the voltage of the drain of T2 (the readout area of the memory 1) will float near GND, which is temporarily stored by the parasitic capacitance of the drain metal line; if the voltage stored in the memory 1 is GND, although it has deviated in the direction of negative voltage VN, as long as the current voltage is still higher than-3V by a threshold voltage Vth, T2 can be turned on, and the voltage of the drain of T2 (the readout area of the memory 1) is equal to the source voltage-3V.

[0039] The second refresh step, the voltage signal Vrf flips from -3V to 3V, which is the global highest voltage. The NMOS sampling switch 2 and the PMOS reset circuit 3 are controlled by the voltage signal Vrf. The sampling switch 2 is opened, and the reset circuit 3 is closed. The sampling switch 2 transmits the readout region voltage of the memory 1 to the input end of the inverter chain 4. The initial voltage of the input end of the inverter chain 4 is 0V. When the readout region voltage of the memory 1 is floating GND, the input voltage of the inverter chain 4 is still floating GND. At this time, the input state of the inverter chain 4 is unstable, and the floating GND may gradually deviate to -3V over time. When the readout region voltage of the memory 1 is -3V, the input voltage of the inverter chain 4 becomes -3V.

[0040] The third refresh step, the voltage signal Vrf_dly also flips to 3V after a certain delay. The NMOS feedback switch S3 and the NMOS output switch 5 in the inverter chain 4 are controlled by the voltage signal Vrf_dly, and both are closed. After S3 is closed, the voltage output by the second stage of the inverter chain 4 is fed back to the input voltage of the first stage, and the input voltage of the first stage is latched, eliminating the non-steady state of the refresh link. At the same time, the input switch 5 is opened, and the third stage output voltage of the inverter chain 4 is transmitted to the source end of the electronic write tube T1 of the memory 1 (the write-in region of the memory 1).

[0041] The fourth refresh step, the gate voltage of the electronic write tube T1 of the memory 1 is changed from -3V to 3V, T1 is opened, and the source end voltage of T1 is transmitted to the storage node SN of the memory 1, completing the refresh. The overall refresh logic is as follows: when the voltage stored in the memory 1 is GND, the voltage of the readout region of the memory 1 is -3V, which is sampled to the input end of the inverter chain 4. After three-stage inversion, the output voltage GND is transmitted back to the storage node of the memory 1. When the voltage stored in the memory 1 is -3V, the voltage of the readout region of the memory 1 is floating GND, which is latched as a strong drive GND after being sampled to the input end of the inverter chain 4. After three-stage inversion, the output -3V is transmitted back to the storage node of the memory 1.

[0042] Embodiment 2

[0043] In this embodiment, the refresh circuit described in Embodiment 1 is used to refresh a composite medium gate three-transistor memory array (referred to as a memory array for short), as shown in FIG. 2. Figure 2As shown, the memory array, refresh circuit, write word line driver, write bit line driver, read word line driver and read bit line driver. The write word line driver drives the write word line WWL connected to the gate of the write transistor T1 of the memory cells in the same row in the memory array, the write bit line driver drives the write bit line WBL connected to the source of the write transistor T1 of the memory cells in the same column in the memory array, the read word line driver drives the read word line RWL connected to the source of the read transistor T2 of the memory cells in the same row in the memory array, and the read bit line driver drives the read bit line RBL connected to the drain of the read transistor T2 of the memory cells in the same column in the memory array. Each column of memory shares a refresh circuit, and the sampling switch S1 of the refresh circuit is connected to the read bit line RBL shared by the column of memory, and the output switch S2 is connected to the write bit line WBL shared by the column of memory.

[0044] The memory array has i rows and j columns, the gate of the write transistor T1 of the memory cells in the same row is connected to form a write word line WWL, the source of the write transistor T1 of the memory cells in the same column is connected to form a write bit line WBL, the source of the read transistor T2 of the memory cells in the same row is connected to form a read word line RWL, and the drain of the read transistor T2 of the memory cells in the same column is connected to form a read bit line RBL. One write word line WWL controls the opening and closing of the input transistor T1 of one row of memory, and when T1 is closed, WWL transmits a negative voltage VN=-3V, and when T1 is opened, WWL transmits a positive voltage VP=3V. One write bit line WBL is responsible for transmitting the write voltage of one column of memory in time, and WBL transmits a negative voltage VN=-3V or GND. One read word line RWL controls the opening and closing of the read transistor T2 of one row of memory, and when T2 is closed, RWL transmits GND, and when T2 is opened, RWL transmits a negative voltage VN=-3V.

[0045] Each column of memory in the memory array shares a refresh circuit, i.e. there are j refresh circuits in total, and the sampling switch S1 of each refresh circuit is connected to the read bit line RBL of the corresponding column, and the output switch S2 is connected to the write bit line WBL of the corresponding column. During refresh, the write word line WWL and the read word line RWL of the row being refreshed need to be changed in coordination, which causes the state of the write transistor and the read transistor of one row of memory to change, so the array-level refresh must be based on one row of memory as the basic operation unit, and the memory in different rows is refreshed in time. The control signals Vrf and Vrf_dly of the refresh operation are global signals, which control the j refresh circuits at the same time. When performing row-by-row refresh, Vrf and Vrf_dly are flipped between -3V and 3V.

[0046] Taking row-by-row refresh as an example, the process of array-level refresh is as follows:

[0047] When the array does not perform refresh operation, Vrf=-3V, all the refresh circuits are in reset state: sampling switch S1 and output switch S2 are disconnected with the corresponding column read bit line RBL and write bit line WBL, and the input voltage of the internal inverter chain of the refresh circuit is GND.

[0048] When refreshing, the first row of memory is refreshed: in the first step, all the write bit lines WBL and read bit lines RBL of the array are floating. In the second step, the read word line RWL of the first row of memory transmits-3V; at the same time, Vrf=3V, the sampling switch S1 of each refresh circuit is connected with the corresponding column RBL, at this time, the refresh circuits 1, 2, 3, …, j sense and sample the storage values of the first, second, third, …, j memory of the first row. In the third step, Vrf_dly=3V, the output switch S2 of each column refresh circuit is connected with the corresponding column WBL, and each column WBL is driven to reach the target voltage. In the fourth step, the write word line WWL of the first row of memory transmits 3V, and each memory of the row stores the voltage on the corresponding WBL, completing the refresh; at the same time, the read word line RWL of the first row transmits GND, closing the electronic read tube. In the fifth step, the WWL of the first row transmits-3V, closing the electronic write tube; at the same time, Vrf=-3V, the sampling switch S1 of all the refresh circuits is disconnected from the corresponding column RBL, and the internal node is reset; at the same time, all the read bit lines RBL of the array transmit GND, pre-charging for the next refresh. In the sixth step, Vrf_dly=-3V, the output switch S2 of all the refresh circuits is disconnected from the corresponding column WBL, and the WBL remains floating. The above is the complete process of refreshing the first row of memory, and the second row of memory is refreshed next: from the second step above, repeat the above steps, only need to change the operation of the first row RWL and WWL in the process to the operation of the second row RWL and WWL. The third, fourth, …, i rows are refreshed in turn.

[0049] It should be noted that the refresh of the memory array must be performed simultaneously for one row, but it does not necessarily refresh row by row, and can refresh a row in any order.

[0050] The timing control of the refresh circuit in the embodiment can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0051] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A refresh circuit based on composite gate-all-around tri-gate memory, connected to a composite gate-all-around tri-gate memory, characterized in that, The composite dielectric gate three-transistor memory comprises an electronic write-in tube, an electronic read-out tube and three series capacitors; a write-in end of the composite dielectric gate three-transistor memory is a write-in source end of the electronic write-in tube, and a read-out end of the composite dielectric gate three-transistor memory is a read-out drain end of the electronic read-out tube; the refresh circuit comprises a sampling switch S1, a reset circuit, an inverter chain with a positive feedback loop, an output switch S2 and a delay timer, the inverter chain with the positive feedback loop is used for latching, enhancing and outputting a sampling value, the read-out end of the composite dielectric gate three-transistor memory is connected with an input end of the inverter chain with the positive feedback loop through the sampling switch S1, the reset circuit is located between the sampling switch S1 and the inverter chain with the positive feedback loop and is connected with the input end of the inverter chain with the positive feedback loop, an output end of the inverter chain with the positive feedback loop is connected with the write-in end of the composite dielectric gate three-transistor memory through the output switch S2, and an output end of the delay timer is connected with the inverter chain with the positive feedback loop and the output switch S2.

2. The refresh circuit based on the composite dielectric gate three-transistor memory according to claim 1, characterized in that, The inverter chain with the positive feedback loop comprises a feedforward circuit formed by cascading three inverters and a feedback switch S3, each inverter of the feedforward circuit comprises a pair of P-type doped MOSFET and N-type doped MOSFET, both of which are connected at the gate as an input end and are connected at the drain as an output end, and one end of the feedback switch S3 is connected with an input end of a first inverter of the inverter chain and the other end is connected with an output end of a second inverter of the inverter chain.

3. The refresh circuit based on composite dielectric gate three-transistor memory according to claim 2, characterized in that, The width-length ratio of the pair of P-type doped MOSFET and N-type doped MOSFET of each inverter of the feedforward circuit increases gradually.

4. The refresh circuit based on composite dielectric gate three-transistor memory according to claim 2, characterized in that, The feedback switch S3 adopts an N-type MOSFET, a source end of which is connected with an output end of a second inverter of the inverter chain with the positive feedback loop, a drain end of which is connected with an input end of a first inverter of the inverter chain with the positive feedback loop, and a gate end of which is connected with the delay timer.

5. The refresh circuit based on composite dielectric gate three-transistor memory according to claim 1, characterized in that, Both the sampling switch S1 and the output switch S2 adopt N-type MOSFETs, a source end of the sampling switch S1 is connected with the read-out end of the composite dielectric gate three-transistor memory, a drain end of the sampling switch S1 is connected with an input end of the inverter chain with the positive feedback loop, a gate end of the sampling switch S1 is connected with an external voltage control signal, a source end of the output switch S2 is connected with an output end of the inverter chain with the positive feedback loop, a drain end of the output switch S2 is connected with the write-in end of the composite dielectric gate three-transistor memory, and a gate end of the output switch S2 is connected with the delay timer.

6. The method of claim 1, wherein the refresh operation is performed in a refresh cycle, and the refresh cycle is divided into a plurality of sub-cycles, and the refresh operation is performed in each of the sub-cycles. The refresh circuit is provided with two external connection voltages: positive voltage VP and negative voltage VN, and a ground voltage GND, and is provided with an external voltage control signal Vrf, and the external voltage control signal Vrf generates a delay signal Vrf_dly through a delay device; the composite dielectric gate three-transistor memory comprises an electronic write transistor and an electronic read transistor, and the voltage of the external port of the composite dielectric gate three-transistor memory is changed in coordination during refresh: in the storage stage, the gate voltage of the electronic write transistor is connected to the negative voltage VN, the source and drain of the electronic read transistor are connected to the ground voltage GND, and the electronic write transistor and the electronic read transistor are both turned off; in the refresh stage, the drain of the electronic read transistor is first connected to the negative voltage VN, the source of the electronic read transistor is left floating, the storage value is induced to the read end of the composite dielectric gate three-transistor memory, then the voltage of the read end of the memory is sampled by the refresh circuit, then the sampled value is latched, enhanced and output by the inverter chain in the refresh circuit, and finally the gate of the electronic write transistor is connected to the positive voltage VP, so that the electronic write transistor is turned on, and the voltage output by the refresh circuit is written back to the composite dielectric gate three-transistor memory.

7. The method of working according to claim 6, characterized in that, The composite dielectric gate three-transistor memory has six external ports: the first port is the source of the electronic write transistor T1; the second port is the gate of the electronic write transistor T1; the third port is the source of the electronic read transistor T2; the fourth port is the drain of the electronic read transistor T2; the fifth port is the upper plate of the capacitor C1, connected to GND; and the sixth port is the lower plate of the capacitor C3, connected to the negative voltage VN; in the write mode of the composite dielectric gate three-transistor memory, the first port transmits GND or the negative voltage VN, the second port transmits the positive voltage VP, the electronic write transistor T1 is turned on, and the voltage transmitted by the first port is transmitted to the storage node SN; In the hold mode of the composite dielectric gate three-transistor memory, the second port transmits the negative voltage VN, the third and fourth ports transmit GND, and the electronic write transistor T1 and the electronic read transistor T2 are both in the off state, at this time, the voltage of the storage node SN gradually changes in the direction of the negative voltage VN; in the read mode of the composite dielectric gate three-transistor memory, the third port transmits the negative voltage VN, and according to the different storage voltages, the electronic read transistor T2 will produce obviously different drain currents, so as to read the stored data.

8. The method of claim 6, wherein, The positive voltage VP needs to satisfy the relationship VP-GND≥Vth, wherein Vth≈0.7V, and GND is the ground voltage 0V.

9. A memory chip based on a composite dielectric gate three-transistor device, characterized by, The memory array comprises a composite dielectric gate three-transistor memory array, the refresh circuit of any one of claims 1-5, a write word line driver, a write bit line driver, a read word line driver and a read bit line driver; the write word line driver drives a write word line WWL formed by connecting the gates of the memory electron write tubes in the same row of the memory array; the write bit line driver drives a write bit line WBL formed by connecting the sources of the memory electron write tubes in the same column of the memory array; the read word line driver drives a read word line RWL formed by connecting the sources of the memory electron read tubes in the same row of the memory array; and the read bit line driver drives a read bit line RBL formed by connecting the drains of the memory electron read tubes in the same column of the memory array; each column of memory shares one refresh circuit, the sampling switch S1 of the refresh circuit is connected to the read bit line RBL shared by one column of memory, and the output switch S2 is connected to the write bit line WBL shared by one column of memory.

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