Method for producing electrode structure of ion trap and method for producing electrode arrangement of three-dimensional ion trap

Abstract

A method (100) for fabricating an electrode structure (206) of an ion trap, comprising: providing (110) a base substrate (202) comprising a patterned metallization arrangement (230) arranged in an insulating material (220) on a semiconductor layer (210); providing (120) an insulating substrate (250) comprising a dielectric material (252); connecting (130) a surface region (224) of the base substrate (202) arranged on the insulating material (220) to the insulating substrate (250) by a bonding process; and back-thinning (140) the base substrate (202) by removing the semiconductor layer (210) to the insulating material (220) of the base substrate (202) wherein the electrode structure (206) of the ion trap is formed by performing a step of back-thinning on the metallization arrangement (230), or by depositing a patterned surface metallization (240) on the insulating material (220) of the back-thinned base substrate (202), or wherein the electrode structure (206) of the ion trap is formed by performing a step of back-thinning on the metallization arrangement (230), or by depositing a patterned surface metallization (240) on the insulating material (220) of the back-thinned base substrate (202). An electrode structure (206) of the ion trap is formed from a patterned metallization arrangement (230).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an electrode structure of an ion trap, in particular, to connecting a base substrate to an insulating substrate. The present invention relates to a method for manufacturing an electrode arrangement of a three-dimensional ion trap.

[0002] For example, a method is proposed for fabricating surface ion traps by single-layer and / or multi-layer metallization on glass, quartz, corundum, diamond or ceramic substrates and for fabricating structures of three-dimensional ion trap arrangements using surface ion traps. Background Art

[0003] A quantum computer is a processor that uses the quantum mechanical states of a system (e.g., qubits). One way to implement qubits in a quantum computer is to use ions in an ion trap. Here, for example, individual ions are held in a row by electromagnetic fields in a vacuum.

[0004] Modern ion traps (e.g., ion traps for quantum computers) include, for example, surface electrodes and are controlled by a multilayer metal structure. Such structures are preferably manufactured in a standardized process sequence for silicon semiconductor production, because the standardized process sequence is particularly controllable and scalable. In combination with other metal structures (e.g., conductive shielding within the silicon substrate), this may produce large parasitic capacitances, which can shorten the coherence time of the ion state.

[0005] It is therefore an object of the present invention to provide an improved method for manufacturing an electrode structure for an ion trap and also to provide an improved method for manufacturing an electrode arrangement for a three-dimensional ion trap, thereby providing an ion trap with improved properties.

[0006] This object is achieved by the subject-matter of the independent claims.

[0007] Specific configurations, embodiments and further developments of the application are defined in the dependent claims. Summary of the invention

[0008] The present invention is based on the realization that the disclosed manufacturing method can be used to manufacture electrode structures using a base substrate having a semiconductor layer that can be manufactured by standard semiconductor manufacturing process steps, and as part of the manufacturing process, the base substrate can be back-thinned, which can remove the semiconductor layer (partially or completely). This can reduce or avoid problems caused by semiconductor materials such as silicon (e.g., high parasitic capacitance). In particular when used in ion traps, this can improve the coherence time of quantum bits. It has been found that connecting to an insulating substrate including a dielectric material provides a carrier that provides mechanical stability to the insulating material with a patterned metallization arrangement for processing (e.g., when back-thinned and connected to other components), but does not exhibit the above-mentioned disadvantages associated with the semiconductor layer, or exhibits these disadvantages to a lesser extent.

[0009] Since the base substrate can be manufactured using standard semiconductor manufacturing process steps, the metallization arrangement can also be manufactured using standard semiconductor manufacturing process steps. Therefore, the metallization arrangement and the resulting electrode structure can be manufactured with high precision and scalability. The base substrate manufactured using standard semiconductor manufacturing process steps includes a structure that generally exhibits uniform behavior during backside thinning, so that the (e.g., flat) shape of the surface of the backside thinned base substrate and the patterned surface metallization deposited on the surface of the backside thinned base substrate can be controlled with high precision.

[0010] It can be appreciated that the advantages of the electrode structure can also be utilized when the electrode structure is connected to the electrode arrangement. The combination of the relative electrode structure increases the flexibility of the field distribution, making it possible to better control the position of the ions in three-dimensional space. For example, a three-dimensional ion trap (e.g., Paul ion trap) arrangement can be realized by two or more electrode structures (or surface traps comprising such electrode structures). The arrangement of the electrode structure and the electric field generated by the arrangement can be controlled during the manufacture of the electrode structure and by the spacer structure.

[0011] Thus, electrode structures and electrode arrangements can be manufactured that can be used in standard semiconductor manufacturing process steps but can reduce the problems caused by materials in semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings and figures. They show:

[0013] Figure 1 is a schematic flow chart of a manufacturing process of the present invention according to an embodiment;

[0014] Figure 2A is a schematic cross-sectional view of an example of a base substrate having a semiconductor layer and a patterned metallization arrangement disposed in an insulating material;

[0015] Figure 2B is a schematic cross-sectional view of an example of a base substrate having a metal pad;

[0016] Figure 3A is a schematic cross-sectional view of an example of an insulating substrate having a dielectric material;

[0017] Figure 3B is a schematic cross-sectional view of an example of an insulating substrate having a metal pad;

[0018] Figure 3C is a schematic cross-sectional view of an example of an insulating substrate having several metal pads;

[0019] Figure 4A is a schematic cross-sectional view of a separation arrangement of a base substrate and an insulating substrate;

[0020] Figure 4B is a schematic cross-sectional view of an arrangement of a base substrate on an insulating substrate;

[0021] Figure 4C is a schematic cross-sectional view of bonding of a base substrate and an insulating substrate;

[0022] Figure 5A is a schematic cross-sectional view of an example of bonding a base substrate to an insulating substrate by a metal bonding process;

[0023] Figure 5B is a schematic cross-sectional view of an example of bonding a base substrate to an insulating substrate by a metal bonding process;

[0024] Fig. 6A is a schematic cross-sectional view of an example of forming an electrode structure of an ion trap by performing a backside thinning step on a metallization arrangement;

[0025] Figure 6B is a schematic cross-sectional view of an example of an electrode structure for forming an ion trap by depositing a patterned surface metallization on an insulating material of a backside thinned base substrate;

[0026] Fig. 7A is a schematic cross-sectional view of an example of a base substrate before forming a groove;

[0027] Figure 7B After the groove has been formed Fig. 7A A schematic cross-sectional view of a base substrate;

[0028] Figure 7C yes Figure 7B A schematic cross-sectional view of a base substrate and an insulating substrate after being connected;

[0029] Fig. 8AThis is done after the back side of the base substrate is thinned. Figure 7C A schematic cross-sectional view of a bonded electrode device;

[0030] Figure 8B After the metallization has been deposited Fig. 8A A schematic cross-sectional view of an electrode device;

[0031] Fig. 9A is a schematic flow chart of a manufacturing process of the present invention according to an embodiment;

[0032] Fig. 9B is a schematic cross-sectional view of an example of an electrode system having an electrode arrangement of a three-dimensional ion trap;

[0033] Fig. 10A is a schematic cross-sectional view of another example of an electrode system having an electrode arrangement of a three-dimensional ion trap;

[0034] Fig. 10B is a schematic cross-sectional view of another example of an electrode system of a three-dimensional ion trap;

[0035] Fig.11A is a schematic cross-sectional view of another example of an electrode system of a three-dimensional ion trap;

[0036] Fig. 11B is a schematic cross-sectional view of another example of an electrode system for a three-dimensional ion trap, wherein a non-metallic sidewall region has a metallized surface thereon; and

[0037] Fig.12 is a schematic top view of an example of an ion trap with electrode devices.

[0038] Before describing the embodiments of the present invention in more detail below with reference to the accompanying drawings, it should be noted that in different figures, the same, functionally equivalent or equivalent elements, objects, functional blocks and / or process steps are provided with the same figure markings, so that the descriptions of these elements, objects, functional blocks and / or process steps (with the same figure markings) shown in different embodiments are interchangeable or mutually applicable. DETAILED DESCRIPTION

[0039] In the following description, the description of the semiconductor layer means that the semiconductor layer includes a semiconductor material, that is, the semiconductor layer is at least partially or completely formed of a semiconductor material. In the following description, the description of the insulating substrate means that the substrate includes an electrically insulating material, that is, the substrate is at least partially or completely formed of an electrically insulating material.

[0040] It will be understood that when an element is described as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intervening elements may be present. Conversely, if an element is described as being "directly" "connected" or "coupled" to another element, there are no intervening elements. Other expressions used to describe relationships between elements should be interpreted in the same manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0041] In order to simplify the description of various embodiments, at least some of the figures have a Cartesian coordinate system x, y, z, wherein the directions x, y, z are arranged orthogonally to one another. In an embodiment, the xy plane corresponds to the main surface area of ​​the carrier or substrate (=reference plane=xy plane), wherein the direction vertically upward relative to the reference plane (xy plane) corresponds to the "+z" direction, and the direction vertically downward relative to the reference plane (xy plane) corresponds to the "-z" direction. In the following description, the term "lateral" refers to a direction parallel to the x-direction and / or the y-direction (i.e., parallel to the xy plane), while the term "vertical" indicates a direction parallel to the +z / -z direction.

[0042] In the context of this specification, terms and / or text paragraphs in brackets should be understood as additional explanations, exemplary configurations, supplements and / or exemplary alternatives (to the previous term or previous text paragraph).

[0043] Figure 1 A schematic flow chart 100 of a manufacturing process of the present invention according to an embodiment is shown. The method is used to manufacture an electrode structure of an ion trap.

[0044] In step 110 , the method includes providing a base substrate including a patterned metallization arrangement in an insulating material disposed on a semiconductor layer.

[0045] Figure 2A A schematic cross section of an example of a base substrate 202 having a semiconductor layer 210 and a patterned metallization arrangement 230 arranged in an insulating material 220 is shown.

[0046] The base substrate 202 can be configured as a standard semiconductor manufacturing substrate or an integrated circuit (IC) substrate. The base substrate 202 (e.g., its semiconductor layer 210) can include at least one of silicon, germanium, and gallium arsenide. The base substrate can be a wafer (e.g., a single crystal semiconductor material), a plurality of wafers, or a portion of a wafer. A standard substrate or IC substrate from semiconductor manufacturing can be manufactured with high precision and scalability or more easily obtained. In addition, manufacturing the electrode structure can optionally be combined with a manufacturing process for a standard substrate.

[0047] The insulating material 220 of the base substrate 202 may include a dielectric from semiconductor manufacturing, such as SiO 2 , HfO 2 or GeO 2. The base substrate 202 may optionally include additional components (e.g., layers), such as at least one of an oxide layer (e.g., on the surface of the semiconductor layer 210 facing and / or facing away from the insulating material 220) and a material for attaching the surface of the semiconductor layer 210 facing away from the insulating material 220 to a carrier substrate.

[0048] Dielectrics from semiconductor manufacturing enable the use of standard semiconductor manufacturing process steps to manufacture the insulating material 220. Thus, the metallization arrangement 230 can be formed by patterning the insulating material 220 using standard semiconductor manufacturing process steps, so that the metallization arrangement 230 and the electrode structure can be formed in a precise and scalable manner.

[0049] In the following description, an embodiment is described in which the semiconductor layer 210 includes silicon and the insulating material 220 includes silicon oxide. However, the present disclosure is not limited to these examples of materials (or other examples described below).

[0050] The metallization arrangement 230 may be configured as a multi-layer metallization arrangement. Thus, the metallization arrangement 230 may have a more complex structure, so that the routing of electrical lines within the insulating material 220 is facilitated, and the electrode structure may be better adapted to the electric field requirements.

[0051] Figure 2A An example of a multilayer metallization arrangement 230 comprising two metallization layers 232a, 232b is shown. The metallization arrangement 230 comprises first vias 234a, 234b, each of which electrically connects the two metallization layers 232a, 232b to each other. The metallization arrangement 230 may comprise further first vias 234a, 234b of further metallization layers 232a, 232b. The metallization arrangement 230 comprises second vias 236a, 236b extending from the (e.g., uppermost) metallization layer 232a to the surface of the insulating material 220. Backside thinning to the uppermost metallization layer 232a enables the electrode structure to be formed completely (or almost completely) within the insulating material 220. Thus, the electrode structure 230 may be formed by standard semiconductor manufacturing process steps.

[0052] The insulating material 220 may include several insulating material layers 220a, 220b. At least one insulating layer 220a, 220b may include one of the metallization layers 232a, 232b and one of the first vias 234a, 234b or the second vias 236a, 236b. The insulating layers 220a, 220b may be used as a carrier layer for forming the metallization arrangement 230. The step of providing 110 the base substrate may include forming a patterned metallization arrangement 230 arranged in the insulating material 220. Forming the insulating material layers 220a, 220b may include forming the metallization layer 232a using photolithography and forming the first vias 234a, 234b using photolithography. The metallization arrangement 230 may include at least one of gold, copper, nickel and silver.

[0053] Figure 2B A schematic cross section of an example of a base substrate 202 having metal pads 238a, 238b is shown.

[0054] The surface area 224 of the base substrate 202 arranged on the insulating material 220 (facing away from the semiconductor layer 210) may include metal pads 238a, 238b (e.g., bonding pads). At least one (or each) of the metal pads 238a, 238b is electrically connected to the metallization arrangement 230 (e.g., through the second via 236a). However, metal pads that are not electrically connected to the metallization arrangement 230 may also be provided (e.g., for field shielding). The step 110 of providing the base substrate may include forming the metal pads 238a, 238b on the surface area 224 of the base substrate 202 (e.g., by photolithography).

[0055] Metal pads 238 a , 238 b may enable insulating material 220 to be connected to insulating substrate 250 (eg, connected to a metal pad of insulating substrate 250 ). Furthermore, metal pads 238 a , 238 b may be used to electrically contact metallization arrangement 230 .

[0056] In step 120 , the method includes providing an insulating substrate including a dielectric material.

[0057] Figure 3A A schematic cross section of an example of an insulating substrate 250 having a dielectric material 252 is shown.

[0058] The dielectric material of the insulating substrate 250 may include or may be formed of glass, diamond, sapphire, corundum, or ceramics. These dielectric materials form a good compromise between reduction of parasitic capacitance, mechanical stability, and compatibility with the base substrate 202.

[0059] The insulating substrate 250 may include at least substantially the same lateral dimensions as the base substrate 202 (eg, Figure 3AThe insulating substrate 250 and the base substrate 202 may have a plate shape (eg, in the form of a wafer). The insulating substrate 250 may include associated metal pads (bonding pads).

[0060] Figure 3B A schematic cross section of an example of an insulating substrate 250 having a metal pad 254 is shown.

[0061] Metal pad 254 completely covers the surface of insulating substrate 250. Due to the size of such metal pad 254, metal pad 254 can facilitate electrical contact.

[0062] The method may include disposing metal pad 254 on a surface of insulating substrate 250 .

[0063] Figure 3C A schematic cross section of an example of an insulating substrate 250 is shown with several metal pads 254. Several metal pads 254 enable individual electrical contact and control.

[0064] Insulating substrate 250 has a surface region 256 , which may be formed by at least one of a surface of dielectric material 252 and at least one metal pad 254 .

[0065] The insulating substrate 250 may include, for example, electrical lines ( FIG. 3A to FIG. 3C The electrical traces of the insulating substrate 250 may be electrically connected to one or more metal pads 254. The electrical traces of the insulating substrate 250 may extend at least partially along one or more surfaces of the insulating substrate 250 and / or within the insulating substrate 250. Alternatively or additionally, the insulating substrate 220 may have electrical traces electrically connected to the metallization arrangement 230. The electrical traces may be laterally (in Figure 2B Extending in the x-direction and / or y-direction).

[0066] FIG. 4A to FIG. 4C A schematic cross section of an arrangement of a base substrate 202 and an insulating substrate 250 is shown. Figure 2A The base substrate 202 and Figure 3A However, any base substrate 202 and insulating substrate 250 described herein may be used.

[0067] Figure 4A A schematic cross section is shown of a separate arrangement of base substrate 202 and insulating substrate 250. Base substrate 202 may be oriented toward the top (e.g., due to a coating process for forming and / or protecting insulating substrate 220) together with insulating substrate 250 (e.g., in a manufacturing device).

[0068] Figure 4B A schematic cross-sectional view of an arrangement of a base substrate 202 on an insulating substrate 250 is shown. Here, the base substrate 202 may be rotated and the surface area 224 of the base substrate 202 may be brought into contact with the surface area 256 of the insulating substrate 250. However, the base substrate 202 and the insulating substrate 250 may also be arranged together in other ways (e.g., rotated together after the base substrate 202 and the insulating substrate 250 have been connected).

[0069] In step 130 , the method includes connecting the surface region 224 of the base substrate 202 disposed on the insulating material 220 to the insulating substrate 250 by a bonding process.

[0070] Figure 4C A schematic cross section of a bonding 204 of a base substrate 202 with an insulating substrate 250 is shown.

[0071] Performing a bonding process between the insulating material 220 of the base substrate 202 and the insulating substrate 250 may be performed using an oxide / oxide bonding process, or may include at least one oxide / oxide bonding process. The oxide / oxide bonding process may include at least one of heating the bonding 204, vibrating the bonding 204, and applying a current to the bonding 204. The oxide / oxide bonding process may include arranging a bonding device between the base substrate 202 and the insulating substrate 250.

[0072] The oxide / oxide bonding process can be implemented using standard semiconductor manufacturing process steps and allows for connections with high mechanical strength. In addition, the oxide / oxide bonding process can reduce the use of metal (eg, in areas where short circuits may occur).

[0073] Figure 5A A schematic cross-sectional view of an example of bonding 204 of a base substrate 202 to an insulating substrate 250 after a metal bonding process is shown. The base substrate 202 includes a substrate such as that described herein. Figure 2B The insulating substrate 250 includes metal pads 238a, 238b as described herein. Figure 3B Description of the metal pad.

[0074] Performing a bonding process between the base substrate 202 and the insulating substrate 250 can be performed by a metal bonding process at the associated metal pads 238a, 238b, 254. The metal bonding process may include at least one of heating, vibration, and applying an electric current. Since the metal pads cover all (or at least most) of the surface of the insulating substrate 250, the alignment of the metal pads 238a, 238b, 254 with each other is simplified.

[0075] The metal bonding process can be performed using standard semiconductor manufacturing process steps and can therefore be performed in a precise and scalable manner. Furthermore, electrical contacting for control electrode structures can be achieved.

[0076] Figure 5B A schematic cross-sectional view of an example of bonding 204 of a base substrate 202 to an insulating substrate 250 after a metal bonding process is shown. The base substrate 202 includes a substrate such as that described herein. Figure 2B The insulating substrate 250 includes the metal pads 238a, 238b described herein. Figure 3C Description of the metal pad.

[0077] Performing a bonding process between the base substrate 202 and the insulating substrate 250 can be performed by a metal bonding process at the associated metal pads 238a, 238b, 254. The metal bonding process may include at least one of heating, vibration, and applying an electric current. The plurality of metal pads 238a, 238b, 254 enables different electrical signals to be applied to different components of the metallization arrangement 230 (e.g., to generate an electric field in an ion trap).

[0078] The bonding process may be performed as a combination of an oxide / oxide bonding process and a metal bonding process (hybrid bonding process). For example, an oxide / oxide bonding process may be performed between the insulating material 220 and the insulating substrate 250. For example, a metal bonding process may be performed between the metallization arrangement 230 (e.g., the second via 236a and the metallization layer extending to the surface area 224 of the base substrate 202 or the metal pads 238a, 238b) and one or more metal pads 254 of the insulating substrate 250.

[0079] The combination of the oxide / oxide bonding process and the metal bonding process (hybrid bonding process) allows more flexibility in selecting the type of connection between different structures of the insulating material 220 and the insulating substrate 250. Thus, for example, a specific electrical contact can be achieved by the metal bonding process, and undesired metal contacts can be reduced by the oxide / oxide bonding process.

[0080] In step 140, the method includes back thinning the base substrate 202 by removing the semiconductor layer 210 to the insulating material 220 of the base substrate 202. The electrode structure of the ion trap is formed by performing the step 140 of back thinning the metallization arrangement 230 or by depositing a patterned surface metallization on the insulating material 220 of the back thinned base substrate 202, wherein the electrode structure of the ion trap is formed by the patterned metallization arrangement.

[0081] During the step of bonding with the insulating substrate 250 and / or backside thinning of the base substrate 202, the base substrate 202 may be fixed to a carrier substrate, for example, made of a dielectric material such as glass, diamond, sapphire, corundum, or ceramic. The carrier substrate facilitates processing and enables processing of multiple base substrates 202 simultaneously.

[0082] Fig. 6A and Figure 6B A schematic cross section of an example of an electrode device 200 with an electrode structure 206 of an ion trap is shown. Fig. 6A An example of an electrode device 200 can be, for example, Figure 5B The bonding 204 is achieved by backside thinning. However, the disclosure described herein is not limited thereto.

[0083] Fig. 6A A schematic cross-sectional view of an example of forming an electrode structure 206 of an ion trap by performing a step of backside thinning of a metallization arrangement 230 is shown. This exposes an uppermost metal surface 232a of the metallization arrangement 230 from the insulating material 220, which forms the electrode structure 206 (e.g., in the form of a surface electrode). The electrode structure 206 may include one, two, three, four or more surface electrodes. Fig. 6A The example of electrode structure 206 shown includes two surface electrodes formed by metallization layer 232a. By applying an electrical signal to metallization arrangement 230 (e.g., via at least one of metal pads 238a, 238b, 254 and electrical lines of insulating substrate 250), electrode structure 206 can generate an electric field. The electric field can be used to control the position of ions 280.

[0084] The exposed metallization layer (eg, Fig. 6A The metallization layer 232a in the surface ion trap can form an electrode structure of a surface ion trap. To this end, the exposed metallization layer 232a can be located in a common plane. The exposed metallization layers 232a, 232b can be controlled by an electrical signal to generate an electric field, which keeps the ions in a position close to the exposed metallization layer 232a, for example, in the gap between the two surface electrodes and spaced apart from the insulating material 220. For example, the exposed metallization layer 232a can have a spacing between 50 and 400 μm (e.g., between 100 μm and 200 μm).

[0085] Backside thinning allows the formation of an at least substantially flat surface, so that an exposed metallization layer or a deposited patterned surface metallization can also be arranged in a flat plane. This means that the electrode structure thus formed can be used to generate an electric field with good precision, which is advantageous for surface traps.

[0086] Figure 6BA schematic cross-sectional view of an example of forming an electrode structure 206 of an ion trap by depositing a patterned surface metallization 240 on an insulating material 220 of a back thinned base substrate 202 is shown. The surface metallization 240 includes first metallization portions 242a, 242b, which are electrically connected to a metallization arrangement 230 (e.g., connected to at least one metallization layer 232a or a second via 236a). In this case, the electrode structure 206 can be formed by the first metallization portions 242a, 242b. The surface metallization 240 includes a second metallization portion 244 that is electrically insulated from the metallization arrangement 230. By applying an electrical signal to the metallization arrangement 230 (e.g., via at least one of the electrical lines of the metal pads 238a, 238b, 254 and the insulating substrate 250), the electrode structure 206 (e.g., the first metallization portions 242a, 242b) can generate an electric field. The second metallization portion 244 can improve electrical shielding.

[0087] Figure 6B The surface metallization 240 in the embodiment includes first metallization portions 242a, 242b and second metallization portions 244. Alternatively, the surface metallization 240 may include only first metallization portions 242a, 242b. The second metallization 244 may also be performed for other electrode devices 200 described herein.

[0088] FIG. 5A to FIG. 6B The metal pads 238a, 238b, 254 in the embodiment are configured as protrusions (protruding beyond the surface of the insulating material 220 and the insulating substrate 250). Alternatively, at least one (or all) of the metal pads 238a, 238b, 254 may be configured to be flush with the surface of the insulating material 220 and the insulating substrate 250 (or recessed into the surface).

[0089] The deposited patterned surface metallization 240 (e.g., first metallization portions 242a, 242b) on the insulating material 220 of the back thinned base substrate 202 can form an electrode structure 206 of a surface ion trap. The surface metallization 240 (e.g., first metallization portions 242a, 242b) can be controlled by an electrical signal to generate an electric field that keeps ions close to the patterned surface metallization 240 (e.g., between the first metallization portions 242a, 242b). For example, the two first metallization portions 242a, 242b can have a distance between 50 and 400 μm (e.g., between 100 μm and 200 μm).

[0090] The step of backside thinning may be performed on the uppermost (or disposed furthest from the insulating substrate 250 ) patterned metallization layer of the multilayer metallization arrangement 230 (eg, at least one of the metallization layers 236 a , 236 b ).

[0091] In the step of thinning the back side of the base substrate 202 , the semiconductor layer 210 of the base substrate 202 may be completely (or almost completely, for example, 99% or more than 99.9%) removed.

[0092] By completely removing the semiconductor layer 210, problems caused by the semiconductor material (e.g., parasitic capacitance and the effect on the electric field) can be completely eliminated. In addition, the surface of the back-thinned base substrate 202 is formed by the surface of the insulating material 220 (or other intermediate layers, such as an oxide layer of a semiconductor material), so that the surface of the base substrate 202 can be controlled not only by the back-thinning, but also (at least mainly) by the surface of the insulating material 220.

[0093] Backside thinning may include removing a portion of, for example, a dielectric of insulating material 220 and / or an optional oxide layer between the dielectric and semiconductor layer 210. Insulating material 220 may be backside thinned to less than 1 μm or less than 0.1 μm.

[0094] Backside thinning may include at least one of dry etching, wet etching, and backside polishing (eg, chemical mechanical polishing).

[0095] The method for manufacturing the electrode structure 200 of the ion trap can be performed using standard semiconductor manufacturing process steps. In addition, the base substrate can be manufactured using standard semiconductor manufacturing process steps. However, the method allows the base substrate 202 to be thinned on the back side, thereby significantly reducing or completely removing the amount of material in the semiconductor layer 210. Common materials (e.g., silicon) used in standard semiconductor manufacturing process steps can produce parasitic capacitance, which may affect some applications, such as use in ion traps. Therefore, the method enables the electrode structure 200 to be manufactured using an efficient and accurate manufacturing process and reduces or eliminates the disadvantages that may be caused by the materials used in the manufacturing process.

[0096] The metallization arrangement 230 embedded in the insulating material 220 can be configured as an antenna structure for providing an electric field to the ion trap. A constant signal (e.g., a constant voltage) or an alternating signal (e.g., an alternating voltage) can be applied to the metallization arrangement 230. A constant field (DC field) can be generated by one portion of the electrode structure 206, and an alternating field (RF field) can be generated by another portion of the electrode structure 206. Based on these signals, the metallization arrangement 230 can generate an electric field as an antenna structure.

[0097] Since ion traps may be susceptible to parasitic capacitance, using the metallization arrangement 230 as an antenna structure may improve the operation of the ion trap. In particular, it may extend the coherence time of the ion state.

[0098] Ion traps may be provided for quantum computing applications. Since quantum mechanical calculations can be performed within the coherence time, ion traps with the electrode structures described herein may enable more complex quantum computing applications.

[0099] The method may further comprise the step of forming a recess in the form of a hole or a trench in the base substrate 202 , which recess passes through the insulating material 220 of the metallization arrangement 230 down to the semiconductor layer.

[0100] When the groove extends through the insulating material of the metallization arrangement 230 (e.g., a multi-layer metallization arrangement), the groove can form a volume in which an electric field is generated by the electrode structure (and optionally, by the portion of the multi-layer metallization arrangement arranged in the insulating material) that allows ions to be positioned within the groove. Due to the manufacturing described herein, the electrode structure can be precisely formed and allows good control of the electric field within the groove.

[0101] Fig. 7A A schematic cross-section of an example of a base substrate 202 prior to forming a groove is shown. The groove may be configured in any base substrate 202 (or bond 204) described herein. Fig. 7A In the example of Figure 2A An implementation of the base substrate 202 , wherein the insulating material 220 further includes an oxide layer 226 (IC insulating oxide, such as an oxide of the material of the semiconductor layer) on a side facing the semiconductor layer 210 . Figure 7B The insulating material 220 in the embodiment may also be free of the oxide layer 226. The oxide layer 226 may be a part of any insulating material 220 described herein.

[0102] Figure 7B After the groove 228 has been formed Fig. 7A Schematic cross section of the base substrate 202.

[0103] The groove 228 may also be formed at a different time. For example, the groove 228 may be configured after step 130 (connecting the base substrate 202 to the insulating substrate 250) and step 140 (backside thinning the base substrate 202).

[0104] The step of forming the recess 228 may be performed by hole or trench etching. The recess 228 may also extend into or through the semiconductor layer 210. The recess 228 may have a cylindrical or cubic shape. The recess 228 may have an elongated rectangular parallelepiped cross-section (e.g., Figure 7B The groove 228 may have the longest extension in the y direction. Figure 7B The insulating material 220 extends completely through the insulating material 220 in the x-direction and / or the y-direction in FIG.

[0105] Hole or trench etching can precisely form this recess and can be performed using standard semiconductor manufacturing process steps.

[0106] The groove 228 includes a sidewall 248. The sidewall 248 may be configured to be flat or rounded. The sidewall 248 may be arranged spaced apart from the metallization arrangement 230. In other words, the groove 228 may be shaped such that the groove 228 does not intersect the metallization arrangement 230.

[0107] Figure 7C Shows the Figure 7B Schematic cross section of the bonding 204 after the base substrate 202 is connected to the insulating substrate 250.

[0108] exist Figure 7B In the example of , the base substrate 202 includes flush metal pads 238a, 238b, and the insulating substrate 250 includes a flush metal pad 254. Connecting the base substrate 202 to the insulating substrate 250 can be achieved by a metal bonding process between the metal pads 238a, 238b, 254. Alternatively, the connection can be achieved by another bonding process described herein. However, the base substrate 202 and / or the insulating substrate 250 may include any of the metal pads 238a, 238b, 254 described herein. In addition, each base substrate 202 and / or the insulating substrate 250 described herein may include flush metal pads 238a, 238b, 254.

[0109] Fig. 8A The back side of the base substrate 202 is thinned by removing the semiconductor layer 210 to the insulating material 220 of the base substrate 202. Figure 7C Schematic cross section of a bonded electrode device 200 .

[0110] The electrode structure 206 of the ion trap is formed by a patterned metallization arrangement 230. Fig. 8A In the example shown, backside thinning is performed on (or partially on) the oxide layer 226. The metallization arrangement 230 may generate an electric field outside the insulating material 220 without protruding from the insulating material 220. For example, the metallization arrangement 230 may generate an electric field within a groove 228 (surrounded by or adjacent to the metallization arrangement 230) for controlling the position of the ions 280 within the groove 228.

[0111] Alternatively, the oxide layer 223 may be removed as part of a backside thinning process or a separate etching process. Optionally, a surface metallization (eg, for shielding or electrical contact with the metallization arrangement 230) may be deposited on the insulating material.

[0112] Figure 8B shows that after metallization has been arranged Fig. 8A Schematic cross section of an electrode device 200 .

[0113] The method may further comprise the step of partially or completely arranging a metallization 246 on the sidewalls 248 of the recess 228 in the insulating material 220 of the back thinned base substrate 202. The metallization 246 may be arranged on the surface of the dielectric of the insulating material 220. Alternatively or additionally, the metallization 246 may be arranged on the surface of the insulating substrate 250 (which bounds the recess 228). If the insulating material 220 comprises an oxide layer 226, the metallization 246 may additionally be arranged on the sidewalls 248 of the oxide layer 226. Figure 8B In the example shown, metallization 246 is disposed on the surface of insulating material 220, insulating substrate 250, and oxide layer 226. Metallization 246 can improve electrical shielding of groove 228. To this end, metallization 246 can be electrically connected to a reference potential (V 参考 ≠0V) or ground potential (V GR =0 V). The metallization can also be arranged at an earlier stage (eg before connection to the insulating substrate 250 or backside thinning of the standard substrate 202).

[0114] For example, the metallization 246 may be configured in a patterned manner (e.g., using optical lithography). The metallization 246 may include one or several cutouts (e.g., edges of holes and / or recesses). The cutouts may be arranged symmetrically about the axis of symmetry of the groove 228 (e.g., rotationally symmetrically about the axis of a cylindrical groove or mirror symmetrically about the mirror axis of an elongated or cuboid groove). The metallization 246 may include at least one sidewall 248 and / or a structure on one of the surfaces of the insulating substrate 250. The patterned metallization 246 may enable or improve the formation of an electric field (e.g., generated by the electrode structure 206).

[0115] The metallization 246 may be configured and patterned to allow an electric (or electromagnetic) field to couple into the recess 228. Thus, the electrode arrangement 208 including the electrode structures 206-1, 206-2 may provide an electric field that may be used to control the position of the ions 280, for example.

[0116] Any electrode device 200 described herein (as well as the electrode system 400 described below) can form an ion trap (e.g., a two-dimensional and / or three-dimensional ion trap) (or at least a portion of an ion trap). Any method for making an electrode device or electrode system described herein can be a method for making an ion trap (e.g., a two-dimensional and / or three-dimensional ion trap) or can include a method for making an ion trap. The method can include electrically coupling an electrode structure (or electrode arrangement) to a power source. The power source can be configured to provide a voltage that causes an electric field to be generated at the electrode structure (or electrode arrangement). The electric field can be configured to control the position of the ions (e.g., by providing an AC voltage and / or a DC voltage).

[0117] Since the base substrate includes a semiconductor layer (at least before the back side is thinned), the insulating material and / or metallization arrangement can be manufactured via a semiconductor process step. This manufacturing method can have various advantages, such as improved precision, automation and / or patterning processes, and improved growth conditions (e.g., growing and forming an accurate oxide layer on single crystal silicon, such as for insulating materials). Since it is connected to an insulating substrate and the back side is thinned, the semiconductor layer can be completely or at least partially removed, thereby reducing the influence of the semiconductor layer. The ion trap with the electrode device 200 (or electrode system 400) has a back side thinned semiconductor layer, so that the influence of semiconductor materials such as silicon can be reduced or avoided. For example, the formation of parasitic capacitance can be reduced. For example, the method can change the substrate material from silicon to glass, quartz or sapphire.

[0118] According to an embodiment, a method for manufacturing an ion trap is provided. The method for manufacturing an ion trap can be performed (partially or completely) by a semiconductor manufacturing process. The ion trap can be provided for quantum computing applications. The method can be used to manufacture a three-dimensional ion trap, or can include manufacturing a three-dimensional ion trap.

[0119] One advantage of the present invention is that standard semiconductor process components can be used. Conventionally, ion traps are manufactured using more complex, expensive and sophisticated microprocessing techniques and metallization processes. Therefore, the present invention enables ion traps to be manufactured more cost-effectively and efficiently, and most importantly, significantly improves the quality and reliability of the product.

[0120] According to an embodiment, a method of manufacturing an ion trap (e.g., for quantum computing applications) includes the following steps: providing a substrate of standard semiconductor manufacturing (e.g., base substrate 202, such as an IC substrate), which includes IC multilayer metallization (e.g., metallization arrangement 230) and optional metallization structures (e.g., metal pads 238b) for a substrate bonding process (metal bonding pads).

[0121] The method may include making (e.g., recessing) trenches (e.g., grooves 228) through one or more dielectrics (e.g., insulating material 220) of an IC substrate (e.g., base substrate 202). In addition, the method may include connecting (e.g., bonding) the IC substrate (e.g., base substrate 202) to a second substrate (e.g., insulating substrate 250) including a dielectric surface (insulating substrate) to form a substrate stack. The connection may be performed by oxide / oxide bonding and metal bonding pads (e.g., metal pads 238b) on the front side (hybrid bonding process). The method may include: back thinning the substrate stack (e.g., including base substrate 202 and insulating substrate 250) to the dielectric layer (e.g., insulating material 220) so that the semiconductor layer (e.g., semiconductor layer 210) of the IC substrate (e.g., base substrate 202) is completely (or partially) removed.

[0122] The back side thinning can be performed on the surface of the semiconductor layer facing away from the insulating substrate. The back side thinning can be performed uniformly on the surface of the semiconductor layer facing away from the insulating substrate (e.g., without patterning and / or masking). In other words, the thickness of the base substrate can be uniformly reduced by back side thinning. The base substrate (e.g., the semiconductor layer 210 or the rest of the insulating material 252) can form a (e.g., single) flat surface on the side of the back side thinning (e.g., the side facing away from the insulating substrate 250).

[0123] For example, an IC substrate (e.g., base substrate 202) may include an insulating oxide, one or more intermetallic dielectrics (e.g., insulating material 220), metallization (e.g., metallization arrangement 230), and a metal bonding pad (e.g., metal pad 238b). The IC substrate may be manufactured using standard semiconductor manufacturing processes. Optionally, a trench etch may be performed through one or more dielectrics (e.g., down to the IC substrate). The method may include bonding the front surface to the insulating substrate (e.g., by oxide / oxide bonding or metal hybrid bonding).

[0124] According to an embodiment, for example, an interconnected 3D integrated system with the following properties is implemented. The structure of the surface ion trap can be implemented by a single layer and / or multilayer metallization on a glass, quartz, sapphire or ceramic substrate. In order to optimize the DC / RF field, a gray tone lithography method can be used to three-dimensionally construct a metal surface (e.g., an electrode structure 206 and / or an electrode arrangement 208). The three-dimensional Paul ion trap arrangement can be patterned by connecting two or more surface ion traps (e.g., two or more electrode structures 206 or an ion trap with an electrode structure 206). The mechanical and / or electrical connection of the ion trap to the carrier (which can also be a surface ion trap) can be ensured (e.g., implemented) by interconnection. According to an embodiment, a method for manufacturing a surface ion trap, for example, by a single layer and / or multilayer metallization on a glass, quartz, corundum, diamond or ceramic substrate is provided. The three-dimensional ion trap structure can include one or more surface ion traps. The method can include three-dimensionally patterning the electrode surface morphology using gray tone lithography to modify the electric field properties.

[0125] Another method for manufacturing a three-dimensional well includes connecting an electrode device to another electrode arrangement. For the following method 300 for manufacturing a three-dimensional well, the steps of the above method 100 can also be used and applied partially or completely and in any combination. The structure described in the above electrode structure can be implemented in a three-dimensional well partially or completely and in any combination. The above technical effects are also applicable to the following embodiments.

[0126] Fig. 9A A schematic flow chart 300 of a manufacturing method of the present invention according to an embodiment is shown. The method 300 is used to manufacture an electrode arrangement of a three-dimensional ion trap.

[0127] In step 310 , the method includes performing method 100 (with steps 110 , 120 , 130 , 140 ) as described herein to fabricate an electrode structure (for an ion trap) on a backside thinned base substrate.

[0128] Thus, step 310 includes providing a base substrate (see also Figure 1 In step 110), the base substrate comprises a patterned metallization arrangement in an insulating material arranged on the semiconductor layer. Figure 2A and Figure 2B An example of a base substrate 202 is shown.

[0129] Step 310 includes providing an insulating substrate including a dielectric material (see also Figure 1 Step 120). FIG. 3A to FIG. 3C An example of an insulating substrate 250 is shown.

[0130] Step 310 also includes connecting the surface portion 224 of the base substrate 202 disposed on the insulating material to the insulating substrate 250 (see also FIG. 2 ) using a bonding process. Figure 1 Step 130). Figure 4A and Figure 4B An example of arrangement of the base substrate 202 to the insulating substrate 250 is shown. Figure 4C , Figure 5A and Figure 5B An example of a bond 204 including a base substrate 202 and an insulating substrate 250 is shown.

[0131] Step 310 also includes back thinning the base substrate 202 by removing the semiconductor layer 210 to the insulating material 220 of the base substrate 202. The electrode structure of the ion trap is formed by performing step 140 of back thinning the metallization arrangement 230, or by depositing a patterned surface metallization on the insulating material 220 of the back thinned base substrate 202, or wherein the electrode structure 206 of the ion trap is formed by the patterned metallization arrangement 230 (see also Figure 1 Step 140). Fig. 6A and Figure 6B An example of an electrode device 200 having a backside thinned base substrate is shown.

[0132] In step 320, the method includes providing another substrate having another electrode structure.

[0133] Another substrate may have a plate shape or a wafer shape. The substrate may include a dielectric material (e.g., glass, diamond, sapphire, corundum or ceramic) or be composed thereof. Another substrate may include a metal. Another substrate may include a surface coating containing a dielectric material on at least one surface. Another electrode structure may be arranged on the dielectric material or the surface coating. Providing another substrate with another electrode structure may include manufacturing another substrate with another electrode structure. Manufacturing another electrode structure may include at least one of optical lithography, gray tone lithography and material deposition. Another substrate may be manufactured using a method with low complexity. For example, another substrate may be manufactured by shaping a metal electrode on a glass substrate. For example, electrical circuits cannot be provided by another substrate.

[0134] However, the further substrate may also have a more complex structure. The providing according to step 320 may include, for example, performing any of the methods (100) described herein to manufacture a further back-thinned base substrate having an electrode structure forming a further electrode structure.

[0135] In this case, step 320 also includes providing and connecting a base substrate and an insulating substrate (method 100) and back thinning the substrate as described with reference to step 310. The further substrate including another back thinned base substrate can enable or facilitate electrical contact on one side of, for example, another back thinned base substrate (or free space for ions) back to the back thinned base substrate and / or another insulating substrate.

[0136] However, the providing according to step 320 may include only parts and / or variations of method 100. For example, step 320 may include providing a base substrate according to step 110 but not according to steps 120, 130, and 140. Another substrate may be configured without an insulating substrate. In another example, in a variation of step 110, the method may include providing a base substrate having a metallization arrangement on an insulating material on a semiconductor layer (rather than in an insulating material).

[0137] Manufacturing an electrode structure may include any combination of any process steps as described herein. An electrode structure may include any combination of any features as described herein. Manufacturing another electrode structure may include any combination of any method steps as described herein. The another electrode structure may include any combination of any features as described herein.

[0138] The electrode structure and the further electrode structure may have (at least substantially) the same features or be produced by the same method steps. The electrode structure and the further electrode structure may be produced, for example, by the same production device or in parallel in the same production process.

[0139] Alternatively, the electrode structure and the further electrode structure may be manufactured by different manufacturing steps and / or comprise different features.

[0140] In step 330, the method includes connecting the back thinned base substrate and another substrate (e.g., another back thinned base substrate) by arranging a spacer structure between the back thinned base substrate and the other substrate, so that the electrode structure and the other electrode structure face each other (vertically) and form an electrode arrangement of a three-dimensional ion trap.

[0141] The insulating material of the electrode device and the optional another insulating material of the other electrode device (e.g., another substrate or another back-thinned base substrate) may face each other. The insulating substrate of the electrode device and the optional another insulating substrate of the other electrode device may be back to back. The electrode structure and at least a portion of the other electrode structure (e.g., some or all of the electrodes and / or conductive paths of the two electrode structures) may be arranged in mirror symmetry, wherein the mirror plane (e.g., vertically) passes through the spacer structure. If the other substrate includes another back-thinned base substrate, at least a portion of the two back-thinned base substrates (e.g., at least a portion of the electrode structure, the metallization arrangement, the insulating material, or any combination thereof) may be arranged in mirror symmetry, wherein the mirror plane (e.g., vertically) passes through the spacer structure.

[0142] Fig. 9B Schematic cross section of an example of an electrode system 400 having an electrode arrangement 208 of a three-dimensional ion trap is shown. The electrode system 400 includes a spacer structure 260 between an electrode device 200-1 and another electrode device 200-2. Fig. 9B In the example of the electrode system 400 shown, the further substrate is formed by the further electrode device 200-2. Alternatively, the electrode system 400 may include any other further substrate described herein.

[0143] The electrode device 200 - 1 includes an insulating substrate 250 - 1 and a backside thinned base substrate 202 - 1 including an insulating material 220 - 1 in which a metallization arrangement 230 - 1 is arranged.

[0144] The further electrode device 200 - 2 comprises a further insulating substrate 250 - 2 and a further backside thinned base substrate 202 - 2 comprising a further insulating material 220 - 2 in which a further metallization arrangement 230 - 2 is arranged.

[0145] Fig. 9B The spacer structure 260 in the example includes two spacer elements 262a, 262b. Alternatively, the spacer structure 260 may include only one or more (e.g., three, four, five or more) spacer elements 262. The spacer structure 260 (or its spacer elements) may have one or more (continuous) openings. The opening may be configured (e.g., together with the electrode structure 206-1 and another electrode structure 206-2) to (at least partially) limit the volume of the 3D ion trap. For example, the spacer structure 260 may include a plate structure having one or more openings, which pass through the plate structure, each opening being arranged between the electrode structures 206-1, 206-2 and another electrode device 200-1, 200-2.

[0146] The spacer structure 260 may include a dielectric material such as glass, diamond, sapphire, corundum, or ceramic.

[0147] In the step of connecting the back-thinned base substrate 202-1 with another back-thinned base substrate 202-2, the spacer structure 260 can be configured as a spacer substrate (for example, having a plate-like structure) and can be arranged between the back-thinned base substrate 202-1 and another back-thinned base substrate 202-2.

[0148] The spacer substrate may include a dielectric material, such as glass, diamond, sapphire, corundum or ceramic. The spacer substrate may include a metal coating on at least one lateral side (e.g., pointing toward the volume to be accommodated for the ions). The metal coating may be electrically connected to a ground potential or a reference potential. For example, the metal coating may be electrically connected to a portion of at least one (e.g., one, two or more electrodes) of the electrode arrangement 208, the electrode structure 206-1, and another electrode structure 206-2, which in turn may be electrically connected to a ground potential or a reference potential. Another (or remaining) portion of the electrode structure 208 may, for example, form a controllable electrode arrangement of a 3D ion trap. Alternatively, the entire electrode arrangement 208 may form a controllable electrode arrangement of a 3D ion trap.

[0149] The spacer structure (or a portion thereof) may be formed on the insulating material 220 - 1 or 220 - 2 by material deposition.

[0150] During the steps of connecting to the insulating substrate 250-1, backside thinning the base substrate 202-1, and connecting to another substrate (e.g., with another backside thinned base substrate 202-2), the base substrate 202-1 can be fixed to a carrier substrate, for example, made of a dielectric material such as glass, diamond, sapphire, corundum, or ceramic. The carrier substrate facilitates processing and enables simultaneous processing of multiple (base) substrates 202-1, 202-2.

[0151] Electrode arrangement 208 includes electrode structures 206-1, 206-2 and allows the generation of an electric field that can be used, for example, to control the position of ions 280. Electrode arrangement 208 can be controlled with a common signal. Alternatively, electrode structures 206-1, 206-2 can be controlled with different signals. Each electrode of the same electrode structure 206-1, 206-2 can be controlled with different signals. Alternatively, electrodes of different electrode structures 206-1, 206-2 can be controlled with the same signal (e.g., to generate a quadrupole field distribution).

[0152] exist Fig. 9BIn the example of the electrode system 400 shown, the electrode devices 200-1, 200-2, the back thinned substrates 202-1, 202-1, the metallization arrangements 230-1, 230-2, and the electrode structures 206-1, 206-2 are arranged mirror-symmetrically about a mirror plane (parallel to the x-axis and the y-axis) through the spacer structure 260. Alternatively, the mirror symmetry can be extended to any combination of the above components.

[0153] Fig. 10A A schematic cross section of another example of an electrode system 400 with an electrode arrangement 208 of a three-dimensional ion trap is shown.

[0154] The method for manufacturing the electrode arrangement 208 may further include arranging an interconnect structure 264-1 on the back thinned base substrate 202-1 (e.g., insulating material 220-1), and arranging another interconnect structure 264-2 on another substrate (e.g., another back thinned base substrate 202-2 (e.g., insulating material 220-1)). The interconnect structures 264-1, 264-2 may be arranged by material deposition or oxide / oxide bonding processes on the respective insulating materials 220-1, 220-2. Fig. 10A In the example of the electrode system 400 shown, the further substrate is formed by the further electrode device 200-2. Alternatively, the electrode system 400 may include any other further substrate described herein.

[0155] The method may further include connecting the backside thinned base substrate 202 - 1 and another substrate (eg another backside thinned base substrate 202 - 2 ) by connecting opposing interconnect structures 264 - 1 , 264 - 2 , wherein the connected interconnect structures 264 - 1 , 264 - 2 (at least partially) form the spacer structure 260 .

[0156] The relative interconnect structures 264-1, 264-2 realize mechanical and / or electrical connection between the (base) substrates 202-1, 202-2. In the case of electrical connection, the arrangement of electrical lines of the electrode system 400 can be simplified. For example, the electrical lines can be routed from the electrode structure 206-1 to one side of the electrode structure 206-2 via the spacer structure 260 to more easily bundle the electrical conductors.

[0157] This arrangement allows, for example, to apply an electrical signal only to one side of the electrode system 400 (e.g., for single-sided control). For example, a portion of the electrical signal can be applied to a portion of the metallization arrangement 230 that is electrically connected to the electrode arrangement 206-1, and another portion of the electrical signal can be applied to another portion of the metallization arrangement 230 that is electrically connected to another electrode arrangement 206-2. In addition, the metallization arrangement 230 may include other portions connected to other components (e.g., one or more metallizations electrically connected to a ground potential or a reference potential via, for example, the metallization arrangement 230). Therefore, electrical conduction via the spacer structure 260 can allow for more flexible and / or easier electrical connection and control. In addition, since, for example, electrical connection through an optional further back thinned base substrate 202-2 and / or through an optional further insulating substrate 250-2 can be omitted, the requirements for another substrate can be reduced.

[0158] For example, the other substrate may include another electrode structure on its surface, which is connected to the electrical circuit on the spacer structure 260. However, for another substrate with low complexity (e.g., without another back thinned base substrate), the electrical circuit on the spacer structure 260 is not necessary. The other electrode structure can also be controlled via other electrical circuits. For example, additional electrical circuits can be routed along the surface of the other substrate from the free space of the 3D ion trap. In addition, the substrate may include metal (e.g., the other electrode structure is locally limited by an electrical insulating layer and / or is at least partially separated from the other electrode structure), which can implement electrical circuits for control.

[0159] Connecting the opposing interconnect structures 264-1, 264-2 may be performed by a bonding process (eg, an oxide / oxide bonding process or a metal bonding process). Prior to connecting the opposing interconnect structures 264-1, 264-2, metallization may be deposited on at least one of the interconnect structures 264-1, 264-2. Fig. 10A In the example shown, interconnect structures 264 - 1 , 264 - 2 are connected by metal connections 266 (eg, to provide one or more conductive traces).

[0160] In the step of connecting the back thinned base substrate 202-1 and another substrate (e.g., another back thinned base substrate 202-1), (at least) two laterally adjacent electrode structures 206-1 of the back thinned base substrate 202-1 can be arranged vertically opposite to two laterally adjacent electrode structures 206-2a, 206-2b of another substrate (e.g., another back thinned base substrate 202-2). Therefore, when an electrical signal is applied to the electrode structures 206-1, 206-2a, 206-2b, different electric fields can be generated. The electrode structures 206-1, 206-2 may include at least substantially the same size (e.g., showing mirror symmetry). The vertically opposite arrangement can improve the symmetry of these electric fields.

[0161] Two pairs of vertically opposed electrode structures can form a controllable electrode arrangement for a 3D ion trap (e.g., for quantum computing applications). Because the pairs of electrode structures are opposite each other, it is easier to generate an electric field that can hold ions in the three-dimensional volume between the electrode structures.

[0162] The method may further include patterning the electrode structures 206-1, 206-2a, 206-2b of the back thinned base substrate 202-1 and / or another substrate (e.g., another back thinned base substrate 202-2), for example using gray tone lithography techniques, to obtain the three-dimensional patterned electrode structures 206-1, 206-2a, 206-2b of the electrode arrangement 208. Gray tone lithography may include moving a photomask during illumination and / or using a photomask with different light transmittances.

[0163] exist Fig. 10A In the example shown, the electrode structure 206-2a has been patterned to obtain a three-dimensional patterned electrode structure 206-2a. Alternatively, several or all of the electrode structures 206-1, 206-2a, 206-2b can be configured as three-dimensional patterned electrode structures 206-1, 206-2a, 206-2b. The three-dimensional electrode structure can improve the flexibility of shaping and optimizing the electric field. This can improve the control of ions in the three-dimensional ion trap.

[0164] Fig. 10B A schematic cross section of another example of an electrode system 400 for a three-dimensional ion trap is shown.

[0165] The electrode system 400 includes an electrode arrangement 208 having electrode structures 206-1, 206-2 that can generate an electric field for controlling the position of ions in a three-dimensional ion trap.

[0166] Back thinned base substrate 202-1 (only in Fig. 10B2 (schematically shown in FIG. 2 ) is connected to a spacer structure 260 including a metallization 268a. The metallization 268a is electrically connected to an electrode structure 206-1 of the base substrate 202-1 through a metal connection 270 (eg, a conductive trace such as a metal conductive trace). The other substrate 200-2 includes another metallization 268b.

[0167] Connect the back thinned base substrate 202-1 and another substrate 200-2 (only in Fig. 10B 268a and another metallization 268b). Thus, the electrode structure 206-1 includes an electrical connection to another substrate 200-2 via a metal bond 270 and metallizations 268a, 268b. Thus, the electrical connections for the electrode system 400 can be bundled on one side of another base substrate 202-2 (e.g., for controlling electrodes 206-1, 206-2 with the same signal). Optionally, the metal connection 270 can be configured in the form of an electrode extension of the electrode structure 206-1. Fig. 10A The described electrical conductors are examples of metal connections 270. Therefore, the metal connections 270 can be configured and used like the electrical conductors described above. Therefore, the advantages disclosed above for the electrical conductors also apply to the metal connections 270. Due to the metal connections 270, one or several (or all) electrodes of the other electrode structure 270 can be controlled via the electrode structure of the back thinned base substrate 202-1 (for example, for single-sided control). The electrode system 400 can be configured to be controlled only from one side via one or several metal connections 270. For example, the other substrate 200-2 may not be provided with electrical lines passing through the other substrate 200-2 (such as Fig. 10B Schematically shown).

[0168] Metal connection 270 (and / or reference Fig. 10AThe configuration described in the form of electrical circuits via the spacer structure 260) can also be combined with another back thinned base substrate 202-2. This can provide more flexibility for controlling the electrode arrangement 208. For example, the electrode can be used to generate the electric field of the 3D ion trap via the metallization arrangement of both the back thinned base substrates 202-1 and 202-2. The electrode system 400 can be configured to be controlled from both sides (e.g., for both sides or double-sided control) (e.g., by controlling from the first side through the back thinned base substrate 202-1 and from the second side through the other back thinned base substrate 202-2). In addition, one electrode (or multiple electrodes) of the back thinned base substrate 202-1 (and / or another back thinned base substrate 202-2) can be connected to the metallized surfaces of both the back thinned base substrates 202-1 and 202-2 via metal connections 270 (and / or via electrical leads above the spacer structure 260). The metallized surfaces can then be electrically connected to a ground potential or a reference potential, for example, together.

[0169] Fig. 10B Only one metal connection (e.g., one or more conductive traces) 270 is shown by way of example. The metal connection 270 may be electrically connected to one, several, or all of the electrodes of the further electrode structure 206-2 (e.g., to apply a common electrical signal). To this end, an electrical connection may be provided along the surface of the further substrate between the further metallization 268b and the electrodes of the further electrode structure 206-2 ( Fig. 10B 206-2). Alternatively, the electrode system 400 may include more than one metal connection 270 (e.g., at the same spacer structure 260 and / or at different spacer structures 260). In addition, the electrode system 400 may include more than one metalization 268a and more than one additional metalization 268b). Multiple metal connections 270 may allow separate electrical connections to electrodes of another electrode structure 206-2. In the same manner, the electrode system may include multiple electrical lines across the spacer structure 260.

[0170] Fig.11A A schematic cross section of another example of an electrode system 400 for a three-dimensional ion trap is shown.

[0171] The electrode system 400 includes a back-thinned base substrate 202-1 (only in Fig.11A ) and another substrate 200-2 (shown schematically in Fig.11A ). The base substrate 202-1 comprises an electrode structure 206-1 and the further substrate 200-2 comprises a further electrode structure 206-2, wherein the electrode structures 206-1, 206-2 are part of an electrode arrangement 208. Fig.11A In the embodiment, the back thinned base substrate 202-1 includes an insulating substrate, but the insulating substrate is Fig.11A The further substrate 200 - 2 may be any substrate 200 - 2 described herein (eg, a dielectric including a further electrode structure or a dielectric including a further backside thinned base substrate).

[0172] Electrode arrangement 208 may be used to control the position of ions 280 between electrode structures 206-1, 206-2. As an example, another electrode structure 206-2 comprises an electrode having a three-dimensional patterned electrode structure. Alternatively, none, several or all of the electrodes of electrode structures 206-1, 206-2 may have a three-dimensional patterned electrode structure.

[0173] The backside thinned base substrate 202 - 1 (and / or the further substrate 200 - 2 ) may include a plurality of base substrate portions 202 - 1 a , 202 - 1 The base substrate portions 202 - 1 a , 202 - 1 may each include an electrode structure 206 - 1 as part of an electrode arrangement 208 .

[0174] like Fig.11A As shown in the example in FIG. 2 , during the step of connecting the backside thinned base substrate 202 - 1 and the opposing further substrate 200 - 2 , a free space 282 may be formed between adjacent spacer structures 262 a , 262 b .

[0175] The method may also include partially or completely disposing a metallized surface on the non-metal sidewall region of the free space 282 .

[0176] Fig. 11B A schematic cross section of another example of an electrode system 400 for a three-dimensional ion trap is shown, wherein non-metallic sidewall regions have metallized surfaces 284 thereon.

[0177] The electrode system 400 includes a backside thinned base substrate 202-1 and a further substrate 200-2 with spacer structures 262a, 262b arranged therebetween. The further substrate 200-2 may be implemented as any further substrate described herein (eg, including a further backside thinned base substrate 202-2).

[0178] like Fig. 11B As shown in the example in FIG. 2 , during the step of connecting the backside thinned base substrate 202 - 1 and the opposing further substrate 200 - 2 , a free space 282 may be formed between adjacent spacer structures 262 a , 262 b (eg, spacers).

[0179] The free space 282 includes non-metal sidewall regions 286 on the surfaces of the insulating material of, for example, the (base) substrates 202-1, 200-2 and on the surfaces of the spacer structures 262a, 262b (at least before arranging the metallized surfaces). Fig. 11BA metallized surface 284 is shown that is partially or completely disposed on a non-metallic sidewall region 286 of the free space 282 .

[0180] The metallized surfaces 284 can improve the shielding of the free space 282 and thus improve the control of the electric field in the free space 282. Some or all of the metallized areas 284 can be electrically connected to a ground potential or a reference potential. Some or all of the metallized areas 284 can be connected via one or several electrodes of the electrode device 208 (and optionally via Fig. 11B One or more metal connections not shown, for example Fig. 10B The metal connection 270 in is electrically connected to a ground potential or a reference potential.

[0181] like FIG. 10A to FIG. 11B As shown, the electrode system 400 may include another electrode structure, which may be part of another electrode device, in addition to the spacer structure 260. Thus, the electrode system 400 may include a plurality of electrode devices 208, each separated by a spacer structure 260.

[0182] Fig.12 A schematic top view of an example of an ion trap 500 with an electrode device is shown. The ion trap 500 can be manufactured by the method described herein (or by a method including the manufacturing method described herein). For example, the ion trap 500 can have a three-dimensional Paul ion trap arrangement. This arrangement can provide a better electric field distribution than a surface trap.

[0183] Any of the electrode devices 400 and / or electrode structures 206 described herein may be implemented in an ion trap.

[0184] The ion trap 500 includes a plurality of electrode structures 206 arranged in a row (wherein, for clarity, Fig.12 , only the top four electrode structures 206 are provided with reference numerals). Fig.12 The electrode structure 206 shown can be, for example, an electrode structure 206 of another substrate 200-2 (for example, including another back-thinned base substrate 202-2). The electrode structure 206 operates with a direct current voltage (DC). In addition, the ion trap includes three common longitudinal electrodes 288 along the row of the electrode structure 206, which operate with an alternating current voltage (RF). The ion trap 400 includes a bonding pad 290, which is, for example, electrically connected to the electrode structure 206 and the longitudinal electrodes 288.

[0185] The electrode structure 206 and the longitudinal electrode 288 generate electric fields due to the applied DC voltage and AC voltage, respectively, which allow the position of the ions in the ion trap to be controlled. Fig.12 In FIG. 2 , four ions 280 are arranged in a row to collectively form an ionic crystal.

[0186] The electrode structures 206 and the longitudinal electrodes 288 also allow for controlling the movement of the ions 280 along the longitudinal electrodes 288. Thus, an electric field can be generated by the electrode structures 206 and the longitudinal electrodes 288 to move the ions from the charging region 292 to the free space between the electrode structures 206 and / or the addressing region 294. The addressing region 294 includes optical pathways to, for example, optically manipulate the ions 280 (e.g., to excite and induce coupling between the ions 280).

[0187] The plurality of electrode structures 206 can be precisely manufactured by the methods described herein, wherein the backside thinned substrate has reduced parasitic capacitance. Thus, the coherence time of the ionic states can be extended.

[0188] Although some aspects have been described in the context of an apparatus, it should be clear that these aspects also represent a description of the corresponding method, so that the blocks or devices of the apparatus also correspond to the corresponding method steps or features of the method steps. Similarly, the aspects described in the context of the method steps also represent the description of the corresponding blocks or details or features of the corresponding apparatus. Some or all of the method steps can be performed by a hardware device (or using a hardware device), such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some or several of the most important method steps can be performed by such a device. According to certain implementation requirements, embodiments of the present invention can be implemented in hardware or software, or at least partially in hardware, or at least partially in software.

[0189] In the preceding detailed description, various features have been grouped together in examples to partially simplify the disclosure. This type of disclosure should not be interpreted as an intention that the examples claimed have more features than those explicitly recited in each claim. On the contrary, as the appended claims reflect, the subject matter can be found in fewer features than all the features of a single disclosed example. Therefore, the appended claims are hereby incorporated into the detailed description, and each claim can serve as its own separate example. Although each claim can serve as its own separate example, it should be noted that although the dependent claims in the claims refer to a specific combination with one or more other claims, other examples also include a combination of a dependent claim with the subject matter of any other dependent claim or any feature with other dependent or independent claims. Such a combination is covered unless it is stated that a specific combination is not intended to be used. It is also intended that even if the claim is not directly subordinate to an independent claim, the combination of the features of a claim with any other independent claim is covered.

[0190] Although specific embodiments have been shown and described herein, it will be clear to those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described herein without departing from the subject matter of the present application. The present application text is intended to cover all adaptations and variations of the specific embodiments described and discussed herein. Therefore, the subject matter of the present application is limited only by the wording of the claims and their equivalent embodiments.

Claims

1. A method (100) for manufacturing an electrode structure (206) for an ion trap, comprising: providing (110) a base substrate (202) comprising a patterned metallization arrangement (230) arranged in an insulating material (220) on a semiconductor layer (210), providing (120) an insulating substrate (250) including a dielectric material (252), connecting (130) a surface area (224) of the base substrate (202) disposed on the insulating material (220) to the insulating substrate (250) by a bonding process, and The base substrate (202) is back-thinned (140) by removing the semiconductor layer (210) to the insulating material (220) of the base substrate (202), wherein the electrode structure (206) of the ion trap is formed by performing a backside thinning step on the metallization arrangement (230), or by depositing a patterned surface metallization (240) on the insulating material (220) of the backside thinned base substrate (202), or Wherein, the electrode structure (206) of the ion trap is formed by the patterned metallization arrangement (230).

2. The method (100) according to claim 1, wherein: The metallization arrangement (230) is configured as a multi-layer metallization arrangement, wherein the electrode structure (206) of the ion trap is formed by performing a backside thinning step on an uppermost patterned metallization layer (232a) of the multi-layer metallization arrangement.

3. The method (100) according to claim 1 or 2, further comprising: The bonding process is performed between the insulating material (220) of the base substrate (202) and the insulating substrate (250) through an oxide / oxide bonding process.

4. The method (100) according to any one of the preceding claims, wherein: The surface area (224) of the base substrate (202) disposed on the insulating material (250) and the insulating substrate (250) each have an associated metal pad (238a, 238b, 254), the method (100) further comprising: The bonding process between the base substrate (202) and the insulating substrate (250) is performed by a metal bonding process at the associated metal pads (238a, 238b, 254).

5. The method (100) according to any one of the preceding claims, wherein: The bonding process is performed as a combination of an oxide / oxide bonding process and a metal bonding process, which is referred to as a hybrid bonding process.

6. The method (100) according to any one of the preceding claims, wherein: An exposed metallization layer (232a) of the metallization arrangement (230) or a deposited patterned surface metallization (240) on the insulating material (220) of the backside thinned base substrate (202) forms the electrode structure (206) of the surface ion trap.

7. The method (100) according to any one of the preceding claims, further comprising: A recess (228) in the form of a hole or a trench is formed in the base substrate (202), the recess (228) passing through the insulating material (220) of the metallization arrangement to the semiconductor layer (210).

8. The method (100) according to claim 7, wherein: The step of forming the recess (228) is performed by hole or trench etching.

9. The method (100) according to claim 7 or 8, further comprising: Metallization (246) is partially or completely disposed on the sidewalls (248) of the recess (228) in the insulating material (220) of the backside thinned base substrate (202).

10. The method (100) according to any one of the preceding claims, wherein: In the step of performing backside thinning on the base substrate (202), the semiconductor layer (210) of the base substrate (202) is completely removed.

11. The method (100) according to any one of the preceding claims, wherein: The metallization arrangement (230) embedded in the insulating material (220) is configured as an antenna structure for providing an electric field for the ion trap.

12. The method (100) according to any one of the preceding claims, wherein: The base substrate (202) is configured as a standard substrate from semiconductor manufacturing or as an IC substrate.

13. The method (100) according to any one of the preceding claims, wherein: The dielectric material of the insulating substrate (250) includes glass, diamond, sapphire, corundum or ceramic.

14. The method (100) according to any one of the preceding claims, wherein: The insulating material (220) of the base substrate (202) comprises a dielectric from semiconductor manufacturing, such as SiO2 or HfO2.

15. The method (100) according to any one of the preceding claims, wherein: The method for manufacturing an electrode structure (206) for an ion trap is performed by standard semiconductor manufacturing process steps.

16. The method (100) according to any one of the preceding claims, wherein: The ion trap is provided for quantum computing applications.

17. A method (300) for manufacturing an electrode arrangement (208) for a three-dimensional ion trap, comprising: performing a method (100) according to any of the preceding claims to produce an electrode structure (206-1) on a back-side thinned base substrate (202-1), providing another substrate (200-2) having another electrode structure (206-2), The back-thinned base substrate (202-1) and the other substrate (200-2) are connected by a spacer structure (260) arranged between the back-thinned base substrate (202-1) and the other substrate (200-2), so that the electrode structure (206-1) and the other electrode structure (206-2) face each other and form an electrode arrangement (208) of the three-dimensional ion trap.

18. The method (300) of claim 17, wherein: Providing the other substrate (200-2) includes performing the method (100) according to any one of claims 1 to 16 to manufacture another back-thinned base substrate (202-2), the other back-thinned base substrate (202-2) having an electrode structure forming the other electrode structure (206-2), wherein connecting the back-thinned base substrate (202-1) and the other substrate (200-2) is performed on the other back-thinned base substrate (202-2).

19. The method (300) according to claim 17 or 18, wherein: In the step of connecting the back-thinned base substrate (202-1) and the other substrate (200-2), two laterally adjacent electrode structures (206-1) of the back-thinned base substrate (202-1) and two laterally adjacent electrode structures (206-2) of the other substrate (200-2) are arranged vertically opposite to each other.

20. The method (300) of claim 19, wherein: Two pairs of vertically opposed electrode structures (206-1, 206-2) form a controllable electrode arrangement (208) of the 3D ion trap for quantum computing applications.

21. The method (300) according to any one of claims 17 to 20, further comprising: Arranging an interconnect structure (264-1) on the back-thinned base substrate (202-1), and arranging another interconnect structure (264-2) on the other substrate (200-2); as well as The backside thinned base substrate (202-1) and the further substrate (200-2) are connected by connecting opposing interconnect structures (264-1, 264-2), wherein the connected interconnect structures (264-1, 264-2) form the spacer structure.

22. The method (300) according to any one of claims 17 to 21, wherein: In the step of connecting the back-thinned base substrate (202-1) and the other substrate (200-2), the spacer structure (260) is configured as a spacer substrate and is arranged between the back-thinned base substrate (202-1) and the other substrate (200-2).

23. The method (300) according to any one of claims 17 to 22, wherein: The spacer structure (260) comprises a dielectric material such as glass, diamond, sapphire, corundum or ceramic.

24. The method (300) according to any one of claims 17 to 23, wherein: During the steps of connecting to the insulating substrates (250-1, 250-2), thinning the back side of the base substrate (202-1), and connecting to the other substrate (200-2), the base substrate (202-1) is fixed on a carrier substrate, which is made of a dielectric material such as glass, diamond, sapphire, corundum or ceramic, for example.

25. The method (300) according to any one of claims 17 to 24, further comprising: The electrode structure (206) of the back-thinned base substrate (202-1) and / or the further substrate (200-2) is patterned, for example by grey tone lithography, so as to obtain a three-dimensional patterned electrode structure (206) of the electrode arrangement (208).

26. The method (300) according to any one of claims 17 to 25, wherein: In the step of connecting the back-thinned base substrate (202-1) and the opposite another substrate (200-2), a free space (282) is formed between adjacent spacer structures (260), and the method (300) further includes: A metallized surface (284) is partially or completely arranged on the non-metallic sidewall region (286) of the free space (282).

27. The method according to any one of claims 17 to 26, further comprising: A metal connection (270) is provided that electrically connects at least a portion of the further electrode structure (206-2) of the further substrate to at least a portion of the electrode structure (206-1) of the backside thinned base substrate (202-1).

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