Chip packaging method, chip packaging structure and electronic equipment
By using a temporary bonding layer to replace solder joints in the chip packaging process, temporary bonding between the interposer and the carrier plate is realized, and vertical electrical interconnection is carried out on both sides of the interposer, the problem of low reliability during the grinding process is solved and the process is simplified And reduce signal delay and loss.
Patent Information
- Application Number
- CN202411218524.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2024-12-24
AI Technical Summary
In the existing chip packaging process, mechanical stress damage, grinding particles contamination or unevenness are prone to low product reliability when removing bonding glue and solder joints.
The first temporary bonding layer is used to realize temporary bonding between the interposer layer and the carrier plate, avoiding additional solder joints, and vertical electrical interconnection is realized on both sides of the interposer layer after removing the temporary bonding layer, simplifying the process and improving reliability.
It effectively simplifies the chip packaging process, improves product reliability, reduces signal transmission delay and loss, and avoids adverse conditions during the grinding process.
Smart Images
Figure CN119181650A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a chip packaging method, a chip packaging structure and an electronic device. Background Art
[0002] In the existing chip packaging embedding process, the interposer and the substrate are usually electrically connected through permanent bonding glue and / or solder joints, and the bonding glue and / or solder joints are removed by grinding to expose the conductive leads on the interposer, and a redistribution layer electrically connected to the conductive leads is made. However, in the above process, in the process of removing the bonding glue and / or solder joints by grinding, mechanical stress damage, grinding particle contamination, or uneven grinding may occur, and the product reliability is not high. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging method, a chip packaging structure and an electronic device.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging method, a chip packaging structure and an electronic device, wherein the chip packaging method includes:
[0005] Providing a first carrier board, and forming a first temporary bonding layer on one side of the first carrier board;
[0006] Making an interposer on a side of the first temporary bonding layer away from the first carrier, wherein the interposer includes a conductive lead penetrating the interposer, and an extending direction of the conductive lead is perpendicular to a plane where the interposer is located;
[0007] A first redistribution layer is fabricated on a side of the interposer away from the first carrier, a first conductive bump is disposed on the side of the first redistribution layer away from the first carrier, and the first redistribution layer is electrically connected to the conductive lead;
[0008] A chip layer is fabricated on a side of the first redistribution layer away from the first carrier board, the chip layer comprising at least one functional chip, the electrode side of the functional chip being arranged toward the first redistribution layer, and the electrode side of the functional chip being electrically connected to the first redistribution layer through the first conductive bump.
[0009] In a possible implementation, the interposer includes a first interconnect structure and a second interconnect structure, and before the step of manufacturing the interposer on a side of the first temporary bonding layer away from the first carrier, the method further includes a step of manufacturing the first interconnect structure, which includes:
[0010] Providing a second carrier board, and manufacturing a first conductive lead on one side of the second carrier board, wherein the extension direction of the first conductive lead is perpendicular to the plane where the second carrier board is located;
[0011] Performing a plastic encapsulation process on the second carrier board on which the first conductive leads are manufactured to form a first interconnection layer that buries the first conductive leads, and performing a grinding process on the first interconnection layer until all the first conductive leads are exposed;
[0012] The first interconnect layer after the grinding process is patterned to form a first interconnect structure, wherein the first interconnect structure includes an enclosed cavity, and the cavity runs through the first interconnect structure.
[0013] In a possible implementation manner, the step of manufacturing an interposer on a side of the first temporary bonding layer away from the first carrier includes:
[0014] placing at least one first interconnect structure on a side of the first temporary bonding layer away from the first carrier, wherein the first interconnect structure comprises a cavity penetrating the first interconnect structure and a first conductive lead;
[0015] Placing the second interconnect structure in the cavity, and performing a plastic encapsulation process on the second interconnect structure in the cavity to form a first plastic encapsulation layer, wherein the first plastic encapsulation layer is used to limit and fix the second interconnect structure in the cavity, and the second interconnect structure includes a second conductive lead that penetrates the second interconnect structure;
[0016] The formed first plastic encapsulation layer is ground until the first conductive lead and the second conductive lead are exposed to obtain the intermediate layer.
[0017] In a possible implementation manner, the step of manufacturing a chip layer on a side of the first redistribution layer away from the first carrier board includes:
[0018] Placing at least one functional chip on a side of the first redistribution layer away from the first carrier board, and welding the electrodes of the functional chip to the first conductive bumps;
[0019] Plastic encapsulation is performed on the first redistribution layer on which the functional chip is welded, and a second plastic encapsulation layer is formed on one side of the first redistribution layer where the functional chip is arranged to encapsulate the functional chip;
[0020] The second plastic packaging layer is ground until the functional chip is exposed to obtain the chip layer.
[0021] In a possible implementation, after the step of manufacturing a chip layer on a side of the first redistribution layer away from the first carrier, the method further includes the step of manufacturing a second redistribution layer, the step including:
[0022] Removing the first temporary bonding layer, and separating the interposer on which the chip layer is manufactured from the first carrier;
[0023] Providing a third carrier board, transferring the medium on which the chip layer is manufactured to the third carrier board, and making the side of the chip layer away from the first redistribution layer contact the third carrier board;
[0024] A second redistribution layer is fabricated on a side of the interposer away from the third carrier, and a second conductive bump is disposed on a side of the second redistribution layer away from the third carrier;
[0025] Ball placement is performed on a side of the second redistribution layer away from the third carrier board to obtain conductive balls electrically connected to the second redistribution layer. The conductive balls are electrically connected to the first redistribution layer through the routing in the redistribution layer and the conductive leads.
[0026] In a possible implementation, after performing ball placement processing on a side of the second redistribution layer away from the third carrier to obtain conductive balls electrically connected to the second redistribution layer, the method further includes:
[0027] Removing the third carrier board, separating the chip layer on which the conductive balls are manufactured from the third carrier board, and obtaining a packaging structure including at least one of the first interconnect structures;
[0028] When there are multiple first interconnect structures, after removing the third carrier, separating the chip layer with the conductive balls formed thereon from the third carrier, and obtaining a packaging structure including at least one first interconnect structure, the method further includes:
[0029] The packaging structure including the plurality of the first interconnect structures is cut to obtain a chip packaging structure, wherein the chip packaging structure includes one first interconnect structure and at least one second interconnect structure located in a cavity of the first interconnect structure.
[0030] In a second aspect, an embodiment of the present application further provides a chip packaging structure, wherein the chip packaging structure is manufactured according to the chip packaging method described in any one of the first aspects above, and the chip packaging structure comprises:
[0031] An intermediary layer, the intermediary layer comprising a conductive lead penetrating the intermediary layer, wherein an extension direction of the conductive lead is perpendicular to a plane where the intermediary layer is located;
[0032] A first redistribution layer, the first redistribution layer is located at one side of the interposer, a first conductive bump is provided on a side of the first redistribution layer away from the interposer, and the first redistribution layer is connected to the conductive lead;
[0033] A chip layer, wherein the chip layer is located on a side of the first redistribution layer away from the intermediate layer, the chip layer comprises at least one functional chip, the electrode side of the functional chip is arranged toward the first redistribution layer, and the electrode side of the functional chip is electrically connected to the first redistribution layer through the first conductive bump.
[0034] In a possible implementation, the intermediate layer includes a first interconnect structure, a second interconnect structure and a first plastic packaging layer;
[0035] The first interconnection structure further includes at least one enclosed cavity, the second interconnection structure is located in the cavity, and the plastic packaging layer is used to fix the second interconnection structure in the cavity;
[0036] The first interconnect structure includes a first conductive lead penetrating the first interconnect structure, the second interconnect structure includes a second conductive lead penetrating the second interconnect structure and the first plastic packaging layer, and the second interconnect structure is used to reconstruct the first interconnect structure.
[0037] In a possible implementation, the chip packaging structure further includes a second redistribution layer and conductive balls;
[0038] The second redistribution layer is located at a side of the interposer away from the first redistribution layer, and the second redistribution layer is electrically connected to the conductive lead;
[0039] A second conductive bump is disposed on a side of the second redistribution layer away from the interposer, the conductive ball is connected to the second conductive bump, and the conductive ball is electrically connected to the conductive lead through the second redistribution layer.
[0040] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a chip packaging structure manufactured according to any one of the chip packaging methods described in the first aspect.
[0041] Based on any of the above aspects, the chip packaging method, chip packaging structure and electronic device provided by the embodiment of the present application realize temporary bonding between the interposer and the first carrier through the first temporary bonding layer. Compared with the prior art of fixing the interposer and the first carrier through solder joints, no additional solder joints need to be made, which can not only effectively simplify the manufacturing process, but also improve product reliability. In addition, after the chip layer is manufactured, the interposer and the first carrier can be separated by removing the first temporary bonding layer, and vertical electrical interconnection can be achieved on two opposite sides of the interposer, effectively reducing the signal transmission path and reducing the delay and loss of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0043] Figure 1 A schematic diagram of a process flow of a chip packaging method provided in an embodiment of the present application;
[0044] Figure 2 for Figure 1 The corresponding process diagram;
[0045] Figure 3 The chip packaging method provided in the embodiment of the present application may include the following steps: Figure 1 ;
[0046] Figure 4 for Figure 3 The corresponding process diagram;
[0047] Figure 5 for Figure 1 Schematic diagram of the sub-process of step S12;
[0048] Figure 6 for Figure 5 The corresponding process diagram;
[0049] Figure 7 is a possible top view in step S121;
[0050] Figure 8 The chip packaging method provided in the embodiment of the present application may include the following steps: Figure 2 ;
[0051] Fig. 9 for Figure 8 The corresponding process diagram;
[0052] Fig.10 A schematic diagram of a chip packaging structure provided in this application Figure 1 ;
[0053] Fig.11 A schematic diagram of a chip packaging structure provided in this application Figure 2 ;
[0054] Fig.12 A schematic diagram of a chip packaging structure provided in this application Figure 3 . DETAILED DESCRIPTION
[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0056] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0057] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0058] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0059] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0060] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0061] To solve the problems in the prior art, please refer to Figure 1 , the present application embodiment provides a method for preparing a chip packaging structure. Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of a process for preparing a chip packaging structure is shown in FIG. Figure 2 For the corresponding process diagram, the following is combined Figure 1 and Figure 2 , each step of the preparation method of the chip packaging structure is described in detail.
[0062] Step S11: providing a first carrier board, and forming a first temporary bonding layer on one side of the first carrier board.
[0063] In this step, the first carrier 210 may be, but not limited to, a glass carrier, a resin carrier, etc. The first temporary bonding layer 211 may be made of a thermal stripping and / or laser stripping material, wherein the first temporary bonding layer 211 may be removed by heating and / or laser treatment. Preferably, the first carrier 210 may be a glass carrier, and the first temporary bonding layer 211 may be made of a laser stripping material.
[0064] Step S12: manufacturing an interposer on a side of the first temporary bonding layer away from the first carrier.
[0065] In this step, the intermediary layer 110 may include conductive leads running through the intermediary layer 110 , wherein the extension direction of the conductive leads may be perpendicular to the plane where the intermediary layer 110 is located, that is, the electronic devices located on both sides of the intermediary layer 110 may be vertically electrically connected through the conductive leads, thereby shortening the signal transmission path.
[0066] Step S13: forming a first redistribution layer on a side of the interposer away from the first carrier.
[0067] In this step, the first redistribution layer 120 can redistribute the circuits on the first side of the interposer 110 and change the contact positions so that it can be applied to different packaging forms. A first conductive bump 121 is disposed on the side of the first redistribution layer 120 away from the first carrier 210, and the first redistribution layer 120 can be electrically connected to the conductive lead through the first conductive bump 121.
[0068] Step S14: manufacturing a chip layer on a side of the first redistribution layer away from the first carrier.
[0069] In this step, the chip layer 130 includes at least one functional chip 131, the electrode side of the functional chip 131 is arranged toward the first redistribution layer 120, and the electrode side of the functional chip 131 is electrically connected to the first redistribution layer 120 through the first conductive bump 121. The functional chip 131 includes but is not limited to chips such as system-on-chip (SoC chip) and high-bandwidth memory chip (HBM).
[0070] In the above embodiment, the temporary bonding of the interposer 110 and the first carrier 210 is achieved through the first temporary bonding layer 211. Compared with the prior art of fixing the interposer 110 and the first carrier 210 through solder joints, no additional solder joints need to be made, which can not only effectively simplify the manufacturing process, but also avoid the undesirable conditions that may occur during the grinding and exposing of the conductive leads, thereby improving product reliability. In addition, after the chip layer 130 is manufactured, the interposer 110 and the first carrier 210 can be separated by removing the first temporary bonding layer 211, and vertical electrical interconnection can be achieved on two opposite sides of the interposer 110, effectively reducing the signal transmission path, and reducing the delay and loss of signal transmission.
[0071] Further, please refer to the figure that the interposer 110 may include a first interconnection structure 111 and a second interconnection structure 112. Before step S12, the chip packaging method provided in the present application may also include a step of manufacturing the first interconnection structure 111, which may be implemented by the following method.
[0072] S101: providing a second carrier board, and manufacturing a first conductive lead on one side of the second carrier board.
[0073] In this step, a second temporary bonding layer 221 can be firstly made on one side of the second carrier 220, and then a first conductive lead 1111 can be made on a side of the second temporary bonding layer 221 away from the second carrier 220 by electroplating, wherein an extension direction of the first conductive lead 1111 is perpendicular to the plane where the second carrier 220 is located, and the first conductive lead 1111 is used to realize vertical electrical connection between the two sides of the first interconnect structure, thereby shortening the signal transmission path.
[0074] S102: performing a plastic encapsulation process on the second carrier board on which the first conductive leads are manufactured to form a first interconnection layer that embeds the first conductive leads, and performing a grinding process on the first interconnection layer until all the first conductive leads are exposed.
[0075] After the step, the first interconnection layer can be separated from the second carrier 220 by removing the second temporary bonding layer 221 , and the seed layer of the first interconnection layer can be etched to remove residual metal, thereby reducing the risk of short circuit of the first conductive lead 1111 .
[0076] S103: performing patterning on the ground first interconnect layer to form a first interconnect structure.
[0077] In this step, the first interconnect structure 111 includes at least one enclosed cavity 1112, and the cavity 1112 runs through the first interconnect structure 111. It should be noted that the cavity 1112 is used to accommodate other interconnect structures or electronic devices, so as to reconstruct the electrical connection line of the first interconnect structure 111 through other interconnect structures or electronic devices. Among them, the cavity 1112 may run through the first interconnect structure 111, or may not run through the first interconnect structure 111. When the cavity 1112 does not run through the first interconnect structure 111, the cavity 1112 can be used to accommodate an electronic device with only single-sided pins, and the pins of the electronic device are oriented toward the opening direction of the cavity 1112.
[0078] In this embodiment, by making the first conductive lead 1111 penetrating the first interconnect structure 111, vertical electrical connection can be achieved on both sides of the first interconnect structure 111, thereby shortening the signal transmission path. In addition, the cavity 1112 can be used to accommodate other interconnect structures or electronic devices, and the first interconnect structure 111 can be reconstructed by other interconnect structures or electronic devices, and the electrical connection lines can be redistributed to make it suitable for different packaging forms.
[0079] Please refer to Figure 5 and Figure 6 , step S12 can be implemented by the following method.
[0080] Step S121: placing at least one first interconnect structure on a side of the first temporary bonding layer away from the first carrier.
[0081] In this step, at least one first interconnect structure 111 may be placed on the side of the first temporary bonding layer 211 away from the first carrier 210. When there are multiple first interconnect structures 111, the placement method of the first interconnect structures 111 on the first carrier 210 may refer to Figure 7 The first interconnect structure 111 includes a first conductive wire 1111 and a cavity 1112 penetrating the first interconnect structure 111 .
[0082] Step S122: placing the second interconnect structure in the cavity, and performing a plastic packaging process on the second interconnect structure in the cavity to form a first plastic packaging layer.
[0083] In this step, the first plastic layer 113 is used to limit and fix the second interconnect structure 112 in the cavity. The second interconnect structure 112 includes a second conductive lead 1121 passing through the second interconnect structure 112. Preferably, the extension direction of the second conductive lead 1121 is perpendicular to the plane where the second interconnect structure 112 is located.
[0084] It should be noted that, in a direction perpendicular to the first carrier 210 , the height of the second conductive lead 1121 is greater than the height of the second interconnect structure 112 . Preferably, the height of the second conductive lead 1121 is equal to that of the first conductive lead 1111 .
[0085] Step S123: grinding the formed first plastic packaging layer until the first conductive lead and the second conductive lead are exposed to obtain an intermediate layer.
[0086] In this embodiment, the second interconnect structure 112 can be placed in the cavity 1112 and fixed by the first plastic layer 113, so that the first interconnect structure 111 can be reconstructed by the second interconnect structure 112 to optimize the electrical connection line. In addition, the vertical first conductive lead 1111 and the second conductive lead 1121 can effectively shorten the transmission path of the electrical signal and improve the interconnection density.
[0087] In some possible implementations, step S14 may be implemented by the following method.
[0088] First, at least one functional chip 131 may be placed on a side of the first redistribution layer 120 away from the first carrier 210, and the electrodes of the functional chip 131 may be welded to the first conductive bumps 121. Next, the first redistribution layer 120 with the functional chip 131 welded thereto may be plastic-sealed, a second plastic-sealing layer wrapping the functional chip 131 may be formed on the side of the first redistribution layer 120 where the functional chip 131 is arranged, and the second plastic-sealing layer may be ground until the functional chip is exposed, thereby obtaining the chip layer 130.
[0089] For further information, please refer to Figure 8 and Fig. 9 After step S14, the chip packaging method provided in the embodiment of the present application may further include a step of manufacturing a second redistribution layer 140, which may be implemented by the following method.
[0090] Step S151: removing the first temporary bonding layer, and separating the interposer on which the chip layer is fabricated from the first carrier.
[0091] In this step, the first temporary bonding layer 211 may be removed by laser treatment and / or heat treatment, and the interposer 110 on which the chip layer 130 is manufactured may be separated from the first carrier board 210 .
[0092] Step S152: providing a third carrier board, and transferring the interposer layer with the chip layer fabricated thereon to the third carrier board.
[0093] In this step, a third temporary bonding layer 231 can be first produced on the third carrier 230, and the intermediate layer 110 with the chip layer 130 produced can be transferred to the side of the third temporary bonding layer 231 away from the third carrier 230, wherein the side of the chip layer 130 away from the first redistribution layer 120 is in contact with the third carrier 230.
[0094] Step S153: fabricating a second redistribution layer on a side of the interposer away from the third carrier board.
[0095] In this step, a second conductive bump 141 is disposed on a side of the second redistribution layer 140 away from the third carrier 230 .
[0096] Step S154: performing ball placement processing on the side of the second redistribution layer 140 away from the third carrier 230 to obtain a conductive ball 150 electrically connected to the second redistribution layer 140 , and the conductive ball 150 is electrically connected to the first redistribution layer 120 through the conductive leads in the second redistribution layer 140 and the intermediate layer 110 .
[0097] In this step, the conductive balls 150 can play a role of adhesion and diffusion when the chip packaging structure is welded with other electronic devices.
[0098] In addition, after this step, the third carrier 230 can be removed by laser treatment and / or heat treatment, and the chip layer 130 with the conductive balls 150 formed thereon can be separated from the third carrier 230 to obtain a packaging structure including at least one first interconnection structure 111. When there are multiple first interconnection structures 111, the packaging structure including multiple first interconnection structures 111 can be cut to obtain a chip packaging structure including one first interconnection structure 111. The chip packaging structure can include one first interconnection structure 111 and at least one second interconnection structure 112, and the second interconnection structure 112 is located in the cavity 1112 of the first interconnection structure 111.
[0099] Based on the same inventive concept, an embodiment of the present application also provides a chip packaging structure 10, which can be manufactured according to any chip packaging method in the above embodiments. Specifically, the chip packaging structure 10 may include an intermediate layer 110, a first redistribution layer 120 and a chip layer 130.
[0100] The first redistribution layer 120 may be located on one side of the intermediary layer 110, a first conductive bump is provided on the side of the first redistribution layer 120 away from the intermediary layer 110, the intermediary layer 110 may include a conductive lead passing through the intermediary layer, the first redistribution layer 120 may be connected to the conductive lead through the first conductive bump, and an extension direction of the conductive lead is perpendicular to the plane where the intermediary layer 110 is located.
[0101] The chip layer 130 may be located on a side of the first redistribution layer 120 away from the interposer 110, and the chip layer 130 includes at least one functional chip 131, the electrode side of the functional chip 131 is arranged toward the first redistribution layer 120, and the electrode side of the functional chip 131 is electrically connected to the first redistribution layer 120 through a first conductive bump. The functional chip 131 includes, but is not limited to, chips such as system-on-chip (SoC chip) and high-bandwidth memory chip (HBM).
[0102] In this embodiment, the interposer 110 includes conductive leads that penetrate the interposer 110, and the extension direction of the conductive leads is perpendicular to the plane where the interposer 110 is located, which can effectively reduce the signal transmission path, reduce the delay and loss of signal transmission, and improve the interconnection density. In addition, during the manufacturing process of the chip packaging structure 10, no additional solder joints need to be made, which simplifies the manufacturing process and reduces the product reliability risk.
[0103] For further information, please refer to Fig.11 The interposer 110 may include a first interconnect structure 111 , a second interconnect structure 112 , and a first molding layer 113 .
[0104] The first interconnect structure 111 also includes at least one enclosed cavity, the second interconnect structure 112 is located in the cavity, and the first plastic layer 113 is used to fix the second interconnect structure 112 in the cavity. The first interconnect structure 111 includes a first conductive lead 1111 that runs through the first interconnect structure 111, and the second interconnect structure 112 includes a second conductive lead 1121 that runs through the second interconnect structure 112 and the first plastic layer 113. The second interconnect structure 112 is used to reconstruct the first interconnect structure 111.
[0105] Furthermore, the chip package structure 10 further includes a second redistribution layer 140 and conductive balls 150. The second redistribution layer 140 is located on a side of the interposer 110 away from the first redistribution layer 120, and the second redistribution layer 140 is electrically connected to the conductive leads.
[0106] A second conductive bump is provided on the side of the second redistribution layer 140 away from the intermediate layer 110, and the conductive ball is connected to the second conductive bump. The conductive ball 150 is electrically connected to the conductive lead through the second redistribution layer 140, wherein the conductive ball 150 can play a role of adhesion and diffusion when the chip packaging structure 10 is welded with other electronic devices.
[0107] In addition, an embodiment of the present application also provides an electronic device, including a chip packaging structure manufactured according to any one of the chip packaging methods in the above embodiments.
[0108] In summary, the embodiments of the present application provide a chip packaging method, a chip packaging structure, and an electronic device. The chip packaging method described above realizes temporary bonding between the interposer and the first carrier through a first temporary bonding layer. Compared with the prior art of fixing the interposer and the first carrier through solder joints, there is no need to make additional solder joints, which can not only effectively simplify the manufacturing process, but also improve product reliability. In addition, after the chip layer is manufactured, the interposer and the first carrier can be separated by removing the first temporary bonding layer, and vertical electrical interconnection can be realized on two opposite sides of the interposer, effectively reducing the signal transmission path, and reducing the delay and loss of signal transmission.
[0109] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging method, characterized in that: The method comprises: Providing a first carrier board, and forming a first temporary bonding layer on one side of the first carrier board; Making an interposer on a side of the first temporary bonding layer away from the first carrier, wherein the interposer includes a conductive lead penetrating the interposer, and an extending direction of the conductive lead is perpendicular to a plane where the interposer is located; A first redistribution layer is fabricated on a side of the interposer away from the first carrier, a first conductive bump is disposed on the side of the first redistribution layer away from the first carrier, and the first redistribution layer is electrically connected to the conductive lead; A chip layer is fabricated on a side of the first redistribution layer away from the first carrier board, the chip layer comprising at least one functional chip, the electrode side of the functional chip being arranged toward the first redistribution layer, and the electrode side of the functional chip being electrically connected to the first redistribution layer through the first conductive bump.
2. The chip packaging method according to claim 1, characterized in that: The interposer includes a first interconnect structure and a second interconnect structure. Before the step of manufacturing the interposer on a side of the first temporary bonding layer away from the first carrier, the method further includes a step of manufacturing the first interconnect structure, which step includes: Providing a second carrier board, and manufacturing a first conductive lead on one side of the second carrier board, wherein the extension direction of the first conductive lead is perpendicular to the plane where the second carrier board is located; Performing a plastic encapsulation process on the second carrier board on which the first conductive leads are manufactured to form a first interconnection layer that buries the first conductive leads, and performing a grinding process on the first interconnection layer until all the first conductive leads are exposed; The first interconnect layer after the grinding process is patterned to form a first interconnect structure, wherein the first interconnect structure includes an enclosed cavity, and the cavity runs through the first interconnect structure.
3. The chip packaging method according to claim 2, characterized in that: The step of manufacturing an interposer on a side of the first temporary bonding layer away from the first carrier board comprises: placing at least one first interconnect structure on a side of the first temporary bonding layer away from the first carrier, wherein the first interconnect structure comprises a cavity penetrating the first interconnect structure and a first conductive lead; Placing the second interconnect structure in the cavity, and performing a plastic encapsulation process on the second interconnect structure in the cavity to form a first plastic encapsulation layer, wherein the first plastic encapsulation layer is used to limit and fix the second interconnect structure in the cavity, and the second interconnect structure includes a second conductive lead that penetrates the second interconnect structure; The formed first plastic encapsulation layer is ground until the first conductive lead and the second conductive lead are exposed to obtain the intermediate layer.
4. The chip packaging method according to claim 3, characterized in that: The step of manufacturing a chip layer on a side of the first redistribution layer away from the first carrier board comprises: Placing at least one functional chip on a side of the first redistribution layer away from the first carrier board, and welding the electrodes of the functional chip to the first conductive bumps; Plastic encapsulation is performed on the first redistribution layer on which the functional chip is welded, and a second plastic encapsulation layer is formed on one side of the first redistribution layer where the functional chip is arranged to encapsulate the functional chip; The second plastic packaging layer is ground until the functional chip is exposed to obtain the chip layer.
5. The chip packaging method according to claim 3, characterized in that: After the step of manufacturing a chip layer on a side of the first redistribution layer away from the first carrier board, the method further includes the step of manufacturing a second redistribution layer, which step includes: Removing the first temporary bonding layer, and separating the interposer on which the chip layer is manufactured from the first carrier; Providing a third carrier board, transferring the medium on which the chip layer is manufactured to the third carrier board, and making the side of the chip layer away from the first redistribution layer contact the third carrier board; A second redistribution layer is fabricated on a side of the interposer away from the third carrier, and a second conductive bump is disposed on a side of the second redistribution layer away from the third carrier; Ball placement is performed on a side of the second redistribution layer away from the third carrier board to obtain conductive balls electrically connected to the second redistribution layer. The conductive balls are electrically connected to the first redistribution layer through the routing in the redistribution layer and the conductive leads.
6. The chip packaging method according to claim 5, characterized in that: After performing ball placement processing on a side of the second redistribution layer away from the third carrier board to obtain conductive balls electrically connected to the second redistribution layer, the method further includes: Removing the third carrier board, separating the chip layer on which the conductive balls are manufactured from the third carrier board, and obtaining a packaging structure including at least one of the first interconnect structures; When there are multiple first interconnect structures, after removing the third carrier, separating the chip layer with the conductive balls formed thereon from the third carrier, and obtaining a packaging structure including at least one first interconnect structure, the method further includes: The packaging structure including the plurality of the first interconnect structures is cut to obtain a chip packaging structure, wherein the chip packaging structure includes one first interconnect structure and at least one second interconnect structure located in a cavity of the first interconnect structure.
7. A chip packaging structure, characterized in that: The chip packaging structure is manufactured according to the chip packaging method according to any one of claims 1 to 6, and the chip packaging structure comprises: An intermediary layer, the intermediary layer comprising a conductive lead penetrating the intermediary layer, wherein an extension direction of the conductive lead is perpendicular to a plane where the intermediary layer is located; A first redistribution layer, the first redistribution layer is located at one side of the interposer, a first conductive bump is provided on a side of the first redistribution layer away from the interposer, and the first redistribution layer is connected to the conductive lead; A chip layer, wherein the chip layer is located on a side of the first redistribution layer away from the intermediate layer, the chip layer comprises at least one functional chip, the electrode side of the functional chip is arranged toward the first redistribution layer, and the electrode side of the functional chip is electrically connected to the first redistribution layer through the first conductive bump.
8. The chip packaging structure according to claim 7, characterized in that: The intermediate layer includes a first interconnect structure, a second interconnect structure and a first plastic packaging layer; The first interconnection structure further includes at least one enclosed cavity, the second interconnection structure is located in the cavity, and the plastic packaging layer is used to fix the second interconnection structure in the cavity; The first interconnect structure includes a first conductive lead penetrating the first interconnect structure, the second interconnect structure includes a second conductive lead penetrating the second interconnect structure and the first plastic packaging layer, and the second interconnect structure is used to reconstruct the first interconnect structure.
9. The chip packaging structure according to claim 7, characterized in that: The chip packaging structure also includes a second redistribution layer and conductive balls; The second redistribution layer is located at a side of the interposer away from the first redistribution layer, and the second redistribution layer is electrically connected to the conductive lead; A second conductive bump is disposed on a side of the second redistribution layer away from the interposer, the conductive ball is connected to the second conductive bump, and the conductive ball is electrically connected to the conductive lead through the second redistribution layer.
10. An electronic device, characterized in that: A chip packaging structure comprising a chip packaging method manufactured according to any one of claims 1-6.