Method of fabricating a semiconductor structure

Abstract

The present disclosure relates to a method for manufacturing a semiconductor structure, comprising: providing a substrate, forming a first electrode on the substrate; forming a gate on the first electrode, a top surface of the gate being covered by an isolation layer; forming a channel hole penetrating through the isolation layer and the gate, the channel hole exposing a part of the top surface of the first electrode; forming a gate dielectric layer covering the sidewall of the channel hole; forming a channel layer covering the gate dielectric layer and the top surface of the first electrode exposed by the channel hole; filling a heat-conducting material into the channel hole to form a heat-conducting layer; after heat annealing treatment of the channel layer and the heat-conducting layer, removing the heat-conducting layer; forming an insulating layer in the channel hole, the insulating layer covering a part of the inner sidewall of the channel layer; forming a second electrode on the insulating layer, the second electrode being in contact with the top of the channel layer. The resistance of the channel layer is reduced, the conductivity of the channel layer is improved, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] With the continuous innovation and development of semiconductor technology, in order to increase the integration density of integrated circuits, the feature size of semiconductor components is constantly decreasing.

[0003] The reduction in feature size of semiconductor devices greatly increases the difficulty of their fabrication, and there are still some technical problems that need to be further improved in fabricating semiconductor devices with smaller nodes. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for fabricating semiconductor structures to address the problems in the existing technology.

[0005] In a first aspect, this disclosure provides a method for fabricating a semiconductor structure, including:

[0006] A substrate is provided, and a first electrode is formed on the substrate;

[0007] A gate is formed on the first electrode, and the top surface of the gate is covered by an isolation layer;

[0008] A channel hole is formed that penetrates the isolation layer and the gate, and the channel hole exposes a portion of the top surface of the first electrode;

[0009] A gate dielectric layer is formed, the gate dielectric layer covering the sidewall of the channel hole;

[0010] A channel layer is formed, which covers the gate dielectric layer and the top surface of the first electrode exposed by the channel hole;

[0011] A thermally conductive layer is formed by filling the channel holes with thermally conductive material.

[0012] After performing a heat annealing treatment on both the channel layer and the thermally conductive layer, the thermally conductive layer is removed.

[0013] An insulating layer is formed in the channel hole, the insulating layer covering a portion of the inner sidewall of the channel layer;

[0014] A second electrode is formed on the insulating layer, and the second electrode is in contact with the top of the channel layer.

[0015] In one embodiment, after the channel layer and the thermally conductive layer are subjected to thermal annealing, the channel layer is formed as a polycrystalline semiconductor layer that conformally covers the sidewalls and bottom surface of the channel hole.

[0016] In one embodiment, the thermally conductive layer includes a barrier layer and a metal layer formed sequentially, wherein the barrier layer is disposed between the metal layer and the channel layer.

[0017] In one embodiment, forming an insulating layer in the channel hole includes:

[0018] An insulating material is deposited to fill the trench holes, the insulating material covering the trench layer and at least partially filling the trench holes;

[0019] The insulating material is then etched back into the channel hole.

[0020] In one embodiment, the top surface of the insulating layer is higher than the top surface of the gate and lower than the top surface of the channel via, and the insulating layer exposes a portion of the inner sidewall of the channel layer.

[0021] In one embodiment, forming the second electrode includes:

[0022] A contact layer is formed, which covers the exposed inner wall of the channel layer and fills the unfilled areas of the channel holes;

[0023] A metal conductive layer is formed, which covers the top surface of the contact layer, the top surface of the channel layer, and the top surface of the isolation layer.

[0024] In one embodiment, forming the metal conductive layer includes: sequentially forming a metal barrier layer and a metal conductive layer, wherein the metal barrier layer is disposed between the metal conductive layer and the contact layer.

[0025] In one embodiment, the contact layer further covers the top surface of the isolation layer, and the contact layer is disposed between the metal conductive layer and the isolation layer.

[0026] In one embodiment, forming the second electrode includes:

[0027] A metal barrier layer is formed, which covers the inner wall of the top of the trench layer, the top surface of the trench layer, and the top surface of the isolation layer;

[0028] A metal conductive layer is formed, which covers the metal barrier layer and fills the unfilled areas of the channel holes.

[0029] In one embodiment, prior to forming the second electrode on the insulating layer, the method further includes:

[0030] The channel layer on the top surface of the isolation layer is etched away to expose the top surface of the isolation layer and the channel layer in each of the channel holes is disconnected.

[0031] The semiconductor structure fabrication method disclosed herein involves depositing a channel layer, followed by forming a thermally conductive layer to cover the channel layer. The thermally conductive layer and the channel layer are then thermally annealed together. Utilizing the excellent thermal conductivity of the thermally conductive layer, heat is conducted during the thermal annealing process to heat the channel layer, ensuring uniform heating of the channel layer. This results in the formation of a conformal polycrystalline semiconductor layer covering the channel holes, reducing the resistance of the channel layer, improving its conductivity, and ultimately enhancing the electrical performance of the semiconductor structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment;

[0034] Figure 2 This is a schematic diagram of the structure after the first electrode, gate, and isolation layer are formed on the substrate, as provided in one embodiment;

[0035] Figure 3 This is a schematic diagram of the structure after the initial channel hole is formed, as provided in one embodiment;

[0036] Figure 4 This is a schematic diagram of the structure after the channel holes and the gate dielectric layer are formed in one embodiment;

[0037] Figure 5 This is a schematic diagram of the structure after the channel layer is formed in one embodiment;

[0038] Figure 6 This is a schematic diagram of the structure after the thermally conductive layer and the channel layer have undergone joint heat treatment in one embodiment;

[0039] Figure 7 This is a schematic diagram of the structure after the thermally conductive layer and the channel layer have undergone joint heat treatment in another embodiment;

[0040] Figure 8 This is a schematic diagram of the structure after the thermally conductive layer has been removed and an insulating layer has been formed inside the channel hole in one embodiment;

[0041] Figure 9 This is a schematic diagram of the structure after the contact layer is formed in one embodiment;

[0042] Figure 10 This is a schematic diagram of a semiconductor structure formed in one embodiment;

[0043] Figure 11 The semiconductor structure formed in one embodiment is along Figure 10 Cross-sectional view of line AA;

[0044] Figure 12 This is a schematic diagram of a semiconductor structure formed in another embodiment;

[0045] Figure 13 The semiconductor structure formed in another embodiment along Figure 12 Cross-sectional view of the BB line.

[0046] Explanation of reference numerals in the attached figures:

[0047] 11. Substrate; 21. First electrode; 211. First conductive layer; 212. First contact layer; 2111. First barrier metal layer; 2112. First conductive metal layer; 2113. Second barrier metal layer; 23. Gate; 24. Isolation layer; 25. Gate dielectric layer; 26. Channel layer; 27. Insulating layer; 28. Isolation sidewall; 29. ​​Second electrode; 291. Contact layer; 292. Metal conductive layer; 2921. Metal barrier layer; 2922. Metal conductive layer; 293. Nitride layer; 30. Thermally conductive layer; 31. Barrier layer; 32. Metal layer; 40. Channel via; 40a. Initial channel via; 41. First dielectric layer; 42. Second dielectric layer;

[0048] D1, first direction; D2, second direction. Detailed Implementation

[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0051] As described in the background section, the reduction in feature size of semiconductor devices greatly increases the difficulty of their fabrication, and there are still some technical problems that need to be further improved in fabricating semiconductor devices with smaller nodes.

[0052] For example, in the process of manufacturing semiconductor devices, it is necessary to form a uniform polycrystalline semiconductor layer. However, it is difficult to guarantee the crystal orientation uniformity and distribution uniformity of the polycrystalline semiconductor layer. In particular, when forming a polycrystalline semiconductor layer on the surface of the previous device, the continuity of the polycrystalline semiconductor layer is difficult to guarantee due to the influence of the morphology of the previous device.

[0053] According to an exemplary embodiment, this exemplary embodiment provides a method for fabricating a semiconductor structure. Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown, such as... Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0054] Step S10: Provide a substrate 11 and form a first electrode 21 on the substrate 11;

[0055] Step S20: A gate 23 is formed on the first electrode 21, and the top surface of the gate 23 is covered by an isolation layer 24;

[0056] Step S30: Form a channel hole 40 that penetrates the isolation layer 24 and the gate 23, and expose a portion of the top surface of the first electrode 21 through the channel hole 40;

[0057] Step S40: Form a gate dielectric layer 25, which covers the sidewall of the channel hole 40;

[0058] Step S50: Form a channel layer 26, which covers the gate dielectric layer 25 and the top surface of the first electrode 21 exposed by the channel hole 40;

[0059] Step S60: Fill the channel hole 40 with thermally conductive material to form a thermally conductive layer 30;

[0060] Step S70: After performing heat annealing on both the channel layer 26 and the thermally conductive layer 30, remove the thermally conductive layer 30;

[0061] Step S80: An insulating layer 27 is formed in the channel hole 40, the insulating layer 27 covering part of the inner sidewall of the channel layer 26;

[0062] Step S90: A second electrode 29 is formed on the insulating layer 27, and the second electrode 29 is in contact with the top of the channel layer 26.

[0063] In the semiconductor structure fabrication method of this embodiment, after depositing and forming the channel layer 26, a thermally conductive layer 30 is formed to cover the channel layer 26. The thermally conductive layer 30 and the channel layer 26 are thermally annealed together. Utilizing the good thermal conductivity of the thermally conductive layer 30, the thermally conductive layer 30 conducts heat to heat the channel layer 26 during the thermal annealing process, so that the channel layer 26 is heated uniformly. The channel layer 26 forms a conformal polycrystalline semiconductor layer covering the channel hole 40, which reduces the resistance of the channel layer 26, improves the conductivity of the channel layer 26, and is beneficial to improving the electrical performance of the semiconductor structure.

[0064] Figures 2-13 This is a cross-sectional schematic diagram illustrating the corresponding steps of the semiconductor structure fabrication method provided in this embodiment. The following is in conjunction with… Figures 2-13 The method for fabricating the semiconductor structure provided in this embodiment will be described in detail.

[0065] In step S10, refer to Figure 2 The substrate 11 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited to these.

[0066] A first electrode 21 is formed on a substrate 11. The first electrode 21 can be a source or a drain. A first conductive layer 211 can be formed on the substrate 11 using physical vapor deposition (PVD). A first contact layer 212 is then deposited on the first conductive layer 211 using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The first contact layer 212 and the first conductive layer 211 are then patterned to form the first electrode 21. The first electrode 21 extends along a first direction D1 and is spaced along a second direction D2, where the first direction D1 is different from the second direction D2.

[0067] In one example, refer to Figure 2 The first conductive layer 211 includes a first barrier metal layer 2111, a first conductive metal layer 2112, and a second barrier metal layer 2113 stacked sequentially.

[0068] For example, the materials of the first barrier metal layer 2111 and the second barrier metal layer 2113 may include titanium nitride, the material of the first conductive metal layer 2112 may include tungsten, and the material of the first contact layer 212 may include doped polycrystalline silicon.

[0069] In this embodiment, after the first electrode 21 is formed, a first dielectric layer 41 can be deposited by CVD. The first dielectric layer 41 covers the first electrode 21 and fills the area between the first electrodes 21. After the first dielectric layer 41 is formed, the top surface of the first dielectric layer 41 is ground into a plane to facilitate the execution of subsequent processes.

[0070] For example, the material of the first dielectric layer 41 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0071] In step S20, refer to Figure 2 A gate conductive layer can be formed by PVD deposition, which covers the first dielectric layer 41. The gate conductive layer is etched to form a gate 23, which extends along the second direction D2 and is spaced apart along the first direction D1.

[0072] For example, gate 23 may include a gate barrier layer and a gate metal layer stacked sequentially from bottom to top, or gate 23 may also include a gate semiconductor layer and / or a gate metal silicide layer, wherein the gate semiconductor layer may be located on the gate metal layer, and the gate metal silicide layer may be located on the gate semiconductor layer or the gate metal layer.

[0073] Then, a second dielectric layer 42 can be formed by CVD deposition, which covers the sidewalls of the gate 23 and fills the gate 23.

[0074] For example, the material of the second dielectric layer 42 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0075] Next, an isolation layer 24 can be formed by CVD deposition, which covers the top surface of the gate 23 and the top surface of the second dielectric layer 42.

[0076] For example, the material of the isolation layer 24 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0077] In steps S30 and S40, firstly, refer to Figure 3 The isolation layer 24 and the gate 23 are patterned to form an initial channel hole 40a that penetrates the isolation layer 24 and the gate 23. The bottom wall of the initial channel hole 40a exposes a portion of the top surface of the underlying first dielectric layer 41, and the sidewall of the initial channel hole 40a exposes a portion of the gate 23.

[0078] Then, refer to Figure 4 A gate dielectric layer 25 can be formed on the surface of the gate 23 exposed by the initial channel via 40a using ALD deposition or thermal oxidation processes. The material of the gate dielectric layer 25 includes oxides, such as silicon oxide or aluminum oxide.

[0079] Next, continue to refer to Figure 4 The gate dielectric layer 25 and the first dielectric layer 41 below the bottom wall of the initial channel hole 40a are etched away until a portion of the top surface of the first electrode 21 is exposed, forming the channel hole 40.

[0080] For example, an anisotropic etching process is used to etch the gate dielectric layer 25 and the first dielectric layer 41 on the bottom wall of the initial channel hole 40a. The etching rate along the direction perpendicular to the substrate 11 is much greater than the etching rate along the direction parallel to the substrate 11.

[0081] In step S50, refer to Figure 5 A channel layer 26 is formed by CVD deposition, covering the bottom wall and sidewalls of the channel via 40 and the top surface of the isolation layer 24. The material of the channel layer 26 includes an amorphous semiconductor material. For example, the material of the channel layer 26 includes amorphous silicon.

[0082] In step S60, refer to Figure 6 A thermally conductive layer 30 is formed by PVD deposition of thermally conductive material. The thermally conductive layer 30 covers the channel layer 26 and fills the unfilled areas of the channel holes 40.

[0083] In one example, the thermally conductive layer 30 fills the unfilled area of ​​the channel hole 40; in another example, the thermally conductive layer 30 fills part of the unfilled area of ​​the channel hole 40.

[0084] In this embodiment, the thermally conductive layer 30 fills the unfilled area of ​​the channel hole 40 to increase the volume of the conductive layer 30, which is beneficial to increase the thermal conductivity uniformity of the thermally conductive layer 30, so that the conductive layer 30 conducts heat uniformly to heat the channel layer 26 during the heat annealing process.

[0085] The thermal conductivity of the heat-conducting layer 30 is greater than that of the channel layer 26, so that heat can be conducted to the channel layer 26 through the heat-conducting layer 30 to heat the channel layer 26.

[0086] Depending on the actual process requirements, the material of the heat-conducting layer 30 may include oxides or nitrides of cobalt, copper, tungsten, aluminum, or the above metals; the material of the heat-conducting layer 30 may also include carbon materials with good thermal conductivity, such as silicon carbide or amorphous carbon.

[0087] In one embodiment, reference Figure 7 As shown, the thermally conductive layer 30 includes a barrier layer 31 and a metal layer 32 formed sequentially, with the barrier layer 31 disposed between the metal layer 32 and the channel layer 26. The barrier layer 31 is used to prevent the metal material of the metal layer 32 from diffusing into other devices or film layers, avoiding short circuits caused by metal material diffusion and improving the reliability of the semiconductor structure.

[0088] The material of the barrier layer 31 includes at least one of cobalt oxide, cobalt nitride, copper oxide, copper nitride, tungsten oxide, tungsten nitride, titanium nitride, titanium oxide, aluminum oxide, or aluminum nitride; the material of the metal layer 32 includes at least one of cobalt, copper, tungsten, or aluminum.

[0089] In one example, the barrier layer 31 is made of cobalt oxide and the metal layer 32 is made of cobalt; in another example, the barrier layer 31 is made of titanium nitride and the metal layer 32 is made of tungsten.

[0090] In step S70, refer to Figure 6 or Figure 7 The channel layer 26 and the thermally conductive layer 30 are heat-annealed. For example, furnace tube annealing or rapid heat annealing can be used.

[0091] During the thermal annealing process, the thermal conductive layer 30 has high thermal conductivity and rapid temperature rise. The temperature of the thermal conductive layer 30 rises rapidly and the overall temperature of the thermal conductive layer 30 is uniform. The thermal conductive layer 30 conducts heat to the channel layer 26, so that the channel layer 26 is heated uniformly. The crystal orientation of the channel layer 26 is rearranged to form a polycrystalline semiconductor layer that conformally covers the channel hole 40.

[0092] In one embodiment, after the channel layer 26 and the thermally conductive layer 30 are subjected to thermal annealing, the channel layer 26 is formed as a polycrystalline silicon layer that conformally covers the sidewalls and bottom surface of the channel hole 40.

[0093] It is understandable that in the semiconductor field, ALD (Atomic Layer Deposition) processes require atomic layer epitaxy to deposit conformal covering films, but ALD processes cannot deposit polycrystalline semiconductor layers. Polycrystalline semiconductor layers require CVD deposition followed by annealing. Since the polycrystalline semiconductor layer covers the preceding device, its morphology influences the heat distribution during thermal annealing, potentially affecting the continuity of the polycrystalline semiconductor layer. In this embodiment, thermal annealing is performed jointly by forming a thermally conductive layer 30 and a channel layer 26. The thermally conductive layer 30 has high thermal conductivity and rapid temperature rise. The increased temperature of the thermally conductive layer 30 uniformly heats the channel layer 26, causing the channel layer 26 to form a conformal polycrystalline silicon layer covering the channel via 40. This improves the conductivity of the channel layer 26 and is beneficial for improving the electrical performance of the semiconductor structure.

[0094] After thermal annealing, the thermally conductive layer 30 is etched away to expose the channel layer 26. Alternatively, a wet process can be used to remove the thermally conductive layer 30, where the etching solution has a high etching ratio to the material of the channel layer 26.

[0095] In one embodiment, step S80, forming an insulating layer 27 in the channel via 40, includes:

[0096] Step S81: Deposit insulating material to fill the channel holes 40, the insulating material covers the channel layer 26 and at least fills part of the channel holes 40;

[0097] Reference Figure 8 Insulating materials can be deposited using CVD or ALD, covering the trench layer 26 and filling the unfilled areas of the trench orifice 40.

[0098] Step S82: Re-etch the insulating material into the channel hole 40.

[0099] Reference Figure 8 The insulating material is etched back to a point where its top surface is lower than the top surface of the channel hole 40, and the insulating material that is etched and retained in the channel hole 40 forms an insulating layer 27.

[0100] For example, the material of insulating layer 27 may include a low-k dielectric material or silicon oxide. The low-k dielectric material may be a material having a lower dielectric constant than silicon oxide. The low-k dielectric material may include one or more of the following: flowable oxide (FOX), TOSZ, undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide.

[0101] In one embodiment, reference Figure 8 The top surface of the insulating layer 27 is higher than the top surface of the gate 23 and lower than the top surface of the channel hole 70, and the insulating layer 27 exposes part of the inner sidewall of the channel layer 26.

[0102] In one embodiment, before forming the second electrode 29 on the insulating layer 27 in step S90, the method further includes: step S81: etching away the channel layer 26 on the top surface of the isolation layer 24 to expose the top surface of the isolation layer 24 and disconnecting the channel layer 26 in each channel hole 40.

[0103] Reference Figure 9 After the insulating layer 27 is formed, the channel layer 26 located on the top surface of the isolation layer 24 is etched away to disconnect the channel layer 26 in each channel hole 40.

[0104] For example, the trench layer 26 on the top surface of the isolation layer 24 can be removed by dry etching.

[0105] In step S90, refer to Figures 9-13 A second electrode 29 is formed, which contacts the top of the channel layer 26. The second electrode 29 extends along a first direction D1 and is spaced apart along a second direction D2. The second electrode 29 is either a drain or a source. Specifically, one of the first electrode 21 and the second electrode 29 is the source, and the other is the drain.

[0106] In one embodiment, step S90, forming the second electrode 29, includes the following steps:

[0107] Step S91a: Form contact layer 291, which covers the exposed inner wall of channel layer 26 and fills the unfilled area of ​​channel hole 40;

[0108] Reference Figure 9 A contact layer 291 can be formed by CVD deposition, which covers the exposed inner wall of the channel layer 26 and fills the unfilled area of ​​the channel hole 40.

[0109] The material of contact layer 291 may include a semiconductor material. For example, the material of contact layer 291 may include polycrystalline silicon.

[0110] Step S92a: Form a metal conductive layer 292, which covers the top surface of the contact layer 291, the top surface of the channel layer 26, and the top surface of the isolation layer 24.

[0111] Reference Figure 10 , Figure 11 A metal conductive layer 292 is formed by PVD deposition. The metal conductive layer 292 may include a single-layer structure or a multi-layer structure.

[0112] Then, the patterned metal conductive layer 292 and the contact layer 291 form a discrete second electrode 29, which extends along the first direction D1 and is spaced apart along the second direction D2.

[0113] In one embodiment, reference Figure 10 , Figure 11 A metal conductive layer 292 is formed, comprising: sequentially forming a metal barrier layer 2921 and a metal conductive layer 2922, wherein the metal barrier layer 2921 is disposed between the metal conductive layer 2922 and the contact layer 291. The metal barrier layer 2921 is used to prevent the metal material in the metal conductive layer 2922 from diffusing into other devices or film layers, avoiding the metal material from inducing short circuits in adjacent devices, and improving the reliability of the semiconductor structure.

[0114] For example, the material of the metal barrier layer 2921 may include at least one of tantalum, tantalum nitride, and titanium nitride; the material of the metal conductive layer 2922 may include tungsten.

[0115] In this embodiment, the second electrode 29 has a metal conductive layer 292 that is connected to the inner sidewall of the top of the channel layer 26 through a contact layer 291. This reduces the contact resistance between the second electrode 29 and the channel layer 26, thereby reducing the overall resistance of the semiconductor structure. This is beneficial for improving the electrical performance and read / write performance of the semiconductor structure, as well as increasing the response rate of the semiconductor structure.

[0116] In one embodiment, the contact layer 291 further covers the top surface of the isolation layer 24, and the contact layer 291 is disposed between the metal conductive layer 292 and the isolation layer 24. This further increases the contact area between the contact layer 291 and the metal conductive layer 292, reduces the contact resistance between the contact layer 291 and the metal conductive layer 292, further improves the electrical performance and read / write performance of the semiconductor structure, and increases the response rate of the semiconductor structure.

[0117] In one embodiment, step S90, forming the second electrode 29, includes the following steps:

[0118] Step S91b: Form a metal barrier layer 2921, which covers the inner wall of the top of the channel layer 26, the top surface of the channel layer 26, and the top surface of the isolation layer 24.

[0119] Step S92b: Form a metal conductive layer 2922, which covers the metal barrier layer 291 and fills the unfilled area of ​​the channel hole 40.

[0120] Reference Figure 12 , Figure 13 The second electrode 29 fabricated by the semiconductor structure fabrication method of this embodiment only includes two layers: a metal barrier layer 291 and a metal conductive layer 2922. This saves the process steps of forming the contact layer 291, thus saving manufacturing costs and time, and also helps to improve the product yield.

[0121] In some embodiments, refer to Figure 10 or Figure 13 After the second electrode 29 is formed, the exposed sidewalls of the metal conductive layer 292 of the second electrode 29 can be nitrided to form a nitride layer 293. The metal nitride layer 293 is used to prevent the metal material in the second electrode 29 from diffusing to other devices or film layers, thereby avoiding the diffusion of metal material and further reducing the risk of short circuits between devices.

[0122] Then, CVD or ALD is used to deposit insulating material to cover the nitride layer 293 and fill it between the second electrode 29 to form an isolation sidewall 28 to isolate the second electrode 29.

[0123] In some embodiments, the nitride layer 293 can be formed by direct deposition of silicon nitride. In this case, the non-metallic nitride layer 293 is located between the metal conductive layer 292 and the isolation sidewall 28, which is used to enhance the isolation effect and strengthen the surface adhesion between the metal conductive layer 292 and the isolation sidewall 28. This enhances the connection strength between the second electrode 29 and the isolation sidewall 28, increases the stability of the semiconductor structure, and reduces the risk of semiconductor structure damage, delamination, and detachment.

[0124] For example, the material of the isolation sidewall 28 may include at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide.

[0125] According to an exemplary embodiment, this embodiment provides a semiconductor structure, which is fabricated using the fabrication method described in the above embodiment. The semiconductor structure can be Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash EPROM, Ferroelectric Random Access Memory (FeRAM), Magnetic Random-Access Memory (MRAM), or other types of memory.

[0126] Reference Figure 10 , Figure 11 , Figure 12 , Figure 13 As shown, the semiconductor structure includes a substrate 11 and a first electrode 21, a gate 23, and a second electrode 29 sequentially stacked on the substrate 11; a first dielectric layer 41 is disposed between the gate 23 and the first electrode 21, the gate 23 and the first electrode 21 are separated by the first dielectric layer 41, and an isolation layer 24 is disposed between the gate 23 and the second electrode 29, the isolation layer 24 covering the top surface of the gate 23.

[0127] A channel hole 40 is provided between the first electrode 21 and the second electrode 29. The channel hole 40 penetrates the isolation layer 24, the gate 23 and the first dielectric layer 41. A channel layer 26 is disposed in the channel hole 40. The channel layer 26 is a polycrystalline semiconductor layer that conformally covers the bottom wall and side wall of the channel hole 40. The bottom wall of the channel layer 26 is in contact with the top surface of the first electrode 21.

[0128] A gate dielectric layer 25 is disposed between the gate 23 and the outer sidewall of the channel layer 26. An insulating layer 27 is disposed on the inner side of the channel layer 26, covering the bottom wall and at least part of the inner sidewall of the channel layer 26. A second electrode 29 is disposed above the insulating layer 27, covering the top surface of the insulating layer 27 and contacting the top of the channel layer 26.

[0129] In some embodiments, the channel layer 26 is a polycrystalline silicon layer that conformally covers the bottom and sidewalls of the channel hole 40.

[0130] In this embodiment, the channel layer 26 is a polycrystalline semiconductor layer that conformally covers the channel hole 40, which reduces the resistance of the channel layer 26 and improves the conductivity of the channel layer 26, thereby improving the electrical performance of the semiconductor structure.

[0131] According to an exemplary embodiment, this embodiment provides an electronic device including the semiconductor structure described in the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a first electrode is formed on the substrate; A gate is formed on the first electrode, and the top surface of the gate is covered by an isolation layer; A channel hole is formed that penetrates the isolation layer and the gate, and the channel hole exposes a portion of the top surface of the first electrode; A gate dielectric layer is formed, the gate dielectric layer covering the sidewall of the channel hole; A channel layer is formed, which covers the gate dielectric layer and the top surface of the first electrode exposed by the channel hole; A thermally conductive layer is formed by filling the channel hole with a thermally conductive material; the thermally conductive layer includes a titanium nitride layer and a metal layer formed sequentially, wherein the titanium nitride layer is disposed between the metal layer and the channel layer; After performing a heat annealing treatment on both the channel layer and the thermally conductive layer, the thermally conductive layer is removed. An insulating layer is formed in the channel hole, the insulating layer covering a portion of the inner sidewall of the channel layer; A second electrode is formed on the insulating layer, and the second electrode is in contact with the top of the channel layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After the channel layer and the thermally conductive layer are subjected to thermal annealing, the channel layer is formed into a polycrystalline semiconductor layer that conformally covers the sidewalls and bottom surface of the channel hole.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of an insulating layer in the channel hole includes: An insulating material is deposited to fill the trench holes, the insulating material covering the trench layer and at least partially filling the trench holes; The insulating material is then etched back into the channel hole.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The top surface of the insulating layer is higher than the top surface of the gate and lower than the top surface of the channel hole, and the insulating layer exposes a portion of the inner sidewall of the channel layer.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The formation of the second electrode includes: A contact layer is formed, which covers the exposed inner wall of the channel layer and fills the unfilled areas of the channel holes; A metal conductive layer is formed, which covers the top surface of the contact layer, the top surface of the channel layer, and the top surface of the isolation layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The formation of the metal conductive layer includes: sequentially forming a metal barrier layer and a metal conductive layer, wherein the metal barrier layer is disposed between the metal conductive layer and the contact layer.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The contact layer also covers the top surface of the isolation layer, and the contact layer is disposed between the metal conductive layer and the isolation layer.

8. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The formation of the second electrode includes: A metal barrier layer is formed, which covers the inner wall of the top of the trench layer, the top surface of the trench layer, and the top surface of the isolation layer; A metal conductive layer is formed, which covers the metal barrier layer and fills the unfilled areas of the channel holes.

9. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Before forming the second electrode on the insulating layer, the method further includes: The channel layer on the top surface of the isolation layer is etched away to expose the top surface of the isolation layer and the channel layer in each of the channel holes is disconnected.

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