Semiconductor package structure

Abstract

The application provides a semiconductor packaging structure. The semiconductor packaging structure comprises a driving module, a power module and a conductive connection layer. The driving module comprises a printed circuit board and a driving circuit, and the driving circuit is located on the printed circuit board. The power module comprises a power semiconductor chip and a substrate, and the power semiconductor chip is located on the substrate. The printed circuit board is located on the side of the power semiconductor chip away from the substrate. The conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected with the printed circuit board and the power semiconductor chip respectively. In the application, the conductive connection layer between the power semiconductor chip and the printed circuit board serves as a buffer layer, which can avoid the direct connection of the power semiconductor chip and the printed circuit board through the bumps in the flip-chip process, so that the copper layer on the surface of the printed circuit board is not easily damaged, thereby solving the problem of the decline of the current carrying capacity of the copper layer on the surface of the PCB caused by the flip-chip welding of the chip and the PCB in the prior art.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] With the development of semiconductor technology, the feature size of chips is constantly shrinking, the integration level is constantly increasing, the number of terminals is constantly increasing, and the spacing between terminals is constantly decreasing. As a result, in order to meet the requirement of smaller spacing between terminals, traditional wire bonding has been gradually phased out in the chip packaging process and replaced by flip-chip bonding technology.

[0003] Furthermore, in existing chip packaging processes, copper pillar bumps or tin-based solder bumps are typically used to directly flip-chip bond the chip and the printed circuit board (PCB). Therefore, the flatness of the spike bumps located between the chip and the PCB is difficult to guarantee, resulting in the spike bumps damaging the copper layer on the PCB surface, which in turn reduces the current carrying capacity of the copper layer on the PCB surface.

[0004] Therefore, a new semiconductor packaging structure is urgently needed to at least solve the above-mentioned technical problems. Summary of the Invention

[0005] The main objective of this invention is to provide a semiconductor packaging structure to solve the problem of reduced current carrying capacity of the copper layer on the PCB surface caused by flip-chip bonding of the chip and PCB board in the prior art.

[0006] To achieve the above objectives, according to one aspect of the present invention, a semiconductor package structure is provided, comprising: a driving module including a printed circuit board and a driving circuit, the driving circuit being located on the printed circuit board; a power module including a power semiconductor chip and a substrate, the power semiconductor chip being located on the substrate, and the printed circuit board being located on the side of the power semiconductor chip away from the substrate; and a conductive interconnect layer being located between the printed circuit board and the power semiconductor chip, and being connected to the printed circuit board and the power semiconductor chip respectively.

[0007] Furthermore, the power semiconductor chip has a first pad, the conductive interconnect layer has a second pad, and the semiconductor package structure further includes a metal solder ball located between the first pad and the second pad for bonding the power semiconductor chip and the conductive interconnect layer.

[0008] Furthermore, the semiconductor package structure also includes a redistribution layer located between the first pad and the metal solder ball.

[0009] Furthermore, the semiconductor packaging structure further includes: a first support member located between the printed circuit board and the substrate, and spaced apart from the power semiconductor chip and the conductive interconnect layer respectively; and / or a second support member located between the printed circuit board and the substrate, and spaced apart from the power semiconductor chip, and in contact with the conductive interconnect layer.

[0010] Furthermore, the driving circuit, printed circuit board, conductive connection layer, power semiconductor chip and substrate are sequentially stacked.

[0011] Furthermore, the power module includes multiple power semiconductor chips spaced apart on a substrate, the printed circuit board and the substrate have at least a cutout area in addition to the power semiconductor chips and the conductive connection layer, and the semiconductor package structure also includes an insulating dielectric layer that fills the cutout area.

[0012] Furthermore, the semiconductor packaging structure also includes a metal sintered layer located between the power semiconductor chip and the substrate.

[0013] Furthermore, the power semiconductor chip includes a silicon carbide substrate.

[0014] Furthermore, the substrate is a silicon carbide substrate.

[0015] Furthermore, liquid metal is embedded in the silicon carbide substrate.

[0016] The present invention provides a semiconductor packaging structure comprising a driving module, a power module, and a conductive connection layer. The printed circuit board (PCB) in the driving module is located on the side of the power semiconductor chip in the power module away from the substrate. The conductive connection layer is located between the PCB of the driving module and the power semiconductor chip of the power module, and connects the PCB and the power semiconductor chip respectively. Compared to the prior art where the power semiconductor chip is directly flip-chip bonded to the PCB, this conductive connection layer between the power semiconductor chip and the PCB acts as a buffer layer, preventing the power semiconductor chip from being directly connected to the PCB via bumps in the flip-chip process. This makes the copper layer on the surface of the PCB less susceptible to damage, thus solving the problem of reduced current-carrying capacity of the copper layer on the PCB surface caused by flip-chip bonding of the chip and the PCB in the prior art. Attached Figure Description

[0017] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0018] Figure 1A cross-sectional structural schematic diagram of one embodiment of a semiconductor packaging structure according to the present invention is shown;

[0019] Figure 2 A cross-sectional structural schematic diagram of another embodiment of a semiconductor packaging structure according to the present invention is shown;

[0020] Figure 3 A cross-sectional schematic diagram of yet another embodiment of a semiconductor packaging structure according to the present invention is shown.

[0021] The above figures include the following reference numerals:

[0022] 10. Substrate; 20. Power semiconductor chip; 30. Conductive connection layer; 40. Printed circuit board; 50. Drive circuit; 60. Metal solder ball; 70. Rewiring layer; 80. First support component; 90. Second support component; 100. First metal sintered layer; 110. Second metal sintered layer; 120. Copper pad layer. Detailed Implementation

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] As mentioned in the background section, existing chip packaging processes typically use copper pillar bumps or tin-based solder bumps to directly flip-chip bond the chip and PCB. Therefore, the flatness of the bumps located between the chip and PCB is difficult to guarantee, leading to the bumps damaging the copper layer on the PCB surface and consequently reducing the current-carrying capacity of the copper layer. To address these technical problems, the inventors of this application provide a semiconductor packaging structure.

[0027] In some optional embodiments, a semiconductor package structure is provided, the semiconductor package structure including a driving module, a power module and a conductive connection layer, wherein the driving module includes a printed circuit board and a driving circuit, and the driving circuit is located on the printed circuit board; the power module includes a power semiconductor chip and a substrate, the power semiconductor chip is located on the substrate, and the printed circuit board is located on the side of the power semiconductor chip away from the substrate; the conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected to the printed circuit board and the power semiconductor chip respectively.

[0028] Specifically, the driving module includes a printed circuit board and a driving circuit, wherein the printed circuit board has a first surface and a second surface opposite to each other. In one exemplary embodiment, the driving circuit is located on the first surface of the printed circuit board, and in another exemplary embodiment, the driving circuit is located on the second surface of the printed circuit board.

[0029] Specifically, since the power semiconductor chip in the power module is located on the substrate and the printed circuit board is located on the side of the power semiconductor chip away from the substrate, in one exemplary embodiment, the driving circuit and the power semiconductor chip can be located between the printed circuit board and the substrate, respectively, or in another exemplary embodiment, the driving circuit is located on the side of the printed circuit board away from the power semiconductor chip and the substrate is located on the side of the power semiconductor chip away from the printed circuit board.

[0030] Specifically, since the conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected to both the printed circuit board and the power semiconductor chip respectively, in an exemplary embodiment, the positional relationship of the printed circuit board, driving circuit, power semiconductor chip, substrate, and conductive connection layer can include: the driving circuit is located on the printed circuit board, the power semiconductor chip is located on the substrate, the driving circuit is located on the side of the printed circuit board away from the power semiconductor chip, and the conductive connection layer is located between the printed circuit board and the power semiconductor chip; or the driving circuit is located on the printed circuit board, the power semiconductor chip is located on the substrate, the driving circuit is located on the side of the printed circuit board closer to the power semiconductor chip, and the conductive connection layer is located between the printed circuit board and the power semiconductor chip, with the driving circuit and the conductive connection layer spaced apart. Optionally, the material of the conductive connection layer can be a metallic material, and further, the conductive connection layer can be a molybdenum layer.

[0031] In the above embodiment, the semiconductor packaging structure includes a driving module, a power module, and a conductive connection layer. The printed circuit board in the driving module is located on the side of the power semiconductor chip in the power module away from the substrate. The conductive connection layer is located between the printed circuit board (PCB) of the driving module and the power semiconductor chip of the power module, and the conductive connection layer connects the printed circuit board and the power semiconductor chip respectively. Compared with the prior art where the power semiconductor chip is directly flip-chip bonded to the printed circuit board, the conductive connection layer between the power semiconductor chip and the printed circuit board acts as a buffer layer, which can prevent the power semiconductor chip and the printed circuit board from being directly connected through the bumps in the flip-chip process. Therefore, the copper layer on the surface of the printed circuit board is not easily damaged, thus solving the problem of reduced current carrying capacity of the copper layer on the PCB surface caused by flip-chip bonding of the chip and the PCB board in the prior art.

[0032] In some alternative embodiments, the power semiconductor chip has a first pad, specifically located on the side surface of the power semiconductor chip near the conductive interconnect layer, and the conductive interconnect layer has a second pad, specifically located on the side surface of the conductive interconnect layer near the power semiconductor chip. The semiconductor package structure may also include a metal solder ball located between the first and second pads for bonding the power semiconductor chip and the conductive interconnect layer.

[0033] Furthermore, the first pad and / or the second pad mentioned above can be micro-bump pads.

[0034] Specifically, the aforementioned metal solder ball is located between the first pad and the second pad, and is used to electrically connect the first pad and the second pad. Optionally, the metal solder of the aforementioned metal solder ball can be any one of electronic packaging solders such as Au, In, Sn, Sn-Sp, Sn-Ag, Sn-Cu, Bi-Sb, etc. Optionally, the metal solder ball used in this application can be a gold solder ball.

[0035] In existing technologies, flip bonding to the printed circuit board is performed only through a first pad (micro-bump) on the power semiconductor chip. Furthermore, the bumps on these first pads (micro-bumps) formed in conventional processes are often uneven. This results in significant stress at the bumps when bonding the power semiconductor chip and the printed circuit board, which can damage the copper-clad film on the printed circuit board, leading to a decrease in the current-carrying capacity of the copper layer on the PCB surface. Therefore, to prevent bump damage to the printed circuit board, this embodiment provides a conductive connection layer between the power semiconductor chip and the printed circuit board. This conductive connection layer has a second pad for soldering to the power semiconductor chip, allowing the power semiconductor chip to be directly bonded to the conductive connection layer. This avoids direct contact between the bumps of the power semiconductor chip and the printed circuit board. The conductive connection layer also alleviates the stress on the bumps, preventing damage to the surface copper layer on the printed circuit board. This solves the problem of reduced current-carrying capacity of the PCB surface copper layer caused by flip bonding of the chip and PCB in existing technologies.

[0036] To align and mount the first pad on the power semiconductor chip with the second pad on the conductive interconnect layer, in some optional embodiments, the semiconductor package structure may further include a redistribution layer. This redistribution layer may be located between the first pad and the metal solder ball, thereby redistributing the first pad connected to the metal solder ball. Optionally, the redistribution layer may be made of electroplated copper, supplemented with a base layer of titanium, copper sputtering, etc.

[0037] In some alternative embodiments, the semiconductor package structure may further include a first support member, which may be located between the printed circuit board and the substrate, and the first support member is spaced apart from the power semiconductor chip and the conductive interconnect layer respectively; and / or a second support member, which may be located between the printed circuit board and the substrate, and the second support member is spaced apart from the power semiconductor chip, and further, the second support member is in contact with the conductive interconnect layer.

[0038] The materials of the first and / or second support components can be the same as or different from the material of the conductive connection layer. In the same case, the materials of the first, second, and conductive connection layers can all be metallic. In different cases, the first and / or second support components can be insulating materials, and the conductive connection layer can be metallic. Further, the materials of the first, second, and conductive connection layers can be molybdenum, so that the first and second support components not only provide support and reduce stress, but also enhance charge carrier capacity and increase insulation capacity, thereby increasing the stability of the packaging structure. In this embodiment, since the printed circuit board and the substrate are arranged in a vertically stacked configuration, a support component is provided between the printed circuit board and the substrate to ensure strong stability in the vertical direction. One end of the support component is located on the substrate, and the other end is located on the printed circuit board. Further, the support component located on the printed circuit board can include a first and a second support component, and each of the first and second support components can include one or more, thereby making the force between the printed circuit board and the substrate more balanced.

[0039] Since sequentially stacking multiple layers on the same printed circuit board helps reduce the area occupied by the printed circuit board, enables three-dimensional high-density packaging of semiconductor packaging structures, improves device integration, and reduces the area of ​​the packaging structure, in some optional embodiments, the driving circuit, printed circuit board, conductive interconnect layer, power semiconductor chip, and substrate are sequentially stacked. Furthermore, because the driving circuit, printed circuit board, conductive interconnect layer, and power semiconductor chip are sequentially stacked in this structure, the electronic circuitry between the driving circuit and the power semiconductor chip is shortened.

[0040] In some alternative implementations, the power module includes a plurality of power semiconductor chips spaced apart on a substrate, and the printed circuit board and the substrate have at least a cutout area in addition to the power semiconductor chips and the conductive interconnect layer. In order for the cutout area to serve as thermal insulation, the semiconductor package structure may also include an insulating dielectric layer that fills the cutout area.

[0041] Specifically, the material of the aforementioned insulating dielectric layer can be insulating adhesive. By filling the aforementioned hollow areas with the insulating dielectric layer (insulating adhesive), any two adjacent power semiconductor chips located between the printed circuit board and the substrate are separated by the insulating dielectric layer (insulating adhesive), thereby isolating heat transfer between power devices. Furthermore, the printed circuit board and the substrate have hollow areas, excluding the power semiconductor chips and conductive connection layers, separated by the insulating dielectric layer (insulating adhesive), thereby forming a thermal gradient between the printed circuit board and the substrate (i.e., the temperature of the substrate is lower than the temperature of the printed circuit board, allowing the heat of the semiconductor package structure to be dissipated from the substrate), ensuring the normal operation of the device. Optionally, the aforementioned insulating adhesive can be epoxy resin.

[0042] To enhance the connection between the power semiconductor chip and the substrate, as well as the connection between the conductive interconnect layer and the printed circuit board, in some optional embodiments, the semiconductor package structure further includes a metal sintering layer located between the power semiconductor chip and the substrate. Further, the aforementioned metal sintering layer may include a first metal sintering layer and a second metal sintering layer. The semiconductor package structure may also include a copper pad layer located between the first and second metal sintering layers, with the first metal sintering layer located between the copper pad and the power semiconductor chip, and the second metal sintering layer located between the copper pad and the substrate.

[0043] Optionally, the material of the aforementioned metal sintered layer can be metallic silver.

[0044] In some alternative implementations, the power semiconductor chip includes a silicon carbide substrate. Further, the substrate is a silicon carbide substrate.

[0045] In the above embodiments, the silicon carbide substrate has a high heat dissipation coefficient, and the main heat in the power module is dissipated through the silicon carbide substrate, thereby improving the heat dissipation efficiency of the power module. Since the silicon carbide substrate and the silicon carbide base material are the same, their coefficients of thermal expansion are the same, which can reduce the thermomechanical stress between them and avoid problems such as warping of the power semiconductor chip caused by mechanical stress when the two are connected and fixed, thereby further ensuring the reliability of the semiconductor packaging structure connection.

[0046] Furthermore, in order to improve the heat dissipation of the substrate, in some alternative embodiments, liquid metal is embedded in the silicon carbide substrate.

[0047] Specifically, in an exemplary embodiment, the above-described semiconductor package structure includes a driving module, a power module, a conductive connection layer, and a first support component, wherein, as... Figure 1As shown, the driving module includes a printed circuit board 40 and a driving circuit 50, with the driving circuit 50 located on the printed circuit board 40. The power module includes a power semiconductor chip 20 and a substrate 10, with the power semiconductor chip 20 located on the substrate 10 and the printed circuit board 40 located on the side of the power semiconductor chip 20 away from the substrate 10. The conductive connection layer 30 is located between the printed circuit board 40 and the power semiconductor chip 20 and is connected to both the printed circuit board 40 and the power semiconductor chip 20. The first support member 80 is located between the printed circuit board 40 and the substrate 10 and is spaced apart from both the power semiconductor chip 20 and the conductive connection layer 30. Further, the semiconductor package structure may also include metal solder balls 60. Specifically, the power semiconductor chip 20 has a first pad, and the conductive connection layer 30 has a second pad. The metal solder ball 60 is located between the first and second pads and is used to bond the power semiconductor chip 20 and the conductive connection layer 30 together. Furthermore, the aforementioned semiconductor package structure may further include a redistribution layer 70, specifically located between the first pad and the metal solder ball 60. Further, the aforementioned semiconductor package structure may further include a first support member 80, wherein the first support member 80 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20 and the conductive interconnect layer 30, respectively. Further, the semiconductor package structure also includes an insulating dielectric layer that fills the printed circuit board 40 and the substrate 10, having at least the cutout areas excluding the power semiconductor chip 20 and the conductive interconnect layer 30. Furthermore, the semiconductor packaging structure also includes a metal sintering layer located between the power semiconductor chip 20 and the substrate 10. The metal sintering layer may include a first metal sintering layer 100 and a second metal sintering layer 110. The semiconductor packaging structure may also include a copper pad layer 120 located between the first metal sintering layer 100 and the second metal sintering layer 110. The first metal sintering layer 100 is located between the copper pad and the power semiconductor chip 20, and the second metal sintering layer 110 is located between the copper pad and the substrate 10.

[0048] Specifically, in another exemplary embodiment, the above-described semiconductor package structure includes a driving module, a power module, a conductive connection layer, and a second support component, wherein, as... Figure 2As shown, the driving module includes a printed circuit board 40 and a driving circuit 50, with the driving circuit 50 located on the printed circuit board 40. The power module includes a power semiconductor chip 20 and a substrate 10, with the power semiconductor chip 20 located on the substrate 10 and the printed circuit board 40 located on the side of the power semiconductor chip 20 away from the substrate 10. The conductive connection layer 30 is located between the printed circuit board 40 and the power semiconductor chip 20 and is connected to both. The second support member 90 is located between the printed circuit board 40 and the substrate 10, spaced apart from the power semiconductor chip 20, and in contact with the conductive connection layer 30. Further, the semiconductor packaging structure may also include metal solder balls 60. Specifically, the power semiconductor chip 20 has a first pad, and the conductive connection layer 30 has a second pad. The metal solder ball 60 is located between the first and second pads and is used to bond the power semiconductor chip 20 and the conductive connection layer 30 together. Furthermore, the aforementioned semiconductor package structure may further include a redistribution layer 70, specifically located between the first pad and the metal solder ball 60. Further, the aforementioned semiconductor package structure may further include a second support member 90, wherein the second support member 90 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20, and is in contact with the conductive interconnect layer 30. Further, the semiconductor package structure also includes an insulating dielectric layer, which fills the printed circuit board 40 and the substrate 10, having at least the cutout areas excluding the power semiconductor chip 20 and the conductive interconnect layer 30. Furthermore, the semiconductor packaging structure also includes a metal sintering layer located between the power semiconductor chip 20 and the substrate 10. The metal sintering layer may include a first metal sintering layer 100 and a second metal sintering layer 110. The semiconductor packaging structure may also include a copper pad layer 120 located between the first metal sintering layer 100 and the second metal sintering layer 110. The first metal sintering layer 100 is located between the copper pad and the power semiconductor chip 20, and the second metal sintering layer 110 is located between the copper pad and the substrate 10.

[0049] Specifically, in another exemplary embodiment, the above-described semiconductor package structure includes a driving module, a power module, a conductive connection layer, a first support component, and a second support component, wherein, as... Figure 3As shown, the driving module includes a printed circuit board 40 and a driving circuit 50, with the driving circuit 50 located on the printed circuit board 40. The power module includes a power semiconductor chip 20 and a substrate 10, with the power semiconductor chip 20 located on the substrate 10 and the printed circuit board 40 located on the side of the power semiconductor chip 20 away from the substrate 10. The conductive connection layer 30 is located between the printed circuit board 40 and the power semiconductor chip 20 and is connected to both the printed circuit board 40 and the power semiconductor chip 20. The first support member 80 is located between the printed circuit board 40 and the substrate 10 and is spaced apart from the power semiconductor chip 20 and the conductive connection layer 30, respectively. The second support member 90 is located between the printed circuit board 40 and the substrate 10 and is spaced apart from the power semiconductor chip 20, and is in contact with the conductive connection layer 30. Furthermore, the above-described semiconductor packaging structure may further include metal solder balls 60. Specifically, the power semiconductor chip 20 has a first pad, and the conductive interconnect layer 30 has a second pad. The metal solder balls 60 are located between the first and second pads and are used to bond the power semiconductor chip 20 and the conductive interconnect layer 30 together. Furthermore, the above-described semiconductor packaging structure may further include a redistribution layer 70. Specifically, the redistribution layer 70 is located between the first pad and the metal solder balls 60. Furthermore, the above-described semiconductor packaging structure may further include a first support member 80 and a second support member 90. The first support member 80 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20 and the conductive interconnect layer 30, respectively. The second support member 90 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20 and in contact with the conductive interconnect layer 30. Furthermore, the semiconductor package structure also includes an insulating dielectric layer that fills the printed circuit board 40 and the substrate 10, having at least a cutout area excluding the power semiconductor chip 20 and the conductive interconnect layer 30. Furthermore, the semiconductor package structure also includes a metal sintering layer located between the power semiconductor chip 20 and the substrate 10. This metal sintering layer may include a first metal sintering layer 100 and a second metal sintering layer 110. The semiconductor package structure may also include a copper pad layer 120 located between the first metal sintering layer 100 and the second metal sintering layer 110. The first metal sintering layer 100 is located between the copper pad and the power semiconductor chip 20, and the second metal sintering layer 110 is located between the copper pad and the substrate 10.

[0050] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0051] The semiconductor packaging structure of this application includes a driving module, a power module, and a conductive connection layer. The printed circuit board (PCB) in the driving module is located on the side of the power semiconductor chip in the power module away from the substrate. The conductive connection layer is located between the PCB of the driving module and the power semiconductor chip of the power module, and connects the PCB and the power semiconductor chip respectively. Compared to the prior art where the power semiconductor chip is directly flip-chip bonded to the PCB, this conductive connection layer between the power semiconductor chip and the PCB acts as a buffer layer, preventing the power semiconductor chip from being directly connected to the PCB via bumps in the flip-chip process. This makes the copper layer on the surface of the PCB less susceptible to damage, thus solving the problem of reduced current-carrying capacity of the copper layer on the PCB surface caused by flip-chip bonding of the chip and PCB in the prior art.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: A drive module includes a printed circuit board and a drive circuit, wherein the drive circuit is located on the printed circuit board; A power module includes a power semiconductor chip and a substrate, wherein the power semiconductor chip is located on the substrate and the printed circuit board is located on the side of the power semiconductor chip away from the substrate; A conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected to both the printed circuit board and the power semiconductor chip respectively. The first support component is located between the printed circuit board and the substrate, and is spaced apart from the power semiconductor chip and the conductive connection layer, respectively. The second support component is located between the printed circuit board and the substrate, and is spaced apart from the power semiconductor chip, and is in contact with the conductive connection layer; The driving circuit, the printed circuit board, the conductive connection layer, the power semiconductor chip, and the substrate are stacked sequentially.

2. The semiconductor packaging structure according to claim 1, characterized in that, The power semiconductor chip has a first pad, the conductive connection layer has a second pad, and the semiconductor package structure further includes: Metal solder balls, located between the first solder pad and the second solder pad, are used to bond the power semiconductor chip and the conductive interconnect layer.

3. The semiconductor packaging structure according to claim 2, characterized in that, The semiconductor packaging structure further includes: A redistribution layer is located between the first pad and the metal solder ball.

4. The semiconductor packaging structure according to any one of claims 1 to 3, characterized in that, The power module includes a plurality of power semiconductor chips spaced apart on the substrate, the printed circuit board and the substrate having at least a cutout area excluding the power semiconductor chips and the conductive interconnect layer, and the semiconductor package structure further includes: An insulating dielectric layer that fills the hollowed-out area.

5. The semiconductor packaging structure according to any one of claims 1 to 3, characterized in that, The semiconductor packaging structure further includes: A metal sintered layer is located between the power semiconductor chip and the substrate.

6. The semiconductor packaging structure according to any one of claims 1 to 3, characterized in that, The power semiconductor chip includes a silicon carbide substrate.

7. The semiconductor packaging structure according to any one of claims 1 to 3, characterized in that, The substrate is a silicon carbide substrate.

8. The semiconductor packaging structure according to any one of claims 7, characterized in that, Liquid metal is embedded in the silicon carbide substrate.

Images