A wide bandgap semiconductor module packaging structure based on planar interconnects

Abstract

The application discloses a wide-bandgap semiconductor module packaging structure based on a planar interconnection, which is electrically connected between wide-bandgap semiconductor chips in the same group in a planar interconnection structure mode and finally connected with a power substrate bottom metal layer, without using a bonding wire, so that the inductance is reduced, the parasitic inductance from the chip to the terminal is greatly balanced through the interconnection mode, and the current sharing capacity of the module is greatly improved; in addition, the metal layer of the power substrate, the power terminal driving terminal and the surface of the planar interconnection structure are all plated with silver, so that the anti-oxidation capacity of the metal in the module under high temperature can be effectively improved, the nano-silver sintering technology is more easily used in the silver-plated surface mode, and the high-temperature resistance of the module is further improved; the wide-bandgap semiconductor module packaging structure has the characteristics of high-temperature resistance, low parasitic inductance and low parasitic inductance imbalance, and is particularly suitable for current sharing of multi-chip in a half-bridge structure, high switching frequency and high working temperature.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to a wide bandgap semiconductor module packaging structure based on planar interconnects. Background Technology

[0002] New-generation wide-bandgap semiconductor devices, with silicon carbide power semiconductor chips at their core, possess superior electrical and thermal characteristics compared to silicon-based devices, and are increasingly being widely used in important military, civilian, and commercial fields such as electric vehicles, high-speed rail, aerospace, pulse power, new energy grid connection, and high-voltage direct current transmission. Furthermore, with the introduction of the "dual-carbon" goal, power modules are continuously developing towards miniaturization, low loss, high power density, high reliability, and high integration.

[0003] However, the traditional power module structure, which is still widely used in silicon carbide devices, has many problems. As a result, the packaging technology structure is becoming a bottleneck factor limiting the performance of silicon carbide devices, mainly manifested in the following ways:

[0004] 1. Traditional power modules use aluminum bonding wires for electrical connections, which have a small contact area and are prone to connection failure at the bonding points.

[0005] 2. Traditional power modules use traditional solder, which melts at high temperatures, causing connection failure and limiting the application of the modules in high-temperature environments.

[0006] 3. Traditional power modules have large parasitic inductance and it is difficult to achieve current sharing of power chips. Especially at high switching frequencies, this can cause severe voltage overshoot and current imbalance, which can further damage the chip or cause module failure.

[0007] In summary, power chips based on wide-bandgap semiconductor materials are limited by traditional packaging, failing to fully utilize the inherent superior performance of silicon carbide materials. Therefore, a novel module package suitable for wide-bandgap semiconductors is needed to overcome the shortcomings and limitations of traditional power module packaging structures and to unleash the excellent performance of wide-bandgap semiconductor chips. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a wide bandgap semiconductor module packaging structure based on planar interconnection, which has the characteristics of high temperature resistance, low parasitic inductance and low parasitic inductance imbalance. It is particularly suitable for current sharing of multi-chip current in half-bridge structure, high switching frequency and high operating temperature, so as to solve the technical problem of uneven current distribution caused by the mismatch of parasitic parameters within the module when parallel chips of high current power module are connected.

[0009] The present invention adopts the following technical solution:

[0010] A wide bandgap semiconductor module packaging structure based on planar interconnect includes several wide bandgap power semiconductor chips connected in series or parallel. The bottom surfaces of the wide bandgap power semiconductor chips are disposed on the top metal layer of a power substrate. The surfaces of the wide bandgap silicon carbide power semiconductor chips are connected to the conductive metal regions disposed on the top metal layer and the surfaces of other wide bandgap power semiconductor chips through the planar interconnect structure. Power terminals and drive terminals are disposed on the top metal layer. The DC positive metal region and DC negative metal region of the top metal layer are respectively connected to decoupling capacitors. The surfaces of the power substrate, power terminals, drive terminals and planar interconnect structure are silver-plated.

[0011] Specifically, an upper bridge arm gate metal region and an upper bridge arm Kelvin source metal region are provided on one side of the DC positive metal region, and an AC electrode metal region, a lower bridge arm gate metal region, and a lower bridge arm Kelvin source metal region are provided between the DC positive metal region and the DC negative metal region.

[0012] Furthermore, the wide-bandgap silicon carbide power semiconductor chip includes multiple upper-arm wide-bandgap power semiconductor chips and corresponding lower-arm wide-bandgap power semiconductor chips. The upper-arm wide-bandgap power semiconductor chips are disposed on the DC positive electrode metal region, and the gates of the upper-arm wide-bandgap power semiconductor chips are connected to the upper-arm gate metal region, and the sources of the upper-arm wide-bandgap power semiconductor chips are connected to the upper-arm Kelvin source metal region, respectively. The lower-arm wide-bandgap power semiconductor chips are disposed on the AC electrode metal region, and the gates of the lower-arm wide-bandgap power semiconductor chips are connected to the lower-arm gate metal region, respectively, and the sources of the lower-arm wide-bandgap power semiconductor chips are connected to the lower-arm Kelvin source metal region, respectively.

[0013] Furthermore, the driving terminals include an upper bridge arm source driving terminal, an upper bridge arm gate driving terminal, a lower bridge arm gate driving terminal, and a lower bridge arm source driving terminal. The upper bridge arm source driving terminal is located in the upper bridge arm Kelvin source metal region, the upper bridge arm gate driving terminal is located in the upper bridge arm gate metal region, the lower bridge arm gate driving terminal is located in the lower bridge arm gate metal region, and the lower bridge arm source driving terminal is located in the lower bridge arm Kelvin source metal region.

[0014] Specifically, the power terminals include a DC positive power terminal, a DC negative power terminal, and an AC power terminal. The DC positive power terminal is located in the DC positive metal area, the DC negative power terminal is located in the DC negative metal area, and the AC power terminal is located in the AC metal area.

[0015] Specifically, the decoupling capacitor includes a first decoupling capacitor and a second decoupling capacitor, and the DC positive metal region is connected to the DC negative metal region through the first decoupling capacitor and the second decoupling capacitor, respectively.

[0016] Specifically, a wide bandgap silicon carbide power semiconductor chip includes several semiconductor chips, which are divided into two groups. The semiconductor chips in each group are connected in parallel, and the series connection of the semiconductor chips between the two groups forms the upper and lower arms of a typical half-bridge structure. The semiconductor chips in the same group are spaced at the same distance.

[0017] Specifically, the planar interconnect structure includes an upper bridge arm planar interconnect structure and a lower bridge arm planar interconnect structure. The upper bridge arm planar interconnect structure interconnects the sources of the upper bridge arm wide bandgap power semiconductor chip and connects them to the AC electrode metal region; the lower bridge arm planar interconnect structure interconnects the sources of the lower bridge arm wide bandgap power semiconductor chip and connects them to the DC negative electrode metal region.

[0018] Furthermore, the upper bridge arm planar interconnect structure includes an upper bridge arm seventh conductive path and an upper bridge arm eighth conductive path. One end of the upper bridge arm seventh conductive path and the upper bridge arm eighth conductive path are respectively connected to the corresponding upper bridge arm wide bandgap power semiconductor chip through several upper bridge arm conductive paths, and the other end is respectively connected to the AC electrode metal region through several upper bridge arm conductive paths.

[0019] The lower bridge arm planar interconnection structure includes a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path of the lower bridge arm that are interconnected. The first conductive path and the second conductive path of the lower bridge arm are connected to the DC negative metal region through a fifth conductive path of the lower bridge arm, and the third conductive path and the fourth conductive path of the lower bridge arm are connected to the DC negative metal region through a sixth conductive path of the lower bridge arm.

[0020] Specifically, an insulating dielectric layer and a bottom metal layer are sequentially arranged below the top metal layer.

[0021] Compared with the prior art, the present invention has at least the following beneficial effects:

[0022] This invention discloses a wide bandgap semiconductor module packaging structure based on planar interconnects. Several wide bandgap semiconductor chips are connected in series or parallel to increase the capacity of the power module. The wide bandgap semiconductor chips connected in parallel within the same group are electrically connected via a planar interconnect structure and ultimately connected to the bottom metal layer of the power substrate. Using a planar interconnect structure to electrically connect the wide bandgap semiconductor surface can significantly reduce the size and imbalance of the source parasitic inductance of each chip, eliminating the need for bonding wires. This reduces inductance and greatly balances the parasitic inductance from the chip to the terminal through interconnection, further improving the module's current sharing capability. Furthermore, this invention also features high-temperature performance. The metal layer of the power substrate, power terminals, drive terminals, and the surface of the planar interconnect structure are all silver-plated to facilitate the use of sintered silver connections, enhance connection stability, and significantly improve the oxidation resistance of the metal at low temperatures. Simultaneously, surface silver plating facilitates the use of nano-silver sintering technology, further improving the module's high-temperature resistance.

[0023] Furthermore, the DC positive electrode metal region, AC electrode metal region, and DC negative electrode metal region of the top metal layer of the power substrate are covered with large areas of copper to enhance current flow capacity and module thermal conductivity.

[0024] Furthermore, a separate Kelvin source metal region is set in the metal layer, and the driving circuit composed of the source and gate of the power semiconductor chip adopts the Kelvin connection method, which can effectively prevent the parasitic inductance of the power source from entering the driving circuit, realize the Kelvin connection of the driving circuit, and eliminate the influence of the power circuit on the common source inductance of the driving circuit.

[0025] Furthermore, the drive terminals are located in the corresponding metal area of ​​the top metal layer of the power substrate, which facilitates the connection between the module and external drive circuits.

[0026] Furthermore, the drive terminals are located in the corresponding metal area of ​​the top metal layer of the power substrate, which facilitates the connection of the module with external power circuits.

[0027] Furthermore, the decoupling capacitors are positioned close to the power terminals to minimize the introduction of inductance from external circuits. At the same time, the DC positive and DC negative power terminals are arranged on the same side, which facilitates the design of a stacked busbar structure and enables the series and parallel connection of modules.

[0028] Furthermore, the wide-bandgap semiconductor power chips are divided into two groups and set in different conductive metal regions to form the upper and lower bridge arm chip groups of the half-bridge structure, which improves the versatility of the module. The chips in the same group are appropriately spaced and the same, providing a similar heat dissipation environment for the chips and establishing thermal coupling between the small chips.

[0029] Furthermore, the planar interconnect structure not only replaces the bonding wire for electrical connection, but also interconnects the sources of the same group of power semiconductor chips. By using coupling paths, it significantly reduces the imbalance between the parasitic inductances of the sources of each chip. At the same time, it greatly increases the contact area at the connection point compared to bonding wire, which reduces the size of parasitic inductance and increases reliability, thereby improving the current sharing capability and reliability of the module.

[0030] Furthermore, by adopting a planar interconnect structure, the source interconnect paths are set between the parallel chips of the upper and lower bridge arms, thereby forming an interconnect network of source inductors, which greatly reduces the problem of parasitic inductance imbalance caused by different chip distances from the terminals.

[0031] Furthermore, the power substrate has a three-layer structure consisting of a metal layer, an insulating dielectric layer, and a metal layer. The double-sided metallization of the insulating dielectric layer effectively mitigates high-temperature bending caused by the difference in thermal expansion coefficients between the metal and ceramic. The bottom metal layer of the power substrate can be directly or indirectly connected to the heat sink via the substrate, increasing the module's heat dissipation capacity. The middle insulating dielectric layer is made of ceramic for thermal conductivity and electrical insulation. The top metal layer is divided into several metal regions, primarily used for the electrical connection of wide-bandgap semiconductor power chips.

[0032] In summary, this invention can reliably operate at high switching frequencies and high temperatures, thereby fully leveraging the superior performance of wide-bandgap power semiconductors.

[0033] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the layout of the power substrate and the top metal region in an embodiment of the invention;

[0035] Figure 2 This is a top view schematic diagram of an embodiment of the present invention that does not include a planar interconnect structure;

[0036] Figure 3 This is an overall structural diagram of an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the upper bridge arm planar interconnect structure and chip source current flow in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the bridge arm planar interconnect structure and chip source current flow in an embodiment of the present invention.

[0039] Wherein: 100. Power substrate; 101. Top metal layer; 102. Insulating dielectric layer; 103. Bottom metal layer; 111. Kelvin source metal region of upper bridge arm; 112. Gate metal region of upper bridge arm; 113. DC positive metal region; 114. AC metal region; 115. Gate metal region of lower bridge arm; 116. Kelvin source metal region of lower bridge arm; 117. DC negative metal region; 201. Wide bandgap power semiconductor chip of first upper bridge arm; 202. Wide bandgap power semiconductor chip of second upper bridge arm; 203. Wide bandgap power semiconductor chip of third upper bridge arm; 204. Wide bandgap power semiconductor chip of first lower bridge arm; 205. Wide bandgap power semiconductor chip of second lower bridge arm; 206. Wide bandgap power semiconductor chip of third lower bridge arm; 301. DC positive power terminal; 302. DC negative power terminal; 303. AC power terminal; 304. Upper bridge arm source drive terminal; 305. Upper bridge arm gate drive terminal; 306. Lower bridge arm gate drive terminal; 307. Lower bridge arm source drive terminal; 401. First decoupling capacitor; 402. Second decoupling capacitor; 500. Upper bridge arm planar interconnect structure; 501. Upper bridge arm first conductive path; 502. Upper bridge arm second conductive path; 503. Upper bridge arm third conductive path; 504. Upper bridge arm fourth conductive path; 505. Upper bridge arm fifth conductive path; 506. Upper bridge arm sixth conductive path; 507. Upper bridge arm seventh conductive path; 508. Upper bridge arm eighth conductive path; 600. Lower bridge arm planar interconnect structure; 601. Lower bridge arm first conductive path; 602. Lower bridge arm second conductive path; 603. Lower bridge arm third conductive path; 604. Lower bridge arm fourth conductive path; 605. Lower bridge arm fifth conductive path; 606. Lower bridge arm sixth conductive path. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0043] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0044] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0045] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0047] This invention provides a wide bandgap semiconductor module packaging structure based on planar interconnects. Wide bandgap semiconductor chips connected in parallel within the same group are electrically connected via a planar interconnect structure and ultimately connected to the bottom metal layer of a power substrate. This eliminates the need for bonding wires, reducing inductance and significantly equalizing parasitic inductance from the chip to the terminals through the interconnection, thereby greatly improving the module's current sharing capability. Furthermore, the metal layer of the power substrate, the power terminal drive terminals, and the surface of the planar interconnect structure are all silver-plated, effectively improving the oxidation resistance of the metal within the module at high temperatures. Simultaneously, the silver plating facilitates the use of nano-silver sintering technology, further enhancing the module's high-temperature resistance. This structure features high-temperature resistance, low parasitic inductance, and low parasitic inductance imbalance, making it particularly suitable for current sharing in multi-chip half-bridge structures, high switching frequencies, and high operating temperatures.

[0048] Please see Figure 1 , Figure 2 and Figure 3 The present invention discloses a wide bandgap semiconductor module packaging structure based on planar interconnect, comprising a power substrate 100, two groups of three wide bandgap power semiconductor chips (totaling six chips), three power terminals, four drive terminals, two decoupling capacitors, and two planar interconnect structures.

[0049] The power substrate 100 includes a top metal layer 101, an insulating dielectric layer 102, and a bottom metal layer 103.

[0050] The six wide bandgap power semiconductor chips include a first upper arm wide bandgap power semiconductor chip 201, a second upper arm wide bandgap power semiconductor chip 202, a third upper arm wide bandgap power semiconductor chip 203, a first lower arm wide bandgap power semiconductor chip 204, a second lower arm wide bandgap power semiconductor chip 205, and a third lower arm wide bandgap power semiconductor chip 206.

[0051] The three power terminals include a DC positive power terminal 301, a DC negative power terminal 302, and an AC power terminal 303.

[0052] The four drive terminals include the upper bridge arm source drive terminal 304, the upper bridge arm gate drive terminal 305, the lower bridge arm gate drive terminal 306, and the lower bridge arm source drive terminal 307.

[0053] The two decoupling capacitors include a first decoupling capacitor 401 and a second decoupling capacitor 402.

[0054] The two planar interconnect structures include an upper bridge arm planar interconnect structure 500 and a lower bridge arm planar interconnect structure 600.

[0055] Among them, two planar interconnect structures are set up corresponding to two groups of wide bandgap semiconductor chips, specifically the upper bridge arm planar interconnect structure and the lower bridge arm planar interconnect structure.

[0056] The bottom surfaces of multiple wide bandgap power semiconductor chips connected in series or in parallel are disposed on the top metal layer 101 of the power substrate 100. The surface of each wide bandgap silicon carbide power semiconductor chip is connected to other conductive metal regions on the top metal layer 101 and the surface of other wide bandgap power semiconductor chips through a planar interconnection structure. Multiple power terminals 300 and multiple drive terminals 4 are disposed on the top metal layer 101. Multiple decoupling capacitors are respectively connected to the DC positive metal region 113 and the DC negative metal region 117 of the top metal layer 101.

[0057] It should be noted that this embodiment includes two sets of wide bandgap power semiconductor chips. Each set consists of three wide bandgap power semiconductor chips connected in parallel using silicon carbide MOSFET chips, forming the upper and lower bridge arm switching transistors of a classic half-bridge structure. In actual operation, the wide bandgap power semiconductor chips can be replaced with other types of transistors, such as IGBTs, as needed. Alternatively, the number of parallel chips can be increased or decreased to change the current carrying capacity, or the number of series chips can be increased or decreased to change the voltage withstand capacity. Or, anti-parallel diode chips can be added as needed.

[0058] Please see Figure 1 The power substrate 100 includes, from top to bottom, a top metal layer 101, an insulating dielectric layer 102, and a bottom metal layer 103. The insulating dielectric layer is made of aluminum oxide, aluminum nitride, or silicon nitride. The top metal layer 101 is made of copper and its surface is plated with silver, and the bottom metal layer 103 is made of copper or aluminum and its surface is plated with silver. The top metal layer 101 of the power substrate includes several metal regions, specifically the upper bridge arm Kelvin source metal region 111, the upper bridge arm gate metal region 112, the DC positive metal region 113, the AC metal region 114, the lower bridge arm gate metal region 115, the lower bridge arm Kelvin source metal region 116, and the DC negative metal region 117.

[0059] Please see Figure 2The first upper arm wide bandgap power semiconductor chip 201, the second upper arm wide bandgap power semiconductor chip 202, the third upper arm wide bandgap power semiconductor chip 203, and the DC positive power terminal 301 are disposed in the DC positive metal region 113 on the top metal layer 101, and the DC negative power terminal 302 is disposed in the DC negative metal region 117 on the top metal layer 101; the first lower arm wide bandgap power semiconductor chip 204, the second lower arm wide bandgap power semiconductor chip 205, the third lower arm wide bandgap power semiconductor chip 206, and the AC electrode... Power terminal 303 is disposed in AC electrode metal region 114 on top metal layer 101; upper bridge arm source drive terminal 304 is disposed in upper bridge arm Kelvin source metal region 111 on top metal layer 101; upper bridge arm gate drive terminal 305 is disposed in upper bridge arm gate metal region 112 on top metal layer 101; lower bridge arm gate drive terminal 306 is disposed in lower bridge arm gate metal region 115 on top metal layer 101; lower bridge arm source drive terminal 307 is disposed in lower bridge arm Kelvin source metal region 116 on top metal layer 101.

[0060] The first decoupling capacitor 401 and the second decoupling capacitor 402 are connected to the DC positive metal region 113 and the DC negative metal region 117.

[0061] The gates of the first upper arm wide bandgap power semiconductor chip 201, the second upper arm wide bandgap power semiconductor chip 202, and the third upper arm wide bandgap power semiconductor chip 203 are respectively connected to the upper arm gate metal region 112; the sources of the first upper arm wide bandgap power semiconductor chip 201, the second upper arm wide bandgap power semiconductor chip 202, and the third upper arm wide bandgap power semiconductor chip 203 are respectively connected to the upper arm Kelvin source metal region 111, forming an upper arm drive circuit;

[0062] The gates of the first lower arm wide bandgap power semiconductor chip 204, the second lower arm wide bandgap power semiconductor chip 205, and the third lower arm wide bandgap power semiconductor chip 206 are respectively connected to the lower arm gate metal region 115; the sources of the first lower arm wide bandgap power semiconductor chip 204, the second lower arm wide bandgap power semiconductor chip 205, and the third lower arm wide bandgap power semiconductor chip 206 are respectively connected to the lower arm Kelvin source metal region 116, forming a lower arm drive circuit.

[0063] Please see Figure 3 and Figure 4 The upper bridge arm planar interconnect structure 500 interconnects the sources of the first upper bridge arm wide bandgap power semiconductor chip 201, the second upper bridge arm wide bandgap power semiconductor chip 202, and the third upper bridge arm wide bandgap power semiconductor chip 203, and connects them to the AC electrode metal region 114 of the top metal layer of the power substrate.

[0064] The upper arm planar interconnect structure 500 includes an upper arm first conductive path 501, an upper arm second conductive path 502, an upper arm third conductive path 503, an upper arm fourth conductive path 504, an upper arm fifth conductive path 505, an upper arm sixth conductive path 506, an upper arm seventh conductive path 507, and an upper arm eighth conductive path 508, wherein the upper arm seventh conductive path 507 and the upper arm eighth conductive path 508 together constitute an interconnect conductive path.

[0065] See Figure 3 and Figure 5 The lower bridge arm planar interconnect structure 600 interconnects the sources of the first lower bridge arm wide bandgap power semiconductor chip 204, the second lower bridge arm wide bandgap power semiconductor chip 205, and the third lower bridge arm wide bandgap power semiconductor chip 206, and connects them to the DC negative electrode metal region 117 of the top metal layer of the power substrate.

[0066] The lower bridge arm planar interconnect structure 600 includes a lower bridge arm first conductive path 601, a lower bridge arm second conductive path 602, a lower bridge arm third conductive path 603, a lower bridge arm fourth conductive path 604, a lower bridge arm fifth conductive path 605, and a lower bridge arm sixth conductive path 606, wherein the lower bridge arm first conductive path 601, the lower bridge arm second conductive path 602, the lower bridge arm third conductive path 603, and the lower bridge arm fourth conductive path 604 together constitute an interconnect conductive path.

[0067] The working principle of the wide bandgap semiconductor module packaging structure based on planar interconnection of the present invention is as follows:

[0068] Using planar interconnect structures instead of bonding wires for electrical connections significantly increases the contact area at the connection points and reduces the size of parasitic inductance. The core of this structure lies in interconnecting the sources of power semiconductor chips within the same group using planar interconnects. By coupling the parasitic inductances of the power circuit sources of each chip, the imbalance between the parasitic inductances of the sources of chips within the same group is greatly reduced. This effectively suppresses voltage overshoot during high-frequency switching and achieves dynamic and static current sharing of the module, significantly improving its electrical reliability. The top and bottom metal layers of the power substrate, power terminals, drive terminals, and the surface of the planar interconnect structure are all silver-plated, significantly improving the oxidation resistance of the metals at low temperatures. Furthermore, the silver plating facilitates the use of nano-silver sintering technology, further enhancing the module's high-temperature resistance.

[0069] This invention realizes a half-bridge structure, which (consisting of one or more structures connected in series and parallel) can form, but is not limited to, various power electronic conversion circuits such as three-phase inverter full-bridge circuits, synchronous rectifiers, and single-phase inverter full-bridge circuits.

[0070] In finite element simulation software, the planar interconnect structure proposed in this invention was compared with that of traditional bonded wire connections. The results showed that the source parasitic inductance range and mean values ​​for bonded wire connections were 2.73 nH and 8.62 nH, respectively, while those for planar interconnects were 0.49 nH and 5.19 nH, significantly reducing the imbalance and magnitude of parasitic inductance. In the simulation of a high-current module with 18 chips connected in parallel, the current imbalance among the chips was 22% in the planar interconnect structure, significantly lower than the 76% in the bonded wire connection structure. The simulation demonstrates that the electrical connection structure based on planar interconnects can effectively achieve current sharing among the chips.

[0071] In summary, the present invention provides a wide bandgap semiconductor module packaging structure based on planar interconnects. It uses the concept and technology of planar interconnects to replace bonding wires for connecting the chip and the power substrate metal layer. This can significantly reduce the imbalance of parasitic inductance while reducing the size of the parasitic inductance of the power source. It is particularly suitable for and can effectively solve the current sharing problem of parallel chips in high-current modules.

[0072] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A wide bandgap semiconductor module packaging structure based on planar interconnects, characterized in that, The device includes several wide-bandgap power semiconductor chips connected in series or in parallel. The bottom surfaces of the wide-bandgap power semiconductor chips are disposed on the top metal layer (101) of the power substrate (100). The surfaces of the wide-bandgap silicon carbide power semiconductor chips are connected to the conductive metal regions disposed on the top metal layer (101) and the surfaces of other wide-bandgap power semiconductor chips through a planar interconnect structure, without the need for bonding wires. Power terminals and drive terminals are disposed on the top metal layer (101). The DC positive metal region (113) and DC negative metal region (117) of the top metal layer (101) are respectively connected to decoupling capacitors. The surfaces of the power substrate (100), power terminals, drive terminals and planar interconnect structure are silver plated. An upper bridge arm gate metal region (112) and an upper bridge arm Kelvin source metal region (111) are provided on one side of the DC positive metal region (113). An AC electrode metal region (114), a lower bridge arm gate metal region (115), and a lower bridge arm Kelvin source metal region (116) are provided between the DC positive metal region (113) and the DC negative metal region (117). The planar interconnect structure includes an upper bridge arm planar interconnect structure (500) and a lower bridge arm planar interconnect structure (600). The upper bridge arm planar interconnect structure (500) interconnects the sources of the upper bridge arm wide bandgap power semiconductor chip and connects them to the AC electrode metal region (114). The lower bridge arm planar interconnect structure (600) interconnects the sources of the lower bridge arm wide bandgap power semiconductor chip and connects them to the DC negative electrode metal region (117). The wide bandgap silicon carbide power semiconductor chip includes several semiconductor chips, which are divided into two groups. The semiconductor chips in each group are connected in parallel. The series connection of the semiconductor chips between the two groups forms the upper and lower arms of a typical half-bridge structure. The semiconductor chips in the same group have the same spacing. The upper arm planar interconnect structure (500) includes the upper arm seventh conductive path (507) and the upper arm eighth conductive path (508). One end of the upper arm seventh conductive path (507) and the upper arm eighth conductive path (508) are respectively connected to the corresponding upper arm wide bandgap power semiconductor chip through several upper arm conductive paths, and the other end is respectively connected to the AC electrode metal region (114) through several upper arm conductive paths. The lower arm planar interconnection structure (600) includes a lower arm first conductive path (601), a lower arm second conductive path (602), a lower arm third conductive path (603), and a lower arm fourth conductive path (604) that are interconnected. The lower arm first conductive path (601) and the lower arm second conductive path (602) are connected to the DC negative metal region (117) through the lower arm fifth conductive path (605). The lower arm third conductive path (603) and the lower arm fourth conductive path (604) are connected to the DC negative metal region (117) through the lower arm planar sixth conductive path (606).

2. The wide bandgap semiconductor module packaging structure based on planar interconnection according to claim 1, characterized in that, The wide bandgap silicon carbide power semiconductor chip includes multiple upper-arm wide bandgap power semiconductor chips and corresponding lower-arm wide bandgap power semiconductor chips. The upper-arm wide bandgap power semiconductor chips are disposed on the DC positive electrode metal region (113). The gates of the upper-arm wide bandgap power semiconductor chips are connected to the upper-arm gate metal region (112), and the sources of the upper-arm wide bandgap power semiconductor chips are connected to the upper-arm Kelvin source metal region (111). The lower-arm wide bandgap power semiconductor chips are disposed on the AC electrode metal region (114). The gates of the lower-arm wide bandgap power semiconductor chips are connected to the lower-arm gate metal region (115), and the sources of the upper-arm wide bandgap power semiconductor chips are connected to the lower-arm Kelvin source metal region (116).

3. The wide bandgap semiconductor module packaging structure based on planar interconnection according to claim 1, characterized in that, The driving terminals include an upper bridge arm source driving terminal (304), an upper bridge arm gate driving terminal (305), a lower bridge arm gate driving terminal (306), and a lower bridge arm source driving terminal (307). The upper bridge arm source driving terminal (304) is located in the upper bridge arm Kelvin source metal region (111), the upper bridge arm gate driving terminal (305) is located in the upper bridge arm gate metal region (112), the lower bridge arm gate driving terminal (306) is located in the lower bridge arm gate metal region (115), and the lower bridge arm source driving terminal (307) is located in the lower bridge arm Kelvin source metal region (116).

4. The wide bandgap semiconductor module packaging structure based on planar interconnection according to claim 1, characterized in that, The power terminals include a DC positive power terminal (301), a DC negative power terminal (302), and an AC power terminal (303). The DC positive power terminal (301) is located in the DC positive metal region (113), the DC negative power terminal (302) is located in the DC negative metal region (117), and the AC power terminal (303) is located in the AC metal region (114).

5. The wide bandgap semiconductor module packaging structure based on planar interconnection according to claim 1, characterized in that, The decoupling capacitors include a first decoupling capacitor (401) and a second decoupling capacitor (402). The DC positive metal region (113) is connected to the DC negative metal region (117) through the first decoupling capacitor (401) and the second decoupling capacitor (402).

6. The wide bandgap semiconductor module packaging structure based on planar interconnect according to claim 1, characterized in that, An insulating dielectric layer (102) and a bottom metal layer (103) are sequentially disposed on the lower side of the top metal layer (101).

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