Forked-piece device with dielectric ridges at cell boundaries

Abstract

Techniques are provided herein for forming a semiconductor device having a cell including a forked device having source or drain regions of the same dopant type on both sides of a forked dielectric ridge. The techniques may be used in any number of integrated circuit applications, and are particularly useful for logic and memory cells. The forked device may include all p-type source or drain regions on both sides of the dielectric ridge or all n-type source or drain regions on both sides of the dielectric ridge. Using forked devices having the same dopant type allows both forked transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be positioned along the forked dielectric ridges rather than along the gate cuts, which provides greater flexibility in designing multi-height cells.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and in particular, to forksheet devices. Background Art

[0002] As the size of integrated circuits continues to shrink downward, many challenges arise. For example, reducing the size of memory and logic cells becomes increasingly difficult, especially given the competing interests in a relatively small amount of space. For example, the repeating unit of a device (often referred to as a cell or standard cell) may impose restrictions on the placement of certain transistor structures that do not maximize the available footprint on a given die. Therefore, there are still many challenges that are difficult to ignore with respect to designing the layout of the various cells of an integrated circuit structure to improve PPA (power, performance, and area) performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a plan view of a standard cell having a dielectric ridge portion of a fork-flap transistor at the cell boundary according to an embodiment of the present disclosure.

[0004] Figure 1B is a plan view of multiple adjacent standard cells having dielectric ridges for fork-flap transistors at cell boundaries with the same dopant type on both sides of a given ridge according to an embodiment of the present disclosure.

[0005] Figure 1C is a through-hole according to an embodiment of the present disclosure Figure 1B Cross-sectional view of gate trenches of multiple adjacent standard cells showing dielectric ridges of a fork-piece device with intra-cell gate cutouts at the cell boundaries.

[0006] Figure 2A is a plan view of another cell architecture including a fork-sheet device and a gate-all-around (GAA) device according to an embodiment of the present disclosure.

[0007] Figure 2B is a through-hole according to an embodiment of the present disclosure Figure 2A Cross-sectional view of the gate trench of a cell architecture showing a fork-piece device and a GAA device with a gate cut between them.

[0008] Figure 3A is a plan view of another multi-cell architecture including a fork-sheet device and a gate-all-around (GAA) device according to an embodiment of the present disclosure.

[0009] Figure 3B and Figure 3C According to the embodiment of the present disclosure Figure 3AAn isometric view of the cell architecture showing the fork-sheet and GAA devices overlapping each other along the width of the cell.

[0010] Figures 4A-4G is a cross-sectional diagram illustrating stages in an example process for forming an integrated circuit configured with both fork blades and GAA devices according to some embodiments of the present disclosure.

[0011] Figure 5 A cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0012] Figure 6 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0013] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent in light of the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the particular configurations shown. For example, although some of the figures generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topology or otherwise be non-smooth, given the real-world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0014] Provided herein are techniques for forming a semiconductor device having a cell including a fork-piece device having source or drain regions of the same dopant type on both sides of a fork-piece dielectric ridge. The techniques can be used in any number of integrated circuit applications and are particularly useful for logic and memory cells. The fork-piece device can include all p-type source or drain regions on both sides of the dielectric ridge or all n-type source or drain regions on both sides of the dielectric ridge. The use of fork-piece devices having the same dopant type allows fork-piece transistors and full-all-around gate (GAA) transistors to be included in the same cell. Cell boundaries can also be placed along the fork-piece dielectric ridge rather than along the gate cut, which provides greater flexibility in designing multi-height cells. Many variations and embodiments will be apparent in light of this disclosure.

[0015] General Overview

[0016] As mentioned above, there are still many challenges that are difficult to ignore regarding the formation of various semiconductor structures. Fork-sheet devices (also known as forkFET devices) include a dielectric ridge extending down the middle of a nanoribbon, thereby dividing the nanoribbon into nanosheets on either side of the dielectric ridge. Standard cell architectures that only include fork-sheet devices can limit the maximum drive of each gate in a given cell. Existing architectures also limit the minimum cell height.

[0017] Therefore, and in accordance with embodiments of the present disclosure, techniques are provided herein for forming a standard cell architecture having a fork-piece device having the same dopant type (e.g., n-type or p-type) on both sides of a dielectric ridge. This allows fork-piece ridges to be placed along cell boundaries and opens up the possibility of including GAA devices within multi-height cells. Including both fork-piece devices and GAA devices in the same cell arrangement can provide the benefits of both types of devices (e.g., significant drive boost using GAA devices and smaller parasitic capacitance using fork-piece devices).

[0018] According to some embodiments, each fork-piece device is designed to have only n-type source or drain regions or only p-type source or drain regions on both sides of the dielectric ridge. The n-type source or drain region may include silicon doped with an n-type dopant, such as phosphorus. The p-type source or drain region may include silicon germanium doped with a p-type dopant, such as boron. According to some embodiments, some cell designs may combine both fork-piece devices and GAA devices by forming one or more fork-piece devices without a dielectric ridge, thereby creating a wide channel GAA device. In some examples, the dielectric ridge continues along the width of a first number of cells, but does not continue along the width of a second number of cells in the same row of cells. Thus, the first number of cells includes fork-piece devices along the dielectric ridge, and the second number of cells includes GAA devices aligned with the fork-piece devices along the width direction of the cells.

[0019] According to an embodiment, an integrated circuit includes a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction, and a first gate structure extending above the first semiconductor region in a second direction. The integrated circuit also includes a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction, and a second gate structure extending above the second semiconductor region in the second direction. The second source or drain region is adjacent to the first source or drain region along the second direction. The integrated circuit also includes a dielectric wall extending between and contacting both the first semiconductor region and the second semiconductor region in the first direction, and extending between the first source or drain region and the second source or drain region in the first direction. Both the first source or drain region and the second source or drain region have n-type dopants, or both have p-type dopants.

[0020] According to another embodiment, an integrated circuit includes: a first semiconductor device, the first semiconductor device having a first semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, and a first gate structure extending over the first semiconductor region in a second direction; a first dielectric wall, the first dielectric wall extending in the first direction and contacting the first semiconductor region, and extending adjacent to both the first source or drain region and the second source or drain region in the first direction; a second dielectric wall, the second dielectric wall extending in the first direction and adjacent to the first semiconductor device, such that the first gate structure extends from the first dielectric wall to the second dielectric wall in the second direction; and a second semiconductor device, the second semiconductor device having a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the first direction, and a second gate structure extending from the second dielectric wall in the second direction and surrounding the second semiconductor region.

[0021] According to another embodiment, an integrated circuit includes a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction, and a first gate structure extending above the first semiconductor region in a second direction. The integrated circuit also includes a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction, and a second gate structure extending above the second semiconductor region in the second direction. The second source or drain region is adjacent to the first source or drain region along the second direction. The integrated circuit also includes a third semiconductor device having a third semiconductor region extending from a third source or drain region in the first direction and collinearly with the first semiconductor region and the second semiconductor region, and a third gate structure extending above the third semiconductor region in the second direction. The third gate structure is spaced apart from the first gate structure and the second gate structure in the first direction. The integrated circuit also includes a dielectric wall extending between and contacting both the first semiconductor region and the second semiconductor region in the first direction, and extending between the first source or drain region and the second source or drain region in the first direction. The dielectric wall does not intersect the third semiconductor region.

[0022] These techniques can be used with any type of non-planar transistor, including FinFETs (sometimes called dual-gate transistors or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called full-ring gate transistors), or forkFETs, to name a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate first process or a gate last process (sometimes called a replacement metal gate or RMG process), or any other gate formation process. Any number of semiconductor materials can be used to form transistors, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0023] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable example analytical tools. For example, in some example embodiments, such a tool may indicate the use of a fork-piece device, wherein each of the source or drain regions of the fork-piece device has the same dopant distribution (n-type or p-type) on both sides of the fork-piece dielectric ridge. In some examples, such a tool may indicate the presence of both a fork-piece device and a GAA device within the same repeating unit architecture. Many configurations and variations will be apparent in light of the present disclosure.

[0024] It should be readily understood that the meaning of "above" and "above" in the present disclosure should be interpreted in the broadest manner, so that "above" and "above" not only mean "directly on something", but also include the meaning of something above with intermediate features or layers therebetween. In addition, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe the relationship between an element or feature as shown in the figure and another (one or more) element or feature. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0025] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A monolayer is a layer consisting of a monolayer of atoms of a given material. A layer may extend over the entire underlying or superstructure, or may have an extent less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or heterogeneous continuous structure, wherein the thickness of the layer is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved) and have a relatively uniform thickness over the entire layer.

[0026] As used herein, "compositionally different" or "compositionally dissimilar" materials refer to two materials having different chemical compositions. This compositional difference can be, for example, due to an element in one material that is not in the other (e.g., SiGe is compositionally different from silicon), or by one material having all of the same elements as a second material, but at least one of these elements is intentionally provided in a different concentration in one material relative to the other material (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this chemical composition diversity, the materials can also have different dopants (e.g., gallium and magnesium), or the same dopants but in different concentrations. In other embodiments, compositionally different materials can further refer to two materials having different crystallographic orientations. For example, (110) silicon is compositionally dissimilar or different from (100) silicon. Creating stacks of different orientations can be achieved, for example, using blanket wafer layer transfer. If two materials are elementally different, one of the materials has an element that is not in the other material.

[0027] Architecture

[0028] Figure 1A 1 is a plan view of a standard cell 102 within an integrated circuit structure according to some embodiments. Cell 102 may be arranged adjacent to any number of other similar cells in a row and column array, where a cell boundary is identified by an edge of cell 102, as shown in FIG1 . It should be understood that a cell boundary does not refer to a specific structure, but rather identifies a demarcation between repeated transistor arrangements. According to some embodiments, each repeated cell 102 contains the same transistor structure arrangement.

[0029] According to some embodiments, a given cell 102 includes at least two transistor devices. In some examples, the cell 102 includes parallel gate structures 104a-104e extending longitudinally along a first direction (e.g., along the height direction of the cell). In some examples, the gate structures 104a and 104e can be dummy structures or can be replaced with dielectric materials, because these structures can act as barriers to separate adjacent cells along a given row of cells. The gate structures 104a-104e can be interrupted by a gate cut 106 extending longitudinally along a second direction different from the first direction (e.g., orthogonal to the first direction or along the width direction of the cell). The gate cut 106 can be any suitable dielectric material to electrically isolate the structures on either side of the gate cut 106 from each other. Therefore, the cell 102 includes six separate gate structures (on both sides of the gate cut 106), and therefore includes six transistors.

[0030] In accordance with some embodiments, the top three transistors are part of a first plurality of fork-piece structures, each fork-piece structure comprising a first dielectric ridge 108a extending longitudinally along a second direction, and the bottom transistors are part of a second plurality of fork-piece structures, each fork-piece structure comprising a second dielectric ridge 108b extending longitudinally along the second direction. The dielectric ridges 108a / 108b may be any suitable dielectric material, and may be the same dielectric material as the gate cutout 106. The dielectric ridges 108a / 108b may comprise silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or spin-on glass, to name a few examples. In accordance with some embodiments, the top three transistors include a gate structure extending over a corresponding semiconductor body, which itself extends in the second direction between a corresponding first source or drain region 110. In accordance with some embodiments, the bottom three transistors include a gate structure extending over a corresponding semiconductor body, which itself extends in the second direction between a corresponding second source or drain region 112. The first source or drain region 110 is either all n-type or all p-type, and the second source or drain region is either all n-type or all p-type. According to some embodiments, the first source or drain region 110 has an opposite dopant type compared to the second source or drain region 112 .

[0031] According to some embodiments, due to the repetitive nature of the cells 102 on the cell array, the first plurality of fork-piece structures includes another set of transistors on the opposite side of the first dielectric ridge 108a, which have a source or drain region with the same dopant type as the first source or drain region 110. Similarly, the second plurality of fork-piece structures includes another set of transistors on the opposite side of the second dielectric ridge 108b, which have a source or drain region with the same dopant type as the second source or drain region 112. This can be Figure 1B and Figure 1C More clearly seen in Figure 1B and Figure 1C A plan view of a portion of a cell array and a cross-sectional view along a gate trench of the cell array are shown, respectively. Cell boundaries are identified with dashed lines between each of the cells 102A-102C.

[0032] exist Figure 1BIn the example shown, according to some embodiments, a first transistor 114a on one side of a first dielectric ridge 108a and a second transistor 114b on the opposite side of the first dielectric ridge 108a are part of a single fork-piece structure that spans the cell boundary between cells 102b and 102c. The source or drain regions 110 of both the first transistor 114a and the second transistor 114b share the same dopant type (n-type or p-type). According to some embodiments, fork-piece structures having one type of source or drain regions alternate with fork-piece structures having another type of source or drain regions along a first direction. For example, according to some embodiments, in the example shown, a third transistor 116a on one side of a second dielectric ridge 108b and a second transistor 116b on the opposite side of the second dielectric ridge 108b are part of a single fork-piece structure that spans the cell boundary between cells 102b and 102a. The source or drain regions 112 of both the second transistor 116 a and the second transistor 116 b share the same dopant type (n-type or p-type) and may be of the opposite dopant doping as the source or drain region 110 .

[0033] Figure 1C 2 shows a cross-sectional view along a gate trench (eg, along a first direction or cell height direction) through a plurality of cells in a given cell column according to some embodiments, as shown in FIG. Figure 1B , as shown by the bold 1C-1C line in . Various fork-piece structures can be formed above substrate 101. Substrate 101 can be, for example, a bulk substrate including a Group IV semiconductor material (such as silicon, germanium, or silicon germanium), a Group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having a desired semiconductor layer above a buried insulator layer (e.g., silicon above silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating silicon layers and SiGe layers, or alternating indium gallium arsenide layers and indium phosphide layers). Any number of substrates can be used. In some embodiments, substrate 101 is removed and replaced with one or more back-side interconnect layers to form back-side signal and power wiring.

[0034] Each transistor includes a semiconductor body, such as nanosheets 118a-118f, extending in a second direction. Each group of vertical nanosheets represents the semiconductor body of a single transistor. Each transistor may include any number of nanosheets. Although each of the illustrated devices includes 4 nanosheets, in some examples, each device may alternatively include only three nanosheets. According to some embodiments, the gate cut 106 extends through the entire thickness of the gate structure to isolate different gate structures 120a-120f along the first direction. Each gate cut 106 may have a width along the first direction, for example, between about 5nm and about 30nm. Each gate structure 120a-120f extends over the corresponding semiconductor body to form a single transistor. In a configuration such as Figure 1C In the case of the fork-sheet device shown in cross-section, note that the gate structure 120 extends along the upper and lower sides of each nanosheet 118 and along the ends of the nanosheets away from the dielectric ridge. This laterally extending fork-sheet gate structure on the side and end surfaces of the nanosheet-based channel region is similar to the vertically extending finFET gate structure on the side and top surfaces of the fin-based channel region.

[0035] According to some embodiments, the first fork-piece structure 122 includes a nanosheet 118b and a gate structure 120b on one side of the first dielectric ridge 108a, and includes a nanosheet 118c and a gate structure 120c on the opposite side of the first dielectric ridge 108a. Each set of nanosheets 118b and 118c extends between source or drain regions having the same dopant type (n-type or p-type) in the second direction. According to some embodiments, the second fork-piece structure 124 includes a nanosheet 118d and a gate structure 120d on one side of the second dielectric ridge 108b, and includes a nanosheet 118e and a gate structure 120e on the opposite side of the second dielectric ridge 108b. According to some embodiments, each set of nanosheets 118d and 118e extends between source or drain regions in the second direction, the source or drain regions having the same dopant type (n-type or p-type) and being of opposite dopant type compared to the source or drain regions of the first fork-piece structure 122. The cell boundaries may be aligned along the various dielectric ridges of the fork-sheet structure to differentiate the cells along a first direction.

[0036] As discussed above, the arrangement of fork-sheet devices across cell boundaries allows for the integration of both fork-sheet devices and GAA devices within the same cell architecture by removing any number of dielectric ridges. Figure 2AAn example is shown according to an embodiment in which the dielectric ridges along the cell boundaries between cell 202a and cell 202b and between cell 202b and cell 202c are removed to form both a fork-chip device and a GAA device. The resulting structure can provide a larger cell with an extended height (e.g., three times the cell height) between the dielectric ridge 108c and the dielectric ridge 108d of the remaining fork-chip device. Thus, Figure 2A The triple-height cell shown in can be repeated any number of times in an array to form an integrated circuit.

[0037] In accordance with some embodiments, omitting a given fork-sheet dielectric ridge leaves a GAA device 204 between adjacent gate cuts 106a-106c. A cell may also include one or more fork-sheet structures to provide a fork-sheet device such as fork-sheet device 206. More than one GAA device within the same cell may be of different transistor types, and more than one fork-sheet device within the same cell may be of different transistor types. For example, one group of GAA devices may include source or drain regions 208 having the same dopant type (n-type or p-type), while another group of GAA devices may include source or drain regions 210 having the opposite dopant type. Similarly, one group of fork-sheet devices may include source or drain regions 212 having the same dopant type (n-type or p-type), while another group of fork-sheet devices may include source or drain regions 214 having the opposite dopant type.

[0038] Figure 2B 2 shows a cross-sectional view along a gate trench (eg, along a first direction or cell height direction) through a plurality of cells in a given cell column according to some embodiments, as shown in FIG. Figure 2A2B-2B line in FIG. Several nanosheets (part of the fork-sheet device) and nanoribbons (part of the GAA device) can be seen along the height of the cell. For example, nanosheet 216 extends (in and out of the page) between corresponding source or drain regions as part of a fork-sheet device 206 having a dielectric ridge 108d and a gate structure 224a. The gate structure 224a can extend between the dielectric ridge 108d and the adjacent gate cutout 106a along a first direction. According to some embodiments, the GAA device 204 can be arranged on the opposite side of the gate cutout 106a. Thus, a set of nanoribbons 218 extends (in and out of the page) between corresponding source or drain regions as part of a GAA device 204 having a gate structure 224b. The gate structure 224b extends in the first direction between the gate cutout 106b and the gate cutout 106c and completely around the nanoribbon 218. Similar transistor structures can be repeated within the cell, as shown, with nanoribbons 220 and nanosheets 222. Each transistor may include any number of nanosheets (for forked-sheet devices) or nanoribbons (for GAA devices). Although each of the illustrated devices includes four nanosheets / nanoribbons, in some examples, each device may instead include only three nanosheets / nanoribbons.

[0039] According to some embodiments, a given dielectric ridge may extend across some cell widths but not across other cell widths in the second direction, which forms a GAA device that is aligned with the fork-sheet device in the second direction. Figure 3A A plan view of an example array of four cells 302a-302d in a 2×2 arrangement is shown. In some examples, the arrangement shown can be repeated as a single cell having double height and double width. The top cell boundary and the bottom cell boundary of the arrangement shown can include dielectric ridges 303a and 303b that extend across the entire double cell width. According to some embodiments, another dielectric ridge 304 can extend across the boundary between cell 302a and cell 302b along a second direction, but does not continue to extend across the boundary between cell 302c and cell 302d. As a result, a GAA device (such as GAA device 306) is formed across the boundary between cell 302c and cell 302d, and a fork-piece device (such as fork-piece devices 308a and 308b) is formed across the boundary between cell 302a and cell 302b.

[0040] The dummy gate structure 310 may extend between the GAA device 306 and the fork blade devices 308a and 308b. In some examples, the dielectric ridge 304 may extend partially into the dummy gate structure 310 in the second direction. According to some embodiments, the dummy gate structure 310 may be partially or completely replaced with a dielectric material.

[0041] The GAA device 306 includes a gate structure 312 extending above a semiconductor nanoribbon in a first direction, and the semiconductor nanoribbon extends between corresponding source and drain regions in a second direction. The first fork-piece device 308a includes a gate structure 314a extending above a first semiconductor nanosheet, the first semiconductor nanosheet extending between corresponding source and drain regions in a second direction, and the second fork-piece device 308b includes a gate structure 314b extending above a second semiconductor nanosheet, the second semiconductor nanosheet extending between corresponding source and drain regions in the second direction. According to some embodiments, the nanoribbon of the GAA device 306 extends along the second direction and in line with the nanosheets of the first fork-piece device 308a and the second fork-piece device 308b. In addition, each of the first fork-piece device 308a and the second fork-piece device 308b and the corresponding source or drain region of the GAA device 306 have the same dopant type (e.g., all n-type or all p-type).

[0042] Figure 3B and Figure 3C Shows Figure 3A , which shows a GAA device 306 and fork-piece devices 308A and 308B. In accordance with some embodiments, the dielectric ridge 304 extends in a second direction across the various gate structures and also across the sets of diffusion contacts 316 and spacer structures 318. The diffusion contacts 316 include any suitable conductive material that provides ohmic contact to the underlying source or drain region 320. In some examples, the diffusion contacts 316 include any of tungsten, ruthenium, molybdenum, or cobalt. The spacer structure 318 includes any suitable dielectric material to separate the source / drain trench (having the source or drain region and the diffusion contact) from the gate trench (having the gate structure). In some examples, the spacer structure 318 includes any of silicon dioxide, silicon nitride, or silicon oxynitride.

[0043] According to some embodiments, the GAA device 306 includes a set of nanoribbons 307 with a gate structure 312 extending along a first direction and completely around the nanoribbons 307. According to some embodiments, the first fork-piece device 308a includes a first set of nanosheets 309a with a gate structure 314a extending partially over the nanosheets 309a in the first direction until the dielectric ridge 304, and the second fork-piece device 308b includes a second set of nanosheets 309b with a gate structure 314b extending partially over the nanosheets 309b in the first direction until the dielectric ridge 304. According to some embodiments, the nanoribbon 307 is an extension of the nanosheets 309a and 309b, such that the nanoribbon 307 extends in the second direction in line with the nanosheets 309a and 309b. In addition, the width of the nanoribbon 307 along the first direction is substantially equal to the combined width of the nanosheets 309a, the nanosheets 309b, and the dielectric ridge 304 along the first direction. Each transistor may include any number of nanosheets (for forked-sheet devices) or nanoribbons (for GAA devices). Although each of the illustrated devices includes four nanosheets / nanoribbons, in some examples, each device may instead include only three nanosheets / nanoribbons.

[0044] Manufacturing method

[0045] Figures 4A-4G are cross-sectional views collectively illustrating an example process for forming an integrated circuit having a unit cell including both a GAA device and a fork-sheet device according to an embodiment of the present disclosure. The accompanying drawings represent cross-sectional views taken along a first direction through a given gate trench that spans multiple devices within a multi-height unit. Each figure illustrates an example structure resulting from a process flow up to that point in time, and thus the illustrated structure evolves as the process flow continues, ultimately reaching Figure 4G The structure shown. Such a structure may be part of an entire integrated circuit (e.g., a processor or memory chip) including, for example, digital logic cells and / or memory cells and analog mixed-signal circuitry. Thus, the integrated circuit structure shown may be part of a larger integrated circuit including other integrated circuit systems not shown. Example materials and process parameters are given, but as will be understood, the present disclosure is not intended to be limited to any particular such materials or parameters.

[0046] Figure 4A A cross-sectional view of multiple material layers formed over a substrate according to an embodiment of the present disclosure is shown. Alternating material layers may be deposited over a substrate 401, including sacrificial layers 402 alternating with semiconductor layers 404. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 404 and sacrificial layers 402 may be deposited over the substrate 401.

[0047] According to some embodiments, sacrificial layer 402 has a different material composition than semiconductor layer 404. In some embodiments, sacrificial layer 402 is silicon germanium (SiGe), while semiconductor layer 404 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material, such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layer 402 and semiconductor layer 404, the germanium concentration between sacrificial layer 402 and semiconductor layer 404 is different. For example, sacrificial layer 402 can include a higher germanium content than semiconductor layer 404. In some examples, semiconductor layer 404 can be doped with an n-type dopant (to produce a p-channel transistor) or a p-type dopant (to produce an n-channel transistor).

[0048] Although the dimensions may vary between different example embodiments, the thickness of each sacrificial layer 402 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 402 is substantially the same (e.g., within 1-2 nm). The thickness of each semiconductor layer 404 may be substantially the same as the thickness of each sacrificial layer 402 (e.g., about 5-20 nm). Each of the sacrificial layer 402 and the semiconductor layer 404 may be deposited using any known material deposition technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0049] Figure 4B FIG. 4 shows a structure after forming a capping layer 405 and subsequently forming a fin under the capping layer 405 according to an embodiment. Figure 4A . The capping layer 405 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The capping layer 405 is patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layer 402 and semiconductor layer 404. The rows of fins extend longitudinally in a second direction (e.g., into and out of the page of each cross-sectional view).

[0050] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of substrate 401, wherein the unetched portion of substrate 401 below the fin forms a sub-fin region 406. The etched portion of substrate 401 may be filled with a dielectric filler 408, which acts as a shallow trench isolation (STI) between adjacent fins. Dielectric filler 408 may be any suitable dielectric material, such as silicon dioxide, and may be recessed to the desired depth shown (in this example case, down to around the upper surface of sub-fin region 406) to define the active portion of the fin that will be covered by the gate structure. In some embodiments, dielectric filler 408 is recessed below the top surface of sub-fin region 406.

[0051] Figure 4C FIG. 4 shows a schematic diagram of a fin after forming a sacrificial gate 410 extending across the fin in a second direction different from the first direction in accordance with some embodiments. Figure 4B . A sacrificial gate 410 may extend across the fin in a first direction orthogonal to the second direction. According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and is removed in all areas not protected by the gate mask layer. The sacrificial gate 410 may be any suitable material that may be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 410 comprises polysilicon.

[0052] The sacrificial gate 410 (along with any gate spacers formed on the sidewalls of the sacrificial gate 410) protects the underlying portion of the fin while etching away the exposed portion of the fin between the gate spacers. In accordance with some embodiments, both the semiconductor layer 404 and the sacrificial layer 402 are etched at substantially the same rate using an anisotropic RIE process to form source / drain trenches. In some embodiments, the inner gate spacer can be formed after etching the source / drain trenches and before any formation of the source or drain regions. For example, a selective etch can be used to laterally recess the sacrificial layer 402, which can then be filled with an inner gate spacer material (e.g., silicon nitride or silicon oxynitride). Any excess gate spacer material can be removed using a directional etch.

[0053] According to some embodiments, a source or drain region is formed after forming the sacrificial gate 410. The source or drain regions are not shown in this cross section because they will exist at the ends of the semiconductor layer 404 that enter and exit the page. According to some embodiments, the source or drain region can be epitaxially grown from the exposed ends of the semiconductor layer 404 so that the materials grow together or otherwise merge toward the middle of the trench between the fins. Note that the epitaxial growth on one semiconductor layer 404 can be completely or partially merged with the epitaxial growth on one or more other semiconductor layers 404 in the same vertical stack. The extent of any such merger can vary between different embodiments. In the example of a PMOS device, a given source or drain region can be a semiconductor material (e.g., a group IV or group III-V semiconductor material) having a p-type dopant with a higher dopant concentration than an n-type dopant. In the example of an NMOS device, a given source or drain region can be a semiconductor material (e.g., a group IV or group III-V semiconductor material) having an n-type dopant with a higher dopant concentration than a p-type dopant. According to some embodiments, source or drain regions grown from different semiconductor devices may be aligned along source / drain trenches in a first direction.

[0054] Figure 4D FIG. 4 shows a schematic diagram of a semiconductor layer 404 after forming nanoribbons 412 from semiconductor layer 404 according to some embodiments. Figure 4C 4 is a cross-sectional view of the structure shown in . Depending on the size of the structure, the nanoribbon 412 may also be considered a nanowire or a nanosheet. The sacrificial gate 410 may be removed using any wet or dry isotropic process to expose the alternating layer stack of fins within the trench left after the sacrificial gate 410 is removed. Once the sacrificial gate 410 is removed, the sacrificial layer 402 may also be removed using a selective isotropic etching process that removes the material of the sacrificial layer 402 but does not remove (or removes very little) the semiconductor layer 404 or any other exposed layer (e.g., an inner gate spacer). At this point, the suspended (sometimes referred to as released) semiconductor layer 404 forms a nanoribbon 412 that extends between the corresponding source or drain regions in the second direction (in and out of the page).

[0055] Figure 4E FIG. 4 shows a gate structure after forming a gate structure around the nanoribbon 412 in the gate trench according to some embodiments. Figure 4D4. As described above, the gate structure includes a gate dielectric 414 and a gate electrode 416. The gate dielectric 414 may be conformally deposited around the nanoribbon 412 using any suitable deposition process, such as atomic layer deposition (ALD). The gate dielectric 414 may include any suitable dielectric, such as silicon dioxide and / or a high-k dielectric material. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, just to provide some examples. According to some embodiments, the gate dielectric 414 is a hafnium oxide having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 414 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some examples, the gate dielectric 414 may be a multilayer structure. For example, gate dielectric 414 may include a first layer on nanoribbon 412 and a second layer on the first layer. The first layer may be, for example, an oxide of a semiconductor layer (e.g., silicon dioxide), and the second layer may be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, when a high-k dielectric material is used, an annealing process may be performed on gate dielectric 414 to improve its quality. In some embodiments, the high-k material may be nitrided to improve its aging resistance.

[0056] The gate electrode 416 can be deposited above the gate dielectric 414 and can be any conductive structure. In some embodiments, the gate electrode 416 includes doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. The gate electrode 416 can include, for example, one or more work function layers, a resistance reduction layer, and / or a barrier layer. The work function layer can include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate, or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate.

[0057] According to some embodiments, any number of GAA devices may be formed along a given gate trench. In the example shown, GAA devices 413a-413d having the same gate structure are formed. Each of the GAA devices 413a-413d may have substantially the same size, but may have a source or drain region with a different dopant profile (e.g., n-type or p-type).

[0058] Figure 4F FIG. 4 shows the structure after deep grooves 417 and 418 are formed in the entire structure according to some embodiments. Figure 4E. Both grooves 417 and 418 can be grooves extending across any number of adjacent cells along a second direction. According to some embodiments, the first groove 417 extends through the corresponding set of nanoribbons in a third direction to form nanosheets, such as nanosheets 412a, 412c, and 412d. According to some embodiments, the second groove 418 extends through the gate structure between the devices in the third direction to separate different devices from each other along the first direction. The third direction can be orthogonal to the first direction and the second direction (e.g., along the Z direction). According to some embodiments, due to the position of the first groove 417 and the second groove 418, GAA devices 413b and 413d can remain intact, while other GAA devices have been divided into corresponding fork-sheet devices 420, 422, and 424.

[0059] According to some embodiments, the first recess 417 and the second recess 418 also separate the gate structure along the first direction into different gate structures having corresponding gate electrodes 416a-416e surrounding the gate dielectric 414. The first recess 417 and the second recess 418 can be formed simultaneously using a reactive ion etching (RIE) process to cut through various materials (while protecting other areas using a patterned mask layer). In other examples, the first recess 417 is formed using a first RIE process and a first mask layer, and the second recess 418 is formed at a later time using a second RIE process and a second mask layer (or vice versa). Each of the first recess 417 and the second recess 418 can extend through at least the entire thickness of the gate structure in the third direction, and can also extend through the entire thickness of the dielectric filler 408. Therefore, the first recess 417 and / or the second recess 418 can extend into a portion of the underlying substrate 401.

[0060] Figure 4G FIG. 4 shows a dielectric ridge 426 formed in the first groove 417 and a gate cutout 428 formed in the second groove 418 in accordance with some embodiments. Figure 4F 4. A cross-sectional view of the structure shown in FIG. 4. Dielectric ridge 426 provides isolation between corresponding fork-sheet devices that are directly adjacent to opposite sides of dielectric ridge 426. Thus, nanosheet 412a is directly adjacent to first dielectric ridge 426a, nanosheet 412c is directly adjacent to one side of second dielectric ridge 426b, and nanosheet 412d is directly adjacent to the opposite side of second dielectric ridge 426b. Gate cutout 428 can be used to separate adjacent devices from each other along a first direction.

[0061] Each of the dielectric ridge 426 and the gate cutout 428 can be filled with one or more dielectric materials. In some examples, the dielectric ridge 426 and the gate cutout 428 include the same dielectric material and are filled during the same one or more dielectric deposition processes. In some embodiments, the gate cutout 428 includes a different dielectric material than the dielectric ridge 426. For example, the gate cutout 428 can include silicon nitride and the dielectric ridge 426 can include silicon dioxide. In some examples, the dielectric ridge 426 can include any of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or spin-on glass. In some examples, the gate cutout 428 includes a first dielectric layer deposited first and a second dielectric layer or dielectric filler formed on the first dielectric layer. The first dielectric layer may include a high-k dielectric material (e.g., a material having a dielectric constant higher than that of silicon oxide or higher than 3.9), and the second dielectric layer may include a low-k dielectric material (e.g., a material having a dielectric constant equal to or lower than that of silicon oxide, such as porous silicon oxide, or a material having a dielectric constant equal to or lower than 3.9).

[0062] Figure 5 An example embodiment of a chip package 500 according to an embodiment of the present disclosure is shown. As can be seen, the chip package 500 includes one or more dies 502. The one or more dies 502 may include at least one integrated circuit having a semiconductor device (e.g., any of the semiconductor devices disclosed herein). In some example configurations, the one or more dies 502 may include any other circuitry for interfacing with other devices formed on the die or connected to the chip package 500.

[0063] As can be further seen, the chip package 500 includes a housing 504 bonded to a package substrate 506. The housing 504 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 500. One or more dies 502 can be conductively coupled to the package substrate 506 using a connection 508, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonding, to name a few examples. The package substrate 506 can be any standard or proprietary package substrate, but in some cases includes a dielectric material with conductive paths (e.g., including conductive vias and lines) extending through the dielectric material between the faces of the package substrate 506 or between different locations on each face. In some embodiments, the package substrate 506 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 512 can be provided at the opposite face of the package substrate 506 for conductively contacting, for example, a printed circuit board (PCB). One or more vias 510 extend through the thickness of the package substrate 506 to provide a conductive path between one or more connections 508 to one or more contacts 512. For ease of illustration, the vias 510 are shown as a single inline through the package substrate 506, although other configurations may be used (e.g., inlays, dual inlays, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 506 to contact one or more intermediate locations therein). In other embodiments, the vias 510 are made of multiple smaller stacked vias, or are staggered at different locations on the package substrate 506. In the illustrated embodiment, the contacts 512 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package engagement mechanism may be used (e.g., pins in a pin grid array arrangement, or lands in a land grid array arrangement). In some embodiments, solder resist is provided between the contacts 512 to inhibit shorting.

[0064] In some embodiments, molding material 514 can be disposed around one or more dies 502 included within housing 504 (e.g., as an underfill material between die 502 and package substrate 506, and as an overfill material between die 502 and housing 504). Although the size and mass of molding material 514 can vary between different embodiments, in some embodiments, the thickness of molding material 514 is less than 1 millimeter. Example materials that can be used for molding material 514 include epoxy molding materials, as appropriate. In some cases, in addition to being electrically insulating, molding material 514 is thermally conductive.

[0065] Example System

[0066] Figure 6 600 is an example computing system implemented using one or more of the integrated circuit structures as disclosed herein according to some embodiments of the present disclosure. As can be seen, computing system 600 houses motherboard 602. Motherboard 602 may include multiple components, including but not limited to processor 604 and at least one communication chip 606, each of which may be physically and electrically coupled to motherboard 602, or otherwise integrated therein. As will be appreciated, motherboard 602 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or the only board of system 600, etc.

[0067] Depending on its application, the computing system 600 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any component included in the computing system 600 may include one or more integrated circuit structures or devices configured according to an example embodiment (e.g., a module including an integrated circuit device on a substrate having one or more unit cells including both a GAA device and a fork-chip device, as provided differently herein). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 606 may be part of the processor 604 or otherwise integrated into the processor 604).

[0068] The communication chip 606 implements wireless communication to transmit data to and from the computing system 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data via non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 606 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.8, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing system 600 may include multiple communication chips 606. For example, the first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, while the second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0069] The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented using one or more semiconductor devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0070] The communication chip 606 may also include an integrated circuit die packaged within the communication chip 606. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described variously herein. As will be understood in light of the present disclosure, note that multi-standard wireless capabilities may be integrated directly into the processor 604 (e.g., where the functionality of any chip 606 is integrated into the processor 604, rather than having a separate communication chip). Further note that the processor 604 may be a chipset with such wireless capabilities. In short, any number of processors 604 and / or communication chips 606 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

[0071] In various embodiments, computing system 600 may be a laptop computer, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

[0072] It will be appreciated that in some embodiments, the various components of computing system 600 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0073] Additional Example Embodiments

[0074] The following examples relate to further embodiments from which numerous permutations and configurations will be apparent.

[0075] Example 1 is an integrated circuit including a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction, and a first gate structure extending above the first semiconductor region in a second direction. The integrated circuit also includes a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction, and a second gate structure extending above the second semiconductor region in the second direction. The second source or drain region is adjacent to the first source or drain region along the second direction. The integrated circuit also includes a dielectric wall extending between and contacting both the first semiconductor region and the second semiconductor region in the first direction, and extending between the first source or drain region and the second source or drain region in the first direction. Both the first source or drain region and the second source or drain region have n-type dopants, or both have p-type dopants.

[0076] Example 2 includes the integrated circuit of Example 1, wherein the dielectric wall directly separates the first gate structure from the second gate structure.

[0077] Example 3 includes the integrated circuit of Example 1 or 2, wherein the dielectric wall comprises silicon and nitrogen.

[0078] Example 4 includes the integrated circuit of any of Examples 1-3, wherein the dielectric wall has a width in the first direction between about 5 nm and about 30 nm.

[0079] Example 5 includes the integrated circuit of any of Examples 1-4, wherein the first semiconductor region includes a plurality of first semiconductor nanosheets and the second semiconductor region includes a plurality of second semiconductor nanosheets.

[0080] Example 6 includes the integrated circuit of Example 5, wherein the plurality of first semiconductor nanosheets and the plurality of second semiconductor nanosheets include germanium, silicon, or a combination thereof.

[0081] Example 7 includes the integrated circuit of any one of Examples 1-6, wherein the dielectric wall is a first dielectric wall, and the integrated circuit further includes: a second dielectric wall extending in a second direction and adjacent to the first semiconductor device, such that the first gate structure extends from the first dielectric wall to the second dielectric wall in the first direction; and a third dielectric wall extending in the second direction and adjacent to the second semiconductor device, such that the second gate structure extends from the first dielectric wall to the third dielectric wall in the first direction.

[0082] Example 8 includes the integrated circuit of any one of Examples 1-6, wherein the dielectric wall is a first dielectric wall, and the integrated circuit further includes: a third semiconductor device having a third semiconductor region extending from a third source or drain region; a fourth semiconductor device having a fourth semiconductor region extending from a fourth source or drain region in a second direction; and a second dielectric wall extending between and contacting both the third semiconductor region and the fourth semiconductor region in the second direction, and extending between the third source or drain region and the fourth source or drain region in the second direction. The third semiconductor device further includes a third gate structure, wherein the third gate structure extends over the third semiconductor region in the first direction, and the third semiconductor region extends from the third source or drain region in the second direction. The fourth semiconductor device further includes a fourth gate structure extending over the fourth semiconductor region in the first direction. The fourth source or drain region is adjacent to the third source or drain region along the first direction. Both the third source or drain region and the fourth source or drain region have n-type dopants, or both have p-type dopants.

[0083] Example 9 includes the integrated circuit of Example 8, further comprising a gate cut structure extending in the second direction and separating the second gate structure from the third gate structure.

[0084] Example 10 includes the integrated circuit of any one of Examples 1-6, wherein the dielectric wall is a first dielectric wall, and the integrated circuit further includes: a third semiconductor device, the third semiconductor device having a third semiconductor region extending from a third source or drain region in the second direction, and a third gate structure extending over the third semiconductor region in the first direction; a fourth semiconductor device, the fourth semiconductor device having a fourth semiconductor region extending from a fourth source or drain region in the second direction, and a fourth gate structure extending over the fourth semiconductor region in the first direction; and a second dielectric wall, the second dielectric wall extending in the second direction and contacting the fourth semiconductor region.

[0085] Example 11 includes the integrated circuit of Example 10, further comprising a gate cut structure extending in a second direction and separating the second gate structure from the third gate structure.

[0086] Example 12 includes the integrated circuit of Example 10 or 11, wherein the first, second, and fourth semiconductor devices are fork-piece transistor devices, and the third semiconductor device is a gate-all-around (GAA) transistor device.

[0087] Example 13 includes the integrated circuit of any of Examples 1-6, wherein the first semiconductor region extends from the first source or drain region to a third source or drain region in the second direction, and the second semiconductor region extends from the second source or drain region to a fourth source or drain region in the second direction, wherein the first, second, third and fourth source or drain regions all have n-type dopants, or all have p-type dopants.

[0088] Example 14 includes the integrated circuit of any of Examples 1-13, wherein the n-type dopant includes phosphorus and the p-type dopant includes boron.

[0089] Example 15 includes the integrated circuit of any of Examples 1-14, wherein the second direction is substantially perpendicular to the first direction.

[0090] Example 16 is a printed circuit board comprising the integrated circuit of any one of Examples 1-15.

[0091] Example 17 is an integrated circuit comprising a first semiconductor device having a first semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, and a first gate structure extending above the first semiconductor region in a second direction; a first dielectric wall extending in the first direction and contacting the first semiconductor region, and extending adjacent to both the first source or drain region and the second source or drain region in the first direction; a second dielectric wall extending in the first direction and adjacent to the first semiconductor device such that the first gate structure extends from the first dielectric wall to the second dielectric wall in the second direction; and a second semiconductor device having a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the first direction, and a second gate structure extending from the second dielectric wall in the second direction and surrounding the second semiconductor region.

[0092] Example 18 includes the integrated circuit of Example 17, wherein the first dielectric wall and the second dielectric wall each include silicon and nitrogen.

[0093] Example 19 includes the integrated circuit of Example 17 or 18, wherein the first semiconductor region includes a plurality of semiconductor nanosheets and the second semiconductor region includes a plurality of semiconductor nanoribbons.

[0094] Example 20 includes the integrated circuit of Example 19, wherein the plurality of semiconductor nanosheets and the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0095] Example 21 includes the integrated circuit of any of Examples 17-20, wherein the first source or drain region and the second source or drain region both have n-type dopants and the third source or drain region and the fourth source or drain region both have p-type dopants, or the first source or drain region and the second source or drain region both have p-type dopants and the third source or drain region and the fourth source or drain region both have n-type dopants.

[0096] Example 22 includes the integrated circuit of Example 21, wherein the n-type dopant includes phosphorus and the p-type dopant includes boron.

[0097] Example 23 includes the integrated circuit of any of Examples 17-22, further comprising a third dielectric wall extending in the second direction and adjacent to the second semiconductor device such that the second gate structure extends from the second dielectric wall to the third dielectric wall in the first direction.

[0098] Example 24 includes the integrated circuit of any of Examples 17-23, wherein the second direction is substantially perpendicular to the first direction.

[0099] Example 25 is a printed circuit board comprising the integrated circuit of any one of Examples 17-24.

[0100] Example 26 is an integrated circuit comprising a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction, and a first gate structure extending above the first semiconductor region in a second direction. The integrated circuit also comprises a second semiconductor device having a second semiconductor region extending from a second source or drain region in a first direction, and a second gate structure extending above the second semiconductor region in a second direction. The second source or drain region is adjacent to the first source or drain region along the second direction. The integrated circuit also comprises a third semiconductor device having a third semiconductor region extending from a third source or drain region in a first direction and colinearly with the first semiconductor region and the second semiconductor region, and a third gate structure extending above the third semiconductor region in a second direction. The third gate structure is spaced apart from the first gate structure and the second gate structure in the first direction. The integrated circuit also comprises a dielectric wall extending between and contacting both the first semiconductor region and the second semiconductor region in the first direction, and extending between the first source or drain region and the second source or drain region in the first direction. The dielectric wall does not intersect the third semiconductor region.

[0101] Example 27 includes the integrated circuit of Example 26, wherein the dielectric wall comprises silicon and nitrogen.

[0102] Example 28 includes the integrated circuit of Example 26 or 27, wherein the dielectric wall directly separates the first gate structure from the second gate structure.

[0103] Example 29 includes the integrated circuit of any of Examples 26-28, wherein the first semiconductor region and the second semiconductor region each include a plurality of semiconductor nanosheets, and the third semiconductor region includes a plurality of semiconductor nanoribbons.

[0104] Example 30 includes the integrated circuit of Example 29, wherein the plurality of semiconductor nanosheets and the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0105] Example 31 includes the integrated circuit of any of Examples 26-30, wherein the first source or drain region, the second source or drain region, and the third source or drain region all have n-type dopants, or all have p-type dopants.

[0106] Example 32 includes the integrated circuit of Example 31, wherein the n-type dopant includes phosphorus and the p-type dopant includes boron.

[0107] Example 33 includes the integrated circuit of any of Examples 26-32, wherein the dielectric wall is a first dielectric wall, and the integrated circuit further comprises a second dielectric wall extending in the second direction and spaced apart from the first dielectric wall in the first direction. The second gate structure extends from the first dielectric wall to the second dielectric wall in the first direction, and the third gate structure extends from the second dielectric wall in the first direction.

[0108] Example 34 includes the integrated circuit of any of Examples 26-33, wherein the second direction is substantially perpendicular to the first direction.

[0109] Example 35 is a printed circuit board comprising the integrated circuit of any one of Examples 26-34.

[0110] For the purpose of illustration and description, the above description of the embodiments of the present disclosure has been presented. It is not intended to be exhaustive or to limit the present disclosure to the precise form described. Many modifications and variations are possible according to the present disclosure. The scope of the present disclosure is not intended to be limited by this detailed description, but is limited by the appended claims.

Claims

1. An integrated circuit, comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region, and a first gate structure extending over the first semiconductor region, the first gate structure extending over the first semiconductor region in a first direction, and the first semiconductor region extending from the first source or drain region in a second direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the second direction, and a second gate structure extending over the second semiconductor region in the first direction, the second source or drain region being adjacent to the first source or drain region along the first direction; as well as A dielectric wall extending between and contacting the first semiconductor region and the second semiconductor region in the second direction, and extending between the first source or drain region and the second source or drain region in the second direction, wherein the first source or drain region and the second source or drain region both have n-type dopants, or both have p-type dopants.

2. The integrated circuit according to claim 1, wherein: The dielectric wall directly separates the first gate structure from the second gate structure.

3. The integrated circuit according to claim 1, wherein: The dielectric wall includes silicon and nitrogen.

4. The integrated circuit according to claim 1, wherein: The dielectric wall has a width in the first direction between about 5 nm and about 30 nm.

5. The integrated circuit according to claim 1, wherein: The first semiconductor region includes a plurality of first semiconductor nanosheets, and the second semiconductor region includes a plurality of second semiconductor nanosheets.

6. The integrated circuit according to claim 5, wherein: The plurality of first semiconductor nanosheets and the plurality of second semiconductor nanosheets include germanium, silicon, or a combination thereof.

7. An integrated circuit according to any one of claims 1 to 6, wherein: The dielectric wall is a first dielectric wall, and the integrated circuit further comprises: a second dielectric wall extending in the second direction and adjacent to the first semiconductor device, such that the first gate structure extends from the first dielectric wall to the second dielectric wall in the first direction; and A third dielectric wall extends in the second direction and is adjacent to the second semiconductor device, such that the second gate structure extends in the first direction from the first dielectric wall to the third dielectric wall.

8. An integrated circuit according to any one of claims 1 to 6, wherein: The dielectric wall is a first dielectric wall, and the integrated circuit further comprises: a third semiconductor device having a third semiconductor region extending from a third source or drain region, and a third gate structure extending over the third semiconductor region, the third gate structure extending over the third semiconductor region in the first direction, and the third semiconductor region extending from the third source or drain region in the second direction; a fourth semiconductor device having a fourth semiconductor region extending from a fourth source or drain region in the second direction, and a fourth gate structure extending over the fourth semiconductor region in the first direction, the fourth source or drain region being adjacent to the third source or drain region along the first direction; and a second dielectric wall extending between and contacting the third semiconductor region and the fourth semiconductor region in the second direction, and extending between the third source or drain region and the fourth source or drain region in the second direction, wherein the third source or drain region and the fourth source or drain region both have n-type dopants, or both have p-type dopants. 9 . The integrated circuit of claim 8 , further comprising a gate cut structure extending in the second direction and separating the second gate structure from the third gate structure.

10. An integrated circuit according to any one of claims 1 to 6, wherein: The dielectric wall is a first dielectric wall, and the integrated circuit further comprises: a third semiconductor device having a third semiconductor region extending from a third source or drain region, and a third gate structure extending over the third semiconductor region, the third gate structure extending over the third semiconductor region in the first direction, and the third semiconductor region extending from the third source or drain region in the second direction; a fourth semiconductor device having a fourth semiconductor region extending from a fourth source or drain region in the second direction, and a fourth gate structure extending over the fourth semiconductor region in the first direction; and A second dielectric wall extends in the second direction and contacts the fourth semiconductor region. 11 . The integrated circuit of claim 10 , further comprising a gate cut structure extending in the second direction and separating the second gate structure from the third gate structure.

12. The integrated circuit of claim 10, wherein: The first semiconductor device, the second semiconductor device, and the fourth semiconductor device are fork-piece transistor devices, and the third semiconductor device is a gate-all-around (GAA) transistor device.

13. An integrated circuit according to any one of claims 1 to 6, wherein: The first semiconductor region extends from the first source or drain region to a third source or drain region in the second direction, and the second semiconductor region extends from the second source or drain region to a fourth source or drain region in the second direction, wherein the first source or drain region, the second source or drain region, the third source or drain region and the fourth source or drain region all have n-type dopants, or all have p-type dopants.

14. An integrated circuit according to any one of claims 1 to 6, wherein: The n-type dopant includes phosphorus, and the p-type dopant includes boron.

15. A printed circuit board comprising an integrated circuit according to any one of claims 1 to 6.

16. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region to a second source or drain region, and a first gate structure extending over the first semiconductor region, the first gate structure extending over the first semiconductor region in a first direction, and the first semiconductor region extending from the first source or drain region to the second source or drain region in a second direction; a first dielectric wall extending in the second direction and contacting the first semiconductor region and extending adjacent to both the first source or drain region and the second source or drain region in the second direction; a second dielectric wall extending in the second direction and adjacent to the first semiconductor device, such that the first gate structure extends from the first dielectric wall to the second dielectric wall in the first direction; as well as A second semiconductor device having a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the second direction, and a second gate structure extending from the second dielectric wall in the first direction and surrounding the second semiconductor region.

17. The integrated circuit of claim 16, wherein: The first semiconductor region includes a plurality of semiconductor nanosheets, and the second semiconductor region includes a plurality of semiconductor nanoribbons.

18. The integrated circuit of claim 16, wherein: The first source or drain region and the second source or drain region both have n-type dopants, and the third source or drain region and the fourth source or drain region both have p-type dopants, or the first source or drain region and the second source or drain region both have p-type dopants, and the third source or drain region and the fourth source or drain region both have n-type dopants.

19. The integrated circuit of any one of claims 16 to 18, further comprising a third dielectric wall extending in the second direction and adjacent to the second semiconductor device, such that the second gate structure extends from the second dielectric wall to the third dielectric wall in the first direction.

20. A printed circuit board comprising an integrated circuit according to any one of claims 16 to 18.

21. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region, and a first gate structure extending over the first semiconductor region, the first gate structure extending over the first semiconductor region in a first direction, and the first semiconductor region extending from the first source or drain region in a second direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the second direction, and a second gate structure extending over the second semiconductor region in the first direction, the second source or drain region being adjacent to the first source or drain region along the first direction; a third semiconductor device having a third semiconductor region extending from a third source or drain region in the second direction and in line with the first semiconductor region and the second semiconductor region, and a third gate structure extending over the third semiconductor region in the first direction, wherein the third gate structure is spaced apart from the first gate structure and the second gate structure in the second direction; and a dielectric wall extending between and contacting both the first semiconductor region and the second semiconductor region in the second direction, and extending between the first source or drain region and the second source or drain region in the second direction, wherein the dielectric wall does not intersect the third semiconductor region.

22. The integrated circuit of claim 21, wherein: The dielectric wall directly separates the first gate structure from the second gate structure.

23. The integrated circuit of claim 21, wherein: The first semiconductor region and the second semiconductor region each include a plurality of semiconductor nanosheets, and the third semiconductor region includes a plurality of semiconductor nanoribbons.

24. An integrated circuit as claimed in any one of claims 21 to 23, wherein: The dielectric wall is a first dielectric wall, and the integrated circuit further includes a second dielectric wall, which extends in the second direction and is spaced apart from the first dielectric wall in the first direction, so that the second gate structure extends from the first dielectric wall to the second dielectric wall in the first direction, and the third gate structure extends from the second dielectric wall in the first direction.

25. A printed circuit board comprising an integrated circuit according to any one of claims 21 to 23.

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