Image sensor

Abstract

An image sensor is disclosed. The image sensor includes: a substrate including a first side configured to receive light and a second side opposite the first side; a pixel separation pattern configured to at least partially define unit pixels in the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer arranged in a first direction in the pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer; a first mesh pattern on the pixel separation pattern; and a second mesh pattern on the first separation pattern and having a lower height than the first mesh pattern.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0079483 filed in the Korean Intellectual Property Office on June 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present inventive concept relates to image sensors and more particularly to image sensors for reducing light loss. Background Art

[0003] An image sensor is a semiconductor device for converting an optical image into an electrical signal. Image sensors can be classified, for example, into charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors implemented in CMOS technology. CMOS image sensors can also be abbreviated as CIS.

[0004] CIS can convert light energy into electrical energy and can read image information. In detail, CIS can convert analog video signals input through the lens into electrical video signals, and can be developed to transmit CMOS digital signals, which is different from CCD image sensors for transmitting charges.

[0005] In more detail, the CIS includes pixels arranged in a two-dimensional manner (e.g., a two-dimensional array), each pixel uses a transistor, and a signal charge generated by a photodiode can be converted into a voltage in each pixel and can be output. The CIS can be manufactured by a commercial CMOS method, so research on an easily manufactured CIS is actively being conducted.

[0006] When manufacturing CIS, there is a problem that light flowing in through a color filter is absorbed by a polysilicon region of DTI (Deep Trench Isolation), resulting in light loss in a structure in which one pixel includes two or more photodiodes. Summary of the invention

[0007] Some example embodiments of the inventive concepts provide an image sensor for reducing optical loss.

[0008] Some example embodiments of the inventive concepts provide an image sensor for acquiring an auto focus (AF) separation ratio.

[0009] Some example embodiments of the inventive concept provide an image sensor, which may include: a substrate including a first side configured to receive light and a second side opposite to the first side; a pixel separation pattern configured to at least partially define a unit pixel in the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction in the pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate, the first separation pattern being between the first photoelectric conversion layer and the second photoelectric conversion layer; a first grid pattern on the pixel separation pattern; and a second grid pattern on the first separation pattern and having a lower height than the first grid pattern. The height of the second grid pattern may satisfy a range of 1 / 10 to 1 / 4 of the height of the first grid pattern.

[0010] The image sensor may include a first color filter on the first and second grid patterns and having a refractive index greater than that of the second grid pattern. A ratio of the refractive index of the second grid pattern to the refractive index of the first color filter on the second grid pattern may satisfy 0.40 to 0.95.

[0011] The refractive index of the second mesh pattern may satisfy 1.0 to 1.6. The first mesh pattern may include a lower first mesh pattern and an upper first mesh pattern on the lower first mesh pattern.

[0012] The lower first mesh pattern and the second mesh pattern may have the same height.The lower first mesh pattern and the upper first mesh pattern may include different materials.

[0013] The image sensor may further include: a third photoelectric conversion layer close to the first photoelectric conversion layer in the unit pixel in the second direction; and a fourth photoelectric conversion layer close to the second photoelectric conversion layer in the second direction, wherein the third photoelectric conversion layer and the fourth photoelectric conversion layer are at least partially defined by a first separation pattern. The first separation pattern may include a first sub-separation pattern and a second sub-separation pattern separated by a specific (or optionally, predetermined) interval.

[0014] The area of ​​the second grid pattern may be equal to or greater than the area of ​​the first sub-separating pattern and the second sub-separating pattern. The pixel separation pattern may be configured to at least partially define an additional unit pixel in the substrate, the additional unit pixel comprising: an additional first photoelectric conversion layer and an additional second photoelectric conversion layer, arranged along a first direction in the pixel separation pattern; an additional first separation pattern, configured to at least partially define an additional first photoelectric conversion layer and an additional second photoelectric conversion layer in the substrate, the additional first separation pattern being between the additional first photoelectric conversion layer and the additional second photoelectric conversion layer; and a third grid pattern, on at least one of the additional first photoelectric conversion layer of the additional unit pixel and the additional second photoelectric conversion layer of the additional unit pixel.

[0015] The third grid pattern may completely cover at least one of the additional first photoelectric conversion layer and the additional second photoelectric conversion layer. The additional first separation pattern may include a first sub-separation pattern and a second sub-separation pattern spaced apart from each other at a specific interval, and the third grid pattern may be on at least a portion of the first sub-separation pattern and the second sub-separation pattern. The third grid pattern may completely cover the first sub-separation pattern and the second sub-separation pattern.

[0016] Some example embodiments of the inventive concept provide an image sensor that may include: a substrate including a first side configured to receive light and a second side opposite to the first side; a pixel separation pattern configured to at least partially define a unit pixel in the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction in the pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate, the first separation pattern being between the first photoelectric conversion layer and the second photoelectric conversion layer; and a first grid pattern on at least one of the first photoelectric conversion layer and the second photoelectric conversion layer. The first grid pattern may cover at least a portion of the first separation pattern. The second grid pattern may be between the first separation pattern and the first grid pattern.

[0017] Some example embodiments of the present invention provide an image sensor, which may include: a substrate including a first side configured to receive light and a second side opposite to the first side; a pixel separation pattern configured to at least partially define a unit pixel in the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer, arranged along a first direction in the pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate, the first separation pattern being between the first photoelectric conversion layer and the second photoelectric conversion layer; a surface insulating layer on each of the pixel separation pattern, the first photoelectric conversion layer, the second photoelectric conversion layer and the first separation pattern; a first grid pattern on at least a first portion of the surface insulating layer on the pixel separation pattern; a second grid pattern on at least a second portion of the surface insulating layer on the first separation pattern and having a height lower than that of the first grid pattern; and a color filter on each of the first grid pattern and the second grid pattern, wherein a height of the second grid pattern satisfies 1 / 10 to 1 / 4 of a height of the first grid pattern.

[0018] The pixel separation pattern can be constructed to at least partially define an additional unit pixel in the substrate, and the additional unit pixel includes: an additional first photoelectric conversion layer and an additional second photoelectric conversion layer, which are arranged along a first direction in the pixel separation pattern; an additional first separation pattern, which is constructed to at least partially define an additional first photoelectric conversion layer and an additional second photoelectric conversion layer in the substrate, and the additional first separation pattern is between the additional first photoelectric conversion layer and the additional second photoelectric conversion layer; and a third grid pattern, on at least one of the additional first photoelectric conversion layer and the additional second photoelectric conversion layer.

[0019] Image sensors according to some example embodiments of the inventive concepts include first and second mesh patterns on a separation pattern to at least partially define a pixel separation pattern and a photoelectric conversion layer, thereby providing an image sensor with reduced light loss.

[0020] Image sensors according to some example embodiments of the inventive concepts have the above advantages and include a unit pixel in which a portion of a photoelectric conversion layer is blocked, thereby providing an image sensor having acquired an auto focus (AF) separation ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A block diagram of an image sensor according to some example embodiments of the inventive concepts is shown.

[0022] Figure 2 Circuit diagrams of unit pixel regions of a pixel array according to some example embodiments of the inventive concept are shown.

[0023] Figure 3 An exploded perspective view of an image sensor according to some example embodiments of the inventive concepts is illustrated.

[0024] Figure 4 An exploded perspective view of an image sensor according to some example embodiments of the inventive concepts is illustrated.

[0025] Figure 5 Layout diagrams of image sensors according to some example embodiments of the inventive concepts are shown.

[0026] Figure 6 FIG. 1 shows some exemplary embodiments of the present invention. Figure 5 A cross-sectional view of the image sensor along the cross-sectional view line AA'.

[0027] Fig. 7A and Figure 7B According to some example embodiments Figure 6 The enlarged area P1.

[0028] Fig. 8A , Figure 8Band Figure 8C FIG. 1 shows some exemplary embodiments of the present invention. Fig. 7A A top plan view of a pixel separation pattern and a first separation pattern along a cross-sectional view line DD' in FIG.

[0029] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D FIG. 1 shows some exemplary embodiments of the present invention. Fig. 7A A top plan view of the first mesh pattern and the second mesh pattern along the cross-sectional line EE' in FIG.

[0030] Fig.10 FIG. 1 shows some exemplary embodiments of the present invention. Figure 5 A partial cross-sectional view of the image sensor along the cross-sectional view line BB'.

[0031] Fig.11A and Fig. 11B They are shown respectively Fig.10 The enlarged areas P2 and P3.

[0032] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F Shows relative to Fig.11A The area P2 of the cross-sectional view line F-F' or relative to Fig. 11B A top plan view of area P3 along the cross-sectional view line G-G'.

[0033] Fig.13 FIG. 1 shows some exemplary embodiments of the present invention. Figure 5 A partial cross-sectional view of the image sensor along the cross-sectional view line CC'.

[0034] Fig.14A and Fig. 14B Shows relative to Fig.13 A top plan view of region P4 and region P5 along the cross-sectional view line HH'.

[0035] Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig.15F , Figure 15G and Fig.15H A method for manufacturing an image sensor according to some example embodiments of the inventive concept is illustrated. DETAILED DESCRIPTION

[0036] The inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the inventive concept.

[0037] Parts irrelevant to the description will be omitted to clearly describe the present inventive concept, and the same elements will be denoted by the same reference numerals throughout the specification.

[0038] For better understanding and ease of description, the size and thickness of each structure shown in the drawings are arbitrarily shown, but the inventive concept is not limited thereto. In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. For ease of explanation, the thickness of some layers and regions is exaggerated.

[0039] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "above" refer to being positioned on or below an object part, and do not necessarily refer to being positioned on the upper side of the object part based on the direction of gravity.

[0040] Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0041] The phrase "in a plan view" means viewing an object portion from the top, and the phrase "in a cross-sectional view" means viewing a section vertically cutting the object portion from the side.

[0042] Throughout the specification, when a component is “connected” to another component, it includes not only the case where the component is “directly connected” to the other component but also the case where the component is “indirectly connected” to the other component with another component in between. In addition, unless explicitly described to the contrary, the word “comprise” and its variations will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0043] It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in the specification, the term "on..." or "over..." refers to being positioned on or below an object part, and does not necessarily mean being positioned on the upper side of the object part based on the direction of gravity.

[0044] The use of the term "the" and similar referents may correspond to both the singular and the plural. Unless otherwise indicated herein or otherwise clearly contradicted by context, the operations constituting the methods may be performed in any suitable order and are not necessarily limited to the order recited.

[0045] All illustrations or illustrative terms are used in some exemplary embodiments only to describe the technical ideas in detail, and the scope of the inventive concept is not limited by the illustrations or illustrative terms unless they are limited by the claims.

[0046] It will be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that may be referred to as "perpendicular", "parallel", "coplanar", etc., relative to other elements and / or their properties (e.g., structures, surfaces, directions, etc.) may be "perpendicular", "parallel", "coplanar", etc., or may be "substantially perpendicular", "substantially parallel", "substantially coplanar", respectively, relative to other elements and / or their properties.

[0047] Elements and / or properties (e.g., structures, surfaces, directions, etc.) that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other elements and / or properties will be understood to be “perpendicular,” “parallel,” or “coplanar,” respectively, relative to other elements and / or properties within manufacturing tolerances and / or material tolerances, and / or have an amplitude and / or angular deviation from “perpendicular,” “parallel,” or “coplanar,” respectively, equal to or less than 10% (e.g., a tolerance of ±10%) relative to other elements and / or properties.

[0048] It will be understood that elements and / or their properties may be described herein as being "same" or "equal" to other elements, and it will also be understood that elements and / or their properties described herein as being "equivalent", "identical" or "equal" to other elements may be "equivalent", "identical" or "equal" or "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their properties. Elements and / or their properties that are "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their properties will be understood to include elements and / or their properties that are equivalent, identical or equal to other elements and / or their properties within manufacturing tolerances and / or material tolerances. Elements and / or their properties that are equivalent or substantially equivalent and / or identical or substantially identical to other elements and / or their properties may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition. Although the terms "same", "equal" or "equivalent" may be used in the description of some example embodiments, it will be understood that there may be some imprecision. Thus, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element or value within a desired manufacturing or operating tolerance range (eg, ±10%).

[0049] It will be understood that elements and / or properties thereof described herein as being "substantially" the same and / or equivalent include elements and / or properties thereof having a relative size difference of 10% or less. Furthermore, regardless of whether elements and / or properties thereof are modified to be "substantially," it will be understood that these elements and / or properties thereof should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the recited elements and / or properties thereof.

[0050] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but rather the tolerance of the shape is within the disclosed range. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0051] As described herein, when an operation is described as being performed, or an effect such as a structure is described as being established “by” or “via” performance of additional operations, it will be understood that the operation may be performed and / or the effect (such as the structure) may be established “based on” the additional operations, which may include performing the additional operations alone or in combination with other additional operations.

[0052] As described herein, an element described as being "spaced apart" from another element generally and / or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as "separated" from another element may be understood to be isolated from the other element generally and / or in a particular direction without direct contact (e.g., isolated from the other element in a vertical direction without direct contact, isolated from the other element in a lateral or horizontal direction without direct contact, etc.). Similarly, elements described as being "spaced apart" from each other generally and / or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as "separated" from each other may be understood to be isolated from each other generally and / or in a particular direction without direct contact (e.g., isolated from each other in a vertical direction without direct contact, isolated from each other in a lateral or horizontal direction without direct contact, etc.). Similarly, a structure described herein as being between two other structures to separate the two other structures from each other may be understood to be constructed to isolate the two other structures from each other without direct contact.

[0053] Hereinafter, some exemplary embodiments of the inventive concept will be described in detail so that those skilled in the art to which the inventive concept belongs can easily practice the inventive concept. However, the inventive concept can be implemented in various different forms and is not limited to the exemplary embodiments provided herein.

[0054] Figure 1 A block diagram of an image sensor according to some example embodiments of the inventive concepts is shown.

[0055] Reference Figure 1 , a semiconductor chip including the pixel array 102 and a semiconductor chip including the logic circuit 202 may be stacked and arranged.

[0056] The pixel array 102 may convert incident light and may generate an electrical signal (e.g., the pixel array 102 may photoelectrically convert the incident light and may generate an electrical signal based on the photoelectric conversion). The pixel array 102 may include unit pixel regions arranged in a matrix format in the row direction and the column direction. In detail, the pixel array 102 may be driven by the control of the logic circuit 202. In more detail, the logic circuit 202 may control the transistors included in the pixel array 102.

[0057] The logic circuit 202 may effectively receive data from the pixel array 102 and may generate an image frame. For example, the logic circuit 202 may use various types of methods, such as a global shutter method for simultaneously sensing a unit pixel area, a dithered shutter method for adjusting an exposure time to simultaneously sense an entire unit pixel area, a rolling shutter method for controlling a unit pixel area of ​​a corresponding row, or a coded rolling shutter method.

[0058] The logic circuit 202 may include a row decoder 21 , a row driver 22 , a timing generator 23 , a correlated double sampler (CDS) 24 , an analog-to-digital converter (ADC) 25 , a latch portion (latch) 26 , and a column decoder 27 .

[0059] The row driver 22 may control the pixel array 102 according to the control of the timing generator 23. The row driver 22 may select at least one row of the pixel array 102 according to the row address. The row driver 22 may decode the row address and may be connected to the selection transistor, the reset transistor, and the source follower transistor. The pixel array 102 may be driven by a driving signal received from the row driver 22, such as a pixel selection signal, a reset signal, and a charge transfer signal.

[0060] The timing generator 23 supplies the timing signal and the control signal to the row decoder 21 and the column decoder 27. The row driver 22 supplies a driving signal for driving the unit pixel to the pixel array according to the result decoded by the row decoder 21. When the unit pixels are arranged in a matrix format, the driving signal is provided for each row of the matrix.

[0061] The correlated double sampler 24 receives, samples, and holds the output signal from the pixel array 102. In detail, the differential level between the noise level and the signal level is output by double sampling the signal level caused by a specific noise level and the output signal.

[0062] The analog-to-digital converter 25 converts the analog signal corresponding to the difference level into a digital signal and outputs the digital signal. In detail, the analog-to-digital converter 25 may convert the analog signal received from the pixel array 102 through the column line into a digital signal. The number of analog-to-digital converters 25 may be determined by the number of unit pixel regions and the number of column lines arranged in a row. As a non-limiting example, the analog-to-digital converter 25 may be at least one.

[0063] The analog-to-digital converter 25 may include a reference signal generator REF, a comparator CMP, a counter CNT, and a buffer BUF. The reference signal generator REF may generate a lamp signal having a specific slope, and may provide the lamp signal as a reference signal for the comparator. The comparator CMP may compare the analog signal with the lamp signal of the reference signal generator REF, and may output a comparison signal having a corresponding transition time according to the effective signal component. The counter CNT may perform a counting operation to generate a count signal, and may provide them to the buffer BUF. The buffer BUF may include a circuit of a latch portion 26 connected to the column line, may latch the count signal output by the counter CNT for each column in response to the transition of the comparison signal, and may output the latched count signal as data.

[0064] Figure 2 Circuit diagrams of unit pixel regions of a pixel array according to some example embodiments of the inventive concept are shown.

[0065] Reference Figure 2 , the pixel array may include a photoelectric conversion layer PD, a transfer transistor TX, a floating diffusion region FD, and a reset transistor RX.

[0066] The photoelectric conversion layer PD may generate charges in proportion to the amount of light input from the outside (e.g., light received from the external environment incident on a pixel array, an image sensor, etc.). The photoelectric conversion layer PD may be a photodiode including an N-type impurity region and a P-type impurity region. The photoelectric conversion layer PD may be coupled to a transfer transistor TX for transferring the generated and stored charges to a floating diffusion region FD. The floating diffusion region FD may have a parasitic capacitance for converting charges into voltages, and may stack and store charges.

[0067] The first end of the transfer transistor TX can be connected to the photoelectric conversion layer PD, and the second end of the transfer transistor TX can be connected to the floating diffusion region. The transfer transistor TX can be formed by a transistor driven by a transfer signal as a specific (or optionally, predetermined) bias. The transfer signal can be applied through the transfer gate TG. In detail, the transfer transistor TX can transfer the charge generated by the photoelectric conversion layer to the floating diffusion region FD according to the transfer signal.

[0068] The source follower transistor SX can amplify the potential change of the floating diffusion region FD that has received the charge from the photoelectric conversion layer PD, and can output the amplified change to the output line Vout. A specific (or optionally, predetermined) potential (e.g., power supply voltage VDD) provided to the drain of the source follower transistor SX can be transmitted to the drain region of the selection transistor. The source follower gate SF of the source follower transistor SX can be connected to the floating diffusion region FD.

[0069] The selection transistor can select the unit pixel area to be read per row unit. The selection transistor can be formed by a transistor driven by a specific (or alternatively, predetermined) bias (e.g., a selection line for applying a row selection signal). The row selection signal can be applied through the selection gate SEL.

[0070] The reset transistor RX can periodically reset the floating diffusion region FD. The reset transistor RX can be formed as a transistor driven by a specific (or optionally, predetermined) bias (e.g., a reset line for applying a reset signal). The reset signal can be applied through the reset gate RG. When the reset transistor RX is turned on by the reset signal, a specific (or optionally, predetermined) potential (e.g., a reset voltage VRESET) provided to the drain of the reset transistor RX can be transmitted to the floating diffusion region FD.

[0071] Figure 2 It is shown that the photoelectric conversion layer PD electrically shares a floating diffusion region FD, which is a non-limiting example. A unit pixel region may include at least one of the photoelectric conversion layer and the floating diffusion region FD as well as a transfer transistor, a source follower transistor, a selection transistor and a reset transistor. The reset transistor RX, the source follower transistor SX or the selection transistor may be shared by adjacent unit pixel regions.

[0072] In some example embodiments, as the area of ​​the unit pixel region decreases, the photoelectric conversion layer PD and the transfer transistor TX may be formed on one semiconductor chip, and the reset transistor, the source follower transistor, and the selection transistor may be formed on another semiconductor chip. The semiconductor chips may be arranged to configure the unit pixel region.

[0073] Figure 2 Some example embodiments are shown in which a unit pixel includes a photoelectric conversion layer PD (in detail, two photoelectric conversion layers PD), which are non-limiting examples, and in some example embodiments, the unit pixel may include multiple photoelectric conversion layers, such as three photoelectric conversion layers PD or four photoelectric conversion layers PD.

[0074] In some example embodiments, the image sensor includes unit pixels. In detail, the unit pixels may be arranged in a matrix format in a row direction or a column direction. Each unit pixel may include a photoelectric conversion layer PD, a floating diffusion region FD, and a transfer transistor, a source follower transistor, a selection transistor, and a reset transistor, which are described in detail as above.

[0075] Figure 3 An exploded perspective view of an image sensor according to some example embodiments of the inventive concepts is illustrated.

[0076] Reference Figure 3 , the image sensor may include a stacked first substrate structure 100 and a second substrate structure 200. The unit pixels may be arranged in a two-dimensional array structure on a plane including an X-axis direction and a Y-axis direction in the first substrate structure 100. In detail, the first substrate structure 100 may include a pixel array 102. The X-axis direction may be perpendicular to the Y-axis direction.

[0077] The second substrate structure 200 may include a structure such as a logic area Logic, which may include at least a portion of the logic circuit 202. The second substrate structure 200 may be disposed below the first substrate structure 100. The first substrate structure 100 may be electrically connected to the second substrate structure 200. The second substrate structure 200 may transmit a pixel signal provided from the first substrate structure 100 to the logic area of ​​the second substrate structure 200.

[0078] The second substrate structure 200 may include the same components as the logic area Logic. The second substrate structure 200 may be disposed below the first substrate structure 100. The first substrate structure 100 may be electrically connected to the second substrate structure 200. The second substrate structure 200 may transmit a pixel signal provided from the first substrate structure 100 to the logic area of ​​the second substrate structure 200.

[0079] A logic device including at least a portion of the logic circuit 202 may be disposed in a logic region of the second substrate structure 200. The logic device may include a circuit for processing a pixel signal received from a unit pixel.

[0080] The first substrate structure 100 and the second substrate structure 200 may be stacked in the Z-axis direction. The Z-axis direction may be perpendicular to (eg, perpendicular to) the X-axis direction and the Y-axis direction.

[0081] Figure 4 An exploded perspective view of an image sensor according to some example embodiments of the inventive concepts is illustrated.

[0082] Reference Figure 4 , the image sensor may further include a third substrate structure 300. The first substrate structure 100, the second substrate structure 200, and the third substrate structure 300 may be sequentially stacked in the Z-axis direction. The third substrate structure 300 may be disposed below the second substrate structure 200. In detail, the second substrate structure 200 may be disposed between the first substrate structure 100 and the third substrate structure 300. As described herein, the substrate structures may be interchangeably referred to as substrates. The detailed descriptions of the first substrate structure 100 and the second substrate structure 200 are the same unless they are referred to in detail. Figure 3 The range described is inconsistent.

[0083] The third substrate structure 300 may include a memory device 302. For example, the third substrate structure 300 may include a volatile memory device such as a DRAM or an SRAM. The third substrate structure 300 may receive signals from the first substrate structure 100 and the second substrate structure 200, and may process the signals through the memory device. In some example embodiments, the memory device 302 may be included as part of the logic circuit 202, so that the logic circuit 202 is provided by the logic region of the second substrate structure 200 and the memory device of the third substrate structure 300.

[0084] Figure 5 Layout diagrams of image sensors according to some example embodiments of the inventive concepts are shown. Figure 6 Shows relative to Figure 5 Sectional view along section line AA'.

[0085] Reference Figure 5 and Figure 6 , the image sensor may include a first substrate structure 100 and a second substrate structure 200. The first substrate structure 100 and the second substrate structure 200 may be a sensor chip and a logic chip, respectively.

[0086] The first substrate structure 100 may include a light receiving area APS, a light blocking area OB, and a pad (or "pad") area PAD. Unit pixel areas PX arranged in a two-dimensional manner (e.g., in a matrix form) may be formed in the light receiving area APS and the light blocking area OB. The unit pixel areas PX may be arranged in a matrix form on a plane on which the first direction D1 and the second direction D2 extend. They may be arranged in a matrix form on a plane on which the first direction D1 and the second direction D2 extend. The first direction D1 may cross the second direction D2. The first direction D1 may be substantially perpendicular to the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2. The third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2. For example, the third direction D3 may be perpendicular to both the first direction D1 and the second direction D2. Here, the third direction D3 may be interchangeably referred to as a vertical direction and may be referred to as an in-plane direction perpendicular to the first substrate structure 100 , the upper substrate 110B, the lower substrate 110A, etc., wherein the in-plane direction may include the first direction D1 and / or the second direction D2 .

[0087] Active pixels for receiving light and generating active signals may be arranged in the light receiving region APS. Optical black pixels for blocking light and generating optical black signals may be arranged in the light blocking region OB. As a non-limiting example, the light blocking region OB is formed around the light receiving region APS (e.g., at least partially or completely surrounding the light receiving region APS in a plane extending along the first direction D1 and the second direction D2).

[0088] In some example embodiments, a dummy unit pixel region DP may be formed in the light blocking region OB. The dummy unit pixel region may be a pixel that does not generate an active signal.

[0089] The pad area PAD may be formed around the light blocking area OB (e.g., at least partially or completely surrounding the light blocking area OB in a plane extending along the first direction D1 and the second direction D2). As a non-limiting example, the pad area PAD may be formed near an edge of the image sensor. The pad area PAD may be connected to a member such as an external device, and may be configured to transmit and receive electrical signals between the image sensor and the external device. In detail, the second pad pattern 455 may be connected to a member (such as an external device) on the upper substrate 110B of the pad area PAD.

[0090] In some example embodiments, the image sensor may include a first substrate structure 100, a pixel separation pattern 120A, a surface insulating layer 150, a first color filter 170, a first grid pattern 160A, a microlens 180, and a second substrate structure 200, the first substrate structure 100 including an upper substrate 110B and a lower substrate 110A, and the second substrate structure 200 is disposed below the first substrate structure 100 and includes a second substrate 210.

[0091] The upper substrate 110B may be a semiconductor substrate. In detail, the upper substrate 110B may be bulk silicon or silicon on insulator (SOI). The upper substrate 110B may be a silicon substrate. For example, the upper substrate 110B may be made of a material including silicon, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In some example embodiments, the upper substrate 110B may be an epitaxial layer formed on a base substrate.

[0092] The upper substrate 110B may include a first side 112a and a second side 112b facing each other. In some example embodiments, the first side 112a of the upper substrate 110B may be a light receiving side. In some example embodiments, the image sensor may be a backside illumination (BSI) image sensor.

[0093] The unit pixel region PX may be formed in the upper substrate 110B of the light receiving region APS and the light blocking region OB. Fig. 7A , Figure 7B and FIG. 8A to FIG. 8C , each unit pixel region PX may include a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2. In some example embodiments, a dummy unit pixel region DP not including the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 (e.g., not including any photoelectric conversion layer) may be further included in the upper substrate 110B of the light blocking region OB, but example embodiments are not limited thereto. A signal generated by the dummy unit pixel region may be used as information for removing processing noise.

[0094] Each unit pixel region PX may include a photoelectric conversion layer PD, a floating diffusion region FD, and a transfer transistor TX. In detail, the photoelectric conversion layer PD1 or PD2 may be formed in the upper substrate 110B of the light receiving region APS and the light blocking region OB. The photoelectric conversion layer PD1 or PD2 may generate charges proportional to the amount of light input from the outside. The photoelectric conversion layer PD1 or PD2 may transfer the generated and stored charges to the floating diffusion region FD.

[0095] The floating diffusion region FD may be formed in the upper substrate 110B of the light receiving region APS and the light blocking region OB. The floating diffusion region FD may be formed in (eg, formed at) the second side 112b of the upper substrate 110B. The charges transferred to the floating diffusion region FD may be applied to Figure 2 of the source follower gate SF.

[0096] The transfer transistor TX may be filled in the upper substrate 110B. The first end of the transfer transistor TX may be connected to the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and the second end of the transfer transistor TX may be connected to the floating diffusion region FD. The transfer transistor TX may transfer charges generated by the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2 to the floating diffusion region FD.

[0097] The transmission transistor TX may include a transmission gate, a gate insulating layer, and a gate spacer. The transmission gate may include a portion filled in the upper substrate 110B. The gate insulating layer may be disposed between the transmission gate and the upper substrate 110B. The gate spacer may be disposed on both sidewalls of the transmission gate.

[0098] The pixel separation pattern 120A may be formed in the upper substrate 110B. The pixel separation pattern 120A may be formed when a conductive material is filled in a deep trench formed by patterning the upper substrate 110B, and may be insulated when a liner layer as an insulating material is formed between the conductive material and the upper substrate 110B.

[0099] The pixel separation pattern 120A may penetrate the upper substrate 110B in the third direction D3. In detail, the pixel separation pattern 120A may extend from the second side 112b to the first side 112a. In more detail, the pixel separation pattern 120A may be a front deep trench isolator (FDTI).

[0100] The pixel separation pattern 120A may define (e.g., at least partially define or completely define) a unit pixel region PX (e.g., in the first direction D1, the second direction D2, and / or the third direction D3). In some example embodiments, the pixel separation pattern 120A may define a unit pixel region PX and a dummy unit pixel (not shown). The pixel separation pattern 120A may be formed to have a lattice shape in a plan view, and may separate the unit pixel regions PX from each other (e.g., in the first direction D1 and the second direction D2). The pixel separation pattern 120A may have a lattice structure extending in the first direction D1 and the second direction D2.

[0101] In the cross-sectional view, the pixel separation pattern 120A may penetrate the upper substrate 110B in the third direction D3. The pixel separation pattern 120A may extend from the second side 112b of the upper substrate 110B to the first side 112a. The pixel separation pattern 120A may be a deep trench isolation (DTI) film. When approaching the first side 112a from the second side 112b of the upper substrate 110B in the third direction D3, the width of the pixel separation pattern 120A in the second direction D2 may gradually decrease or may have the same width. However, the technical scope of the inventive concept is not limited thereto.

[0102] The pixel separation pattern 120A may include a liner 120L, a first pixel separation filling film 120F1, and a cover film 120C. The liner 120L may be disposed on the sidewall and bottom side of the first trench t1. In some example embodiments, the bottom side of the first trench t1 refers to a side facing the first side 112a of the upper substrate 110B. The first pixel separation filling film 120F1 may be disposed on the liner 120L. The cover film 120C may be disposed on the first pixel separation filling film 120F1. In some embodiments, the liner 120L may be disposed only on the sidewall of the first trench t1.

[0103] The pad layer 120L may include an oxide layer having a refractive index lower than that of the upper substrate 110B. As a non-limiting example, the pad layer 120L may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and any combination thereof.

[0104] The pad layer 120L having a refractive index lower than that of the upper substrate 110B may refract light obliquely input to the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2. The pad layer 120L may prevent photocharges generated in a specific unit pixel region PX by incident light from moving to an adjacent unit pixel region PX according to random drift. In detail, the pad layer 120L may increase the light receiving rate of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, and may improve the quality of the image sensor.

[0105] The first pixel separation filling film 120F1 may include an insulating material or a conductive material. The insulating material may include a silicon-based insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, and a high dielectric material such as hafnium oxide, aluminum oxide, or tantalum oxide. In some example embodiments, the first pixel separation filling film 120F1 may be a low resistance conductive material. As a non-limiting example, the conductive material may include silicon doped with polycrystalline silicon (poly-Si), arsenic (As), phosphorus (P), or carbon (C).

[0106] In some example embodiments, a negative voltage may be applied to the first pixel separation filling film 120F1 including a conductive material. Therefore, electrostatic discharge (ESD) damage defects of the image sensor may be effectively prevented. ESD damage defects refer to a phenomenon in which stains such as an image or damage are generated when charges generated by a reaction such as ESD are accumulated on the surface (e.g., the first side 112a) of the substrate.

[0107] The cover film 120C may include an insulating material. For example, the cover film 120C may include a silicon-based insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, and a high dielectric material such as hafnium oxide or aluminum oxide. As a non-limiting example, the cover film 120C may include the same material as the first cover pattern 375 and the second cover pattern 475.

[0108] In some example embodiments, a first separation pattern 120B for defining (e.g., configured to at least partially define) the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 may be included in the first substrate structure 100 (e.g., included in the first substrate structure 100, the upper substrate 110B, etc.) and between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 (e.g., between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in a horizontal direction such as the first direction D1). The first separation pattern 120B may include a liner layer 120L, a first separation filling film 120F2, and a covering film 120C. The liner layer 120L may be disposed on the sidewall and bottom side of the second trench t2. In some example embodiments, the bottom side of the second trench t2 faces the first side 112a of the upper substrate 110B. The first separation filling film 120F2 may be disposed on the liner layer 120L. The covering film 120C may be disposed on the first separation filling film 120F2. In some embodiments, liner layer 120L may be disposed only on the sidewall of second trench t2. First separation pattern 120B is identical to pixel separation pattern 120A within a non-contradictory range except that first and second photoelectric conversion layers PD1 and PD2 are separated in unit pixel region PX.

[0109] In some example embodiments, a trench isolation pattern 105 may be provided. The trench isolation pattern 105 may be provided in the upper substrate 110B. For example, the trench isolation pattern 105 may be provided in a trench from which a portion of the upper substrate 110B is recessed. In detail, the trench may be recessed from the second side 112b of the upper substrate 110B. The trench isolation pattern 105 may be a shallow trench isolation (STI) film. The trench isolation pattern 105 may define an active region.

[0110] When approaching the first side 112a from the second side 112b of the upper substrate 110B, the width of the trench isolation pattern 105 in the first direction D1 or the second direction D2 may gradually decrease. The trench isolation pattern 105 may overlap the pixel separation pattern 120A in the second direction D2 or the first direction D1. The pixel separation pattern 120A may penetrate the trench isolation pattern 105 in the third direction D3. The trench isolation pattern 105 may include an insulating material. For example, the insulating material may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0111] The trench isolation pattern 105 may define an active region. As a non-limiting example, the active region may have a linear shape extending in the second direction D2 in a plan view. A floating diffusion region FD, a transfer transistor TX, a selection transistor, a reset transistor RX, and a source follower transistor SX may be disposed in the active region. In detail, the transfer transistor TX may include a transfer gate TG.

[0112] In some example embodiments, the floating diffusion region FD may be provided to one side of the transfer transistor TX. The floating diffusion region FD may have a conductivity opposite to that of the upper substrate 110B. For example, N-type impurities may be doped into the floating diffusion region FD. The floating diffusion region FD may cover the transfer gate TG of the transfer transistor TX.

[0113] In some example embodiments, a portion of the unit pixel region PX may include a selection transistor and a source follower transistor SX. The selection transistor may include a selection gate SEL, and the source follower transistor SX may include a source follower gate SF. The other portion of the unit pixel region PX may include a reset transistor RX. The reset transistor RX may include a reset gate RG. However, the technical scope of the inventive concept is not limited thereto, and the arrangement and quantity (e.g., number) of transistors included in the unit pixel region PX may be changed in many ways.

[0114] In some example embodiments, the image sensor may further include first wire insulating layers 131, 132, 133, 134, 135, and 136. The first wire insulating layers 131, 132, 133, 134, 135, and 136 may cover the second side 112b of the upper substrate 110B. The upper substrate 110B and the first wire insulating layers 131, 132, 133, 134, 135, and 136 may configure the first substrate structure 100. Figure 6 The first wire insulating layers 131 , 132 , 133 , 134 , 135 , and 136 are illustrated, and are not limited thereto, and the number of layers of the first wire insulating layers is not limited thereto.

[0115] For example, the first wire insulating layers 131 , 132 , 133 , 134 , 135 , and 136 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide.

[0116] In some example embodiments, the first wire insulating layer 136 connects the second substrate structure 200 with the lower substrate 110A and may be divided into an upper insulating layer 136T and a lower insulating layer 136B. The upper insulating layer 136T and the lower insulating layer 136B may be made of the same film material and may be divided by an interface to which the second substrate structure 200 and the lower substrate 110A are connected.

[0117] The first contacts 141 and 143 and the first wiring patterns 142, 144, and 145 may be disposed in the first wire insulating layers 131, 132, 133, 134, 135, and 136. The first contacts 141 and 143 may electrically connect the floating diffusion region FD and the first wiring patterns 142, 144, and 145. Some of the first wiring patterns 142, 144, and 145 may be connected to the first connection structure 360. This is a non-limiting example, and the first contacts 141 and 143 may be connected to the first wiring patterns 142, 144, and 145 in many forms, and their number is not limited thereto.

[0118] As non-limiting examples, the first contacts 141 and 143 and the first wiring patterns 142 , 144 , and 145 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0119] The second substrate 210 is one of the constituent elements of the second substrate structure 200 disposed below the first substrate structure 100, and it may be bulk silicon or silicon on insulator (SOI). The second substrate 210 may be a silicon substrate. For example, the second substrate 210 may include silicon germanium, indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The second substrate 210 may have an epitaxial layer formed on a base substrate.

[0120] The transistor TR may be formed on an upper side of the second substrate 210. The transistor TR may control the transfer transistor TX, the reset transistor RX, the selection transistor, and the source follower transistor SX.

[0121] The second wire insulating layer 230 may be formed on the second substrate 210. For example, the second wire insulating layer 230 may cover the upper side of the second substrate 210. The upper side of the second wire insulating layer 230 may contact the third side 100c which is the lower side of the lower substrate 110A of the first substrate structure 100 and may be bonded thereto. As a non-limiting example, the second wire insulating layer 230 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide.

[0122] The second contact 241 and the second wiring pattern 242 may be disposed in the second wire insulating layer 230. The second contact 241 may be connected to the second wiring pattern 242, the second wiring pattern 242 may be connected to the transistor TR, and may be connected to the floating diffusion region FD of the first substrate structure 100. For example, some of the second wiring patterns 242 may be connected to the first connection structure 360. Other of the second wiring patterns 242 may be connected to the second connection structure 450.

[0123] As a non-limiting example, the second contact 241 and the second wiring pattern 242 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but are not limited thereto.

[0124] The surface insulating layer 150 may be formed on the first side 112a of the upper substrate 110B. The surface insulating layer 150 may extend along the first side 112a of the upper substrate 110B. In some example embodiments, at least a portion of the surface insulating layer 150 may contact the pixel separation pattern 120A and the first separation pattern 120B. Here, the lower side of the surface insulating layer 150 may smoothly contact the pixel separation pattern 120A and the first separation pattern 120B.

[0125] The surface insulating layer 150 may include an insulating material. For example, the surface insulating layer 150 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, and any combination thereof, and is not limited thereto.

[0126] The surface insulating layer 150 may be used as an anti-reflection film to prevent reflection of light input to the upper substrate 110B, and allows incident light to be easily input to improve the light receiving rate of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2. In addition, the surface insulating layer 150 may be used as a planarization layer, and the first color filter 170 and the microlens 180 may be formed on the surface insulating layer 150 to have a uniform height without deformation.

[0127] The first color filter 170 may be formed on the surface insulating layer 150 of the light receiving area APS. In some example embodiments, the first color filter 170 may be formed on the surface insulating layer 150 of the light receiving area APS. In some example embodiments, the first color filter 170 may be arranged to correspond to the corresponding unit pixel area PX. In detail, the first color filter 170 may be arranged in a two-dimensional form (e.g., in a matrix form).

[0128] The first color filter 170 may have various color filters according to the unit pixel area PX. For example, the first color filter 170 may be arranged as a Bayer array including a red filter, a green filter, and a blue filter. This is a non-limiting example, and the first color filter 170 may include a yellow filter, a magenta filter, and a cyan filter, and may also include a white filter.

[0129] The first mesh pattern 160A may be formed on the surface insulating layer 150 and thus on the pixel separation pattern 120A. The first mesh pattern 160A may be formed to have a lattice shape on a plane (e.g., a horizontal plane extending in the first direction D1 and the second direction D2), and may be disposed between the first color filters 170. The first mesh pattern 160A may improve the quality of the image sensor (e.g., improve the quality of an image generated by the image sensor, and thus improve the function of the image sensor) by refracting or reflecting light obliquely input to the image sensor, thereby reducing the loss of the incident light caused by the incident light to the photoelectric conversion layer PD being absorbed by elements of the image sensor other than the photoelectric conversion layer PD, and thus improving the sensitivity of the image sensor to the incident light (e.g., improving absorption and photoelectric conversion).

[0130] The first grid pattern 160A may include a metal material for reflecting light or a material having a low refractive index lower than that of silicon (Si). For example, the first grid pattern 160A may include at least one of tungsten metal, aluminum metal, titanium metal, titanium nitride, silicon oxide, silicon oxide having an air layer collected therein, a polymer material having a low refractive index, and any combination thereof, without limitation thereto. Since the first grid pattern 160A has a refractive index lower than that of silicon (Si), light can be prevented from being absorbed into the pad layer 120L, or such absorbance can be reduced or minimized. As a result, the loss of light caused by light incident on structures other than the photoelectric conversion layer PD of the image sensor can be reduced, minimized, or prevented, so that the image sensor can be constructed to improve the amount and / or proportion of incident light received at the image sensor that is absorbed and photoelectrically converted by the photoelectric conversion layer, thereby improving the sensitivity of the image sensor to the incident light, improving the quality of the image generated by the image sensor based on the incident light, and the like.

[0131] In some example embodiments, a second mesh pattern 160B disposed on the first separation pattern 120B may be included. As shown, the first mesh pattern 160A may be on at least a first portion of the surface insulating layer 150 on the pixel separation pattern 120A, and the second mesh pattern 160B may be on at least a second portion of the surface insulating layer 150 on the first separation pattern 120B. In detail, the second mesh pattern 160B may include a metal material for reflecting light or a material having a low refractive index lower than that of silicon (Si). For example, the second mesh pattern 160B may include at least one of tungsten metal, aluminum metal, titanium metal, titanium nitride, silicon oxide, silicon oxide having collected an air layer, a polymer material having a low refractive index, and any combination thereof, without limitation thereto.

[0132] In some example embodiments, the first mesh pattern 160A may have the same material as the second mesh pattern 160B, or may have a different material from the second mesh pattern 160B. When the first mesh pattern 160A and the second mesh pattern 160B have the same material, and light input from the first color filter 170 is reflected at the first mesh pattern 160A and the second mesh pattern 160B, the light may be reflected at the same angle, so that the light may be easily input to the photoelectric conversion layers PD1 and PD2 (and thus absorbed and / or photoelectrically converted by the photoelectric conversion layers PD1 and PD2).

[0133] When the first mesh pattern 160A and the second mesh pattern 160B have different materials and light input from the first color filter 170 is reflected at the first mesh pattern 160A and the second mesh pattern 160B, the amount of light input to the photoelectric conversion layers PD1 and PD2 (and thus absorbed and / or photoelectrically converted by the photoelectric conversion layers PD1 and PD2) can be increased or maximized by changing the angle at which the incident light is reflected by the first mesh pattern 160A and / or the second mesh pattern 160B.

[0134] In some example embodiments, a first protective layer 165 may be formed on the surface insulating layer 150, the first mesh pattern 160A, and the second mesh pattern 160B. The first protective layer 165 may be disposed between the surface insulating layer 150 and the first color filter 170 and between the first mesh pattern 160A and the second mesh pattern 160B and the first color filter 170. For example, the first protective layer 165 may prevent the surface insulating layer 150, the first mesh pattern 160A, and the second mesh pattern 160B from being damaged.

[0135] The microlenses 180 may be formed on the first color filter 170. The microlenses 180 may be arranged to correspond to the corresponding unit pixel regions PX. For example, the microlenses 180 may be arranged in a two-dimensional manner (eg, in a matrix form) on a plane.

[0136] The microlens 180 may have a convex shape and may have a radius of curvature within a specific (or alternatively, predetermined) range. When the radius of curvature is within a specific (or alternatively, predetermined) range, the microlens 180 may gather light input to the photoelectric conversion layers PD1 and PD2. For example, as a non-limiting example, the microlens 180 may include a light-transmitting resin.

[0137] In some example embodiments, a second protective layer 185 may be formed on the microlens 180. The second protective layer 185 may extend along the surface of the microlens 180. For example, the second protective layer 185 may include an inorganic oxide layer. As a non-limiting example, the second protective layer 185 may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and any combination thereof. In some example embodiments, for example, the second protective layer 185 may include a low temperature oxide (LTO).

[0138] The second protective layer 185 may protect the microlens 180 from the outside (e.g., the outside of the image sensor). For example, since the second protective layer 185 includes an inorganic oxide layer, it may protect the microlens 180 including an organic material. In addition, the second protective layer 185 may improve the light-gathering performance of the microlens 180. For example, the second protective layer 185 may fill the space between the microlenses 180 to thereby reduce the reaction (such as reflection, refraction, or scattering) of the incident light reaching the space between the microlenses 180.

[0139] In some example embodiments, the image sensor may further include a first connection structure 360. The first connection structure 360 ​​may be formed in the light blocking region OB. The first connection structure 360 ​​may be disposed in the light blocking region OB and may block light input to the light blocking region OB. The first connection structure 360 ​​may be formed on the surface insulating layer 150 of the light blocking region OB. The first connection structure 360 ​​may contact the pixel separation pattern 120A.

[0140] A third trench t3 for exposing the pixel separation pattern 120A may be formed in the upper substrate 110B and the surface insulating layer 150 of the light blocking area OB. A first connection structure 360 ​​may be formed in the third trench t3 and may contact the pixel separation pattern 120A in the light blocking area OB. The first connection structure 360 ​​may extend along the contour of the sidewall and bottom side of the third trench t3.

[0141] The first connection structure 360 ​​may be electrically connected to the pixel separation pattern 120A. For example, the first connection structure 360 ​​may be connected to a conductive layer of the pixel separation pattern 120A. As a non-limiting example, the first connection structure may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film sequentially stacked.

[0142] In some example embodiments, a first pad pattern 365 may be formed on the first connection structure 360. The first pad pattern 365 is made of a metal material for blocking light around the pixel array, and it may fill the third trench t3 remaining after filling the first connection structure 360. A first voltage may be applied to the pixel separation pattern 120A through the first pad pattern 365. For example, a negative voltage may be applied to the conductive layer through the first pad pattern 365 including a conductive material and the first connection structure 360, and thus, charges generated by a reaction such as ESD may be discharged to the first pad pattern 365 through the pixel separation pattern 120A, and an ESD damage defect may be prevented.

[0143] As a non-limiting example, the first pad pattern 365 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and any alloy thereof.

[0144] In some example embodiments, the fourth trench t4 may be formed in the upper substrate 110B of the light blocking region OB. The fourth trench t4 may expose a portion of the first wiring pattern 145 of the first substrate structure 100. For example, the fourth trench t4 may represent a through silicon via.

[0145] The fourth trench t4 may expose a portion of the third wiring pattern 243 of the second substrate structure 200. The first connection structure 360 ​​may be formed in the fourth trench t4 and may connect the first wiring pattern 145 and the third wiring pattern 243. The first connection structure 360 ​​may extend along the sidewall and bottom side of the fourth trench t4.

[0146] In some example embodiments, a first filling insulating layer 370 may be formed on the first connection structure 360. As a non-limiting example, the first filling insulating layer 370 may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and any combination thereof.

[0147] In some example embodiments, a first capping pattern 375 may be formed on the first filling insulating layer 370. The first capping pattern 375 may include a silicon-based insulating material such as silicon nitride, silicon oxide, and silicon oxynitride, and a high dielectric material such as hafnium oxide and aluminum oxide. The first capping pattern 375 may include the same material as the capping film 120C, but is not limited thereto.

[0148] In some example embodiments, the second color filter 170C may be formed on the first connection structure 360. The second color filter 170C may cover a portion of the first protection layer 165 of the light blocking area OB. As a non-limiting example, the second color filter 170C may include a blue color filter.

[0149] In some example embodiments, a third protective layer 380 may be formed on the second color filter 170C. For example, the third protective layer 380 may cover a portion of the first protective layer 165 in the light blocking region OB. In some example embodiments, the second protective layer 185 may extend along a surface of the third protective layer 380. As a non-limiting example, the third protective layer 380 may include a light-transmitting resin. In some example embodiments, the third protective layer 380 may include the same material as the microlens 180.

[0150] The third connection structure 457 may be formed in the pad area PAD. The second connection structure 450 may be formed on the surface insulating layer 150 of the pad area PAD. In some example embodiments, the fifth trench t5 may be formed in the first substrate structure 100 of the pad area PAD. The second connection structure 450 may be formed on the sidewall and bottom side of the fifth trench t5.

[0151] A sixth trench t6 for exposing the third wiring pattern 243 may be formed in the second substrate structure 200 of the pad area PAD. A third connection structure 457 may be formed on a sidewall and a bottom side of the sixth trench t6.

[0152] The third connection structure 457 may be formed in the sixth trench t6 and may contact a portion of the third wiring pattern 243. The third connection structure 457 may electrically connect a portion of the third wiring pattern 243 and the second pad pattern 455. The third connection structure 457 may be, for example, a sequential stack of a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film.

[0153] The second pad pattern 455 may be formed on the second connection structure 450. The second pad pattern 455 may fill the fifth trench t5 remaining after filling the second connection structure 450. As a non-limiting example, the second pad pattern 455 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and any alloy thereof.

[0154] In some example embodiments, a portion of the second pad pattern 455 may be exposed. An exposure opening may be formed to expose the second pad pattern 455. Therefore, the second pad pattern 455 may be configured to be connected to an external device and transmit / receive an electrical signal between the image sensor according to some example embodiments and the external device.

[0155] The second filling insulating layer 470 may fill the sixth trench t6 remaining after filling the third connection structure 457. For example, the second filling insulating layer 470 may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and any combination thereof, and is not limited thereto.

[0156] In some example embodiments, a second capping pattern 475 may be formed on the second filling insulating layer 470. For example, the second capping pattern 475 may include a silicon-based insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride, and a high dielectric material such as hafnium oxide and / or aluminum oxide. In detail, as a non-limiting example, the second capping pattern 475 may include the same material as the capping film 120C.

[0157] In some example embodiments, the fourth protective layer 480 may be formed on the third connection structure 457 of the pad area PAD. For example, the fourth protective layer 480 may be formed to cover a portion of the first protective layer 165 in the pad area PAD. In some example embodiments, the second protective layer 185 may extend along a surface of the fourth protective layer 480. For example, the fourth protective layer 480 may include a light-transmitting resin, but is not limited thereto. In some example embodiments, the fourth protective layer 480 may include the same material as the microlens 180.

[0158] In some example embodiments, the image sensor may further include a fifth connection structure (not shown). The fifth connection structure may be further formed in the light blocking region OB. The fifth connection structure may block light formed and input into the light blocking region OB. The fifth connection structure may be formed on the surface insulating layer 150 of the light blocking region OB.

[0159] The fifth connection structure may contact at least a portion of the pixel separating pattern 120A. The fifth connection structure may contact at least a portion of the conductive layer of the pixel separating pattern 120A. The fifth connection structure may refer to the first connection structure 360 ​​within a scope not inconsistent.

[0160] In some example embodiments, a seventh groove (not shown) for exposing the pixel separation pattern 120A may be formed in the upper substrate 110B and the surface insulating layer 150 of the light blocking area OB. A fifth connection structure may be formed in the seventh groove and may contact at least a portion of the pixel separation pattern 120A in the light blocking area OB. The fifth connection structure may extend along the contour of the sidewall and bottom side of the seventh groove.

[0161] The fifth connection structure may be electrically connected to the pixel separation pattern 120A. In detail, as a non-limiting example, the fifth connection structure may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film sequentially stacked.

[0162] In some example embodiments, an additional pad pattern (not shown) may be formed on the fifth connection structure. The additional pad pattern may fill the seventh groove remaining after filling the fifth connection structure. A voltage may be applied to the pixel separation pattern 120A through the additional pad pattern including a conductive material and the fifth connection structure. For example, the voltage may be a well bias voltage.

[0163] As a non-limiting example, the additional pad pattern may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and any alloys thereof.

[0164] Fig. 7A and Figure 7B According to some example embodiments Figure 6 The enlarged area P1.

[0165] Reference Fig. 7A , an image sensor according to some example embodiments may include a first mesh pattern 160A disposed on a pixel separation pattern 120A and a second mesh pattern 160B disposed on the first separation pattern 120B and having a lower height than the first mesh pattern 160A, wherein the height of an element may refer to a thickness of the element in a third direction D3, and the third direction D3 may extend perpendicularly to an in-plane direction of the first substrate structure 100 (e.g., perpendicular to an upper surface and / or a bottom surface of the first substrate structure 100). In detail, a height H1 of the first mesh pattern may be different from a height H2 of the second mesh pattern.

[0166] In some example embodiments, the height H1 of the first grid pattern (hereinafter also referred to as the first height) may be greater than the height H2 of the second grid pattern (hereinafter also referred to as the second height). In detail, the height H2 of the second grid pattern may satisfy a range of 1 / 10 to 1 / 4 of the height H1 of the first grid pattern. In detail, the range may satisfy 1 / 8 to 1 / 5. The height H2 of the second grid pattern satisfies the above range of the height H1 of the first grid pattern, so that when the light L is input according to the offset, the input light L can be controlled to be easily input to the photoelectric conversion layers PD1 and PD2.

[0167] When the height (e.g., the height H2 of the second mesh pattern 160B) is greater than the highest value of the range (e.g., greater than 1 / 4 of the height H1 of the first mesh pattern 160A), the light L is captured by the second mesh pattern 160B when it is deflected, and thus, it is difficult to reflect the light L to the photoelectric conversion layers PD1 and PD2. When the height (e.g., the height H2 of the second mesh pattern 160B) is lower than the lowest value of the range (e.g., less than 1 / 10 of the height H1 of the first mesh pattern 160A), the light yield effect of the second mesh pattern 160B is weak.

[0168] In some example embodiments, the second mesh pattern 160B may have a refractive index lower than that of the first color filter 170. Since the first color filter 170 has a refractive index greater than that of the second mesh pattern 160B, light L input to the first color filter 170 may be refracted or reflected while passing through the second mesh pattern 160B and may be easily input to the photoelectric conversion layers PD1 and PD2.

[0169] In some example embodiments, a ratio of a refractive index of the second mesh pattern 160B to a refractive index of the first color filter 170 may satisfy a range of 0.40 to 0.95. In detail, the range may satisfy 0.43 to 0.90.

[0170] When the refractive index satisfies this range, the light L input to the first color filter 170 can be easily input to the photoelectric conversion layers PD1 and PD2, and the light yield can be improved. When the refractive index deviates from this range, the input light L is not input to the photoelectric conversion layers PD1 and PD2 and is reflected, or is absorbed into the pad layer 120L in the pixel separation pattern 120A.

[0171] In some example embodiments, the refractive index of the first color filter 170 may satisfy the range of 1.7 to 2.5. In some example embodiments, the refractive index of the second mesh pattern 160B may satisfy the range of 1.0 to 1.6. In detail, the range may satisfy 1.2 to 1.5.

[0172] Since the first color filter 170 has a greater refractive index than the second mesh pattern 160B as described above, Fig. 7A and Figure 7B As shown in FIG. , the incident light L propagating from the first color filter 170 to the second mesh pattern travels from a dense medium to a sparse medium, the refraction angle becomes greater than the incident angle, and total reflection may be performed (eg, increased).

[0173] Reference Figure 7B , the first mesh pattern 160A may include a lower first mesh pattern 160AB and an upper first mesh pattern 160AT disposed on the lower first mesh pattern 160AB. In detail, the first mesh pattern 160A may have a stacked structure. The stacked structure may be generated in a process for stacking the first mesh pattern 160A and the second mesh pattern 160B.

[0174] In some example embodiments, the lower first mesh pattern 160AB and the second mesh pattern 160B may have the same or different refractive indices. When the lower first mesh pattern 160AB and the second mesh pattern 160B are made of a material having the same refractive index, the first mesh pattern 160A and the second mesh pattern 160B may be easily formed in a process for manufacturing an image sensor, which is an advantage. When the lower first mesh pattern 160AB and the second mesh pattern 160B are made of a material having a different refractive index, refraction or reflection of incident light may be controlled according to design, and light yield may be improved, which is an advantage because the performance of the image sensor may be improved based on an increase in light yield (e.g., the amount of incident light absorbed and / or photoelectrically converted at the photoelectric conversion layer PD) as described herein.

[0175] In some example embodiments, the lower first mesh pattern 160AB and the second mesh pattern 160B may have the same height (e.g., the same height in the third direction D3). As described, the lower first mesh pattern 160AB and the second mesh pattern 160B having the same height may be simultaneously formed by arranging the first mesh pattern 160A in a stacked structure, and the process may be simplified by forming the upper first mesh pattern 160AT.

[0176] Fig. 8A , Figure 8B and Figure 8C 1 and 2 show the pixel separation pattern 120A and the first separation pattern 120B relative to each other according to some example embodiments of the inventive concept. Fig. 7A A top plan view of the section line D-D'.

[0177] Reference Fig. 8A and Figure 8B In some example embodiments, the first separating pattern 120B may include a first sub-separating pattern 120BT and a second sub-separating pattern 120BB. In detail, the first sub-separating pattern 120BT may protrude from one side of the pixel separating pattern 120A, and the second sub-separating pattern 120BB may protrude from the other side of the pixel separating pattern 120A facing the one side.

[0178] For example, the widths of the first and second sub-separating patterns 120BT and 120BB may be 10 nm to 500 nm. Fig. 8A It is shown that the first sub-separating pattern 120BT and the second sub-separating pattern 120BB have the same width, which is an example, and respective widths of the first sub-separating pattern 120BT and the second sub-separating pattern 120BB may be different from each other.

[0179] In some example embodiments, the first and second sub-separating patterns 120BT and 120BB may be spaced apart (eg, separated) from each other at a certain (or alternatively, predetermined) interval DC. The certain (or alternatively, predetermined) interval may be, for example, 100 nm to 1000 nm.

[0180] Since the first and second sub-separating patterns 120BT and 120BB are spaced apart at a certain (or alternatively, predetermined) interval DC, an overflow path may be formed between the photoelectric conversion layers PD1 and PD2, and the loss of optical signals may be reduced, minimized, or prevented, thereby improving the function of the image sensor. Fig. 8A and Figure 8B As shown in FIG. 1 , a specific (or alternatively, predetermined) interval DC between the first sub-separating pattern 120BT and the second sub-separating pattern 120BB may be appropriately designed and modified within the range of forming an overflow path.

[0181] Reference Figure 8C The image sensor may further include a third photoelectric conversion layer PD3 disposed near the first photoelectric conversion layer PD1 in the second direction D2 and a fourth photoelectric conversion layer PD4 disposed near the second photoelectric conversion layer PD2 in the second direction D2 in the unit pixel. In detail, Figure 8C It is shown that one unit pixel includes first to fourth photoelectric conversion layers PD1 , PD2 , PD3 , and PD4 .

[0182] In some example embodiments, the third photoelectric conversion layer PD3 and the fourth photoelectric conversion layer PD4 may be at least partially defined by the first separation pattern 120B. In detail, the third photoelectric conversion layer PD3 may be separated from the first photoelectric conversion layer PD1 by a third sub-separation pattern 120BL of the first separation pattern 120B, and the fourth photoelectric conversion layer PD4 may be separated from the second photoelectric conversion layer PD2 by a fourth sub-separation pattern 120BR of the first separation pattern 120B.

[0183] In some example embodiments, the third sub-separation pattern 120BL and the fourth sub-separation pattern 120BR may be spaced apart from each other at a specific (or alternatively, predetermined) interval DC'. Within the scope of non-contradiction, the detailed description of the specific (or alternatively, predetermined) interval DC' may refer to the content of the specific (or alternatively, predetermined) interval DC described with respect to the first sub-separation pattern 120BT and the second sub-separation pattern 120BB. Figure 8C It is shown that the specific (or optionally, predetermined) interval DC of the first and second sub-separation patterns 120BT and 120BB is the same as the specific (or optionally, predetermined) interval DC' of the third and fourth sub-separation patterns 120BL and 120BR, which is a non-limiting example and the intervals may be different.

[0184] In some example embodiments, the image sensor may perform an auto focus (AF) function by using the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2. The corresponding unit pixel may perform a phase detection auto focus (PDAF) function by using a divided pair of photoelectric conversion layers PD1 and PD2.

[0185] The photoelectric conversion layers in the unit pixel may be divided and arranged in other directions. In detail, they may include in the unit pixel a third photoelectric conversion layer PD3 arranged near (e.g., close to) the first photoelectric conversion layer PD1 in the second direction D2 and a fourth photoelectric conversion layer PD4 arranged near the second photoelectric conversion layer PD2 in the second direction D2. Thus, the image sensor may perform an autofocus function in the first direction D1 and the second direction D2.

[0186] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D FIG. 1 shows some exemplary embodiments of the present invention. Fig. 7A FIG. 1 is a top plan view of the first mesh pattern 160A and the second mesh pattern 160B taken along the cross-sectional line EE′ in FIG.

[0187] Reference Fig.9A , Fig. 9B , Fig. 9C and Fig.9D , the interval for setting the second mesh pattern 160B may be confirmed with reference to a specific (or optionally, predetermined) interval DC between the first sub-separating pattern 120BT and the second sub-separating pattern 120BB.

[0188] Reference Fig.9A, the first grid pattern 160A may be disposed on the pixel separation pattern 120A, and the second grid pattern 160B may be disposed on the first separation pattern 120B. Since the first grid pattern 160A and the second grid pattern 160B are disposed on the pixel separation pattern 120A and the first separation pattern 120B, respectively, light (e.g., incident light) may be prevented from being absorbed into the pad layer 120L including polysilicon in the pixel separation pattern 120A and the first separation pattern 120B, or such absorption may be reduced or minimized, and light loss may be prevented, or such loss may be reduced or minimized. Therefore, since the loss caused by such light being absorbed into the pixel separation pattern 120A and / or the first separation pattern 120B is reduced, minimized or prevented, the amount and / or proportion of such light absorbed and / or photoelectrically converted by the photoelectric conversion layer may be increased or maximized. As a result, the image sensor may be configured to have improved light detection performance and thus have improved image generation performance, and the image sensor may also be configured to produce an image with higher quality due to the improved light detection performance and thus having improved image generation performance.

[0189] In some example embodiments, the second mesh pattern 160B may have the same area as the first sub-separating pattern 120BT and the second sub-separating pattern 120BB in the first separation pattern 120B (e.g., wherein the area is in a horizontal plane extending along the first direction D1 and the second direction D2, in a horizontal plane extending parallel to the in-plane direction of the first substrate structure 100, etc.). The second mesh pattern 160B may have the same length and width as the first sub-separating pattern 120BT and the second sub-separating pattern 120BB (e.g., in a horizontal plane), and may cover the first sub-separating pattern 120BT and the second sub-separating pattern 120BB (e.g., overlap the first sub-separating pattern 120BT and the second sub-separating pattern 120BB in the third direction D3), thereby preventing light input by the first color filter 170 from being absorbed into the pad layer 120L, or reducing or minimizing such absorption.

[0190] Reference Fig. 9BIn some example embodiments, the second mesh pattern 160B may have an area larger than the areas of the first sub-separation pattern 120BT and the second sub-separation pattern 120BB in the first separation pattern 120B (for example, wherein the area is in a horizontal plane extending along the first direction D1 and the second direction D2, in a horizontal plane extending parallel to the in-plane direction of the first substrate structure 100, etc.). In detail, the second mesh pattern 160B may have an interval GD of the second mesh pattern narrower than a specific (or optionally, predetermined) interval DC between the first sub-separation pattern 120BT and the second sub-separation pattern 120BB. Since the interval GD of the second mesh pattern is shorter than the specific (or optionally, predetermined) interval DC between the first sub-separation pattern 120BT and the second sub-separation pattern 120BB, light input by the first color filter 170 may be more effectively prevented from being absorbed into the pad layer 120L. Therefore, since the loss caused by such light being absorbed into the backing layer 120L is reduced, minimized or prevented, the amount and / or proportion of such light absorbed and / or photoelectrically converted by the photoelectric conversion layer can be increased or maximized. As a result, the image sensor can be configured to have improved light detection performance and thus improved image generation performance, and the image sensor can also be configured to produce images with higher quality due to the improved light detection performance and thus improved image generation performance.

[0191] Reference Fig. 9C In some example embodiments, the second grid pattern 160B may completely cover a specific (or optionally, predetermined) interval DC between the first sub-separation pattern 120BT and the second sub-separation pattern 120BB in the first separation pattern 120B (e.g., overlap the specific (or optionally, predetermined) interval DC in the third direction D3). In detail, the second grid pattern 160B may seal the first sub-separation pattern 120BT and the second sub-separation pattern 120BB, and may more effectively prevent light input by the first color filter 170 from being absorbed into the pad layer 120L. Therefore, due to the reduction, minimization or prevention of the loss caused by such light being absorbed into the pad layer 120L, the amount and / or proportion of such light absorbed and / or photoelectrically converted by the photoelectric conversion layer may be increased or maximized. As a result, the image sensor may be configured to have improved light detection performance and thus improved image generation performance, and the image sensor may also be configured to produce an image with higher quality due to the improved light detection performance and thus improved image generation performance.

[0192] Reference Fig.9D , when the image sensor has Figure 8CWhen the four photoelectric conversion layers PD1, PD2, PD3, and PD4 are shown in FIG, the image sensor may have a second grid pattern 160B for dividing the four photoelectric conversion layers PD1, PD2, PD3, and PD4. The second grid pattern 160B has two portions spaced apart from each other at a gap GD1 in the second direction D2, and two portions spaced apart from each other at a gap GD2 in the first direction D1.

[0193] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D The second mesh pattern 160B is shown to have the same width as the first and second sub-separating patterns 120BT and 120BB, which is a non-limiting example, and the second mesh pattern 160B may have a wider width than the first and second sub-separating patterns 120BT and 120BB.

[0194] Fig.10 FIG. 1 shows some exemplary embodiments of the present invention. Figure 5 A partial cross-sectional view of the image sensor along the cross-sectional view line BB'.

[0195] Reference Fig.10 , an image sensor according to some example embodiments of the present inventive concept may include: a first substrate structure 100 including a first side 112a for receiving light and a second side 112b opposite to the first side 112a; a pixel separation pattern 120A for defining adjacent unit pixels in the first substrate structure 100; a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2 arranged along a first direction D1 in the pixel separation pattern 120A; a first separation pattern 120B for defining the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in the first substrate structure 100 between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2; and a third mesh pattern 160C disposed on at least one of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2. Referring to Fig.10 For the purpose of description, the unit pixel included in region P2 may be referred to as a unit pixel, and the unit pixel included in region P3 may be interchangeably referred to as an “additional” unit pixel or “another” unit pixel, and the individual separation patterns, photoelectric conversion layers, etc. of the unit pixels in region P3 may be interchangeably referred to as “additional” or “another” separation patterns, photoelectric conversion layers, etc.

[0196] The third grid pattern 160C may be on one of the first photoelectric conversion layer PD1 of the unit pixel in the region P2 and the second photoelectric conversion layer PD2 of the unit pixel in the region P2 (e.g., vertically at least partially overlapping the one photoelectric conversion layer in the third direction D3). The third grid pattern 160C may be on one of the additional first photoelectric conversion layer PD1 of the additional unit pixel in the region P3 and the additional second photoelectric conversion layer PD2 of the additional unit pixel in the region P3 (e.g., vertically at least partially overlapping the one additional photoelectric conversion layer in the third direction D3). The third grid pattern 160C may be disposed on the first photoelectric conversion layer PD1 in the unit pixel region PX, and may be disposed on the second photoelectric conversion layer PD2 in another (“additional”) unit pixel region PX (e.g., overlapping the second photoelectric conversion layer PD2 in the third direction D3). In detail, the third grid pattern 160C can block (e.g., completely cover, also referred to herein as completely overlapped in the third direction D3, the third direction D3 also being interchangeably referred to herein as a vertical direction extending perpendicular to the in-plane direction of the first substrate structure 100) one of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 of a given unit pixel to quickly confirm the light signal and perform the autofocus function more quickly. However, the inventive concept is not limited thereto. The third grid pattern 160C can be disposed on both the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in the unit pixel region PX or on both the additional first photoelectric conversion layer PD1 and the additional second photoelectric conversion layer PD2 of the additional unit pixel.

[0197] For example, the light signal of the second photoelectric conversion layer PD2 can be determined more quickly from the light input to the second photoelectric conversion layer PD2 in a unit pixel area PX where the third grid pattern 160C blocks the first photoelectric conversion layer PD1, and the light signal of the first photoelectric conversion layer PD1 can be determined more quickly from the light input to the first photoelectric conversion layer PD1 in another unit pixel area PX, thereby increasing the autofocus contrast in the image sensor.

[0198] Fig.10 It is shown that third mesh pattern 160C blocks the first and second photoelectric conversion layers PD1 and PD2 in adjacent unit pixel regions PX, which does not limit the inventive concept, and third mesh pattern 160C may block the first and second photoelectric conversion layers PD1 and PD2 in spaced-apart unit pixel regions PX.

[0199] Fig.11A and Fig. 11B They are shown respectively Fig.10 The enlarged areas P2 and P3.

[0200] Reference Fig.11A and Fig. 11B In some example embodiments, third grid pattern 160C may completely cover first photoelectric conversion layer PD1 or second photoelectric conversion layer PD2. Third grid pattern 160C may cover first photoelectric conversion layer PD1 in unit pixel region PX, and third grid pattern 160C may cover second photoelectric conversion layer PD2 in another unit pixel region PX, thereby quickly determining a signal of light input to first photoelectric conversion layer PD1 or second photoelectric conversion layer PD2 in unit pixel region PX and increasing an autofocus contrast in an image sensor, thereby improving an image generation function of the image sensor.

[0201] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F Shows relative to Fig.11A The area P2 of the cross-sectional view line F-F' or relative to Fig. 11B A top plan view of the area P3 of the cross-sectional view line G-G' in FIG. Fig. 12A , Fig. 12C and Fig.12E Shows relative to Fig.11A A top plan view of the area P2 along the sectional view line F-F' in FIG. Fig. 12B , Fig.12D and Fig.12F Shows relative to Fig. 11B A top plan view of area P3 along the cross-sectional view line G-G'.

[0202] Reference Fig. 12A and Fig. 12B The third grid pattern 160C may be disposed on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and may not be disposed on the first sub-separation pattern 120BT and the second sub-separation pattern 120BB (for example, the first sub-separation pattern 120BT and the second sub-separation pattern 120BB may be completely exposed in the third direction D3 and / or may not overlap with the first sub-separation pattern 120BT and the second sub-separation pattern 120BB in the third direction D3).

[0203] Reference Fig. 12C and Fig.12D, the third mesh pattern 160C may be disposed on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and may be disposed on at least a specific (or optionally, predetermined) region of the first sub-separation pattern 120BT and the second sub-separation pattern 120BB (for example, may overlap with the at least specific (or optionally, predetermined) region in the third direction D3). In detail, the third mesh pattern 160C may cover at least a specific (or optionally, predetermined) region of the width DCW of the first sub-separation pattern 120BT and the second sub-separation pattern 120BB.

[0204] Reference Fig.12E and Fig.12F , the third mesh pattern 160C may be disposed on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2 , and may be disposed to completely cover the first sub-separating pattern 120BT and the second sub-separating pattern 120BB.

[0205] Reference FIG. 12E to FIG. 12F Since the third mesh pattern 160C completely covers the first and second sub-separating patterns 120BT and 120BB, incident light may be prevented from being absorbed into the pad layer 120L of the first and second sub-separating patterns 120BT and 120BB.

[0206] Fig.13 FIG. 1 shows some exemplary embodiments of the present invention. Figure 5 A partial cross-sectional view of the image sensor along the cross-sectional view line CC'.

[0207] Reference Fig.13 In some example embodiments, third mesh pattern 160C may simultaneously block portions of first photoelectric conversion layer PD1 and second photoelectric conversion layer PD2 .

[0208] Fig.14A and Fig. 14B Shows relative to Fig.13 A top plan view of region P4 and region P5 along the cross-sectional view line HH'.

[0209] Reference Fig.14A , the third mesh pattern 160C may block portions of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, and may block the second sub-separating pattern 120BB. Fig. 14B , third mesh pattern 160C may block portions of first photoelectric conversion layer PD1 and second photoelectric conversion layer PD2 , and may block first sub-separating pattern 120BT.

[0210] In detail, since light-blocked unit pixels coexist in portions of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 (for example, the lower area or the upper area in the unit pixel area PX), the third grid pattern 160C can more quickly determine the light signals on the lower area and the upper area of ​​the unit pixel area PX, and can perform autofocus more quickly, thereby improving the image generation function of the image sensor based on constructing the image sensor to provide an improved autofocus function.

[0211] Fig.14A and Fig. 14B The third mesh pattern 160C is shown to completely cover the first sub-separation pattern 120BT or the second sub-separation pattern 120BB (for example, overlapping with the first sub-separation pattern 120BT or the second sub-separation pattern 120BB in the third direction D3), which is a non-limiting example, and the third mesh pattern 160C having the same length as the first sub-separation pattern 120BT and the second sub-separation pattern 120BB can be set.

[0212] An image sensor according to some example embodiments of the present inventive concept may include: a first substrate structure 100 including a first side 112a for receiving light and a second side 112b opposite to the first side 112a; a pixel separation pattern 120A for defining adjacent unit pixels in the first substrate structure 100; a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2 arranged along a first direction in the pixel separation pattern 120A; a first separation pattern 120B for defining the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in the first substrate structure 100 between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2; a first mesh pattern 160A disposed at the pixel separation pattern 120A; Pattern 120A; and a second grid pattern 160B, which is arranged on the first separation pattern 120B and has a lower height than the first grid pattern 160A, and another unit pixel separated from the unit pixel may include: a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2, which are arranged along a first direction in the pixel separation pattern 120A; a first separation pattern 120B, which is used to separate the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in the first substrate structure 100 between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2; and a third grid pattern 160C, which is arranged on at least one of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2.

[0213] In some example embodiments, the second mesh pattern 160B may be disposed between the first separation pattern 120B and the third mesh pattern 160C. In detail, the third mesh pattern 160C may cover at least a portion of the second mesh pattern 160B. For example, the third mesh pattern 160C may cover a portion of the second mesh pattern 160B, or may cover the entire second mesh pattern 160B.

[0214] In detail, a unit pixel in the image sensor includes a second grid pattern 160B, and another unit pixel arranged near or separated from the unit pixel has a structure in which at least a portion of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 blocks light, so that autofocusing can be performed faster from the unit pixel having the light blocking structure, photosensitivity can be increased simultaneously from the unit pixel including the second grid pattern 160B, and a high autofocusing separation ratio can be obtained.

[0215] Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig.15F , Figure 15G and Fig.15H A method for manufacturing an image sensor according to some example embodiments of the inventive concept is illustrated.

[0216] Reference Fig.15A , a first substrate structure 100 including a second side 112b and a third side 110c facing each other may be provided. A trench isolation pattern 105 may be formed in the first substrate structure 100. A trench, a portion of which is recessed from the second side 112b of the first substrate structure 100, may be formed in the first substrate structure 100. The trench isolation pattern 105 may be formed in the trench. The trench isolation pattern 105 may define an active region.

[0217] Reference Fig. 15B , a first mask layer M1 may be formed on the second side 112b of the first substrate structure 100. The first mask layer M1 may have an opening for defining the positions of the first trench t1 and the second trench t2. The first mask layer M1 may be formed of at least one of a photoresist layer, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), a silicon oxide layer, and a silicon nitride layer. The first trench t1 and the second trench t2 may be formed by using the first mask layer M1 as an etching mask. The first trench t1 and the second trench t2 may penetrate the trench isolation pattern 105.

[0218] Reference Fig. 15CA pre-liner film 120Lp may be formed along the sidewalls and bottom sides of the first trench t1 and the second trench t2. A pre-pixel separation filling film 120Fp may be formed on the pre-liner film 120Lp.

[0219] The pre-liner film 120Lp may extend along an upper side of the first mask layer M1. The pre-liner film 120Lp may include an insulating material. As a non-limiting example, the pre-liner film 120Lp may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and any combination thereof.

[0220] The pre-pixel separation filling film 120Fp may include an insulating material or a conductive material. The insulating material may include a silicon-based insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, and a high dielectric material such as hafnium oxide, aluminum oxide, or tantalum oxide. For example, the conductive material may include silicon doped with polycrystalline silicon (poly-Si), arsenic (As), phosphorus (P), boron (B), or carbon (C), and is not limited thereto.

[0221] In order to form a front deep trench isolator (FDTI), a pre-pixel separation filling film 120Fp may be deeply formed on the second side 112b in the direction of the third side 110c, and the pre-pixel separation filling film 120Fp may be filled in the first trench t1 and the second trench t2, and a first separation pattern 120B and a pixel separation pattern 120A may be formed.

[0222] Reference Fig.15D , a pixel separation pattern 120A and a first separation pattern 120B may be formed. The pixel separation pattern 120A may include a liner layer 120L, a first pixel separation filling film 120F1, and a cover film 120C. The first separation pattern 120B may include a liner layer 120L, a first separation filling film 120F2, and a cover film 120C.

[0223] The first pixel separation filling film 120F1 and the first separation filling film 120F2 may be formed by etching a portion of the pre-pixel separation filling film 120Fp. The first pixel separation filling film 120F1 and the first separation filling film 120F2 may be formed by an etch-back process. A pre-covering film (not shown) may be formed on the first pixel separation filling film 120F1 and the first separation filling film 120F2.

[0224] The liner layer 120L and the cover film 120C may be formed by removing portions of the pre-cover film, the pre-liner film 120Lp, and the first mask layer M1. The second side 112b of the first substrate structure 100 may be exposed by removing portions of the pre-cover film, the pre-liner film 120Lp, and the first mask layer M1.

[0225] Reference Fig.15E, the first side 112a may be formed by polishing the third side 110c which is the rear side of the first substrate structure 100. In order to polish the third side 110c, various types of polishing methods such as chemical mechanical polishing (CMP) may be used as a non-limiting example. According to the polishing method, polishing may be performed so that portions of the first pixel separation filling film 120F1 and the first separation filling film 120F2 may be disposed on the same plane of the first side 112a.

[0226] The first side 112a of the first substrate structure 100 may be rinsed. As a non-limiting example, the rinsing of the first side 112a of the first substrate structure 100 may be performed by using a material such as HF.

[0227] Reference Fig.15F , a surface insulating layer 150 may be applied on the washed first side 112a.

[0228] The surface insulating layer 150 may include an insulating material. For example, the surface insulating layer 150 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, and any combination thereof, and is not limited thereto.

[0229] Reference Figure 15G , a lower first mesh pattern 160AB and a second mesh pattern 160B may be formed on the surface insulating layer 150. The lower first mesh pattern 160AB and the second mesh pattern 160B may be made of the same material, for example, they may be formed according to a deposition or coating process. In some example embodiments, the lower first mesh pattern 160AB and the second mesh pattern 160B may be deposited or coated at the same height.

[0230] Reference Fig.15H , an upper first mesh pattern 160AT may be formed on the lower first mesh pattern 160AB. When the upper first mesh pattern 160AT is deposited or applied on the lower first mesh pattern 160AB, the first mesh pattern 160A including the upper first mesh pattern 160AT and the lower first mesh pattern 160AB is formed to be higher than the second mesh pattern 160B, so that when light is input according to the offset, the incident light may be controlled to be easily input to the photoelectric conversion layers PD1 and PD2.

[0231] Since the first mesh pattern 160A and the second mesh pattern 160B are formed in a stacked structure, the process may be simplified and an image sensor having a high light yield may be efficiently manufactured.

[0232] As described herein, any device, system, unit, block, circuit, controller, processor and / or portion thereof according to any example embodiment (for example, including a semiconductor chip, a pixel array 102, a logic circuit 202, a row decoder 21, a row driver 22, a timing generator 23, a correlated double sampler 24, an analog-to-digital converter 25, a latch portion 26, a column decoder 27, a first substrate structure 100, a second substrate structure 200, a third substrate structure 300, a memory device 302, any portion thereof, etc. as described herein) may include, may be included in and / or may be implemented by one or more instances of a processing circuit, which is hardware such as including a logic circuit; a hardware / software combination (such as a processor executing software); or any combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) storing an instruction program (e.g., a solid-state drive memory device), and a processor (e.g., a CPU) configured to execute the instruction program to implement the functions and / or methods performed by some or all of any device, system, unit, block, circuit, controller, processor, and part thereof according to any example embodiment.

[0233] Although the inventive concept has been described in conjunction with what are presently considered to be practical example embodiments, it will be understood that the inventive concept is not limited to these example embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended claims. Therefore, the above-described example embodiments are merely examples and should not be interpreted as being limiting in any respect.

[0234] <Description of Reference Numerals>

[0235] 100: First base structure

[0236] 200: Second base structure

[0237] PX: unit pixel area

[0238] 120A: Pixel separation pattern

[0239] 120B: First separation pattern

[0240] 150: Surface insulation layer

[0241] 160A: First grid pattern

[0242] 160B: Second grid pattern

[0243] 160C: Third grid pattern

Claims

1. An image sensor, comprising: a substrate including a first side configured to receive light and a second side opposite the first side; a pixel separation pattern configured to at least partially define a unit pixel in the substrate; A first photoelectric conversion layer and a second photoelectric conversion layer are arranged along a first direction in a pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate, the first separation pattern being between the first photoelectric conversion layer and the second photoelectric conversion layer; a first grid pattern on the pixel separation pattern; as well as The second mesh pattern is on the first separation pattern and has a lower height than the first mesh pattern.

2. The image sensor according to claim 1, wherein: The height of the second mesh pattern satisfies the range of 1 / 10 to 1 / 4 of the height of the first mesh pattern.

3. The image sensor according to claim 1, wherein: The image sensor includes a first color filter on the first grid pattern and the second grid pattern, a refractive index of the first color filter being a refractive index greater than a refractive index of the second grid pattern.

4. The image sensor according to claim 3, wherein: A ratio of a refractive index of the second mesh pattern to a refractive index of the first color filter on the second mesh pattern satisfies 0.40 to 0.

95.

5. The image sensor according to claim 1, wherein: The refractive index of the second mesh pattern satisfies 1.0 to 1.

6.

6. The image sensor according to claim 1, wherein: The first mesh pattern includes a lower first mesh pattern and an upper first mesh pattern, the upper first mesh pattern being on the lower first mesh pattern.

7. The image sensor according to claim 6, wherein: The lower first mesh pattern and the second mesh pattern have the same height.

8. The image sensor according to claim 6, wherein: The lower first mesh pattern and the upper first mesh pattern include different materials.

9. The image sensor according to claim 1, further comprising: a third photoelectric conversion layer, close to the first photoelectric conversion layer in the second direction in the unit pixel; as well as The fourth photoelectric conversion layer is close to the second photoelectric conversion layer in the second direction, The third photoelectric conversion layer and the fourth photoelectric conversion layer are at least partially defined by the first separation pattern.

10. The image sensor according to claim 1, wherein: The first separating pattern includes first and second sub-separating patterns spaced apart at certain intervals.

11. The image sensor according to claim 10, wherein: An area of ​​the second mesh pattern is equal to or greater than areas of the first sub-separating pattern and the second sub-separating pattern.

12. The image sensor according to claim 1, wherein: The pixel separation pattern is configured to at least partially define an additional unit pixel in a substrate, the additional unit pixel comprising: an additional first photoelectric conversion layer and an additional second photoelectric conversion layer, arranged along a first direction in the pixel separation pattern; an additional first separation pattern, configured to at least partially define an additional first photoelectric conversion layer and an additional second photoelectric conversion layer in the substrate, the additional first separation pattern being between the additional first photoelectric conversion layer and the additional second photoelectric conversion layer; and a third grid pattern, the third grid pattern being on at least one of the additional first photoelectric conversion layer of the additional unit pixel and the additional second photoelectric conversion layer of the additional unit pixel.

13. The image sensor according to claim 12, wherein: The third mesh pattern completely covers at least one of the additional first photoelectric conversion layer and the additional second photoelectric conversion layer.

14. The image sensor according to claim 12, wherein: The additional first separating pattern includes a first sub-separating pattern and a second sub-separating pattern spaced apart from each other at a certain interval, and The third mesh pattern is on at least a portion of the first sub-separating pattern and the second sub-separating pattern.

15. The image sensor according to claim 14, wherein: The third mesh pattern completely covers the first and second sub-separated patterns.

16. An image sensor, comprising: a substrate including a first side configured to receive light and a second side opposite the first side; a pixel separation pattern configured to at least partially define a unit pixel in the substrate; A first photoelectric conversion layer and a second photoelectric conversion layer are arranged along a first direction in a pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate, the first separation pattern being between the first photoelectric conversion layer and the second photoelectric conversion layer; as well as A first mesh pattern is on at least one of the first photoelectric conversion layer and the second photoelectric conversion layer.

17. The image sensor according to claim 16, wherein: The first mesh pattern covers at least a portion of the first separation pattern.

18. The image sensor according to claim 16, further comprising: The second mesh pattern is between the first separation pattern and the first mesh pattern.

19. An image sensor, comprising: a substrate including a first side configured to receive light and a second side opposite the first side; a pixel separation pattern configured to at least partially define a unit pixel in the substrate; A first photoelectric conversion layer and a second photoelectric conversion layer are arranged along a first direction in a pixel separation pattern; a first separation pattern configured to at least partially define the first photoelectric conversion layer and the second photoelectric conversion layer in the substrate, the first separation pattern being between the first photoelectric conversion layer and the second photoelectric conversion layer; a surface insulating layer on each of the pixel separation pattern, the first photoelectric conversion layer, the second photoelectric conversion layer, and the first separation pattern; a first grid pattern on at least a first portion of the surface insulating layer on the pixel separation pattern; a second mesh pattern having a lower height than the first mesh pattern on at least a second portion of the surface insulating layer on the first separation pattern; as well as a color filter on each of the first grid pattern and the second grid pattern, The height of the second grid pattern is 1 / 10 to 1 / 4 of the height of the first grid pattern.

20. The image sensor according to claim 19, wherein: The pixel separation pattern is configured to at least partially define an additional unit pixel in a substrate, the additional unit pixel comprising: an additional first photoelectric conversion layer and an additional second photoelectric conversion layer, arranged along a first direction in the pixel separation pattern; an additional first separation pattern, configured to at least partially define an additional first photoelectric conversion layer and an additional second photoelectric conversion layer in the substrate, the additional first separation pattern being between the additional first photoelectric conversion layer and the additional second photoelectric conversion layer; and a third grid pattern on at least one of the additional first photoelectric conversion layer and the additional second photoelectric conversion layer.

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