High voltage semiconductor device

Abstract

A high voltage semiconductor device (100) includes a substrate (410) having a background doping of a first conductivity type. The substrate (410) includes a doped shielding region (416) of a complementary second conductivity type formed along the first substrate surface (411). An insulator layer (420) is formed on the first substrate surface (411). A semiconductor layer (430) is formed on the insulator layer (420) so as to face the substrate (410). A first interlayer dielectric (440) is formed on the semiconductor layer (430). A first metal layer (450) including laterally spaced first field plate elements (456) is formed on a first portion of the first interlayer dielectric (440) in the termination region (650). A second interlayer dielectric (460) is formed on the first metal layer (450) and on a second portion of the first interlayer dielectric (440) between the first field plate elements (456).

Description

Technical Field

[0001] Examples of the present disclosure relate to semiconductor devices having active elements integrated in high voltage terminations between high voltage domains and low voltage domains. In particular, the present disclosure may relate to gate driver circuits having signal paths that exchange electrical signals between high voltage domains and low voltage domains. Background Art

[0002] HV (high voltage) semiconductor devices in CMOS (complementary metal oxide semiconductor) technology form an interface between standard CMOS devices with input voltages up to 5V on the one hand and industrial or consumer circuits operating at signal voltage levels higher than 30V on the other hand. The application of such HV semiconductor devices exists in various power conversions and power drives up to the kW range, such as in power converters, robots and the automotive industry. Such HV semiconductor devices generally include a low voltage part as a low voltage domain and an HV part as a high voltage domain. In the low voltage part, most of the signal processing is completed at a low operating voltage. The HV part operates at a higher voltage level and provides a signal interface for power semiconductors using a higher voltage level and / or having a higher current drive and absorption capability. An example of such an HV semiconductor device is a gate driver circuit that enables a microcontroller or DSP (digital signal processor) to effectively turn on and off a power semiconductor switch. The HV termination separates two or more CMOS circuits in different voltage domains, and the potentials of the different voltage domains may differ by hundreds of volts to thousands of volts. The lateral width of the HV termination depends on the voltage breakdown capability required between the voltage domains. The HV termination may include a field plate structure and typically occupies a significant portion of the HV semiconductor device.

[0003] There is a continuing need to improve the area efficiency of HV semiconductor devices with little additional effort. Summary of the invention

[0004] In a field plate structure made of a single metal layer, each individual field plate element forms a 3D structure having a lower portion and two upper portions, wherein the lower portion lines a gap in the field plate oxide and each of the two upper portions covers a portion of the surface of the field plate oxide that is directly adjacent to the gap. The thickness of the metal layer is selected to be thin enough to enable a high wiring density on the semiconductor device and thick enough to provide a sufficiently stable wire bonding pad. Typically, a deposition process using a high-density plasma is used to deposit a passivation layer on the lower and upper portions of the field plate elements and on portions of the field plate oxide between the field plate elements. The passivation layer is deposited on the lower and upper portions of the field plate elements and on the field plate oxide with approximately the same thickness. The present embodiment is intended to avoid the limitations of this approach.

[0005] An embodiment of a semiconductor device includes a substrate having a background doping of a first conductivity type and including a doped shielding region of a complementary second conductivity type formed along a surface of the first substrate. An insulator layer is formed on the surface of the first substrate. A semiconductor layer is formed on the insulator layer opposite to the substrate. A first interlayer dielectric is formed on the semiconductor layer. A first metal layer including laterally spaced first field plate elements is formed on a first portion of the first interlayer dielectric. A second interlayer dielectric is formed on the first metal layer and on a second portion of the first interlayer dielectric between the first field plate elements.

[0006] An embodiment of a semiconductor device includes a substrate having a background doping of a first conductivity type and including a doped shielding region of a complementary second conductivity type formed along a surface of the first substrate. An insulator layer is formed on the surface of the first substrate. A semiconductor layer is formed on the insulator layer opposite to the substrate. A first interlayer dielectric is formed on the semiconductor layer. A first metal layer including laterally spaced first field plate elements is formed on a first portion of the first interlayer dielectric. A second interlayer dielectric is formed on the first metal layer and on a second portion of the first interlayer dielectric between the first field plate elements. An uppermost metal layer is formed on the second interlayer dielectric. The uppermost metal layer includes laterally spaced second field plate elements. The second interlayer dielectric longitudinally spaces the second field plate elements from the first field plate elements. A lateral gap is formed between adjacent ones of the second field plate elements, wherein at least 50% of the lateral extension of the lateral gap is laterally overlapped by one of the first field plate elements.

[0007] In the case where the field plate structure in the termination area is formed by a single metal layer, the top surface of the passivation layer formed on the metal layer using high-density plasma includes terraces at different distances from the substrate. In contrast, in a high-voltage semiconductor device according to an embodiment, a first metal layer is specifically formed on a first portion of a first interlayer dielectric, so that a second interlayer dielectric formed on a second portion of the first interlayer dielectric between the first metal layer and the first field plate element can be flattened, and one or more other metal layers can be formed on the second interlayer dielectric. Other metal layers can be designed to form an electric field in the termination area of ​​the substrate and form a stable wire bonding substrate. The first metal layer makes it possible to define the lower portion of the field plate structure in the termination area and the interconnection lines of the electrical components in the device portion formed on both sides of the termination area in a single patterning process. The thickness of the other metal layers and the thickness of the first metal layer can be different and can be independently adapted to the corresponding requirements.

[0008] The present invention relates to a high voltage semiconductor device having a high voltage domain and a low voltage domain. A more specific example of such a high voltage semiconductor device is a gate driver device having a high side portion (as the high voltage domain) and a low side portion (as the low voltage domain).

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are provided for a further understanding of the embodiments and constitute an integral part of the specification. The accompanying drawings illustrate embodiments of HV semiconductor devices with active components integrated in HV termination structures and together with the specification explain the basic principles of the embodiments. Additional embodiments are described in the following detailed description and claims. The features of the various illustrated embodiments may be combined with each other.

[0011] Figure 1 is a schematic longitudinal cross-sectional view of a portion of a semiconductor device having active elements integrated in a high voltage termination structure according to an embodiment, the embodiment having a laterally spaced first field plate element formed on a first portion of a first interlayer dielectric, and a second interlayer dielectric covering a second portion of the first interlayer dielectric and the first field plate element.

[0012] Figure 2 According to the implementation method Figure 1 Schematic plan view of a field plate element of a semiconductor device.

[0013] Figure 3 is a schematic longitudinal cross-sectional view of a portion of a semiconductor device with active elements integrated in a high voltage termination structure according to an embodiment with a second field plate element formed on a second interlayer dielectric.

[0014] Figure 4 is a schematic longitudinal cross-sectional view of a portion of a semiconductor device with active elements integrated in a high voltage termination structure according to an embodiment with an intermediate metal layer and an intermediate dielectric layer between a second interlayer dielectric and a second field plate element.

[0015] Figure 5 According to the implementation method Figure 3 or Figure 4 A schematic horizontal cross-sectional view of a semiconductor device in a plane cutting through a doped shielding region formed in a substrate.

[0016] Figure 6 According to the implementation method Figure 3 or Figure 4 A schematic plan view of a semiconductor device.

[0017] Figure 7 is a schematic longitudinal cross-sectional view of a portion of a semiconductor device having a semiconductor diode integrated in a high voltage termination structure according to an embodiment.

[0018] Fig. 8A is a schematic plan view of a semiconductor device having a field plate structure including a modified portion below an active element integrated in a high voltage termination structure according to an embodiment.

[0019] Figure 8B FIG. 1 shows an embodiment related to a modified field plate portion having a reduced peak dopant concentration. Fig. 8A Details of the field plate structure.

[0020] Figure 8C FIG. 1 shows an embodiment related to a modified field plate portion having a narrow width. Fig. 8A Details of the field plate structure.

[0021] Fig. 9 is a schematic block diagram of a gate driver circuit having two level-shift transistors for exchanging electrical signals between a high-side part and a low-side part according to an embodiment.

[0022] Fig.10 is a schematic plan view of a semiconductor device having active elements integrated in a high voltage termination structure according to an embodiment.

[0023] Fig.11 is a schematic plan view of a semiconductor device having active elements integrated in a high voltage termination structure according to an embodiment.

[0024] Fig.12 is a schematic plan view of a HV semiconductor diode integrated in a high voltage termination structure of a semiconductor device and including a compensation structure according to an embodiment.

[0025] Fig.13 is a schematic plan view of a HV semiconductor diode integrated in a high voltage termination structure of a semiconductor device and including a compensation structure according to another embodiment.

[0026] Fig.14 is a schematic plan view of a level-shift transistor integrated in a high voltage termination structure of a semiconductor device and including a compensation structure according to an embodiment.

[0027] Fig.15A and Fig. 15B is a schematic longitudinal cross-sectional view of a portion of a semiconductor device having a field effect transistor integrated in a high voltage termination structure according to an embodiment.

[0028] Fig.16A and Fig. 16B is a schematic longitudinal cross-sectional view of a portion of a semiconductor device having a field effect transistor integrated in a high voltage termination structure according to an embodiment. DETAILED DESCRIPTION

[0029] In the following detailed description, reference is made to the accompanying drawings forming a part of this document, in which certain embodiments of semiconductor devices having active elements integrated in high voltage termination structures are shown as illustrations. Structural or logical changes may be made to the illustrated embodiments without departing from the scope of the present disclosure. For example, features shown or described for one embodiment may be used on or in combination with other embodiments to produce another embodiment. The present disclosure is intended to include such modifications and variations. The embodiments are described in a manner that should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale but are for illustration purposes only. Unless otherwise specified, corresponding elements are represented by the same reference numerals in the various drawings.

[0030] The terms "having", "containing", "including", "comprising", etc. are open ended, and these terms indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" include plural as well as singular.

[0031] The term "direct electrical connection" describes a permanent low resistance ohmic connection between electrically connected elements, such as a direct contact between the relevant elements or a low resistance connection via metal and / or heavily doped semiconductor material.

[0032] The terms "signal connection" and "electrical coupling" include permanent low-resistance ohmic connections between electrically connected elements, such as direct contact between the relevant elements or low-resistance connections via metal and / or heavily doped semiconductor materials, but do not exclude the presence of other passive and / or active elements in the signal path between the "signal connection" or "electrical coupling" elements. For example, other elements may include resistors, resistive conductor lines, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, etc.

[0033] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30 V (e.g., 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV, or higher) and having a nominal on-state current or forward current of at least 200 mA (e.g., 1 A, 10 A, or higher).

[0034] A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a voltage controlled device and includes all types of IGFETs (Insulated Gate Field Effect Transistors) having a gate electrode based on doped semiconductor material and / or metal and having a gate dielectric made of oxide and / or dielectric material other than oxide.

[0035] An ohmic contact describes a non-rectifying electrical junction between two conductors, such as a semiconductor material and a metal. According to Ohm's law, an ohmic contact has a linear or nearly linear IV curve in the first and third quadrants of a current-voltage (IV) diagram.

[0036] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value such as "at most" and "at least".

[0037] The term “on” should not be interpreted as meaning only “directly on.” Rather, if one element is “on” another element (e.g., a layer is “on” another layer or is “on” a substrate), additional components (e.g., additional layers) may be located between the two elements (e.g., if a layer is “on” a substrate, the additional layers may be located between the layer and the substrate).

[0038] Two adjacent doped regions in a semiconductor layer form a semiconductor junction. Two adjacent doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, such as an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa. Two adjacent doped regions with complementary conductivity form a pn junction.

[0039] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions can have the same or different absolute doping concentrations.

[0040] The present disclosure relates to a high voltage semiconductor device including a substrate having a background doping of a first conductivity type. The substrate may include a doped shielding region of a complementary second conductivity type formed along a first substrate surface. An insulator layer is formed on the first substrate surface. A semiconductor layer is formed on the insulator layer opposite to the substrate. A first interlayer dielectric is formed on the semiconductor layer. A first metal layer that may include a laterally spaced first field plate element is formed on a first portion of the first interlayer dielectric. A second interlayer dielectric is formed on a second portion of the first interlayer dielectric between the first metal layer and the first field plate element.

[0041] The substrate may have a flat first substrate surface extending along a horizontal direction. A normal line on the first substrate surface defines a longitudinal direction. The substrate, the insulator layer, the semiconductor layer, the first interlayer dielectric, the first metal layer and the second interlayer dielectric or at least a portion thereof are stacked longitudinally on each other along the longitudinal direction.

[0042] The doped shielding region may form a doped shielding structure in the substrate. The doped shielding structure is formed in a termination region having a high voltage blocking capability between the first device region and one or more other device regions. The doped shielding structure may form a frame around the first device region. The frame may be closed or have gaps. Along the periphery of the frame, the size, dopant dosage and / or dopant distribution of the doped shielding region may be constant or variable.

[0043] The semiconductor layer may be formed on the planar front surface of the insulator layer. The semiconductor layer may include a plurality of laterally spaced apart device portions, wherein the lateral insulator structure may space the device portions apart in a horizontal direction.

[0044] The first interlayer dielectric may be a homogeneous layer or a layer stack comprising two or more sublayers of different composition and / or internal structure. The first interlayer dielectric may be a deposited silicon oxide layer and / or may include doped or undoped silicate glass, silicon nitride and / or silicon oxynitride. The first interlayer dielectric covers a lateral insulator structure between a device portion of the semiconductor layer and an adjacent device portion. The first interlayer dielectric may be in direct contact with the device portion of the semiconductor layer.

[0045] The first metal layer having the one or more first field plate elements may be in direct contact with the first interlayer dielectric.The first metal layer may be a homogeneous layer or include two or more sub-layers having different compositions.

[0046] The second interlayer dielectric may be a homogeneous layer or a layer stack including two or more sublayers of different composition and / or internal structure. The second interlayer dielectric may be a deposited silicon oxide layer and / or may include doped or undoped silicate glass, silicon nitride and / or silicon oxynitride. The second interlayer dielectric covers the first metal layer with the first field plate elements and fills the gaps between the first field plate elements. In the gaps between the first field plate elements, the second interlayer dielectric is directly formed on the second portion of the first interlayer dielectric. The top surface of the second interlayer dielectric may be flat, for example, flattened by a CMP (chemical mechanical polishing) process.

[0047] The first field plate elements and the doping shielding regions are at predetermined lateral positions relative to each other. The number of first field plate elements may be equal to the number of doping shielding regions. For some or all of the first field plate elements, a longitudinal projection of one first field plate element on the surface of the first substrate may just overlap with one of the doping shielding regions.

[0048] The first field plate element may be formed in the same patterning process as an interconnection line of the electrical device formed in the device portion of the semiconductor layer. The interconnection line and the first field plate element are formed from different parts of one deposited metal layer or metal layer stack and may be defined in the same lithographic mask.

[0049] According to an embodiment, the high voltage semiconductor device may include a first field plate element laterally surrounding a first device region.

[0050] The first field plate element forms a first field plate structure that can completely surround the first device region. The first field plate structure can be completely formed in a termination region that laterally separates the first device region and the second device region. The termination region is formed with a high voltage blocking capability between a conductive and / or semiconductor element formed in the first device region and a conductive and / or semiconductor element formed in the second device region.

[0051] The first device region may include a first active element operating at a first signal voltage level. The second device region may include a second active element operating at a second signal voltage level different from the first signal voltage level. The difference between the first signal voltage level and the second signal voltage level may be several hundred volts or even up to 2000V.

[0052] According to an embodiment, a top surface of the second interlayer dielectric opposite to the first metal layer may be flat. The second interlayer dielectric may include an opening extending from the top surface to the first metal layer.

[0053] Forming the second interlayer dielectric may include depositing a material of the second interlayer dielectric and planarizing the deposited material by CMP to obtain a planar top surface. The thickness of the second interlayer dielectric may be in the range of 250 nm to 4 μm, for example, 500 nm to 2 μm.

[0054] According to an embodiment, the high voltage semiconductor device may further include an uppermost metal layer formed on the second interlayer dielectric.

[0055] The uppermost metal layer may be formed directly on a flat top surface of the second interlayer dielectric opposite to the first metal layer. Alternatively, other layers may be formed between the second interlayer dielectric and the uppermost metal layer.

[0056] The top metal layer may be a homogeneous layer or include two or more sub-layers having different compositions. The thickness of the top metal layer is independent of the thickness of the first metal layer. For example, the top metal layer and the first metal layer may have approximately the same thickness.

[0057] According to an embodiment, the uppermost metal layer may include a laterally spaced second field plate element.The second interlayer dielectric may longitudinally space the second field plate element from the first field plate element.

[0058] The second field plate element forms a second field plate structure. The second field plate structure may be formed completely in the termination region. The second field plate structure may completely surround the first device region.

[0059] According to an embodiment, the field plate contact may extend from the second field plate element through the opening in the second interlayer dielectric to the first field plate element.

[0060] The field plate contact may electrically connect each of the second field plate elements with one single first field plate element such that each first field plate element is connected to one second field plate element and each second field plate element is connected to one first field plate element.

[0061] A first field plate element and a second field plate element form a longitudinally patterned field plate. The longitudinal cross-section of the field plate can be changed by changing the lateral width of the first field plate element and the second field plate element and / or by a lateral offset between the lateral centers of the first field plate element and the second field plate element, so that the electric field distribution in the termination area can be adjusted for a desired trade-off between high voltage breakdown capability and area efficiency.

[0062] According to an embodiment, the uppermost metal layer is formed directly on the second interlayer dielectric.

[0063] No further layers, in particular no further metal layers, are formed between the first metal layer and the uppermost metal layer.

[0064] According to another embodiment, at least one intermediate metal layer is formed between the first metal layer and the uppermost metal layer.

[0065] One or more intermediate interlayer dielectrics separate the intermediate metal layer from the first metal layer and / or the uppermost metal layer from each other.

[0066] According to an embodiment, each intermediate metal layer of the at least one intermediate metal layer may include an intermediate field plate element, wherein each intermediate field plate element may be electrically connected to one of the first field plate elements.

[0067] A first field plate element, a second field plate element and an intermediate field plate element of each intermediate metal layer can form a longitudinally patterned field plate. By changing the lateral width of the first field plate element, the second field plate element and the intermediate field plate element, and / or by the lateral offset between the lateral centers of the first field plate element, the second field plate element and the intermediate field plate element, the longitudinal cross-section of the final field plate can be changed, so that the electric field distribution in the termination area can be adjusted to achieve a desired compromise between high voltage breakdown capability and area efficiency.

[0068] According to an embodiment, a first lateral gap is formed between adjacent first field plate elements of the first field plate elements, wherein at least 50% or at least 80% of the lateral extension of the first lateral gap is laterally overlapped by one of the second field plate elements. In another embodiment, 100% (e.g., + / - 5% due to tolerances) of the gap is laterally overlapped by the second field plate element, while the second field plate element overlaps only one of the adjacent first field plate elements. In this case, the second field plate element overlaps one of the adjacent first field plate elements, while the sides of the second field plate element and the other adjacent first field plate element are laterally aligned.

[0069] According to an embodiment, one of the second field plate elements laterally overlaps at least a portion of each of two adjacent ones of the first field plate elements.

[0070] According to another embodiment, one of the second field plate elements also laterally overlaps one of two adjacent first field plate elements of the first field plate elements by at least 20% or at least 50%.

[0071] According to an embodiment, a second lateral gap is formed between adjacent second field plate elements of the second field plate elements, wherein at least 50% of the lateral extension of the second lateral gap is laterally overlapped by one of the first field plate elements. In another embodiment, 100% (e.g., + / - 5% due to tolerances) of the gap is laterally overlapped by the first field plate element, while the first field plate element overlaps only one of the adjacent second field plate elements. In this case, the first field plate element overlaps one of the adjacent second field plate elements, while the sides of the first field plate element and the other adjacent second field plate element are laterally aligned.

[0072] According to an embodiment, one of the first field plate elements laterally overlaps at least a portion of each of two adjacent ones of the second field plate elements.

[0073] According to another embodiment, one of the first field plate elements also laterally overlaps one of two adjacent ones of the second field plate elements by at least 20% or at least 50%.

[0074] According to an embodiment, the thickness of the uppermost metal layer may be at least 1.2 times, eg at least twice, the thickness of the first metal layer.

[0075] In particular, the uppermost metal layer may be suitable as a wire bonding substrate. For example, the uppermost metal layer may be formed of an alloy containing aluminum Al and / or copper Cu. The thickness of the uppermost metal layer may be at most 10 times the thickness of the first metal layer.

[0076] The second field plate element may be formed in the same patterning process as the wire bond pad.The wire bond pad and the second field plate element are formed from different portions of one deposited metal layer or metal layer stack and may be defined in the same photolithographic mask.

[0077] According to an embodiment, the doping shielding region may form a laterally spaced-apart frame around the first device region.

[0078] Each of the first field plate element, the second field plate element, and the doping shielding region has a width along a line directly connecting the first device region and the second device region. The width of each field plate element and the width of each doping shielding region can be consistent along the entire perimeter of the termination region. Alternatively, the width of each doping shielding region can vary, depending on whether an active element is formed in the semiconductor layer of the relevant portion of the termination region, and if an active element is formed, depending on which active element is formed in the semiconductor layer of the relevant portion of the termination region.

[0079] Each first field plate element can be formed directly above a single one of the doping shielding regions. The widths of the first field plate element and the associated doping shielding region can be different. The lateral centerlines of the first field plate element and the associated doping shielding region can be longitudinally aligned with each other or can be slightly offset from each other, wherein the lateral centerline of the first field plate element can be offset inwardly or outwardly relative to the lateral centerline of the doping shielding region.

[0080] Each second field plate element is formed directly above a single one of the doping shielding regions. At least some, most or all of the second field plate elements are wider in their longitudinal projection than the corresponding first field plate elements and / or wider in their longitudinal projection than the corresponding doping shielding regions. The lateral centerlines of the second field plate elements and the associated doping shielding regions may be longitudinally aligned with each other, or may be offset inwardly or outwardly relative to the first device region.

[0081] A distance between two adjacent second field plate elements may be smaller than a distance between two associated first field plate elements and / or a distance between two associated doping screening regions.

[0082] According to an embodiment, the active element is formed in a transition device portion of the semiconductor layer.

[0083] The transition device portion may extend from the first device region or from within the first device region on the first side of the first field plate element to the second device region or into the second device region on the second side of the first field plate element.

[0084] That is, the transition device portion extends from a first side of the first field plate structure including the first field plate element to a second side of the first field plate structure.

[0085] The semiconductor layer includes one or more laterally spaced first device portions in a first device region. The first device portion is formed entirely on a first side of a first field plate structure. The second device portion is formed entirely on a second side of the first field plate structure. The active element includes a main portion formed in a termination region and may also include an inner sub-portion in the first device region and / or an outer sub-portion in the second device region.

[0086] The active element may be a level shifter transistor, or a high voltage diode (HV diode), such as a bootstrap diode or an ESD (electrostatic discharge) diode. The high voltage semiconductor device may include multiple transition device regions with more than one ESD diode, more than one bootstrap diode and / or more than one level shifter transistor.

[0087] According to an embodiment, the doping shielding region forms a laterally spaced frame around the first device region. A first portion of the doping shielding region directly facing the transition device portion may differ in width, dopant dose and / or dopant distribution from a second portion of the doping shielding region not directly facing the transition device portion.

[0088] The doping shielding region may form a closed loop of different widths and / or different dopant distributions. The semiconductor layer may include more than one transition device portion, wherein in each transition device portion, another different active element is formed. Opposite to each transition device portion, another portion of the doping shielding region may be formed. Each portion of the doping shielding region may have another width and / or another maximum dopant concentration.

[0089] According to an embodiment, a portion of at least one of the doping shielding regions is produced by implanting dopants through a mask having parallel mask grooves.

[0090] The distance between adjacent mask trenches may be small enough so that after implantation and annealing, a continuous doped shielding region without gaps is formed in the associated substrate region below the mask trenches.A common implantation process may be shared to form the different doped portions of the doped shielding region.

[0091] According to an embodiment, the active element may be a bootstrap diode.

[0092] According to another embodiment, the active element may be a level shift transistor.

[0093] The high voltage semiconductor device may include multiple active elements, for example, more than one ESD diode, more than one bootstrap diode and / or more than one level shifter transistor.

[0094] According to an embodiment, the high voltage semiconductor device comprises a further active element having a different function than the active element, wherein the first field plate element laterally overlaps the two active elements in respective overlapping regions, and wherein the first field plate elements have the same spacing from one another in the two overlapping regions.

[0095] The first field plate elements may have the same size and spacing to each other in the region of the two active elements. Furthermore, the second field plate elements, any intermediate field plate elements and the doping shielding region may have the same size and spacing to each other for both active elements. The final longitudinally patterned field plate has the same effect in both active elements and provides the same lateral field distribution along the radial direction for both active elements. This may be applicable to more than two active elements, for example, for all active elements formed in an HV termination.

[0096] According to an embodiment, the active element may include a compensation structure. The compensation structure may include p-doped regions and n-doped regions alternately arranged along a horizontal direction orthogonal to a current flow direction in the active element.

[0097] The compensation structure can have a superjunction configuration in which the dopant in the p-doped region and the dopant in the n-doped region highly compensate each other. The width and dopant distribution of the p-doped region and the n-doped region are selected to meet the tradeoff between HV breakdown voltage and drive current capability and / or can be used to fine-tune the voltage blocking capability of the termination region. The p-doped region and the n-doped region can be formed by low-dose implantation, which is otherwise available in the baseline process. The formation of the p-doped region can be combined with the body implantation of the logic MOSFET in the first device portion and the second device portion of the semiconductor layer.

[0098] According to an embodiment, the thickness of the insulator layer may be in the range of 40 nm to 1000 nm.

[0099] Figure 1 A high voltage semiconductor device 100 is shown including a first device region 610 , a second device region 690 , and a termination region 650 laterally spacing the first device region 610 and the second device region 690 .

[0100] The semiconductor device includes a substrate 410 having a flat first substrate surface 411. The first substrate surface 411 extends in a horizontal (lateral) direction. The normal on the first substrate surface 411 defines a longitudinal direction. The substrate 410 includes a semiconductor material. For example, the semiconductor material can be any IV group element semiconductor, such as silicon Si or germanium Ge, any IV group compound semiconductor, such as silicon carbide SiC or silicon germanium SiGe, or any III / V group compound semiconductor. The substrate 410 is single crystalline and can have a uniform n-type background doping. In the termination region 650, a p-doped shielding region 416 extends from the first substrate surface 411 into the substrate 410. The p-doped shielding region 416 forms a doping shielding structure 415 between the first device region 610 and the second device region 690.

[0101] The insulator layer 420 formed directly on the first substrate surface 411 separates the substrate 410 from the semiconductor layer 430 formed on the side of the insulator layer 420 opposite to the substrate 410. The insulator layer 420 is a homogeneous layer or a layer stack including two or more sublayers of different composition and / or internal structure. For example, the insulator layer 420 includes or consists of deposited silicon oxide and / or thermally grown silicon oxide. The thickness of the insulator layer 420 can be in the range of 40nm to 1000nm.

[0102] The semiconductor layer 430 is formed directly on the planar front surface 421 of the insulator layer 420. The semiconductor layer 430 includes a transition device portion 435, wherein at least a portion of the transition device portion 435 is formed in the termination region 650. In the illustrated embodiment, the transition device portion 435 extends laterally into the first device region 610 and the second device portion 690. In other embodiments, the transition device portion 435 may be formed entirely within the termination region 650, may extend from the termination region 650 only into the first device region 610, or may extend from the termination region 650 only into the second device region 690.

[0103] The lateral insulator structure 439 laterally separates the transition device portion 435 from other device portions of the semiconductor layer 430. The lateral insulator structure 439 fills the gap between the transition device portion 435 and other device portions and may include a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI). The longitudinal extension of the lateral insulator structure 439 and the longitudinal extension of the transition device portion 435 may be equal.

[0104] The first interlayer dielectric 440 is formed directly on the semiconductor layer 430 on the side opposite to the insulator layer 420. The first interlayer dielectric 440 can be a homogeneous layer or a layer stack including two or more sublayers of different composition and / or internal structure. The first interlayer dielectric 440 can be or include a deposited silicon oxide layer and / or a doped or undoped silicate glass layer, a silicon nitride layer and / or a silicon oxynitride layer. The first interlayer dielectric 440 covers the transition device portion 435 of the semiconductor layer 430 and the lateral insulator structure 439 surrounding the transition device portion 435. The lateral insulator structure 439 can be formed of a material forming the first interlayer dielectric 440.

[0105] The first metal layer 450 is formed directly on a flat top surface 441 on a side of the first interlayer dielectric 440 opposite to the semiconductor layer 430. The first metal layer 450 includes a laterally spaced first field plate element 456 formed on a first portion of the top surface 441 of the first interlayer dielectric 440. The first metal layer 450 may be a homogeneous layer or may include two or more sublayers containing metals. The first metal layer 450 may include one or more elemental metals, such as aluminum Al, copper Cu, tungsten W, tantalum Ta or titanium Ti, metal nitrides, such as titanium nitride TiN, tantalum nitride TaN and / or a metal alloy containing at least one of aluminum Al and copper Cu. The first field plate element 456 forms a first field plate structure 455 between the first device region 610 and the second device region 690.

[0106] The first field plate structure 455 and the doping shield structure 415 cooperate to provide a high voltage blocking capability between the first device region 610 and the second device region 690 with high area efficiency.

[0107] To this end, the first field plate elements 456 and the doping shielding regions 416 are laterally aligned with each other, wherein each lateral edge of each first field plate element 456 has a predetermined lateral distance to the corresponding lateral edge of the corresponding doping shielding region 416. The number of first field plate elements 456 and the number of doping shielding regions 416 can be equal. The longitudinal projection of each first field plate element 456 on the first substrate surface 411 overlaps with one of the doping shielding regions 416 to some extent. The width of the first field plate element 456 can be greater or less than the width of the corresponding doping shielding region 416. Alternatively, the width of the first field plate element 456 and the width of the corresponding doping shielding region 416 can be equal.

[0108] The second interlayer dielectric 460 is formed directly on the first metal layer 450 on the side opposite to the first interlayer dielectric 440. The second interlayer dielectric 460 may be a homogeneous layer or a layer stack including two or more sublayers of different composition and / or internal structure. The second interlayer dielectric 460 may be composed of or include a deposited silicon oxide layer and / or may include a doped or undoped silicate glass layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0109] The second interlayer dielectric 460 covers the first field plate elements 456 and fills the gaps between the first field plate elements 456. The second interlayer dielectric 460 is formed directly on a second portion of the top surface 441 of the first interlayer dielectric 440 exposed by the first metal layer 450 in the gaps between the first field plate elements 456. Forming the second interlayer dielectric 460 may include depositing a material of the second interlayer dielectric 460 and planarizing the deposited material by chemical-mechanical polishing (CMP) to obtain a planar top surface 461. The contact via 462 may extend from the top surface 461 of the second interlayer dielectric 460 to the first metal layer 450.

[0110] The substrate 410 , the insulator layer 420 , the semiconductor layer 430 , the first interlayer dielectric 440 , the first metal layer 450 , and the second interlayer dielectric 460 are longitudinally stacked on one another along a longitudinal direction.

[0111] The first field plate element 456 in the termination region 650 may be formed in the same patterning process as an interconnect line that electrically connects electrical devices formed in the device portion of the semiconductor layer 430 in the device regions 610, 690 of the semiconductor device 100. The interconnect line and the first field plate element 456 are formed from the same deposited metal layer or different portions of a metal layer stack and may be defined in the same photolithography mask.

[0112] Figure 2 A first field plate structure 455 is shown laterally surrounding the first device region 610 .

[0113] In the illustrated semiconductor device 100, the first field plate structure 455 includes three laterally spaced first field plate elements 456. The first field plate structure 455 is formed entirely in a termination region 650 that laterally spaces apart a first device region 610 and a second device region 690. The termination region 650 provides a high voltage blocking capability between conductive and / or semiconducting elements formed in the first device region 610 and conductive and / or semiconducting elements formed in the second device region 690.

[0114] Figure 3 The uppermost metal layer 490 is shown formed directly on the flat top surface 461 on the side of the second interlayer dielectric 460 opposite the first metal layer 450. The uppermost metal layer 490 includes a laterally spaced second field plate element 496 formed on a first portion of the top surface 461 of the second interlayer dielectric 460. The uppermost metal layer 490 may include one or more elemental metals such as aluminum Al, copper Cu, tungsten W, tantalum Ta or titanium Ti, metal nitrides such as titanium nitride TiN, tantalum nitride TaN and / or a metal alloy containing at least one of aluminum Al and copper Cu. The second field plate element 496 forms a second field plate structure 495 between the first device region 610 and the second device region 690.

[0115] The second field plate structure 495 is completely formed in the termination region 650 and may completely surround the first device region 610 .

[0116] A field plate contact 469 extends from the second field plate element 496 through the opening in the second interlayer dielectric 460 to the first field plate element 456 .

[0117] The field plate contact 469 can electrically connect each of the second field plate elements 496 to the first field plate element 456 , for example, to a single first field plate element 456 , so that each second field plate element 496 is connected to at least one first field plate element 456 , and each first field plate element 456 is connected to one second field plate element 496 .

[0118] A set of first field plate elements 456 and second field plate elements 496, for example, one first field plate element 456 and one second field plate element 496, forms a longitudinally patterned field plate. The longitudinal cross-section of the longitudinally patterned field plate can be changed by changing the lateral width of the first field plate element 456 and the second field plate element 496 and / or by the lateral offset between the lateral centers of the first field plate element 456 and the second field plate element 496, so that the electric field distribution in the termination region 650 can be adjusted for the desired trade-off between high voltage breakdown capability and area efficiency.

[0119] exist Figure 3 In the semiconductor device 100 , no other metal layer is formed between the first metal layer 450 and the uppermost metal layer 490 .

[0120] exist Figure 4 In the semiconductor device 100 shown, an intermediate metal layer 470 and an intermediate interlayer dielectric 480 are formed between the first metal layer 450 and the uppermost metal layer 490 .

[0121] The intermediate metal layer 470 includes laterally spaced apart intermediate field plate elements 476. Each intermediate field plate element 476 is electrically connected to at least one of the first field plate elements 456 and at least one of the second field plate elements 496.

[0122] In the illustrated embodiment, each intermediate field plate element 476 is electrically connected to one of the first field plate elements 456 and one of the second field plate elements 496, wherein one first field plate element 456, one intermediate field plate element 476 electrically connected to the first field plate element 456, and one second field plate element 496 electrically connected to the intermediate field plate element 476 form a longitudinally patterned field plate. By varying the lateral widths of the first field plate element 456, the second field plate element 496, and the intermediate field plate element 476, and / or by a lateral offset between the lateral centers of the first field plate element 456, the second field plate element 496, and the intermediate field plate element 476, the longitudinal cross-section of the resulting longitudinally patterned field plate can be varied, so that the electric field distribution in the termination region 650 can be adjusted to achieve a desired trade-off between high voltage breakdown capability and area efficiency.

[0123] The thickness of the intermediate metal layer 470 and the thickness of the first metal layer 450 may be equal to the average value of the two or deviate from the average value of the two by at least 20% of the average value. The thickness of the intermediate metal layer 470 and the thickness of the uppermost metal layer 450 may be equal to the average value of the two or deviate from the average value of the two by at least 20% of the average value.

[0124] Figure 3 and Figure 4The thickness of the uppermost metal layer 490 is shown to exceed the thickness of the first metal layer 450 by at least 2 times.

[0125] Figure 3 The top metal layer 490 and the second interlayer dielectric 460 or Figure 4 The middle interlayer dielectric 480 may be thick enough to serve as a wire bonding base. For example, the uppermost metal layer 490 may be formed of an alloy containing at least aluminum Al and copper Cu, and Figure 3 The second interlayer dielectric 460 or Figure 4 The thickness of the intermediate interlayer dielectric 480 is in the range of 500 nm to 2 μm.

[0126] The second field plate element 496 may be formed in the same patterning process as the wire bond pads 491 in the first device region 610 and the wire bond pads 499 in the second device region 690. The wire bond pads 491, 499 and the second field plate element 496 are formed from different portions of one deposited metal layer or metal layer stack and may be defined in the same photolithographic mask.

[0127] exist Figure 4 In the semiconductor device 100 shown, an intermediate metal layer 470 and an intermediate interlayer dielectric 480 are formed between the first metal layer 450 and the topmost metal layer 490. Other embodiments may provide two or more intermediate metal layers 470 and intermediate interlayer dielectrics 480, wherein each pair of two longitudinally adjacent intermediate metal layers 470 is separated by one of the additional intermediate interlayer dielectrics 480.

[0128] Figure 5 A semiconductor device 100 is shown having a doping shielding structure 415, which includes four doping shielding regions 416 forming a laterally spaced frame around a first device region 610. The doping shielding regions 416 have the same width or approximately the same width. The distance between adjacent doping shielding regions 416 decreases as the distance to the first device region 610 increases.

[0129] The doping shielding structure 415 forms a closed multi-part frame around the first device region 610. In the illustrated embodiment, the size and / or dopant concentration of the doping shielding region 416 is constant along the perimeter of the frame. According to other embodiments, the size and / or dopant concentration of the doping shielding region 416 may vary along the perimeter of the frame.

[0130] The illustration of the doped regions in the first device region and the second device region is simplified. Each of the first device region and the second device region may include one or more p-doped regions.

[0131] Figure 6 A semiconductor device 100 is shown having a second field plate structure 495 including four second field plate elements 496 forming a laterally spaced apart frame around a first device region 610. The width of the second field plate elements 496 can decrease with increasing distance from the first device region 610. The distances between adjacent second field plate elements 496 can be equal. The second field plate structure 495 forms a closed multi-part frame around the first device region 610. Figure 6 The second field plate structure 495 can be connected with Figure 5 The doping shielding structure 415 is combined, wherein Figure 6 Each of the second field plate elements 496 of the Figure 5 One of the doped shielding regions 416 laterally overlaps.

[0132] exist Figure 7 , each of the first field plate elements 456 of the semiconductor device 100 is formed directly above a single doping shielding region 416 in the doping shielding region 416. The lateral center lines of the first field plate elements 456 and the associated doping shielding region 416 are longitudinally aligned with each other. Each second field plate element 496 is formed directly above a single first field plate element 456 in the first field plate elements 456. All second field plate elements 496 are wider than the corresponding first field plate elements 456 in their longitudinal projections, and are wider than the corresponding doping shielding region 416 in their longitudinal projections. The lateral center lines of the second field plate elements 496 and the associated doping shielding region 416 are longitudinally aligned with each other. The distance between two adjacent second field plate elements 496 is less than the distance between two associated first field plate elements 456 and between two associated doping shielding regions 416.

[0133] The semiconductor layer 430 of the semiconductor device 100 includes a transition device portion 435 extending from within the first device region 610 on a first side of the second field plate element 496 to within the second device region 690 on a second side of the second field plate element 496. In other words, the transition device portion 435 extends from a first side of the second field plate structure 495 including the second field plate element 496 to a second side of the second field plate structure 495.

[0134] In addition, the semiconductor layer 430 includes one or more laterally spaced first device portions 431 in the first device region 610 and one or more laterally spaced second device portions 432 in the second device region 690. The first device portion 431 is formed entirely on a first side of the first field plate structure 455. The second device portion 432 is formed entirely on a second side of the first field plate structure 455.

[0135] Active element 700 formed in transition device portion 435 includes a first portion formed in first device region 610, a second portion formed in second device region 690, and a third portion formed in termination region 650. In the illustrated embodiment, active element 700 is a level shift transistor 851.

[0136] The level shift transistor 851 is an n-channel field effect transistor, including a heavily n+ doped source region 710 formed at the end of the transition device portion 435 toward the first device region 610 and a heavily n+ doped drain region 790 formed at the end of the transition device portion 435 toward the second device region 690. The source region 710 and the p-doped body region 720 form a longitudinal pn junction. The drift structure 750 connects the body region 720 and the drain region 790. The drift structure 750 can be weakly and uniformly n-doped. Alternatively, the drift structure 750 can include a superjunction structure. The superjunction structure includes a regular pattern of p-doped strips and n-doped strips alternating along a direction orthogonal to the cross-sectional plane. The p-doped strips and the body region 720 form a longitudinal unipolar junction. The n-doped strips and the body region 720 form a longitudinal pn junction. The p-doped strips and the drain region 790 can be separated by n-doped regions. The n-doped strip and the drain region 790 form a vertical unipolar junction. A gate electrode 445 is formed in a portion of the first interlayer dielectric 440 over the body region 720. A gate dielectric 446 separates the gate electrode 445 and the transition device region 435.

[0137] exist Figure 7 In the embodiment, the drift structure 750 is formed in the termination region 650 , the source region 710 is formed in the first device region 610 , and the drain region 790 is formed in the second device region 690 .

[0138] FIG. 8A to FIG. 8C A semiconductor device 100 is shown that includes doping shielding regions 416 forming a laterally spaced frame around a first device region 610. The width in a portion of each doping shielding region 416 depends on whether an active component is formed in a longitudinal projection of the associated portion of the doping shielding region 416, and if so, what type of active component is formed in the longitudinal projection of the associated portion of the doping shielding region 416. Each doping shielding region 416 forms a closed loop of different width and / or different dopant distribution.

[0139] exist Fig. 8A , each doping shielding region 416 includes two modified portions 417. The modified portions 417 are formed in a straight portion of the doping shielding region 416. Each modified portion 417 faces a transition device portion (not shown). The modified portion 417 may differ from an unmodified portion in width and / or dopant dosage.

[0140] The modified portion 417 may be formed by implanting dopants through a mask having parallel mask grooves.

[0141] Fig. 8A Also shown are two active elements 700 having different functions formed in the transition device region in a portion of the termination region 650 including the modified portion 417 .

[0142] The modified portion 417 laterally overlaps the two active elements 700 without further changing the lateral size, doping and spacing between the modified portions 417. Therefore, the first field plate element 456, the second field plate element 496 and all the intermediate field plate elements 476 can laterally overlap the two active elements 700 without changing the lateral size and lateral spacing between the modified portions 417, so that the resulting longitudinal patterned field plate has the same effect in the two active elements 700 and provides the same lateral field distribution along the radial direction for the two active elements 700.

[0143] This may apply to more than two active components, for example to all active components formed in the HV termination.

[0144] Figure 8B A top view of a portion of a substrate 410 after implanting dopants for forming doped shielding regions 416 is shown. For each doped shielding region 416, the implantation mask includes a frame-shaped mask opening. The frame-shaped mask opening has one strip-shaped mask opening for each unmodified portion. To form modified portions 417, the frame-shaped mask opening is fanned out into a plurality of parallel strip-shaped mask openings (mask slots) separated by mask fins.

[0145] Thus, the implantation process forms a precursor doping screening region including a plurality of parallel implant stripes 418 in which modified portions 417 are to be formed. The thermal treatment diffuses the dopants contained in the implant stripes 418 to form laterally continuous modified portions 417 having a greater width than unmodified portions.

[0146] The total width of the fan-shaped mask openings in the modified portion 417 and the width of the mask openings in the unmodified portion can be the same, so that the modified portion 417 and the unmodified portion of the doping shielding region 416 have the same dopant dose per unit length along the circumferential direction and differ only in the lateral distribution of the dopant dose across the circumferential direction.

[0147] Figure 8C A modified portion 417 is shown having a smaller width across the circumferential direction than the unmodified portion of the doped shielding region 416 .

[0148] Fig. 9A block diagram of a gate driver circuit 800 is shown as an example of a semiconductor device having active elements integrated in a high voltage termination between a high voltage domain and a low voltage domain.

[0149] The CMOS portion 810 of the gate driver circuit 800 forms a signal interface to a standard CMOS device. The CMOS portion 810 particularly includes a low-side (LS) control logic 811, which passes the active gate input signal to the first level-shift transistor 851 as long as the error condition is not met. The first level-shift transistor 851 is an n-channel field effect transistor. The CMOS portion 810 also includes an error output logic 812 for outputting an error signal received from a second level-shift transistor 852. The second level-shift transistor 852 is a p-channel field effect transistor. The CMOS portion 810 represents a low voltage domain where the signal voltage level is less than 5V.

[0150] The HV portion 890 of the gate driver circuit 800 forms a signal interface to the power semiconductor switch. The HV portion 890 may include, among other things, a high-side driver logic 891 for controlling an active gate input signal received from the first level-shift transistor 851. The HV portion 890 may also include an error detection logic 892 for outputting an error signal to the second level-shift transistor 852 when a fault condition is detected. The HV portion 890 represents a high voltage domain with signal voltage levels above 15V.

[0151] The bootstrap diode 855 periodically charges a capacitor connected to the VB terminal of the gate driving circuit 800 to obtain a power supply voltage for the HV part 890 .

[0152] The first level-shift transistor 851 and the second level-shift transistor 852 are part of a signal path that exchanges an electrical signal between the HV portion 890 and the CMOS portion 810 .

[0153] The first level-shift transistor 851 , the second level-shift transistor 852 , and the bootstrap diode 855 may be active elements formed in any of the aforementioned transition device portions 435 .

[0154] The transition device portion 435 is primarily formed in the termination region 650 between the first device region 610 and the second device region 690, as described with reference to any of the previous figures. In the illustrated gate driver circuit 800, the CMOS portion 810 is formed in the first device region 610 and the HV portion 890 is formed in the second device region 690. According to an embodiment not shown, the HV portion 890 is formed in the first device region 610 and the CMOS portion 810 is formed in the second device region 690.

[0155] Fig.10 and Fig.11 The arrangement of various active elements integrated in the termination region 650 between the first device region 610 and the second device region 690 of the gate driver circuit 800 is shown. The termination region 650 includes four straight segments and four quarter-circle segments, wherein each quarter-circle segment connects two adjacent straight segments.

[0156] exist Fig.10 , the termination region 650 includes two long straight segments and two short straight segments. In each of the four straight segments, a portion of a bootstrap diode 855 is formed. In one of the long straight segments, a first level shift transistor 851 and a second level shift transistor 852 are formed side by side.

[0157] exist Fig.11 , the termination region 650 includes four straight segments of equal length. In each of three of the four straight segments, a portion of a bootstrap diode 855 is formed. In the fourth straight segment, a first level-shift transistor 851 and a second level-shift transistor 852 are formed, wherein two equal-sized portions of the second level-shift transistor 852 are formed on opposite sides of the first level-shift transistor 851.

[0158] Fig.12 , Fig.13 and Fig.14 Active elements 700 are shown with compensation structures 755. Each active element 700 is formed in a transition device portion 435 of the semiconductor layer, wherein each transition device portion 435 is primarily formed in a termination region between the first device region 610 and the second device region 690. Arrows indicate current flow direction 759 when the active element 700 is in an on state or forward conduction state.

[0159] Each compensation structure 755 includes a p-doped region 751 and an n-doped region 752 arranged alternately along a horizontal direction orthogonal to a current direction 759 in the active element 700. The compensation structure 755 has a superjunction structure in which the dopant heights in the p-doped region 751 and the n-doped region 752 compensate each other. The widths and dopant distributions of the p-doped region 751 and the n-doped region 752 are selected to meet the tradeoff between the HV breakdown voltage and the drive current capability and / or can be used to fine-tune the static voltage blocking capability of the termination region 650 and the dynamic blocking stability during switching of a unipolar device such as a level-shift transistor. The p-doped region 751 and the n-doped region 752 can be formed by low-dose implantation, otherwise available in a baseline process. For example, the formation of the p-doped region 751 can be combined with the body implantation of the logic MOSFET in the first device portion 610 and the second device portion 690.

[0160] exist Fig.12 and Fig.13 , the active element 700 is a HV diode 854, for example, a bootstrap diode comprising a heavily p+ doped anode region 730 at the end of the transition device region 435 towards the first device region 610 and a heavily n+ doped cathode region 740 at the end of the transition device region 435 towards the second device region 690. The p-doped region 751 and the n-doped region 752 are strip-shaped, with their longitudinal axes parallel to the current direction 759.

[0161] exist Fig.12 In FIG. 7 , the p-doped region 751 has a uniform lateral width along the entire length, and the n-doped region 752 has a uniform lateral width along the entire length.

[0162] exist Fig.13 , the width of the p-doped region 751 varies between a first width and a second width along the current direction 759. The width of a portion of the p-doped region 751 depends on whether the doping shielding region 416 is formed in the longitudinal projection of the portion. For example, the portion of the p-doped region 751 in the longitudinal projection of the doping shielding region 416 has a first width, and the portion of the p-doped region 751 outside the longitudinal projection of the doping shielding region 416 has a second width. The first width can be narrower or wider than the second width.

[0163] exist Fig.14 In the example, the active element 700 is a p-channel field effect transistor, such as Fig. 9 4. A second level-shift transistor 852 is provided in the embodiment of the present invention. The second level-shift transistor 852 includes a heavily p+ doped source region 710 at an end of the transition device region 435 toward the first device region 610 and a heavily p+ doped drain region 790 at an end of the transition device region 435 toward the second device region 690. The source region 710 and the n-doped body region 720 form a pn junction. The drift structure between the body region 720 and the drain region 790 includes a compensation structure 755 having a superjunction structure including a regular pattern of strip-shaped p-doped regions 751 and strip-shaped n-doped regions 752. The n-doped region 752 and the body region 720 form a longitudinal unipolar junction. The p-doped region 751 and the body region 720 form a pn junction. The n-doped region 752 and the drain region 790 may be separated by a p-doped region. The p-doped region 751 and the drain region 790 form a longitudinal unipolar junction. The gate electrode 445 is formed in a portion of the first interlayer dielectric over the body region 720 .

[0164] Fig.15A and Fig. 15BThe semiconductor device 100 in the embodiment includes a level shift transistor formed in a transition device portion 435 of a semiconductor layer 430, which is separated from a substrate 410 by an insulator layer 420. In addition to a doping shielding structure 415 having a p-doped shielding region 416, an n-doped surface layer 412 is formed in the substrate 410 along a first substrate surface 411. Fig. 15B Shows Fig.15A A magnified excerpt of , labeled “CUT”.

[0165] The passivation layer 510 at least partially covering the uppermost metal layer 490 includes a first sublayer 511 formed at least on the exposed portion of the second interlayer dielectric 460 and a second sublayer 512 formed on the first sublayer 511 and, if applicable, on the uppermost metal layer 490. The second field plate element 496 toward the first device region 610 is electrically connected to the source region 710 of the level-shift transistor. The second field plate element 496 toward the second device region 690 is electrically connected to the drain region 790 of the level-shift transistor.

[0166] Fig.16A and Fig. 16B Shown with Fig.15A and Fig. 15B Similar devices. Fig. 16B Shows Fig.16A A magnified excerpt of the , marked as "CUT". The main difference is in the field plate design. Fig.15A and Fig. 15B In FIG. 4 , each first field plate element 456 overlaps only one second field plate element 496 .

[0167] exist Fig.16A and Fig. 16B In the embodiment, a lateral gap g is formed between adjacent ones of the second field plate elements 496 , wherein at least 50% of the lateral extension of the lateral gap g is laterally overlapped by one of the first field plate elements 456 . Fig. 16B In FIG. 4 , the overlap between the gap g and the first field plate element 456 is marked as OV. Fig.16A and Fig. 16B , about 100% of the gap g is laterally overlapped by the first field plate element 456, while the first field plate element 456 overlaps only one of the adjacent second field plate elements 496. Therefore, the first field plate element 456 overlaps one of the adjacent second field plate elements 496, and the sides of the first field plate element 456 and the other adjacent second field plate element 496 are laterally aligned. In addition, one of the first field plate elements 456 also laterally overlaps one of the two adjacent second field plate elements of the second field plate elements 496 by at least 20% or at least 50%.

[0168] Similarly, another first lateral gap (not shown) is formed between adjacent ones of the first field plate elements 456, and at least 50% or at least 80% of the lateral extension of the first lateral gap is laterally overlapped by one of the second field plate elements 496. Again, in this embodiment, the overlap is approximately 100%. One of the second field plate elements 496 also laterally overlaps one of two adjacent ones of the first field plate elements 456 by at least 20% or at least 50%.

Claims

1. A high voltage semiconductor device, comprising: A substrate (410) having a background doping of a first conductivity type and comprising a doped shielding region (416) of a complementary second conductivity type formed along a first substrate surface (411); an insulator layer (420), the insulator layer (420) being formed on the first substrate surface (411); a semiconductor layer (430), the semiconductor layer (430) being formed on the insulator layer (420) opposite to the substrate (410); A first interlayer dielectric (440), the first interlayer dielectric (440) being formed on the semiconductor layer (430); a first metal layer (450) including laterally spaced first field plate elements (456) formed on a first portion of the first interlayer dielectric (440) in a termination region (650); as well as A second interlayer dielectric (460) is formed on the first metal layer (450) and on a second portion of the first interlayer dielectric (440) between the first field plate elements (456).

2. The high voltage semiconductor device according to claim 1, in, The first field plate element (456) laterally surrounds a first device region (610).

3. A high voltage semiconductor device according to any one of the preceding claims, in, A top surface (461) of the second interlayer dielectric (460) opposite to the first metal layer (450) is flat, and wherein the second interlayer dielectric (460) includes an opening extending from the top surface (461).

4. The high voltage semiconductor device according to any one of the preceding claims, further comprising: An uppermost metal layer (490), the uppermost metal layer (490) is formed on the second interlayer dielectric (460).

5. The high voltage semiconductor device according to claim 4, wherein: The uppermost metal layer (490) includes a laterally spaced second field plate element (496), and wherein the second interlayer dielectric (460) vertically spaces the second field plate element (496) from the first field plate element (456).

6. The high voltage semiconductor device according to claim 5, wherein: A first lateral gap is formed between adjacent ones of the first field plate elements (456), wherein at least 50% or at least 80% of a lateral extension of the first lateral gap is laterally overlapped by one of the second field plate elements (496).

7. The high voltage semiconductor device according to claim 5 or 6, wherein: A second lateral gap is formed between adjacent ones of the second field plate elements (496), wherein at least 50% of a lateral extension of the second lateral gap is laterally overlapped by one of the first field plate elements (456).

8. The high voltage semiconductor device according to any one of claims 5 to 7, wherein: One of the first field plate elements (456) laterally overlaps at least a portion of each of two adjacent second field plate elements (496) of the second field plate elements (496).

9. The high voltage semiconductor device according to claim 6 or 7, wherein: One of the first field plate elements (456) also laterally overlaps one of two adjacent second field plate elements (496) of the second field plate elements (496) by at least 20% or at least 50%.

10. The high voltage semiconductor device according to any one of claims 5 to 9, further comprising: A field plate contact (469) extends from the second field plate element (496) through an opening in the second interlayer dielectric (460) to the first field plate element (456).

11. The high voltage semiconductor device according to any one of claims 4 to 10, in, The uppermost metal layer (490) is formed directly on the second interlayer dielectric (460).

12. The high voltage semiconductor device according to any one of claims 4 to 10, further comprising: At least one intermediate metal layer (470) is formed between the first metal layer (450) and the uppermost metal layer (490).

13. The high voltage semiconductor device according to claim 12, in, Each intermediate metal layer (470) of the at least one intermediate metal layer (470) comprises an intermediate field plate element (476), and wherein each intermediate field plate element (476) is electrically connected to one of the first field plate elements (456).

14. The high voltage semiconductor device according to any one of claims 4 to 13, in, The thickness of the uppermost metal layer (490) is at least 1.2 times the thickness of the first metal layer (450).

15. A high voltage semiconductor device according to any one of the preceding claims, in, The doping shielding region (416) forms a laterally spaced frame around the first device region (610).

16. The high voltage semiconductor device according to any one of the preceding claims, further comprising: An active element (700) is formed in a transition device portion (435) of the semiconductor layer (430), wherein the transition device portion (435) extends from a first device region (610) on a first side of the first field plate element (456) to a second device region (690) on a second side of the first field plate element (456).

17. The high voltage semiconductor device according to claim 16, in, The doping shielding region (416) forms a laterally spaced frame around the first device region (610), and wherein a modified portion (417) of the doping shielding region (416) facing the transition device portion (435) differs in width and / or dopant concentration from an unmodified portion of the doping shielding region (416).

18. The high voltage semiconductor device according to claim 17, in, The modified portion (417) of at least one of the doping shielding regions (416) is produced by implanting dopants through a mask having parallel mask grooves.

19. The high voltage semiconductor device according to any one of claims 16 to 18, in, The active element (700) is a bootstrap diode (855).

20. The high voltage semiconductor device according to any one of claims 16 to 18, in, The active element (700) is a level shift transistor (851, 852).

21. The high voltage semiconductor device according to any one of claims 16 to 20, further comprising: Another active element (700) having a different function from the active element (700), wherein the first field plate element (456) laterally overlaps both the active element (700) and the other active element (700) in respective overlapping regions, and the first field plate elements (456) have the same spacing between each other in the respective overlapping regions.

22. The high voltage semiconductor device according to any one of claims 16 to 21, in, The active element (700) comprises a compensation structure (755), wherein the compensation structure (755) comprises p-doped regions (751) and n-doped regions (752) arranged alternately along a horizontal direction orthogonal to a current direction (759) in the active element (700).

23. A high voltage semiconductor device according to any one of the preceding claims, in, The thickness of the insulator layer (420) is in the range of 40 nm to 1000 nm.

24. A high voltage semiconductor device comprising: A substrate (410) having a background doping of a first conductivity type and comprising a doped shielding region (416) of a complementary second conductivity type formed along a first substrate surface (411); an insulator layer (420), the insulator layer (420) being formed on the first substrate surface (411); a semiconductor layer (430), the semiconductor layer (430) being formed on the insulator layer (420) opposite to the substrate (410); A first interlayer dielectric (440), the first interlayer dielectric (440) being formed on the semiconductor layer (430); a first metal layer (450) including laterally spaced first field plate elements (456) formed on a first portion of the first interlayer dielectric (440) in a termination region (650); as well as a second interlayer dielectric (460) formed on the first metal layer (450) and on a second portion of the first interlayer dielectric (440) between the first field plate elements (456); an uppermost metal layer (490), the uppermost metal layer (490) being formed on the second interlayer dielectric (460); wherein, The uppermost metal layer (490) includes laterally spaced second field plate elements (496), and wherein the second interlayer dielectric (460) vertically spaces the second field plate elements (496) from the first field plate elements (456); and wherein, A lateral gap is formed between adjacent ones of the second field plate elements (496), wherein at least 50% of a lateral extension of the lateral gap is laterally overlapped by one of the first field plate elements (456).

Images