TOPCon solar cell and preparation method thereof

Abstract

The invention relates to the field of TOPCon cells, in particular to a TOPCon solar cell and a preparation method thereof. The preparation method of the TOPCon solar cell comprises the following steps: S1, cleaning and texturing a silicon substrate of a substrate; s2, front boron diffusion and rear boron diffusion are carried out on the silicon wafer; s3, the front BSG layer and the back BSG layer are removed, and wet chemical alkali polishing is carried out; s4, depositing a tunneling oxide layer and a Poly layer; s5, carrying out primary phosphorus diffusion and depositing a SiOx layer; s6, locally slotting the back SE; s7, secondary phosphorus diffusion; s8, PSG and RCA are removed for cleaning; s9, depositing a passivation film and an antireflection film; s10, metallizing the front and back surfaces; s11, laser-assisted sintering is carried out; in the step S5, a PSG layer is formed through primary phosphorus diffusion, and the thickness of the PSG layer is 150-300 nm. According to the preparation method of the TOPCon cell, the back SE technology and the laser-assisted sintering technology are combined, so that the process is relatively simple, the cost increase is less, the control difficulty is low, the window is large, the Uoc and FF can be further improved, and the cell conversion efficiency is effectively improved.

Description

Technical Field

[0001] The invention relates to the field of TOPCon cells, and in particular to a TOPCon solar cell and a preparation method thereof. Background Art

[0002] The pursuit of high-efficiency cells is a development trend in the photovoltaic industry, which takes both cost and process into consideration. The current mainstream product is still the PERC (passivated emitter rear surface fully diffused) cell, but its efficiency has become a bottleneck, and a new cell structure has been introduced, the tunneling oxide passivated contact cell. This structure provides good surface passivation for the back of the silicon substrate. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking minority hole recombination, and then the electrons are transported laterally in the polysilicon layer and collected by the metal, thereby greatly reducing the metal contact recombination current and improving the open circuit voltage and short circuit current of the cell.

[0003] The conventional process preparation route of TOPCon cells is: texturing - front boron diffusion - front SE (laser diffusion technology) - rear boron diffusion - back and edge BSG removal - alkali polishing + front BSG removal - back LPCVD amorphous silicon plating - P diffusion - front and edge PSG removal - RCA edge and front Poly removal - front aluminum oxide deposition + silicon nitride anti-reflection film deposition - back silicon nitride deposition - back aluminum paste + silver paste printing - front silver paste printing - sintering - light injection - testing, sorting. The existing TOPCon preparation process route has the following shortcomings:

[0004] ① The process window of one-time P expansion + front SE diffusion is narrow and difficult to control. The amorphous silicon layer is thin and easy to be damaged, which leads to the problem of slurry burning through and destroying the tunneling structure.

[0005] ② The existing SE technology is mainly used on the front side, and there are very few research examples of back-side application, which makes the technology difficult. At present, the main manufacturing technologies of back-side laser SE include direct laser diffusion and laser grooving superimposed with secondary poly deposition and secondary P expansion. The direct laser diffusion manufacturing technology is to use laser energy to directly push the diffusion source in the PSG after P expansion after P diffusion in the amorphous silicon layer. The subsequent processes proceed normally and the process steps are simple. However, since the thickness of the amorphous silicon layer is only 50-200nm and the surface PSG flatness is difficult to control, direct laser diffusion requires a narrow laser power control window and high energy stability requirements, which can easily damage the amorphous silicon layer of the silicon wafer, further increasing the risk of the slurry burning through the amorphous silicon layer and destroying the tunneling structure. In the laser grooving superimposed secondary poly deposition and secondary P expansion production technology, the back amorphous silicon is thinned during production, and then a low-concentration P diffusion is performed. Subsequently, a second thicker layer of amorphous silicon is deposited and a higher-concentration P diffusion is performed at the same time. After completion, laser grooving is performed to remove the second layer of amorphous silicon layer that is not in contact with the slurry, and the remaining area is the SE selective emitter. This process has a cumbersome production process, complex steps, and increased costs. It also has higher requirements for the matching of the front and rear processes and is more difficult to control, which is not conducive to mass production. Summary of the invention

[0006] The present invention aims at the above-mentioned problems, makes up for the deficiencies of the prior art, and provides a method for preparing a TOPCon solar cell to solve the problems arising from the above-mentioned background technology.

[0007] A first aspect of the present invention provides a method for preparing a TOPCon solar cell, comprising the following steps:

[0008] S1 cleans and texturizes the silicon substrate;

[0009] S2 performs front boron diffusion and back boron diffusion on the silicon wafer;

[0010] S3 removes the front BSG layer, the back BSG layer and wet chemical alkali polishing;

[0011] S4 deposits a tunnel oxide layer and a Poly layer;

[0012] S5 one-step phosphorus diffusion and deposition of SiO x layer;

[0013] The S6 has a partial slot on the back SE;

[0014] S7 secondary phosphorus diffusion;

[0015] S8 removes PSG and RCA wash;

[0016] S9 deposits passivation film and anti-reflection film;

[0017] S10 is metallized on the front and back;

[0018] S11 laser assisted sintering;

[0019] In the step S5, a PSG layer is formed by phosphorus diffusion once, and the thickness of the PSG layer is 150-300 nm. Specifically, the thickness of the PSG layer is 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm; more preferably, the thickness of the PSG layer is 200-300 nm.

[0020] Preferably, the substrate silicon base in S1 is N-type, and the cleaning uses acid-base chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer; the texturing uses an alkaline solution with a mass fraction of 0.5-2wt% for etching and texturing, and the etching time is 400s-600s.

[0021] Preferably, the temperature of the front boron diffusion and the back boron diffusion in S2 is 800-1000°C, the diffusion time is 5min-60min; the surface concentration of the front boron diffusion is 5.2E+19cm -3 -5.5E+19cm -3 , node depth 0.2-0.28um, square resistance 155-175Ω / sqr; surface concentration of post-boron diffusion 4.8E+18cm -3 -5.1E+19cm -3 , node depth 0.62-0.67um, square resistance 280-340Ω / sqr.

[0022] Preferably, in S3, the silicon wafer is pickled in hydrofluoric acid with a concentration of 0.5%-50% for a pickling time of 10s-1200s to remove the BSG layer on the back and front sides and to perform etching and polishing on the surface of the single crystal silicon wafer.

[0023] Preferably, in the S4, in the LPCVD furnace tube, O2 is used as the oxidant, the oxidation temperature is 550-650°C, the time is 2-4min, and a tunneling oxide layer is deposited with a thickness of 1-2nm; then SiH4 is used as the reaction gas, N2 is used as the dilution gas, the deposition temperature is 550-650°C, the time is 30-70min, and a Poly layer is deposited with a thickness of 120-180nm.

[0024] Preferably, the phosphorus diffusion in S5 is a light surface diffusion, the ECV surface concentration is 0.3-1*E20, the square resistance is 20-50Ω / sqr, the junction depth is 0.1-0.2μm, and the S5 uses thermal oxidation technology to deposit a layer of SiO x layer with a thickness of 1-3nm.

[0025] Preferably, the SE on the back side of S6 is partially grooved, and the PSG is grooved according to the screen printing pattern using a laser, and the P atoms of the PSG layer are pushed to the amorphous silicon layer to form a back side SE area. The laser setting parameters are: wavelength 200nm-1064nm, power ≥1W, scanning speed 5-50mm / s, and frequency 200-2000kHz.

[0026] Preferably, the S7 secondary P diffusion is local heavy diffusion, the ECV surface concentration of the back non-SE area is 0.5-1.5*E20, the square resistance is 30-70Ω / sqr, and the junction depth is 0.15-0.3μm. The back SE area is a heavy diffusion N++ area, with an ECV surface concentration of 0.8-2.0*E20, a square resistance of 20-60Ω / sqr, and a junction depth of 0.2-0.38μm.

[0027] Preferably, the diffusion temperature of the primary phosphorus diffusion in S5 and the secondary phosphorus diffusion in S7 is 800° C.-900° C., and the diffusion time is 5 min-60 min.

[0028] Preferably, in S8, the silicon wafer is pickled in hydrofluoric acid with a concentration of 0.5%-50% for a pickling time of 10s-1200s to remove the PSG layer; and then the silicon substrate is cleaned according to RCA standards to remove surface pollutants.

[0029] Preferably, the S9 adopts ALD atomic layer deposition method, uses TMA as a precursor, controls the reaction temperature at 200-350°C, and deposits a layer of AlOx film with a thickness of 6-10nm on the front surface of the silicon wafer; adopts tubular or plate PECVD to deposit an anti-reflection layer on the front and back of the silicon wafer, and the front anti-reflection layer is one or more combinations of SiNx, SiOxNy, SiOx, and its thickness is 70-150nm.

[0030] Preferably, the S10 sets metal electrodes on the front and back sides of the silicon substrate, and the metal electrodes are preferably silver metal electrodes.

[0031] Preferably, the S11 laser assisted sintering uses a laser to locally apply high-intensity laser pulses to the front side of the silicon wafer and maintain a constant reverse voltage. The parameters set by the laser are: bias voltage 20-50V, laser power 5-25%, temperature 700-1000°C, wavelength 400-600nm, frequency 100-500kHz, peak energy 4.5-11.0J / cm 2 , the scanning speed is 4-40m / s, the spot diameter is 10-35um, and the induced sintering time is 0.5-3s.

[0032] A second aspect of the present invention provides a TOPCon solar cell, which is prepared by the preparation method described in the first aspect.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention combines the back SE technology with the laser-assisted sintering technology, making the process relatively simple, with less cost increase, low control difficulty, and a large window, which can further improve the open circuit voltage, short circuit current, fill factor, and reduce resistance, thereby effectively improving the battery conversion efficiency: the present invention can realize the introduction of the back SE technology under the condition of effectively avoiding the damage of the laser energy to the amorphous silicon layer during laser grooving by appropriately increasing the thickness of the PSG after phosphorus expansion. Since the thickness of the PSG on the surface of the amorphous silicon is increased, the laser process window becomes larger, the selectivity of the laser equipment is greatly increased, and the procurement cost is reduced; at the same time, the secondary phosphorus expansion is superimposed at high temperature, and the phosphorus element in the grooving area is further diffused into the amorphous silicon layer to form a heavily diffused selective emitter N++ area. Through the local phosphorus element heavy diffusion on the back, the Al and silver paste series resistance is reduced and the FF is improved; in addition, the back phosphorus diffusion further absorbs impurities and improves the BSF effect, thereby improving the open circuit voltage of the battery. After the back SE technology is introduced, the LECO process is superimposed, and a high-intensity laser pulse is applied locally on the front of the silicon cell, and a constant reverse voltage is maintained, and the local current generated by the laser is used to significantly reduce the contact resistivity between the semiconductor and the metal electrode. The hot spots caused by laser heating will locally and precisely destroy the passivation layer on the silicon wafer, allowing the silver to form direct contact with the silicon wafer and establish an effective electron transmission path. At the same time, under the action of high temperature, silver-silicon alloy is locally formed to form a better ohmic contact, further improving Uoc and FF, while improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the TOPCon solar cell structure in Example 1, in which: 1-N-type silicon substrate, 2-P+Poly layer, 3-passivation layer, 4-front anti-reflection layer, 5-front metal electrode, 6-tunneling oxide layer, 7-N+Poly layer, 8-back anti-reflection layer, 9-N++ region, 10-back metal electrode;

[0036] Figure 2 This is a process flow chart for preparing TOPCon solar cells in Example 1. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0038] The TOPCon solar cell and the preparation method thereof of the present invention are further described below through specific examples and comparative examples.

[0039] Example 1

[0040] like Figure 1 As shown, an N-type TOPCon cell comprises an N-type silicon substrate 1, wherein the front side of the N-type silicon substrate 1 is provided with a P+Poly layer 2, a passivation layer 3, a front anti-reflection layer 4, and a front metal electrode 5 in sequence from the inside to the outside, and the back side of the N-type silicon substrate 4 is provided with a tunneling oxide layer 6, an N+Poly layer 7, a back anti-reflection layer 8, an N++ region 9, and a back metal electrode 10 in sequence from the inside to the outside;

[0041] In the step S5, a PSG layer is formed by one-time phosphorus diffusion, and the thickness of the PSG layer is 220 nm.

[0042] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0043] S1 selects a P-diffused N-type silicon substrate with a resistivity of 1.5Ωcm and a thickness of 130μm; uses a 1.3wt% NaOH solution to eliminate organic contamination and metal impurities on the surface of the silicon substrate, and uses a 1.3wt% NaOH solution by mass fraction to etch and texturize, and the etching time is 500s.

[0044] S2 puts the silicon substrate into the boron diffusion tube for back-to-back front boron diffusion. The diffusion temperature is 900℃, the diffusion time is 30min, the boron diffusion source is BBr3, and the surface concentration of the front boron diffusion is 5.3E+19cm -3 , node depth 0.24um, square resistance 160Ω / sqr; then the post-boron diffusion is carried out on the silicon substrate, the diffusion temperature is 900℃, the diffusion time is 30min, the boron diffusion source is BBr3, and the surface concentration of the post-boron diffusion is 7.0E+18cm -3 , node depth 0.65um, square resistance 310Ω / sqr.

[0045] S3: The silicon wafer is pickled in 25% hydrofluoric acid for 600 seconds to remove the BSG layer on the back and front sides, and the surface of the single crystal silicon wafer is corroded and polished.

[0046] S4 puts the silicon wafer into the LPCVD furnace tube, uses O2 as the oxidant, the oxidation temperature is 600℃, the time is 3min, and a tunneling oxide layer with a thickness of 1.5nm is deposited on the back of the silicon wafer; then SiH4 is used as the reaction gas, N2 is used as the dilution gas, the deposition temperature is 600℃, the time is 50min, and a Poly layer with a thickness of 150nm is deposited on the tunneling oxide layer.

[0047] S5 puts the silicon wafer into a phosphorus diffusion tube for phosphorus diffusion. The diffusion temperature is 850℃, the diffusion time is 30min, the diffusion source is POCl3, the first phosphorus diffusion is a light surface diffusion, the ECV surface concentration is 0.6*E20, the square resistance is 35Ω / sqr, the junction depth is 0.15μm, and the PSG thickness is 220nm; a layer of SiO2 is deposited using thermal oxidation technology with a thickness of 2nm.

[0048] S6 locally grooves the SE on the back side of the silicon wafer, uses laser to groove the PSG according to the screen-printed pattern, and pushes the P atoms of the PSG layer to the amorphous silicon layer to form the SE area on the back side. The laser setting parameters are: wavelength 600nm, power ≥1W, scanning speed 25mm / s, and frequency 1200kHz.

[0049] S7 puts the silicon wafer into the phosphorus expansion tube for secondary phosphorus expansion. There is a thick PSG barrier in the non-SE area on the back, and the P atoms are doped slowly to form an N+Poly layer. The ECV surface concentration is 1.0*E20, the square resistance is 50Ω / sqr, and the junction depth is 0.2μm; the P atoms in the SE area on the back are quickly deposited and diffused into the amorphous silicon to form the N++ area on the back. The ECV surface concentration is 1.5*E20, the square resistance is 40Ω / sqr, and the junction depth is 0.3μm; after the deposition, the surface is post-oxygen treated, and a SiO2 layer with a thickness of 80nm is grown on the surface of the N++ area.

[0050] S8: The silicon wafer is placed in a 25% hydrofluoric acid solution for pickling for 600 seconds to remove the PSG layer; the silicon substrate is then cleaned according to the RCA standard to remove surface contaminants.

[0051] S9 adopts ALD atomic layer deposition method, with TMA as precursor and reaction temperature controlled at 280℃, to deposit a layer of Al2O3 film with thickness of 8nm on the surface of diffusion inner expansion layer on the front side of silicon wafer; and adopts tubular or plate PECVD to deposit anti-reflection layer on the front and back side of silicon wafer. The front anti-reflection layer is SiNx with thickness of 110nm.

[0052] S10 prints Ag paste on the front and back sides of the silicon substrate, and after drying and sintering, obtains the front and back metal electrodes.

[0053] S11 uses a laser to apply high-intensity laser pulses locally on the front side of the silicon wafer and maintain a constant reverse voltage. The laser setting parameters are: bias voltage 25V, laser power 15%, temperature 850℃, wavelength 500nm, frequency 300kHz, peak energy 8J / cm 2 , the scanning speed is 20m / s, the spot diameter is 25um, and the induced sintering time is 2s.

[0054] Example 2

[0055] like Figure 1 As shown, an N-type TOPCon cell comprises an N-type silicon substrate 1, wherein the front side of the N-type silicon substrate 1 is provided with a P+Poly layer 2, a passivation layer 3, a front anti-reflection layer 4, and a front metal electrode 5 in sequence from the inside to the outside, and the back side of the N-type silicon substrate 4 is provided with a tunneling oxide layer 6, an N+Poly layer 7, a back anti-reflection layer 8, an N++ region 9, and a back metal electrode 10 in sequence from the inside to the outside;

[0056] In the step S5, a PSG layer is formed by one-time phosphorus diffusion, and the thickness of the PSG layer is 150 nm.

[0057] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0058] S1 selects a P-diffused N-type silicon substrate with a resistivity of 1.5Ωcm and a thickness of 130μm; uses a 1.3wt% NaOH solution to eliminate organic contamination and metal impurities on the surface of the silicon substrate, and uses a 0.5wt% NaOH solution to etch and texture the substrate, and the etching time is 600s.

[0059] S2 puts the silicon substrate into the boron diffusion tube for back-to-back front boron diffusion. The diffusion temperature is 800℃, the diffusion time is 60min, the boron diffusion source is BBr3, and the surface concentration of the front boron diffusion is 5.2E+19cm -3 , node depth 0.2um, square resistance 155Ω / sqr; then the post-boron diffusion is carried out on the silicon substrate, the diffusion temperature is 800℃, the diffusion time is 60min, the boron diffusion source is BBr3, and the surface concentration of the post-boron diffusion is 4.8E+18cm -3 , node depth 0.62um, square resistance 280Ω / sqr.

[0060] S3: The silicon wafer is pickled in 0.5% hydrofluoric acid for 1200 seconds to remove the BSG layer on the back and front sides, and the surface of the single crystal silicon wafer is corroded and polished.

[0061] S4 puts the silicon wafer into the LPCVD furnace tube, uses O2 as the oxidant, the oxidation temperature is 550℃, the time is 4min, and a tunneling oxide layer with a thickness of 1nm is deposited on the back of the silicon wafer; then SiH4 is used as the reaction gas, N2 is used as the dilution gas, the deposition temperature is 550℃, the time is 70min, and a Poly layer with a thickness of 120nm is deposited on the tunneling oxide layer.

[0062] S5 puts the silicon wafer into a phosphorus diffusion tube for phosphorus diffusion. The diffusion temperature is 800℃, the diffusion time is 60min, the diffusion source is POCl3, the first phosphorus diffusion is a light surface diffusion, the ECV surface concentration is 0.3*E20, the square resistance is 20Ω / sqr, the junction depth is 0.1μm, and the PSG thickness is 150nm; a SiO2 layer is deposited using thermal oxidation technology with a thickness of 1nm.

[0063] S6 locally grooves the SE on the back side of the silicon wafer, uses laser to groove the PSG according to the screen-printed pattern, and pushes the P atoms of the PSG layer to the amorphous silicon layer to form the SE area on the back side. The laser setting parameters are: wavelength 200nm, power ≥1W, scanning speed 5mm / s, and frequency 200kHz.

[0064] S7 puts the silicon wafer into a phosphorus expansion tube for secondary phosphorus expansion. There is a thicker PSG barrier in the non-SE area on the back, and the P atoms are slowly doped to form an N+Poly layer. The ECV surface concentration is 0.5*E20, the square resistance is 30Ω / sqr, and the junction depth is 0.15μm; the P atoms in the SE area on the back are quickly deposited and diffused into the amorphous silicon to form the N++ area on the back. The ECV surface concentration is 0.8*E20, the square resistance is 20Ω / sqr, and the junction depth is 0.2μm; after the deposition is completed, the surface is post-oxygen treated, and a SiO2 layer with a thickness of 30nm is grown on the surface of the N++ area.

[0065] S8: The silicon wafer is placed in 0.5% hydrofluoric acid for pickling for 1200 seconds to remove the PSG layer; the silicon substrate is then cleaned according to the RCA standard to remove surface contaminants.

[0066] S9 adopts ALD atomic layer deposition method, with TMA as precursor and reaction temperature controlled at 200℃, to deposit a layer of Al2O3 film with thickness of 6nm on the surface of diffusion inner expansion layer on the front side of silicon wafer; and adopts tubular or plate PECVD to deposit anti-reflection layer on the front and back side of silicon wafer, and the front anti-reflection layer is SiNx with thickness of 70nm.

[0067] S10 prints Ag paste on the front and back sides of the silicon substrate, and after drying and sintering, obtains the front and back metal electrodes.

[0068] S11 uses a laser to apply high-intensity laser pulses locally on the front side of the silicon wafer and maintain a constant reverse voltage. The laser setting parameters are: bias voltage 20V, laser power 5%, temperature 700℃, wavelength 400nm, frequency 100kHz, peak energy 4.5J / cm 2 , the scanning speed is 4m / s, the spot diameter is 10um, and the induced sintering time is 3s.

[0069] Example 3

[0070] like Figure 1 As shown, an N-type TOPCon cell comprises an N-type silicon substrate 1, wherein the front side of the N-type silicon substrate 1 is provided with a P+Poly layer 2, a passivation layer 3, a front anti-reflection layer 4, and a front metal electrode 5 in sequence from the inside to the outside, and the back side of the N-type silicon substrate 4 is provided with a tunneling oxide layer 6, an N+Poly layer 7, a back anti-reflection layer 8, an N++ region 9, and a back metal electrode 10 in sequence from the inside to the outside;

[0071] In the step S5, a PSG layer is formed by one-time phosphorus diffusion, and the thickness of the PSG layer is 300 nm.

[0072] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0073] S1 selects a P-diffused N-type silicon substrate with a resistivity of 1.5Ωcm and a thickness of 130μm; uses a 1.3wt% NaOH solution to eliminate organic contamination and metal impurities on the surface of the silicon substrate, and uses a 2.0wt% NaOH solution to etch and texture the substrate, and the etching time is 400s.

[0074] S2 puts the silicon substrate into the boron diffusion tube for back-to-back front boron diffusion. The diffusion temperature is 1000℃, the diffusion time is 5min, the boron diffusion source is BBr3, and the surface concentration of the front boron diffusion is 5.5E+19cm -3 , node depth 0.28um, square resistance 175Ω / sqr; then the post-boron diffusion is carried out on the silicon substrate, the diffusion temperature is 900℃, the diffusion time is 30min, the boron diffusion source is BBr3, and the surface concentration of the post-boron diffusion is 5.1E+19cm -3 , node depth 0.67um, square resistance 340Ω / sqr.

[0075] S3: The silicon wafer is placed in a 50% hydrofluoric acid solution for pickling for 10 seconds to remove the BSG layer on the back and front sides, and the surface of the single crystal silicon wafer is corroded and polished.

[0076] S4 puts the silicon wafer into the LPCVD furnace tube, uses O2 as the oxidant, the oxidation temperature is 650℃, the time is 2min, and a tunneling oxide layer with a thickness of 2nm is deposited on the back of the silicon wafer; then SiH4 is used as the reaction gas, N2 is used as the dilution gas, the deposition temperature is 650℃, the time is 30min, and a Poly layer with a thickness of 180nm is deposited on the tunneling oxide layer.

[0077] S5 puts the silicon wafer into a phosphorus diffusion tube for phosphorus diffusion. The diffusion temperature is 900℃, the diffusion time is 5min, the diffusion source is POCl3, the first phosphorus diffusion is a light surface diffusion, the ECV surface concentration is 1*E20, the square resistance is 50Ω / sqr, the junction depth is 0.2μm, and the PSG thickness is 300nm; a SiO2 layer is deposited using thermal oxidation technology with a thickness of 3nm.

[0078] S6 locally grooves the SE on the back side of the silicon wafer, uses laser to groove the PSG according to the screen-printed pattern, and pushes the P atoms of the PSG layer to the amorphous silicon layer to form the SE area on the back side. The laser setting parameters are: wavelength 1064nm, power ≥1W, scanning speed 50mm / s, and frequency 2000kHz.

[0079] S7 puts the silicon wafer into the phosphorus expansion tube for secondary phosphorus expansion. There is a thick PSG barrier in the non-SE area on the back, and the P atoms are doped slowly to form an N+Poly layer. The ECV surface concentration is 1.5*E20, the square resistance is 70Ω / sqr, and the junction depth is 0.3μm; the P atoms in the SE area on the back are quickly deposited and diffused into the amorphous silicon to form the N++ area on the back. The ECV surface concentration is 2.0*E20, the square resistance is 60Ω / sqr, and the junction depth is 0.38μm; after the deposition, the surface is post-oxygen treated, and a SiO2 layer with a thickness of 150nm is grown on the surface of the N++ area.

[0080] S8: The silicon wafer is placed in a 50% hydrofluoric acid solution for pickling for 10 seconds to remove the PSG layer; the silicon substrate is then cleaned according to the RCA standard to remove surface contaminants.

[0081] S9 adopts ALD atomic layer deposition method, with TMA as precursor and reaction temperature controlled at 350℃, to deposit a layer of Al2O3 film with thickness of 10nm on the surface of diffusion inner expansion layer on the front side of silicon wafer; and adopts tubular or plate PECVD to deposit anti-reflection layer on the front and back side of silicon wafer, and the front anti-reflection layer is SiNx with thickness of 150nm.

[0082] S10 prints Ag paste on the front and back sides of the silicon substrate, and after drying and sintering, obtains the front and back metal electrodes.

[0083] S11 uses a laser to apply high-intensity laser pulses locally on the front side of the silicon wafer and maintain a constant reverse voltage. The laser setting parameters are: bias voltage 50V, laser power 25%, temperature 1000℃, wavelength 600nm, frequency 500kHz, peak energy 11J / cm 2 , the scanning speed is 40m / s, the spot diameter is 35um, and the induced sintering time is 0.5s.

[0084] Example 4

[0085] like Figure 1 As shown, an N-type TOPCon cell comprises an N-type silicon substrate 1, wherein the front side of the N-type silicon substrate 1 is provided with a P+Poly layer 2, a passivation layer 3, a front anti-reflection layer 4, and a front metal electrode 5 in sequence from the inside to the outside, and the back side of the N-type silicon substrate 4 is provided with a tunneling oxide layer 6, an N+Poly layer 7, a back anti-reflection layer 8, an N++ region 9, and a back metal electrode 10 in sequence from the inside to the outside;

[0086] In the step S5, a PSG layer is formed by one-time phosphorus diffusion, and the thickness of the PSG layer is 140 nm.

[0087] The preparation method of this embodiment is different from that of embodiment 2 in that:

[0088] The thickness of PSG formed in S5 is 140 nm; the rest are the same.

[0089] Example 5

[0090] like Figure 1 As shown, an N-type TOPCon cell comprises an N-type silicon substrate 1, wherein the front side of the N-type silicon substrate 1 is provided with a P+Poly layer 2, a passivation layer 3, a front anti-reflection layer 4, and a front metal electrode 5 in sequence from the inside to the outside, and the back side of the N-type silicon substrate 4 is provided with a tunneling oxide layer 6, an N+Poly layer 7, a back anti-reflection layer 8, an N++ region 9, and a back metal electrode 10 in sequence from the inside to the outside;

[0091] In the step S5, a PSG layer is formed by one-time phosphorus diffusion, and the thickness of the PSG layer is 310 nm.

[0092] The preparation method of this embodiment is different from that of embodiment 3 in that:

[0093] The thickness of PSG formed in S5 is 310 nm; the rest are the same.

[0094] Comparative Example 1

[0095] The preparation method of this comparative example is compared with that of Example 1, except that step 11 is missing, and the rest are the same.

[0096] Comparative Example 2

[0097] The preparation method of this comparative example is compared with that of Example 1, except that step 6 and step 7 are missing, and the rest are the same.

[0098] Comparative Example 3

[0099] The preparation method of this comparative example is different from that of Example 1 in that step S6 and step S7 occur on the front side, specifically:

[0100] S6 locally grooves the SE on the front side of the silicon wafer, uses laser to groove the BSG according to the screen-printed pattern, and pushes the P atoms of the BSG layer to the amorphous silicon layer to form the SE area on the front side. The laser setting parameters are: wavelength 600nm, power ≥1W, scanning speed 25mm / s, and frequency 1200kHz.

[0101] S7 puts the silicon wafer into a phosphorus expansion tube for secondary phosphorus expansion. There is a thick BSG barrier in the non-SE area on the front side, and the P atoms are doped slowly to form a P+Poly layer with an ECV surface concentration of 1.0*E20, a square resistance of 50Ω / sqr, and a junction depth of 0.2μm. The P atoms in the SE area on the back side are rapidly deposited and diffused into the amorphous silicon to form a P++ area on the back side with an ECV surface concentration of 1.5*E20, a square resistance of 40Ω / sqr, and a junction depth of 0.3μm. After the deposition, the surface is post-oxygenated and a SiO2 layer with a thickness of 80nm is grown on the surface of the P++ area.

[0102] The rest are the same.

[0103] The batteries in Examples 1-5 and Comparative Examples 1-3 were tested under the same conditions. The test results are shown in Table 1.

[0104] Table 1 Test results of battery of embodiment and comparative example

[0105]

[0106] As can be seen from Table 1, from the comparison of the test data of Examples 1-5 and Comparative Example 1, it can be seen that when the front laser-assisted sintering of step 11 is missing, the open circuit voltage, short circuit current, and fill factor of the battery are all reduced, and the series resistance is increased, thereby reducing the conversion efficiency of the battery; from the test data of Examples 1-5 and Comparative Example 2, it can be seen that when the back SE technology of steps 6 and 7 is missing, the open circuit voltage, short circuit current, and fill factor of the battery are all reduced, and the series resistance is increased, thereby reducing the conversion efficiency of the battery; from the test data of Examples 1-5 and Comparative Example 3, it can be seen that when the SE technology of steps 6 and 7 occurs on the front, the open circuit voltage, short circuit current, and fill factor of the battery are all reduced, and the series resistance is increased, thereby reducing the conversion efficiency of the battery. From the test data of Examples 1-3 and Examples 4-5, it can be seen that when the thickness of the PSG layer is 150-300nm, the open circuit voltage, short circuit current, fill factor, resistance, and conversion efficiency of the battery are better.

[0107] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a TOPCon solar cell, characterized in that: The steps include: S1 cleans and texturizes the silicon substrate; S2 performs front boron diffusion and back boron diffusion on the silicon wafer; S3 removes the front BSG layer, the back BSG layer and wet chemical alkali polishing; S4 deposits a tunnel oxide layer and a Poly layer; S5 one-step phosphorus diffusion and deposition of SiO x layer; The S6 has a partial slot on the back SE; S7 secondary phosphorus diffusion; S8 removes PSG and RCA wash; S9 deposits passivation film and anti-reflection film; S10 is metallized on the front and back; S11 laser assisted sintering; In the step S5, a PSG layer is formed by one-time phosphorus diffusion, and the thickness of the PSG layer is 150-300 nm.

2. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The substrate silicon base in S1 is N-type.

3. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The temperatures of the front boron diffusion and the back boron diffusion in S2 are both 800-1000°C, and the diffusion time is 5-60min; the surface concentration of the front boron diffusion is 5.2E+19cm -3 -5.5E+19cm -3 , node depth 0.2-0.28um, square resistance 155-175Ω / sqr; surface concentration after boron diffusion 4.8E+18cm -3 -5.1E+19cm -3 , node depth 0.62-0.67um, square resistance 280-340Ω / sqr.

4. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The S4 deposits a tunnel oxide layer and an amorphous silicon layer at a deposition temperature of 550-650°C.

5. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The first phosphorus diffusion in S5 is a light surface diffusion, so that its ECV surface concentration is 0.3-1*E20, the square resistance is 20-50Ω / sqr, and the junction depth is 0.1-0.2μm.

6. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The S6 back side SE is partially grooved, and the PSG is grooved according to the screen printing pattern using a laser, and the P atoms of the PSG layer are pushed to the amorphous silicon layer to form a back side SE area.

7. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The S7 secondary P diffusion is a local heavy diffusion, so that the ECV surface concentration of the non-SE area on the back is 0.5-1.5*E20, the square resistance is 30-70Ω / sqr, and the junction depth is 0.15-0.3μm. The SE area on the back is a heavy diffusion N++ area, so that the ECV surface concentration is 0.8-2.0*E20, the square resistance is 20-60Ω / sqr, and the junction depth is 0.2-0.38μm.

8. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The diffusion temperature of the primary phosphorus diffusion in S5 and the secondary phosphorus diffusion in S7 is 800° C.-900° C., and the diffusion time is 5 min-60 min.

9. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The S11 laser-assisted sintering uses a laser to locally apply high-intensity laser pulses to the front side of the silicon wafer and maintain a constant reverse voltage. The parameters set by the laser are: bias voltage 20-50V, laser power 5-25%, temperature 700-1000°C, wavelength 400-600nm, frequency 100-500kHz, peak energy 4.5-11.0J / cm 2 , the scanning speed is 4-40m / s, the spot diameter is 10-35um, and the induced sintering time is 0.5-3s.

10. A TOPCon solar cell structure, characterized in that: The TOPCon solar cell structure is prepared according to the method according to any one of claims 1 to 9.

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