Pulse power amplifier detection control method and system

Abstract

The invention relates to a pulse power amplifier detection control method and system, and belongs to the technical field of pulse power amplifier detection control. The signal sampling and processing module samples and converts forward radio frequency signals to obtain forward pulse digital voltage signals, samples and converts reverse radio frequency signals to obtain reverse pulse protection signals, and the reverse pulse protection signals serve as input of the detection control module composed of the MCU and the FPGA. In the detection control module, the MCU calculates a period counting threshold value and a high level counting threshold value based on the set maximum pulse width and the set maximum duty ratio and sends the period counting threshold value and the high level counting threshold value to the FPGA, and the FPGA detects and counts an obtained high level counting value exceeding the high level counting threshold value by detecting an input forward pulse digital voltage signal in a single detection period. According to the invention, fault control is started and detection is stopped only when the reverse pulse protection signal is determined to be at a high level or the reverse pulse protection signal is determined to be at a high level, and continuous detection is carried out by counting a clock cycle and repeatedly and circularly detecting a cycle, so that the problems of low precision, poor real-time performance, easy interference and high resource occupation in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse power amplifier detection and control, and in particular to a pulse power amplifier detection and control method and system. Background Art

[0002] Over-pulse width and over-duty cycle protection are effective protection functions for overload of pulse power amplifier RF power tube and transmitter power supply. Over-pulse width usually means that the duration of "signal" of pulse signal exceeds the normal standard time length, and over-duty cycle means that within a certain period of time, the ratio of the time occupied by "signal" to the entire time exceeds the index requirements. Over-pulse width and over-duty cycle will cause the pulse power amplifier to exceed the use requirements of its RF power tube and the design requirements of the transmitter power supply, which may cause damage to the pulse power amplifier and power supply. Generally, it is necessary to sample and detect the maximum pulse width and maximum duty cycle of the pulse power amplifier RF signal to see if they exceed the set threshold. If over-pulse width and over-duty cycle faults are found, the protection control is activated.

[0003] Commonly used traditional over-pulse width and over-duty cycle protection methods include processor detection method and single-cycle CPLD detection method. Among them, the analog comparison circuit relies on the principle of capacitor charging and discharging, and obtains over-pulse width and over-duty cycle signals by comparing with the fixed voltage threshold. It has low accuracy and is easily affected by environmental factors. The processor detection method uses the processor circuit to detect the pulse edge signal, and uses interrupts, timers and other external designs to calculate the pulse width and duty cycle. It occupies a lot of CPU resources, has poor real-time performance, and has large errors in the case of short pulse widths. The CPLD-based detection method makes up for the shortcomings of analog circuits and processor circuits, but it needs to capture the edge of each pulse signal, sample the pulse width and period, and calculate and compare the duty cycle. It is easily interfered by burr signals and requires a separate CPLD detection, which is costly.

[0004] In summary, existing pulse power amplifier detection and control methods generally have the problems of low accuracy, poor real-time performance, susceptibility to interference, and high resource usage. Summary of the invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide a pulse power amplifier detection and control system to solve the problems of low pulse power amplifier detection accuracy, poor real-time performance, susceptibility to interference, and high resource occupation in the prior art.

[0006] On the one hand, an embodiment of the present invention provides a pulse power amplifier detection and control system, the system includes a signal sampling and processing module, a detection and control module, wherein:

[0007] The signal sampling and processing module is used to collect the power amplifier radio frequency signal and convert it into forward and reverse pulse protection signals, and output them to the detection control module;

[0008] The detection control module is used to read the maximum pulse width and the maximum duty cycle, and obtain a cycle counting threshold and a high level counting threshold based on the maximum pulse width and the maximum duty cycle, and count the high level of the forward pulse digital voltage signal to obtain a high level counting value in each detection cycle; the detection cycle includes multiple clock cycles; the clock cycles are counted to obtain a cycle counting value; and whether to perform fault control is determined based on the high level counting threshold, the high level counting value and the reverse pulse protection signal.

[0009] The beneficial effects of the above technical solution are as follows: In a pulse power amplifier detection and control system provided by this embodiment, the detection module calculates the cycle counting threshold and the high level counting threshold based on the read maximum pulse width and maximum duty cycle of the pulse power amplifier, and detects and records the number of high levels, the high level counting threshold, or whether the reverse pulse protection signal appears at a high level based on the forward pulse digital voltage signal output by the signal sampling and processing module in each detection cycle to determine whether to start fault control. Compared with the prior art, the detection and control of excessive pulse width and excessive duty cycle of the pulse power amplifier has higher accuracy and real-time performance, the algorithm is simple, and it occupies less system resources and has better effect.

[0010] Based on the further improvement of the above system, the determining whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal includes:

[0011] When any of the following conditions is met, fault control is started, and the conditions specifically include:

[0012] (1) The high level count value detected in a single detection cycle exceeds the high level threshold;

[0013] (2) The reverse pulse protection signal is detected to be at a high level.

[0014] The beneficial effects of the above further improved scheme are: the judgment algorithm for fault control is simple, and compared with the existing technology, the real-time performance and effect of pulse power amplifier detection and control are better.

[0015] Based on the further improvement of the above system, the detection control module further performs the following process, which specifically includes:

[0016] When it is determined to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal, the current detection cycle is terminated;

[0017] When the fault control is not performed, it is determined whether the cycle count value reaches the cycle count threshold value. If yes, the detection cycle is restarted and the cycle count value and the high level count value are recounted.

[0018] The beneficial effect of the above further improved solution is that accurate control of the detection cycle is achieved.

[0019] Based on the further improvement of the above system, the detection control module includes MCU and FPGA;

[0020] The MCU obtains a cycle count threshold and a high level count threshold based on the maximum pulse width and the maximum duty cycle, and sends them to the FPGA;

[0021] The FPGA starts a cycle counter and a high level counter, the high level counter counts the high level of the positive pulse digital voltage signal to obtain the high level count value; at the same time, the cycle counter counts the clock cycle to obtain the cycle count value.

[0022] The beneficial effect of the above further improvement scheme is: the MCU reads the maximum pulse width and maximum duty cycle of the pulse power amplifier and calculates the cycle counting threshold and the high-level counting threshold, and sends them to the FPGA. The FPGA starts the cycle counter and the high-level counter, and counts the high level of the positive pulse digital voltage signal. The clock cycle counting method avoids occupying MCU system resources, and the FPGA can achieve more accurate detection and control of excessive pulse width and excessive duty cycle of the pulse power amplifier through the cycle counter and the high-level counter, avoiding excessive consumption of FPGA resources.

[0023] Based on the further improvement of the above system, the cycle counting threshold is calculated by the following formula, which is specifically expressed as:

[0024] CT period =(T midth ×F clk ×100) / D max , where CT period is the cycle count threshold, T midth is the maximum pulse width, F clk is the FPGA clock frequency, D max is the maximum duty cycle.

[0025] The beneficial effect of the above further improved solution is that the cycle counting threshold can be calculated.

[0026] Based on the further improvement of the above system, the high level counting threshold is calculated by the following formula, which is specifically expressed as:

[0027] CT th =T midth ×F clk , where CT th is the high level count threshold.

[0028] The beneficial effect of the above further improved solution is that the high level counting threshold can be calculated.

[0029] Based on the further improvement of the above system, the signal sampling and processing module includes a forward signal sampling and processing circuit and a reverse signal sampling and processing circuit, wherein the forward signal sampling and processing circuit and the reverse signal sampling and processing circuit both include a signal detection circuit, a conditioning circuit, a high-speed comparison circuit, and a reference voltage circuit.

[0030] The reference voltage circuit is used to generate a reference voltage signal;

[0031] The detection circuit is used to collect the power amplifier radio frequency signal to obtain a sampled analog voltage signal;

[0032] The conditioning circuit conditions the sampled analog voltage signal;

[0033] The high-speed comparison circuit captures the pulse digital voltage signal based on the comparison result between the conditioned analog voltage signal and the reference voltage signal and outputs it to the detection control module.

[0034] The beneficial effect of the above further improved solution is that it is possible to obtain pulse power amplifier signal sampling to generate forward and reverse pulse protection signals.

[0035] On the other hand, an embodiment of the present invention provides a pulse power amplifier detection and control method, the method specifically comprising:

[0036] S1: based on the power amplifier RF sampling signal conversion and obtain the forward pulse digital voltage signal and reverse pulse protection signal;

[0037] S2: Setting a maximum pulse width and a maximum duty cycle, and obtaining a period count threshold and a high level count threshold based on the maximum pulse width and the maximum duty cycle;

[0038] S3: Detect whether there is a running fault control, and if so, stop the running fault control;

[0039] S4: Start fault detection. In each detection cycle, perform the following steps, which specifically include:

[0040] S41: Counting the high level of the positive pulse digital voltage signal to obtain a high level count value; the detection cycle includes a plurality of clock cycles; counting the clock cycles to obtain a cycle count value;

[0041] S42: determining whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal, and if so, terminating the current detection cycle,

[0042] Otherwise, it is determined whether the cycle count value reaches the cycle count threshold value. If yes, the current detection cycle is terminated, a new detection cycle is restarted, and the cycle count value and the high level count value are recounted.

[0043] The beneficial effects of the above technical solution are as follows: based on the read maximum pulse width and maximum duty cycle of the pulse power amplifier, the cycle counting threshold and the high level counting threshold are calculated, and based on the detection of the forward pulse digital voltage signal in each detection cycle and the recording of the number of high levels, the high level counting threshold, or whether the reverse pulse protection signal appears at a high level, it is determined whether to start fault control. Compared with the existing technology, the detection and control of excessive pulse width and excessive duty cycle in the pulse power amplifier has higher accuracy and real-time performance, the algorithm is simple, and it occupies less system resources and has better effect.

[0044] Based on a further improvement of the above method, the detection period is the product of the period counting threshold and the clock period.

[0045] The beneficial effect of adopting the above further improved solution is that the detection cycle length can be obtained.

[0046] Based on a further improvement of the above method, within a single detection cycle, when the high level count value reaches the high level threshold, or a high level of a reverse pulse protection signal is detected, fault control is started.

[0047] The beneficial effect of adopting the above further improved solution is that fault control can be started by processing the above further improved solution with a simpler algorithm than the prior art.

[0048] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0050] Figure 1 This is a schematic diagram of the structure of the pulse power amplifier detection control system of Example 1 of the present invention. DETAILED DESCRIPTION

[0051] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0052] Embodiment 1:

[0053] A specific embodiment of the present invention discloses a pulse power amplifier detection and control system, such as Figure 1 shown.

[0054] The system includes a signal sampling and processing module and a detection and control module, wherein:

[0055] The signal sampling and processing module is used to collect the power amplifier radio frequency signal and convert it into forward and reverse pulse protection signals, and output them to the detection control module;

[0056] The detection control module is used to read the maximum pulse width and the maximum duty cycle, and obtain a cycle counting threshold and a high level counting threshold based on the maximum pulse width and the maximum duty cycle, and count the high level of the forward pulse digital voltage signal to obtain a high level counting value in each detection cycle; the detection cycle includes multiple clock cycles; the clock cycles are counted to obtain a cycle counting value; and whether to perform fault control is determined based on the high level counting threshold, the high level counting value and the reverse pulse protection signal.

[0057] Generally, a pulse power amplifier outputs a forward RF signal and a reverse RF signal through a dual directional coupler. The forward RF signal and the reverse RF signal provide signal input sources for the pulse power amplifier, which are used to perform forward signal detection and reverse signal detection respectively to determine whether fault control needs to be performed. The forward signal is related to the output power of the pulse power amplifier, and the reverse signal is related to the reverse pulse generated after the pulse power amplifier outputs the power. Based on the working principle of the pulse power amplifier, the forward signal output exceeds the set maximum duty cycle, or the reverse pulse appears, which may cause damage to the pulse power amplifier and cause a fault. Therefore, it is necessary to detect these two abnormal conditions. When one of them is detected, the pulse power amplifier needs to be fault controlled immediately.

[0058] Specifically, the signal sampling and processing module includes a forward signal sampling and processing circuit and a reverse signal sampling and processing circuit, wherein the forward signal sampling and processing circuit and the reverse signal sampling and processing circuit both include a signal detection circuit, a conditioning circuit, a high-speed comparison circuit, and a reference voltage circuit.

[0059] The reference voltage circuit is used to generate a reference voltage signal;

[0060] The detection circuit is used to collect the power amplifier radio frequency signal to obtain a sampled analog voltage signal;

[0061] The conditioning circuit conditions the sampled analog voltage signal;

[0062] The high-speed comparison circuit captures the pulse digital voltage signal based on the comparison result between the conditioned analog voltage signal and the reference voltage signal and outputs it to the detection control module.

[0063] The function of the signal sampling and processing module is to sample the forward RF signal of the power amplifier through the forward signal sampling and processing circuit and generate a forward pulse digital voltage signal, and to sample the reverse RF signal of the power amplifier through the reverse signal sampling and processing circuit and generate a reverse pulse protection signal, which are output to the detection control module for detection. Since the forward signal sampling and processing circuit and the reverse signal sampling and processing circuit have the same structure and working process, the working process is introduced by taking the forward signal sampling and processing circuit as an example. Specifically, the detection circuit samples the power amplifier RF signal and converts it to obtain a sampled analog voltage signal, and outputs it to the conditioning circuit; the conditioning circuit specifically includes a high-speed operational amplifier, which is used to adjust the amplitude range and signal polarity of the input sampled analog voltage signal, and then output a conditioned voltage signal that meets the detection accuracy requirement to the high-speed comparison circuit; the high-speed comparison circuit specifically includes a high-speed comparator, and the high-speed comparator has two input ends, one for the conditioned voltage signal and the other for the reference voltage signal output by the reference voltage circuit, wherein the reference voltage signal is used to measure whether the conditioned voltage signal exceeds the amplitude limit, and the conditioned voltage signal and the reference voltage signal are input into the high-speed comparator. When the amplitude of the conditioned voltage signal is higher than the amplitude of the reference voltage signal, the high-speed comparator outputs a positive high-level pulse digital voltage signal to the detection control module, otherwise, it outputs a low-level positive pulse digital voltage signal to the detection control module.

[0064] The detection control module includes MCU and FPGA;

[0065] The MCU obtains a cycle count threshold and a high level count threshold based on the maximum pulse width and the maximum duty cycle, and sends them to the FPGA;

[0066] The FPGA starts a cycle counter and a high level counter, the high level counter counts the high level of the positive pulse digital voltage signal to obtain the high level count value; at the same time, the cycle counter counts the clock cycle to obtain the cycle count value.

[0067] In this embodiment, the function of the MCU is mainly parameter setting, storage and sending, wherein the maximum pulse width and the maximum duty cycle are set in the MCU. The MCU calculates the cycle count threshold and the high level count threshold based on the maximum pulse width and the maximum duty cycle, and sends them to the FPGA to complete the parameter setting and sending. At the same time, the MCU saves the read maximum pulse width, the maximum duty cycle, and the calculated cycle count threshold and the high level count threshold. Therefore, the MCU occupies very little resources.

[0068] Furthermore, the cycle count threshold is calculated by the following formula, which is specifically expressed as:

[0069] CT period =(T midth ×F clk ×100) / D max , where CT period is the cycle count threshold, T midth is the maximum pulse width, F clk is the FPGA clock frequency, D max is the maximum duty cycle;

[0070] The high level counting threshold is calculated by the following formula, which is specifically expressed as:

[0071] CT th =T midth ×F clk , where CT th is the high level count threshold.

[0072] The function of the FPGA is to determine whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal. Specifically, the FPGA starts a cycle counter and a high level counter, detects the input positive pulse digital voltage signal and counts the detected high level in each detection cycle, and detects whether the reverse pulse protection signal has a high level, and determines whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal, including:

[0073] When any of the following conditions is met, fault control is started, and the conditions specifically include:

[0074] (1) The high level count value detected in a single detection cycle exceeds the high level threshold;

[0075] (2) The reverse pulse protection signal is detected to be at a high level.

[0076] Wherein, if the high level count value detected in the single detection cycle exceeds the high level threshold, it means that the pulse power amplifier output exceeds the set maximum duty cycle; if the reverse pulse protection signal is detected to be high level in the single detection cycle, it means that the reverse signal of the pulse power amplifier has a reverse pulse. When either of the two is detected, fault control must be started immediately.

[0077] When the fault control is performed, the FPGA immediately terminates the current detection cycle;

[0078] When the fault control is not performed, the FPGA determines whether the cycle count value reaches the cycle count threshold value. If yes, the detection cycle is restarted and the cycle count value and the high level count value are recounted.

[0079] Compared with the prior art, the pulse power amplifier detection and control system provided in the present embodiment integrates a detection circuit in the signal sampling and processing module, realizes sampling of the radio frequency signal and converts it into an analog voltage signal, and then adjusts the analog voltage signal output by the detection circuit through a conditioning circuit and outputs a conditioned voltage signal that meets the detection accuracy requirement, and then inputs the reference voltage signal output by the reference voltage circuit and the conditioned voltage signal into the high-speed comparison circuit to output a pulse digital voltage signal as the input of the detection control module, thereby improving the sampling and processing accuracy of the radio frequency signal, and helping to improve the detection reliability and processing efficiency; in the detection control module, the MCU reads the maximum pulse width and the maximum duty cycle of the pulse power amplifier and calculates the cycle counting threshold and the high level counting threshold and sends them to the FPGA, which greatly reduces the resource consumption of the MCU; the FPGA starts fault control and stops detection only when the high level count value obtained by detecting and counting the input forward pulse digital voltage signal exceeds the high level counting threshold or the reverse pulse protection signal appears high level in a single detection cycle, and through a simple processing method of continuously detecting the clock cycle counting and repeating the detection cycle, real-time, fast and accurate fault detection and control of the pulse power amplifier are realized without occupying a large amount of FPGA resources.

[0080] Embodiment 2:

[0081] Another specific embodiment of the present invention discloses a pulse power amplifier detection and control method. This embodiment includes all the technical features of embodiment 1.

[0082] The method specifically comprises:

[0083] S1: based on the power amplifier RF sampling signal conversion and obtain the forward pulse digital voltage signal and reverse pulse protection signal;

[0084] S2: Setting a maximum pulse width and a maximum duty cycle, and obtaining a period count threshold and a high level count threshold based on the maximum pulse width and the maximum duty cycle;

[0085] S3: Detect whether there is a running fault control, and if so, stop the running fault control;

[0086] S4: Start fault detection. In each detection cycle, perform the following steps, which specifically include:

[0087] S41: Counting the high level of the positive pulse digital voltage signal to obtain a high level count value; the detection cycle includes a plurality of clock cycles; counting the clock cycles to obtain a cycle count value;

[0088] S42: determining whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal, and if so, terminating the detection cycle,

[0089] Otherwise, it is determined whether the cycle count value reaches the cycle count threshold value. If yes, the current detection cycle is terminated, a new detection cycle is restarted, and the cycle count value and the high level count value are recounted.

[0090] In combination with Example 1, it can be known that the function of step S1 is to convert the power amplifier RF sampling signal to obtain the forward pulse digital voltage signal and the reverse pulse protection signal, which are the voltage signals obtained after the power amplifier RF sampling signal is converted into an analog voltage signal and then conditioned, and the high-level or low-level forward pulse digital voltage signal and the reverse pulse protection signal are obtained by comparing with the reference voltage. The purpose is to realize accurate sampling and conversion processing of the pulse power amplifier RF signal, so as to facilitate the implementation of subsequent detection and control processes.

[0091] The function of step S2 is to obtain the maximum pulse width and maximum duty cycle of the pulse power amplifier, and calculate the cycle counting threshold and the high level counting threshold, in order to obtain the two thresholds required for detection and control, so as to facilitate the implementation of the subsequent detection and control process.

[0092] The function of step S3 is to shut down the fault control in operation so that the forward and reverse pulse protection signals obtained in step S1 and the cycle counting threshold and high level counting threshold obtained in step S2 can start the fault detection and control process corresponding to the maximum pulse width and maximum duty cycle of the pulse power amplifier read in step S2.

[0093] Step S4 is a fault detection and control process initiated based on steps S1-S3. In each detection cycle, cycle counting and high-level counting are performed, wherein the detection cycle is the product of the cycle counting threshold and the clock cycle; the clock cycle is counted to obtain a cycle counting value, and when the cycle counting value reaches the cycle counting threshold, a detection cycle is ended.

[0094] In a single detection cycle, when the high-level count value reaches the high-level threshold, or the reverse pulse protection signal is detected to be at a high level, fault control is started. If neither of the two situations occurs, when the cycle count value reaches the cycle count threshold, that is, a single detection cycle ends, a new round of detection cycle is started, and the cycle count and high-level count are performed again.

[0095] Compared with the prior art, this embodiment has a simpler process for sampling, fault detection and control of the pulse power amplifier, and the algorithm is concise and efficient. Without consuming a lot of resources, it can achieve rapid, real-time and accurate detection and control of pulse power amplifier over-pulse width and over-duty cycle faults.

[0096] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0097] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A pulse power amplifier detection and control system, characterized in that: The system includes a signal sampling and processing module and a detection and control module, wherein: The signal sampling and processing module is used to collect the power amplifier radio frequency signal and convert it into a forward pulse digital voltage signal and a reverse pulse protection signal, and output them to the detection control module; The detection control module is used to read the maximum pulse width and the maximum duty cycle, and obtain a cycle counting threshold and a high level counting threshold based on the maximum pulse width and the maximum duty cycle, and count the high level of the forward pulse digital voltage signal to obtain a high level counting value in each detection cycle; the detection cycle includes multiple clock cycles; the clock cycles are counted to obtain a cycle counting value; and whether to perform fault control is determined based on the high level counting threshold, the high level counting value and the reverse pulse protection signal.

2. A pulse power amplifier detection and control system according to claim 1, characterized in that: The determining whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal comprises: When any of the following conditions is met, fault control is started, and the conditions specifically include: (1) The high level count value detected in a single detection cycle exceeds the high level threshold; (2) The reverse pulse protection signal is detected to be at a high level.

3. A pulse power amplifier detection and control system according to claim 1, characterized in that: The detection control module also performs the following process, which specifically includes: When it is determined to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal, the current detection cycle is terminated; When the fault control is not performed, it is determined whether the cycle count value reaches the cycle count threshold value. If yes, the detection cycle is restarted and the cycle count value and the high level count value are recounted.

4. A pulse power amplifier detection and control system according to claim 2, characterized in that: The detection control module includes MCU and FPGA; The MCU obtains a cycle count threshold and a high level count threshold based on the maximum pulse width and the maximum duty cycle, and sends them to the FPGA; The FPGA starts a cycle counter and a high level counter, the high level counter counts the high level of the positive pulse digital voltage signal to obtain the high level count value; at the same time, the cycle counter counts the clock cycle to obtain the cycle count value.

5. A pulse power amplifier detection and control system according to claim 1, characterized in that: The cycle count threshold is calculated by the following formula, which is specifically expressed as: CT period =(T midth ×F clk ×100) / D max , where CT period is the cycle count threshold, T midth is the maximum pulse width, F clk is the FPGA clock frequency, D max is the maximum duty cycle.

6. A pulse power amplifier detection and control system according to claim 4, characterized in that: The high level counting threshold is calculated by the following formula, which is specifically expressed as: CT th =T midth ×F clk , where CT th is the high level count threshold.

7. A pulse power amplifier detection and control system according to claim 1, characterized in that: The signal sampling and processing module includes a forward signal sampling and processing circuit and a reverse signal sampling and processing circuit, wherein the forward signal sampling and processing circuit and the reverse signal sampling and processing circuit both include a signal detection circuit, a conditioning circuit, a high-speed comparison circuit, and a reference voltage circuit. The reference voltage circuit is used to generate a reference voltage signal; The detection circuit is used to collect the power amplifier radio frequency signal to obtain a sampled analog voltage signal; The conditioning circuit conditions the sampled analog voltage signal; The high-speed comparison circuit captures the pulse digital voltage signal based on the comparison result between the conditioned analog voltage signal and the reference voltage signal and outputs it to the detection control module.

8. A pulse power amplifier detection and control method, characterized in that: The method specifically comprises: S1: based on the power amplifier RF sampling signal conversion and obtain the forward pulse digital voltage signal and reverse pulse protection signal; S2: Setting a maximum pulse width and a maximum duty cycle, and obtaining a period count threshold and a high level count threshold based on the maximum pulse width and the maximum duty cycle; S3: Detect whether there is a running fault control, and if so, stop the running fault control; S4: Start fault detection. In each detection cycle, perform the following steps, which specifically include: S41: Counting the high level of the positive pulse digital voltage signal to obtain a high level count value; the detection cycle includes a plurality of clock cycles; counting the clock cycles to obtain a cycle count value; S42: determining whether to perform fault control based on the high level count threshold, the high level count value and the reverse pulse protection signal, and if so, terminating the current detection cycle, Otherwise, it is determined whether the cycle count value reaches the cycle count threshold value. If yes, the current detection cycle is terminated, a new detection cycle is restarted, and the cycle count value and the high level count value are recounted.

9. A pulse power amplifier detection and control method according to claim 8, characterized in that: The detection period is the product of the period counting threshold and the clock period.

10. A pulse power amplifier detection and control method according to claim 8, characterized in that: In a single detection cycle, when the high level count value reaches the high level threshold, or a high level is detected in the reverse pulse protection signal, the fault control is started.

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