A message transmission method and apparatus

Abstract

This application provides a message transmission method and apparatus. The method includes: for a data writing process, sequentially traversing each first serial port, reading M first data blocks from an external storage medium, where M is the number of time slots occupied by the first serial port; for each first data block, selecting a basic storage unit from an internal storage medium, storing the first data block through the basic storage unit, and recording the offset position of the basic storage unit in the internal storage medium in a mapping table; for a data sending process, sequentially traversing each second serial port, for each second data block of the second serial port, obtaining the offset position of the basic storage unit where the second data block is located from the mapping table, reading the second data block from the basic storage unit of the internal storage medium based on the offset position; and sending each second data block of the second serial port during the time slots occupied by the second serial port. This solution enables a larger number of serial ports and improves the utilization rate of the internal storage medium.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a message transmission method and apparatus. Background Technology

[0002] In communication fields such as voice calls, the CPOS (Channelized Packet over SONET) interface is widely used for aggregation and forwarding of E1 and T1 interfaces.

[0003] The CPOS interface allows multiple independent logical channels, called serial ports, to be partitioned from a single physical POS interface. For example, a 155.520 Mbps CPOS interface can be divided into 63 E1 interfaces, each of which can be divided into 32 time slots, with each time slot transmitting one byte of data. Based on this, the E1 interfaces can be further configured as channels, dividing them into multiple serial ports (e.g., 1-31 serial ports). Thus, the 63 E1 interfaces of the CPOS interface can be partitioned into a maximum of 1953 serial ports.

[0004] When dividing the CPOS interface into multiple serial ports, there is still no effective way to efficiently transmit data across these ports, resulting in poor data transmission efficiency. Furthermore, although the CPOS interface can be divided into up to 1953 serial ports, the number of usable ports is limited by the limited buffer space. Summary of the Invention

[0005] This application provides a message transmission method applied to a processing device, wherein the target interface corresponding to the processing device is divided into multiple wide area network (WAN) interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot. The method includes:

[0006] For the data writing process, each first serial port is traversed sequentially, and M first data blocks of the first serial port are read from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port.

[0007] For each first data block, a basic storage unit for the first data block is selected from the internal storage medium of the processing device, the first data block is stored through the basic storage unit, and the offset position of the basic storage unit in the internal storage medium is recorded in the mapping table.

[0008] For the data transmission process, each second serial port is traversed sequentially. For each second data block of the second serial port, the offset position of the basic storage unit where the second data block is located is obtained from the mapping table. Based on the offset position, the second data block is read from the basic storage unit of the internal storage medium.

[0009] Each second data block of the second serial port is transmitted in the time slot occupied by the second serial port.

[0010] This application provides a message transmission device applied to a processing device. The target interface corresponding to the processing device is divided into multiple wide area network (WAN) interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot. The device includes:

[0011] The message buffer module is used to sequentially traverse each first serial port and read M first data blocks from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port.

[0012] For each first data block, a basic storage unit for the first data block is selected from the internal storage medium of the processing device, the first data block is stored through the basic storage unit, and the offset position of the basic storage unit in the internal storage medium is recorded in the mapping table.

[0013] The framing module is used to sequentially traverse each second serial port, and for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position;

[0014] An interface sending module is used to send each second data block of the second serial port in the time slot occupied by the second serial port after the framing module reads the second data block.

[0015] As can be seen from the above technical solutions, in this embodiment, by utilizing the mutual exclusion feature of serial port binding time slots under the same WAN interface of the CPOS interface, the polling performance of multiple serial port transmit buffers under the CPOS interface can be optimized. Under similar logical cache resource conditions, a larger number of serial ports can be reliably implemented, solving the problem of limited total number of serial ports, and more fully releasing the performance of the CPOS interface to meet user needs. The total cache size of the internal storage medium is determined by the number of time slots, and the linked list technology is used to realize the dynamic allocation and polling scheduling of multiple serial ports, thereby dynamically allocating the cache resources of the internal storage medium and dynamically adjusting the number of packet bytes read out by each serial port in polling, improving the utilization rate and scheduling efficiency of the internal storage medium, and saving storage resources. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the uplink forwarding process of the CPOS interface in one embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the downlink forwarding process of the CPOS interface in one embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the downlink forwarding process of the CPOS interface in one embodiment of this application;

[0019] Figure 4 This is a schematic diagram showing the correspondence between the E1 interface and the serial port in one embodiment of this application;

[0020] Figure 5 This is a schematic diagram illustrating the correspondence between local cache RAM and serial port in one embodiment of this application;

[0021] Figure 6 This is a schematic diagram of the dynamic management of the BM linked list RAM of the serial port in one embodiment of this application;

[0022] Figure 7 This is a schematic diagram of the address queue and BM linked list RAM in one embodiment of this application;

[0023] Figure 8 This is a flowchart illustrating a message transmission method in one embodiment of this application;

[0024] Figure 9 This is a scheduling diagram of a serial port polling FIFO in one embodiment of this application;

[0025] Figure 10 This is a schematic diagram of the address linked list update process in one embodiment of this application;

[0026] Figure 11 This is a flowchart illustrating a message transmission method in one embodiment of this application;

[0027] Figure 12 This is a schematic diagram of the structure of a message transmission device according to one embodiment of this application. Detailed Implementation

[0028] In communication fields such as voice calls, CPOS interfaces are widely used for aggregation and forwarding of E1 and T1 interfaces. A CPOS interface is a channelized interface for transmitting data packets using SONET (Synchronous Fiber Network), or a channelized interface for transmitting data packets using SDH (Synchronous Digital Hierarchy). The E1 interface is a digital communication interface widely used in digital communication systems for transmitting voice and data. The E1 interface has a transmission rate of 2.048 Mbps and can be divided into 32 time slots (one time slot for frame synchronization, and the others for transmitting voice or data information). The T1 interface is a digital transmission standard interface used for transmitting data and audio signals in telephone networks. It has a transmission rate of 1.544 Mbps and can be divided into 24 time slots (one time slot for frame synchronization, and the others for transmitting voice or data information). For ease of description, the E1 interface will be used as an example in the following explanation.

[0029] The CPOS interface allows for the division of a single physical POS interface into multiple independent logical channels, called serial ports (a type of interface used for data communication between a computer and external devices). For example, a CPOS interface with a speed of 155.520 Mbps can be divided into 63 E1 interfaces (or 84 T1 interfaces). Each E1 interface can be divided into 32 time slots, with each time slot transmitting one byte of data. Based on this, the E1 interface can be further configured with channelization, dividing it into multiple serial ports (e.g., 1-31 serial ports, meaning a minimum of one serial port bound to 31 time slots, and a maximum of 31 serial ports, each bound to one time slot; obviously, a serial port must be bound to at least one time slot, while time slot 0 is used to transmit the E1 frame header and cannot be bound). Taking an example of each E1 interface being divided into 31 serial ports, the 63 E1 interfaces of the CPOS interface can be divided into a maximum of 1953 serial ports.

[0030] See Figure 1 The diagram illustrates the uplink forwarding process (message reception direction) of the CPOS interface of a network device (such as a router or switch). Network packets are sent to the interface processing module via the CPOS interface. The interface processing module performs CPOS frame parsing, E1 frame parsing, HDLC (High-level Data Link Control Protocol) frame parsing, and packet buffering on the network packets. Finally, the serial port packets are sent to the protocol controller (such as the CPU) for further processing.

[0031] See Figure 2The diagram illustrates the downlink forwarding process (packet transmission direction) of the CPOS interface on a network device. After receiving a network packet for the CPOS interface, the protocol controller (such as the CPU) sends the serial packet to the interface processing module. The interface processing module performs various processing on the serial packet, including packet buffering, HDLC protocol framing (for adding HDLC header information), E1 protocol framing (for adding E1 header information), and CPOS protocol framing (for adding CPOS header information), before sending the packet through the CPOS interface.

[0032] In the message sending direction, since the protocol controller sends network messages to the interface processing module in the form of "packets," a single communication packet can be any number of bytes from 4 to 9600. However, the CPOS interface is characterized by a large number of serial ports and low communication bandwidth (e.g., the downlink bandwidth of each serial port on the E1 interface is between 64Kbps and 2.048Mbps). This means that the ingress message traffic is characterized by high bursts, while the egress bandwidth is low. Therefore, the interface processing module needs to buffer messages in whole packets, but the egress is sent byte by byte. Consequently, the interface processing module typically needs to buffer a large number of messages, and these messages need to be buffered separately according to serial port number, resulting in high requirements for buffer space.

[0033] The interface processing module can be implemented using processing devices, which may include, but are not limited to, processing protocol chips or programmable logic devices (such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits)). Because the number of serial ports split from the CPOS interface is relatively large (e.g., 128-2000), and each serial port needs to store multiple messages, the processing device typically lacks sufficient buffer space for message storage. Therefore, it typically uses external DDR (Double Data Rate) memory to store the messages.

[0034] See Figure 3 The diagram illustrates the downlink forwarding process (packet sending direction) of the CPOS interface on a network device. After receiving a network packet for the CPOS interface, the protocol controller (such as the CPU) sends the serial port packet to the interface processing module. The packet write buffer module stores the serial port packet in the external DDR memory of the processing device (also known as the external storage medium of the processing device).

[0035] The message write buffer module and the downlink buffer polling and scheduling module exchange storage information. The downlink buffer polling and scheduling module reads messages from DDR memory and stores them in the corresponding local buffer. That is, the downlink buffer polling and scheduling module reads messages from DDR memory for each serial port according to the downlink rate of each serial port and stores them in the local buffer of the processing device (which can also be called the internal storage medium of the processing device).

[0036] For example, local cache 1 corresponds to serial port 1, and the messages from serial port 1 are stored in local cache 1; local cache 2 corresponds to serial port 2, and the messages from serial port 2 are stored in local cache 2, and so on.

[0037] The serial port framing module (i.e., the HDLC framing module) can read messages from the local buffer and perform framing operations on the messages, that is, add serial port information to the messages. For example, for serial port 1, the serial port framing module reads messages from local buffer 1 and adds serial port information to the messages. For serial port 2, the serial port framing module reads messages from local buffer 2 and adds serial port information to the messages, and so on.

[0038] The E1 framing module can perform framing operations on messages, that is, add E1 header information to the message. For serial port 1, the serial port framing module sends the message with the added serial port information to the E1 framing module, and the E1 framing module adds E1 header information to the message. For serial port 2, the serial port framing module sends the message with the added serial port information to the E1 framing module, and the E1 framing module adds E1 header information to the message, and so on.

[0039] The CPOS framing module can perform packet framing operations, that is, add CPOS header information to the packet. For serial port 1, the E1 framing module sends the packet with the added E1 header information to the CPOS framing module, the CPOS framing module adds the CPOS header information to the packet, and sends the packet through the CPOS interface. For serial port 2, the E1 framing module sends the packet with the added E1 header information to the CPOS framing module, the CPOS framing module adds the CPOS header information to the packet, and sends the packet through the CPOS interface, and so on.

[0040] Because the CPOS interface has a relatively slow downlink serial port speed (64Kbps-2.048Mbps), while DDR memory has a fast read speed (e.g., 800Mbps, 16-bit DDR3 memory, with an interface bandwidth of 0.5Gbps-10Gbps, depending on the number of bytes read each time; the more bytes read at once, the greater the available bandwidth), each serial port's corresponding "local buffer" only needs a small buffer of 8-100 bytes. The downlink buffer polling scheduling module must ensure that the local buffer corresponding to the serial port is not empty, and promptly retrieve the corresponding serial port's packets from DDR memory and put them into the local buffer (ensuring continuous transmission of complete packets while reaching the maximum speed limit), while also avoiding retrieving too many packets at once, which would cause the local buffer to overflow.

[0041] Therefore, under the condition of limited local cache, the multi-serial port downlink cache scheduling method directly affects the number of serial ports that can be implemented (performance metric). Under the same logical resource conditions, proper multi-serial port downlink cache scheduling can maximize the number of serial ports and better meet the aggregation and forwarding requirements of the CPOS interface.

[0042] Based on the above findings, this application proposes a method for optimizing the multi-serial port transmit buffering and scheduling under the CPOS interface. By utilizing the mutual exclusion feature of serial port binding time slots under the same E1 interface under the CPOS interface, the total amount of local buffer can be determined based on the number of time slots used by the E1 interface. The linked list technology is used to realize the dynamic allocation and round-robin scheduling of the local buffer for multiple serial ports, thereby optimizing the polling performance of the multi-serial port transmit buffer under the CPOS interface. Under the condition of similar logical buffer resources, a larger number of serial ports can be reliably achieved.

[0043] In one example, the interface processing module of the CPOS interface can be implemented using a processing device (such as an FPGA). However, processing devices typically do not have a large amount of buffer space for storing messages; that is, their internal storage medium (such as local cache) is limited. Therefore, external DDR memory can be used to store messages. DDR memory is an external storage medium for the processing device. See also... Figure 3 As shown, the downlink serial port messages from the protocol controller are first stored in DDR memory. Then, the downlink buffer polling and scheduling module retrieves messages from each serial port from the DDR memory in byte-level increments, based on the downlink rate of each serial port, and stores them in the internal storage medium (local cache) of the processing device. The serial port framing module then retrieves the messages from the internal storage medium, assembles them into frames, and sends them to the E1 framing module, which finally frames and outputs them from the CPOS interface.

[0044] Because different users have different requirements for the bandwidth and number of serial ports supported by the CPOS interface, the relationship between the serial port and the E1 interface can have the following characteristics: 1) A serial port must belong to a certain E1 interface and can be bound to one or more time slots of all time slots of the E1 interface. That is, a serial port can be bound to one time slot, and a serial port can also be bound to multiple time slots. For example, an E1 interface can have 32 time slots. Except for time slot 0, which only supports non-framed mode, the other time slots can be bound to any serial port.

[0045] 2) Under one user configuration, one time slot of the E1 interface belongs to only one serial port (i.e., multiple serial ports cannot correspond to the same time slot at the same time). The time slots bound to all serial ports are mutually exclusive. Under the same E1 interface, the bandwidth of the serial ports will not exceed the total bandwidth of the E1 interface, such as a total bandwidth of 2.048Mbps.

[0046] Taking the serial port generated by the E1 interface as an example, see Figure 4The diagram shows the correspondence between the E1 interface and the serial ports under the CPOS interface. Serial ports 0-31 correspond to the E1-1 interface, serial ports 32-63 correspond to the E1-2 interface, and so on. These 32 serial ports (0-31) correspond to 32 time slots of the E1-1 interface. Taking one serial port per time slot as an example, 32 serial ports correspond to 32 time slots. A single serial port can also correspond to multiple time slots, meaning fewer serial ports (such as serial ports 1-6) correspond to 32 time slots of the E1-1 interface. Similarly, these 32 serial ports (32-63) correspond to 32 time slots of the E1-2 interface. Again, taking one serial port per time slot as an example, a single serial port can correspond to multiple time slots, meaning fewer serial ports correspond to 32 time slots of the E1-2 interface, and so on.

[0047] Users can use any serial port corresponding to any E1 interface. Each serial port can be bound to one or more time slots of the E1 interface, depending on the user's configuration. The speed of all serial ports is configurable, ranging from 64Kbps to 2.048Mbps. For example, User 1 can use serial port 1 of the E1-1 interface, binding it to one or more time slots. User 2 can use serial port 2 of the E1-1 interface, binding it to one or more time slots, and so on, with each serial port having a speed of 64Kbps. As another example, a user can use serial port 32 of the E1-2 interface to bind it as a non-framed serial port (containing all time slots of the E1-2 interface), with a speed of 2.048Mbps. Users can also use serial port 65 corresponding to the E1-3 interface, binding it to four time slots (1, 3, 4, and 30) of the E1-3 interface, with a speed of 256Kbps.

[0048] In one example, each serial port corresponds to a local cache RAM (Random Access Memory) within the processing device. The local cache RAMs corresponding to all serial ports constitute the internal storage medium of the processing device, that is, the internal storage medium includes the local cache RAM corresponding to each serial port.

[0049] See Figure 5 The diagram illustrates the correspondence between local cache RAM and serial ports. Serial port 0 corresponds to local cache RAM 0, serial port 1 corresponds to local cache RAM 1, serial port 2 corresponds to local cache RAM 2, and so on, with serial port 2015 corresponding to local cache RAM 2015. Clearly, each serial port corresponds to one local cache RAM. Furthermore, the internal storage medium may include these 2016 local cache RAMs.

[0050] See Figure 5As shown, if a constant-speed polling method is used for each serial port, the same bytes are read and placed in the local buffer RAM of the serial port each time. Ignoring the serial port's speed, the polling scheduling efficiency is low, leading to high local buffer RAM usage and a limited number of executable serial ports. This is because when the number of serial ports reaches a certain point, due to the speed differences between them, the time taken for all serial ports to poll once cannot guarantee the continuous transmission of messages by the faster serial ports. If the continuous transmission of messages cannot be guaranteed, it will lead to packet errors or failure to meet the interface's speed limit.

[0051] In this embodiment, based on the mutual exclusion characteristic of the time slots of the E1 interface bound between serial ports, a method is proposed to dynamically adjust the local RAM cache using a linked list, dynamically allocate the local cache RAM according to the serial port rate, and dynamically adjust the number of message bytes read by each serial port in polling mode. This solves the problem of low utilization of local cache RAM and limited total number of serial ports, and more fully releases the performance of the CPOS interface.

[0052] In one example, a local cache RAM can be allocated in the internal storage medium of the processor. This local cache RAM is shared by all serial ports, rather than allocating a separate local cache RAM for each serial port.

[0053] The local cache RAM can be divided into multiple basic memory units (BM). The size of the basic memory unit is a fixed value, which can be 4 bytes, 16 bytes, etc., and there is no restriction on it.

[0054] In one example, a storage area (denoted as BM linked list RAM) can be partitioned in the internal storage medium of the processing device. A mapping table is stored in the BM linked list RAM, and the mapping table can include a fixed relationship table and an address linked list. The fixed relationship table can include a data table entry corresponding to each serial port (the table entry in the fixed relationship table is denoted as a data table entry), and the address linked list (such as the BM linked list) can include multiple linked list entries shared by all serial ports (the table entry in the address linked list is denoted as a linked list entry).

[0055] For example, for each serial port, if the serial port corresponds to multiple time slots, multiple data blocks for that serial port are read from DDR memory; if the serial port corresponds to only one time slot, one data block for that serial port is read from DDR memory. The size of the data block can be the same as the size of the basic storage unit, or it can be smaller than the size of the basic storage unit. For each data block, a basic storage unit can be selected from the local cache RAM to store the data block.

[0056] When selecting a basic storage unit from the local cache RAM, the basic storage unit can be selected randomly or by using a certain strategy; there are no restrictions on this selection method.

[0057] For multiple data blocks of this serial port, the addresses of the basic storage units of different data blocks may not be contiguous. In other words, the multiple data blocks of this serial port are not stored contiguously in the local cache RAM.

[0058] Based on this, for the first data block of the serial port, the offset position of the basic storage unit where the data block is located is recorded in a fixed relationship table (this offset position represents the starting address of the basic storage unit in the local cache RAM, and the basic storage unit can be found based on this offset position and the size of the basic storage unit).

[0059] For example, a fixed relationship table can include a data table entry corresponding to each serial port. For the first serial port, the first data table entry can record the offset position of the basic storage unit where the data block is located. For the second serial port, the second data table entry can record the offset position of the basic storage unit where the data block is located, and so on. Furthermore, the data table entries in the fixed relationship table can also record the offset address of the linked list entry for the next data block in the address linked list.

[0060] For non-first data blocks of the serial port, the offset position of the basic storage unit where the data block is located is recorded in the address chain (this offset position represents the starting address of the basic storage unit in the local cache RAM, and the basic storage unit can be found based on this offset position and the size of the basic storage unit).

[0061] For example, an address linked list can include multiple linked list entries. An unused linked list entry can be selected from these entries for the data block, and the offset of the basic storage unit containing the data block can be recorded in the selected linked list entry. Furthermore, the offset address of the next data block's linked list entry in the address linked list can also be recorded in the linked list entries.

[0062] For example, suppose that data block 1 of serial port 1 is stored in basic storage unit a1, data block 2 of serial port 1 is stored in basic storage unit a2, and data block 3 of serial port 1 is stored in basic storage unit a3, and the addresses of basic storage units a1, a2 and a3 are not contiguous.

[0063] Therefore, the offset position of basic storage unit a1 can be recorded in the first data table entry of the fixed relationship table (the data table entry corresponding to serial port 1). The offset position of basic storage unit a2 can be recorded in the linked list entry b1 of the address linked list, where linked list entry b1 is any unused linked list entry in the address linked list. The offset position of basic storage unit a3 can be recorded in the linked list entry b2, where linked list entry b2 is any unused linked list entry in the address linked list, and the addresses of linked list entry b2 and linked list entry b1 are not contiguous.

[0064] Building upon this, the first entry of the fixed relationship table can record the offset address of linked list item b1 (i.e., the linked list item of the next data block after the current data block) in the address linked list. This offset address represents the starting address of linked list item b1 in the address linked list, allowing the linked list item b1 to be found from the address linked list based on this offset address. Furthermore, linked list item b1 can also record the offset address of linked list item b2 (i.e., the linked list item of the next data block after the current data block) in the address linked list. This offset address represents the starting address of linked list item b2 in the address linked list, and so on. The offset address of the next linked list item in the address linked list can be recorded in each linked list item, up to the last linked list item. For the last linked list item, an end marker can be recorded in that item to indicate that there are no other linked list items following it.

[0065] For the reading process of serial port 1, the offset position of basic storage unit a1 and the offset address of linked list item b1 can be read from the first data table entry of the fixed relation table. Based on the offset address of linked list item b1, linked list item b1 can be found in the address linked list, and the offset position of basic storage unit a2 and the offset address of linked list item b2 can be read from linked list item b1. Based on the offset address of linked list item b2, linked list item b2 can be found in the address linked list, and the offset position of basic storage unit a3 can be read from linked list item b2, and so on, until the last linked list item. Since the last linked list item includes an end marker, no further linked list items are read.

[0066] In summary, the offset positions of basic storage units a1, a2, and a3 can be read. Based on the offset position of basic storage unit a1, data block 1 can be read from basic storage unit a1 of the local cache RAM; based on the offset position of basic storage unit a2, data block 2 can be read from basic storage unit a2 of the local cache RAM; and based on the offset position of basic storage unit a3, data block 3 can be read from basic storage unit a3 of the local cache RAM.

[0067] See Figure 6The diagram illustrates the dynamic management of the BM linked list RAM for a serial port. A mapping table can be stored in the BM linked list RAM, which may include a fixed relationship table and an address linked list. The local cache RAM can include multiple basic memory units. Dynamic management of these basic memory units is achieved by configuring fixed relationship tables and address linked lists for them. The linked list RAM is a linked list data structure implemented using random access memory (RAM) for dynamically managing data in memory. The linked list consists of a series of nodes, each containing data and one or more pointers to other nodes. It features dynamic memory allocation, flexible size, and high efficiency in insertion and deletion operations.

[0068] Each time a message is written, the address of the previously used basic storage unit on the same serial port is used as the address, and the address of the basic storage unit being written this time is used as the data. This is written to the address linked list, creating a link relationship between two consecutive basic storage units on the same serial port. That is, by simply recording the address of the initial basic storage unit of a serial port (located in a fixed relationship table), all messages of that serial port can be found according to the address linked list.

[0069] See Figure 6 As shown, when reading a message from each serial port, the address of the basic storage unit needs to be found first according to the fixed relationship table and the address linked list, and then the message is read from the address space of the local cache RAM.

[0070] In one example, a storage area can be partitioned in the internal storage medium of the processing device to store an address queue. This address queue can be called a FIFO (First In First Out) queue of basic memory cell addresses (i.e., BM addresses), and this address queue is used to record the offset position of unoccupied basic memory cells (the starting address of the basic memory cell in the local cache RAM).

[0071] Initially, all basic storage units are unoccupied, and the address queue records the offset positions of all basic storage units. During data block writing, the offset position of a basic storage unit can be selected from this address queue, and the data block is stored in that basic storage unit based on that offset position. This requires deleting the offset position from the address queue, and so on, continuously deleting the offset positions of occupied basic storage units from the address queue. Furthermore, during data block reading, data blocks are also read from basic storage units, making those basic storage units unoccupied again. The offset position of these basic storage units is then re-recorded in the address queue, and so on, continuously adding the offset positions of basic storage units whose data has been released to the address queue.

[0072] In summary, the offset positions of the basic storage units (also known as the addresses of the basic storage units, which are also pointers to the address linked list) are all placed in the address queue. When a data block needs to be written to a basic storage unit, the offset position of one basic storage unit is read from this address queue (e.g., using a FIFO method), and the message content is written to the basic storage unit corresponding to that offset position. After reading the content from a basic storage unit, the offset position of the basic storage unit can be recycled back into the address queue (e.g., using a FIFO method), thus allowing for reuse.

[0073] See Figure 7 The diagram shows a local cache RAM, an address queue, and a BM linked list RAM. The address queue (denoted as BM address FIFO) can record the offset positions of all unoccupied basic storage units. The offset positions of these basic storage units are called BM Addr (i.e., BM address).

[0074] In one example, the cache space of the internal storage medium, i.e. the size of the local cache RAM, can be determined based on the number of WAN interfaces (such as E1 interfaces or T1 interfaces) divided by the CPOS interface, the number of timeslots corresponding to each WAN interface, and the number of bytes sent in each timeslot; where the cache space can be greater than or equal to K*P*U, i.e. the size of the local cache RAM can be greater than or equal to K*P*U.

[0075] For example, K can represent the number of WAN interfaces divided by the CPOS interface, P can represent the number of time slots corresponding to each WAN interface, and U can represent the number of bytes sent in each time slot.

[0076] For example, the total size of the buffer space is determined by the total number of E1 time slots. Assuming each time slot is U bytes, that is, U bytes of data are sent in each time slot, and the CPOS interface is divided into 32 E1 interfaces, each containing 32 time slots, then the total size of the buffer space can be U*32*32, or 1024*U bytes.

[0077] As long as 1024 serial port messages with a rate of 64Kbps are uniformly scheduled continuously, the continuity of U*N byte messages scheduled by the serial port with N time slots can be guaranteed.

[0078] In one example, the amount of RAM temporarily allocated to a serial port can be determined based on the number of time slots configured for that port. For instance, if a serial port occupies one time slot, it corresponds to using two basic storage units; if it occupies 32 time slots, it can use 64 basic storage units. Since the time slots bound to different serial ports are mutually exclusive, the total dynamically allocated cache for all serial ports is guaranteed not to exceed the total RAM space, meaning the RAM space is always sufficient. For high-speed serial ports, the local cache can be increased proportionally. Therefore, a single scheduling operation can read multiple times more packets into the local cache, equivalent to buffering multiple single-time-slot 64Kbps serial port packets at once. Even using average probability polling, polling for one week ensures continuous packets from the high-speed serial port, preventing the local cache from becoming empty and discontinuous. Furthermore, for DDR memory read operations, the more bytes read at once, the higher the read efficiency. Therefore, reading U*N bytes at once is generally more efficient than reading N times, each time reading U bytes. Reading messages of multiple basic storage unit sizes at once further reduces the time required for all serial ports to poll once, thus improving efficiency.

[0079] In one example, serial port messages are polled according to the principle of "enqueue when there are messages, dequeue when there are none" to reduce the situation of "idling" when there are no messages to send, and further improve the efficiency of polling scheduling.

[0080] In one example, a local cache RAM can be set up using linked lists as the basic storage unit, and the local cache RAM, address queue, and BM linked list RAM can be used together. See [link to relevant documentation]. Figure 7 As shown. The method for setting the size of the local cache RAM (i.e., the size and number of basic storage units) is as follows:

[0081] Assuming the processing device uses L E1 interfaces, round-robin scheduling of all serial ports under L E1 interfaces can be achieved. When each E1 interface is configured with "one serial port bound to one available time slot", 31*L serial ports will be generated to complete the continuous scheduling of this number of serial port messages. The minimum buffer space required for each serial port is J bytes (this can be calculated based on the actual DDR memory scheduling efficiency, or confirmed through actual debugging; the value of J is not limited). Based on this, the size of the local cache RAM can be set to 32*L*J. For scheduling convenience, the number of bytes scheduled each time is J / 2, that is, the size of each basic storage unit is defined as J / 2, and the number of BMs in the local cache RAM is equal to (64*L).

[0082] This application proposes a message transmission method that can be applied to a processing device (such as an FPGA). The processing device can be an interface processing module of a target interface, and the target interface can include a channelized POS interface, i.e., a CPOS interface. The CPOS interface is divided into multiple wide area network interfaces (WAN interfaces can include, but are not limited to, E1 interfaces or T1 interfaces, etc.), each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot.

[0083] See Figure 8 The diagram shown is a flowchart of a message transmission method, which may include:

[0084] Step 801: After receiving a serial port message, store the serial port message in the external storage medium of the processing device. For example, the processing device includes a message write buffer module. After receiving a serial port message, the message write buffer module stores the serial port message in DDR memory, which is an external storage medium.

[0085] Step 802: Iterate through each first serial port in sequence and read M first data blocks of the first serial port from the external storage medium of the processing device. M can be the number of time slots occupied by the first serial port.

[0086] For example, the processing device may include a downlink cache polling scheduling module, which sequentially traverses each serial port (each serial port is called the first serial port). For instance, it first traverses first serial port 1. If first serial port 1 occupies 3 time slots, then it reads 3 first data blocks (each data block is called a first data block) from the external storage medium. The size of the first data block can be the same as or smaller than the size of the basic storage unit. Then, it traverses first serial port 2. If first serial port 2 occupies 6 time slots, then it reads 6 first data blocks from the external storage medium, and so on, requiring polling and traversing the first data blocks of each first serial port.

[0087] In one example, the processor can configure a serial port polling FIFO, which records the serial ports to be scheduled (i.e., the first serial port traversed above, meaning each first serial port is traversed sequentially from the serial port polling FIFO). See also Figure 9 The diagram shows the scheduling of the serial port polling FIFO. In the initial state, the serial port polling FIFO is empty. When a message is stored in DDR memory on a certain serial port S, and the message needs to be scheduled and output to the local buffer RAM, the information of serial port S is added to the serial port polling FIFO.

[0088] Once a serial port has read data from its polling FIFO (i.e., reached during the polling process) and completed scheduling, it has read M first data blocks from DDR memory. Then, it checks if the serial port is empty, meaning if there are still data packets to be read. If the DDR memory is empty, the serial port will not re-polle the FIFO after reading from it. Otherwise, the serial port will re-polle the FIFO and continue participating in the polling scheduling.

[0089] In one example, the length of each message from DDR memory to the local cache RAM (i.e., the length of M first data blocks) can be set according to the serial port speed, i.e., the number of bound time slots. Assuming that the cache space corresponding to each time slot is 2 basic storage units, and each basic storage unit corresponds to C bytes, then for a serial port bound to M time slots (such as an E1 interface serial port with a speed of (64*T)Kbps), the number of bytes scheduled each time is M*C, i.e., M first data blocks, and the size of each first data block is C bytes. In this embodiment, a data block represents C bytes of data.

[0090] In one example, for each serial port, taking serial port S as an example, the method to determine the local buffer space set for serial port S can be: record the number of messages output by serial port S from the local buffer RAM as Dout (with the basic storage unit buffer bytes as the basic counting unit), and record the number of messages scheduled out from DDR memory by serial port S as Din (with the basic storage unit buffer bytes as the basic counting unit). Assuming the serial port contains M time slots, the total buffer is 2M basic storage units. Based on this, the local buffer space Dfree can be expressed by the following formula: Dfree = 2M + Dout - Din.

[0091] Step 803: For each first data block of the first serial port, select the basic storage unit of the first data block from the internal storage medium of the processing device, and store the first data block through the basic storage unit.

[0092] For example, a local cache RAM can be allocated in the internal storage medium. This local cache RAM is shared by all serial ports and includes multiple basic storage units. Based on this, after the downlink cache polling scheduling module reads the first data block of the first serial port from the DDR memory, it selects a basic storage unit from all the basic storage units and stores the first data block in the selected basic storage unit.

[0093] In one example, an address queue can be pre-stored to record the offsets of unoccupied basic storage units. Based on this, when selecting the basic storage unit for the first data block, the offset can be chosen from this address queue. For example, the first offset can be read from the address queue using a FIFO method, the basic storage unit corresponding to that offset can be designated as the basic storage unit for the first data block, and the offset can be removed from the address queue (i.e., the basic storage unit corresponding to that offset is now occupied). In this way, the first data block can be stored using this basic storage unit.

[0094] In one example, the address queue can be processed as follows: Remove the basic storage unit at address 0 (as an invalid basic storage unit, used to initialize the address linked list and the initial value of the unused serial port buffer address), and write the offsets of the remaining basic storage units sequentially into the address queue. When a data block needs to be written, read the offset of one basic storage unit from the address queue. When the content of the data block stored in a basic storage unit is read out, reclaim the offset of that basic storage unit and write it back to the address queue.

[0095] Step 804: For each first data block of the first serial port, after storing the first data block through the basic storage unit, record the offset position of the basic storage unit in the internal storage medium in the mapping table.

[0096] For example, the mapping table may include a fixed relationship table and an address linked list. The fixed relationship table includes a data table entry corresponding to each serial port, and the address linked list (such as the BM linked list) includes multiple linked list entries shared by all serial ports. Based on this, for the first data block of the first serial port, the downlink cache polling scheduling module determines the target data table entry corresponding to the first serial port from the fixed relationship table, records the offset position of the basic storage unit where the first data block is located in the target data table entry, and records the offset address of the target linked list entry of the next first data block in the address linked list in the address linked list.

[0097] For a non-first data block of the first serial port, the downlink cache polling scheduling module can select an unused linked list item from multiple linked list items in the address linked list for the first data block. This unused linked list item is used as the target linked list item corresponding to the first data block. The offset position of the basic storage unit where the first data block is located is recorded in the target linked list item, and the offset address of the target linked list item of the next first data block in the address linked list is also recorded in the target linked list item.

[0098] In one example, see Figure 10 The diagram shown illustrates the update process of the address linked list.

[0099] Step 1001: In the initial state, determine whether the address list has been initialized to 0. If yes, proceed to step 1002; otherwise, continue waiting and return to step 1001. For example, initializing the address list to 0 means initializing the address list to an invalid value (invalid basic memory unit space).

[0100] Step 1002: Enter the address list continuously updated state.

[0101] Step 1003: When a message needs to be written to the local cache RAM from the serial port (let the serial port number be S), find the offset position of the previous basic storage unit of the serial port S corresponding to the message, and record it as ADDR_OLD.

[0102] Step 1004: Determine if ADDR_OLD is equal to 0 (0 indicates invalid).

[0103] If yes, then proceed to step 1005; if no, then proceed to step 1006.

[0104] Step 1005: If ADDR_OLD equals 0, it means that the serial port S is buffering a message for the first time. Therefore, read the offset address ADDR_NEW of one basic storage unit from the address queue, and write the address and content of the offset address ADDR_NEW into the address linked list.

[0105] Step 1006: If ADDR_OLD is not equal to 0, it means that the serial port S is not buffering the message for the first time. Therefore, read the offset address ADDR_NEW of one basic storage unit from the address queue, use the offset position ADDR_OLD as the address, and write the content of the offset address ADDR_NEW into the address linked list.

[0106] After step 1005, return to step 1002. After step 1006, return to step 1002.

[0107] This completes the address list update process, and we can proceed with the next steps.

[0108] Step 805: Iterate through each second serial port in sequence. For each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position.

[0109] For example, the processing device may include a serial port framing module, which sequentially traverses each serial port (each serial port is called a second serial port). For instance, it first traverses second serial port 1. If second serial port 1 corresponds to 3 second data blocks (each data block is called a second data block), then it obtains the offset position of the basic storage unit where second data block 1 is located from the mapping table, and reads second data block 1 from the basic storage unit corresponding to that offset position. It then obtains the offset position of the basic storage unit where second data block 2 is located from the mapping table, and reads second data block 2 from the basic storage unit corresponding to that offset position, and so on.

[0110] In one example, the processing device can set up a serial port polling FIFO, which can record the serial ports to be scheduled. Based on this, the downlink buffer polling scheduling module sequentially traverses each first serial port from the serial port polling FIFO and executes step 802 for each first serial port. The serial port framing module sequentially traverses each second serial port from the serial port polling FIFO and executes step 805 for each second serial port.

[0111] For the second serial port currently being traversed, first determine the data table entry corresponding to the second serial port from the fixed relationship table (e.g., the first data table entry corresponds to the first second serial port, and so on). Then, obtain the offset position of the basic storage unit where the second data block 1 (i.e., the first second data block of the second serial port) is located from this data table entry. Finally, obtain the offset address corresponding to the next second data block 2 (this offset address represents the offset address of the linked list entry of the second data block 2 in the address linked list) from this data table entry. Then, the offset position and offset address recorded in this data table entry can also be deleted.

[0112] Based on the offset address corresponding to the second data block 2, the linked list entry for the second data block 2 is determined from the address linked list; the offset position of the basic storage unit where the second data block 2 is located is obtained from the linked list entry, and the offset address corresponding to the next second data block 3 is obtained from the linked list entry. Then, the offset position and offset address recorded in the linked list entry can also be deleted.

[0113] Based on the offset address corresponding to the second data block 3, determine the linked list item of the second data block 3 from the address linked list; obtain the offset position of the basic storage unit where the second data block 3 is located from the linked list item, and so on, repeat the above process until the offset position of the basic storage unit where the last second data block is located is obtained.

[0114] Step 806: For each second data block of the second serial port, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, the offset position of the basic storage unit where the second data block is located is recorded in the address queue, that is, the offset position is reclaimed in the address queue.

[0115] Step 807: For each second data block of the second serial port, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, perform a framing operation on the second data block.

[0116] For example, the processing device may include a serial port framing module. After reading the second data block from the basic storage unit, the serial port framing module performs a serial port framing operation on the message, that is, adds serial port information to the message. The processing device may also include an E1 framing module. The E1 framing module obtains the message after the serial port framing operation from the serial port framing module and performs an E1 interface framing operation on the message, that is, adds E1 header information to the message. Finally, the processing device may include a CPOS framing module. The CPOS framing module obtains the message after the E1 interface framing operation from the E1 framing module and performs a CPOS framing operation on the message, that is, adds CPOS header information to the message.

[0117] Step 808: Send each second data block of the second serial port during the time slot occupied by the second serial port.

[0118] For example, regarding the second serial port currently being traversed, assuming this second serial port occupies 3 time slots, then in the first time slot occupied by this second serial port, the second data block 1 is sent, such as sending a message after framing. In the second time slot occupied by this second serial port, the second data block 2 is sent. In the third time slot occupied by this second serial port, the second data block 3 is sent. Thus, each second data block of the second serial port can be sent.

[0119] In one example, taking serial port S as an example, the number of messages written to the local cache RAM, Dwr, can be recorded. The number of messages, Dwr, represents the total number of data blocks stored for serial port S through the internal storage medium. This number will be referred to as the second number. The second number represents the total number of data blocks, or it can represent the total number of bytes (in bytes) of all data blocks. The Head Address of the address list of messages written to the serial port can also be recorded.

[0120] After each second data block (i.e., the second data block of serial port S) is read from the basic storage unit, the number of packets Drd of the second data block read (read) from the internal storage medium can also be determined. The number of packets Drd represents the total number of data blocks read from the local cache RAM for serial port S, which will be referred to as the first number. The first number can represent the total number of data blocks or the total number of bytes of all data blocks (in BYTE). The Tail Address of the read address list is also recorded.

[0121] Based on this, the remaining readable quantity can be determined based on the first quantity and the second quantity. For example, the remaining readable quantity Dram can be determined using the following formula: Dram = Dwr - Drd.

[0122] If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port has not been completed, and data reading needs to continue. For example, the offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on that offset position. For example, the serial port framing module can use the Tail Address to find the message at that address in the local cache RAM and the linked list address of the next basic storage unit to be read (i.e., the offset address corresponding to the linked list item in the address linked list). Alternatively, if the remaining readable quantity is equal to 0, it is determined that the data reading for the second serial port has been completed, that is, there is no data for the second serial port in the local cache RAM. The serial port framing module does not read the message from the local cache RAM, but directly fills the IDLE code onto the line, without any restrictions.

[0123] For example, this process can be implemented using processing devices such as FPGAs. The above information is recorded in each clock cycle, and the output conditions are detected in real time (if the data reading for the second serial port is not completed, it means that the condition is met; if the data reading for the second serial port is completed, it means that the condition is not met), thereby realizing the writing and reading scheduling of messages in the local buffer RAM.

[0124] In one example, when a user needs to release a serial port (such as serial port S), they can clear the buffer information of serial port S and unregister the port. For instance, the following clearing operations can be performed: Clear the number of packets Dwr written to the local buffer RAM of serial port S. Clear the Head Address of the address list of packets written to the buffer RAM. Clear the number of packets Drd read from the buffer RAM. Clear the Tail Address of the address list read from the buffer RAM. Release the address list ultimately occupied by serial port S into the address queue for use by other serial ports. When the serial port framing module corresponding to serial port S requests packets from the local RAM and sees that the address list is 0, it returns no packets to send, and the serial port framing module continues to send IDLE codes to the line.

[0125] As can be seen from the above technical solutions, in this embodiment, by utilizing the mutual exclusion of serial port binding time slots under the same WAN interface of the CPOS interface, the polling performance of multiple serial port transmission buffers under the CPOS interface can be optimized. Under similar logical buffer resource conditions, a larger number of serial ports can be reliably implemented, solving the problem of limited total number of serial ports, and more fully releasing the performance of the CPOS interface to meet user needs. The total amount of internal storage medium buffer is determined by the number of time slots, and linked list technology is used to realize dynamic allocation and polling scheduling of multiple serial ports, thereby dynamically allocating the buffer resources of internal storage medium, dynamically adjusting the number of packet bytes read out by each serial port in polling, improving the utilization rate and scheduling efficiency of internal storage medium, and saving more storage resources. The size of the local buffer RAM is dynamically adjusted according to the serial port rate, improving the utilization rate of local buffer RAM and the efficiency of DDR scheduling, and better ensuring the continuity of serial port transmission. A serial port scheduling scheme of enqueuing when there are packets and dequeuing when there are no packets is proposed, reducing the idle situation of serial ports without packets and improving the polling scheduling efficiency. The size of the local buffer RAM is set based on the number of time slots contained in all E1 interfaces, ensuring that all available serial ports contain one time slot (at the minimum rate), and that uniform scheduling guarantees the minimum buffer size required for continuous message transmission. A serial port polling join and leave mechanism is configured. When a message is stored in DDR on serial port S and needs to be scheduled for output to the local buffer RAM, the information of serial port S is added to the polling FIFO. When the serial port reads from the polling FIFO, completes scheduling, and the serial port message is empty, it is not re-enqueued. A clear register is configured. By clearing the number of messages written to the local buffer RAM and the head address of the address list, and reading the number of messages and the tail address of the address list, the serial port buffer is released, resolving the issue of the serial port temporarily using one time slot buffer for deregistration.

[0126] This application proposes a message transmission method applied to a processing device. The target interface corresponding to the processing device is divided into multiple wide area network (WAN) interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot. The target interface includes a channelized POS interface. See also... Figure 11 The diagram shown is a flowchart of the method, which may include:

[0127] Step 1101: For the data writing process, traverse each first serial port sequentially and read M first data blocks from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port.

[0128] Step 1102: For each first data block, select the basic storage unit of the first data block from the internal storage medium of the processing device, store the first data block through the basic storage unit, and record the offset position of the basic storage unit in the internal storage medium in the mapping table.

[0129] Step 1103: For the data transmission process, traverse each second serial port in sequence. For each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position.

[0130] Step 1104: Send each second data block of the second serial port in the time slot occupied by the second serial port.

[0131] In one example, selecting the basic storage unit of the first data block from the internal storage medium of the processing device may include: selecting the offset position of the basic storage unit from the address queue, determining the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and deleting the offset position from the address queue; wherein the address queue is used to record the offset positions of unoccupied basic storage units.

[0132] In one example, after reading the second data block from the basic storage cell of the internal storage medium based on the offset position, the offset position of the basic storage cell where the second data block is located can also be determined and the offset position of the basic storage cell can be recorded in the address queue.

[0133] In one example, the mapping table may include a fixed relationship table and an address linked list. The fixed relationship table may include data table entries corresponding one-to-one with each serial port, and the address linked list may include multiple linked list entries shared by all serial ports. Based on this, recording the offset position of the basic storage unit in the internal storage medium in the mapping table may include: for the first data block of the first serial port, determining the target data table entry corresponding to the first serial port from the fixed relationship table, recording the offset position of the basic storage unit where the first data block is located in the target data table entry, and recording the offset address of the target linked list entry of the next first data block in the address linked list in the target data table entry; for non-first data blocks of the first serial port, selecting the target linked list entry corresponding to the first data block from the address linked list, recording the offset position of the basic storage unit where the first data block is located in the target linked list entry, and recording the offset address of the target linked list entry of the next first data block in the address linked list in the target linked list entry.

[0134] In one example, obtaining the offset position of the basic storage unit where the second data block is located from the mapping table may include: for the first second data block of the second serial port, determining the data table entry corresponding to the second serial port from a fixed relationship table, obtaining the offset position of the basic storage unit where the second data block is located from the data table entry, and obtaining the offset address corresponding to the next second data block from the data table entry; wherein, the offset address represents the offset address corresponding to the linked list entry in the address linked list; for a non-first second data block of the second serial port, determining the linked list entry of the second data block from the address linked list based on the offset address corresponding to the second data block; obtaining the offset position of the basic storage unit where the second data block is located from the linked list entry, and obtaining the offset address corresponding to the next second data block from the linked list entry.

[0135] In one example, after obtaining the offset position of the basic storage unit where the second data block is located from the data table entry, and obtaining the offset address corresponding to the next second data block from the data table entry, the offset position and offset address recorded in the data table entry can also be deleted.

[0136] In one example, after obtaining the offset position of the basic storage unit where the second data block is located from the linked list item, and obtaining the offset address corresponding to the next second data block from the linked list item, the offset position and offset address recorded in the linked list item can also be deleted.

[0137] In one example, after each second data block is read from a basic storage unit of the internal storage medium, a first number of second data blocks read from the internal storage medium is determined; based on the first number and the second number, a remaining readable number is determined, where the second number represents the total number of data blocks stored for the second serial port through the internal storage medium; if the remaining readable number is greater than 0, it is determined that the data reading for the second serial port has not been completed, the offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position; if the remaining readable number is equal to 0, it is determined that the data reading for the second serial port has been completed.

[0138] In one example, the cache space of the internal storage medium can be determined based on the number of WAN interfaces divided by the target interface, the number of time slots corresponding to each WAN interface, and the number of bytes sent in each time slot; wherein, the cache space can be greater than or equal to K*P*U.

[0139] Where K represents the number of WAN interfaces divided by the target interface, P represents the number of time slots corresponding to each WAN interface, and U represents the number of bytes sent in each time slot.

[0140] As can be seen from the above technical solutions, in this embodiment, by utilizing the mutual exclusion feature of serial port binding time slots under the same WAN interface of the CPOS interface, the polling performance of multiple serial port transmit buffers under the CPOS interface can be optimized. Under similar logical cache resource conditions, a larger number of serial ports can be reliably implemented, solving the problem of limited total number of serial ports, and more fully releasing the performance of the CPOS interface to meet user needs. The total cache size of the internal storage medium is determined by the number of time slots, and the linked list technology is used to realize the dynamic allocation and polling scheduling of multiple serial ports, thereby dynamically allocating the cache resources of the internal storage medium and dynamically adjusting the number of packet bytes read out by each serial port in polling, improving the utilization rate and scheduling efficiency of the internal storage medium, and saving storage resources.

[0141] Based on the same concept as the above method, this application proposes a message transmission device applied to a processing device. The target interface corresponding to the processing device is divided into multiple wide area network (WAN) interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot. See [link to previous document]. Figure 12 The diagram shown is a structural schematic of the device, which may include:

[0142] The message buffer module 1201 is used to sequentially traverse each first serial port and read M first data blocks of the first serial port from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port.

[0143] For each first data block, a basic storage unit for the first data block is selected from the internal storage medium of the processing device, the first data block is stored through the basic storage unit, and the offset position of the basic storage unit in the internal storage medium is recorded in the mapping table.

[0144] The framing module 1202 is used to sequentially traverse each second serial port, and for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position.

[0145] The interface sending module 1203 is used to send each second data block of the second serial port in the time slot occupied by the second serial port after the framing module reads the second data block.

[0146] In one example, when the message caching module 1201 selects the basic storage unit of the first data block from the internal storage medium of the processing device, it is specifically used for:

[0147] Select the offset position of the basic storage unit from the address queue, determine the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and delete the offset position from the address queue; wherein, the address queue is used to record the offset positions of unoccupied basic storage units;

[0148] The framing module 1202 is further configured to, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, determine the offset position of the basic storage unit where the second data block is located, and record the offset position of the basic storage unit in the address queue.

[0149] In one example, the mapping table includes a fixed relationship table and an address linked list. The fixed relationship table includes a data table entry corresponding to each serial port, and the address linked list includes multiple linked list entries shared by all serial ports. When the message caching module 1201 records the offset position of the basic storage unit in the internal storage medium in the mapping table, it specifically performs the following: For the first data block of the first serial port, it determines the target data table entry corresponding to the first serial port from the fixed relationship table, records the offset position of the basic storage unit where the first data block is located in the target data table entry, and records the offset address of the target linked list entry of the next first data block in the address linked list in the target data table entry; For a non-first data block of the first serial port, it selects the target linked list entry corresponding to the first data block from the address linked list, records the offset position of the basic storage unit where the first data block is located in the target linked list entry, and records the offset address of the target linked list entry of the next first data block in the address linked list in the target linked list entry.

[0150] In one example, when the framing module 1202 obtains the offset position of the basic storage unit where the second data block is located from the mapping table, it is specifically used for:

[0151] For the first second data block of the second serial port, determine the data table entry corresponding to the second serial port from the fixed relationship table, obtain the offset position of the basic storage unit where the second data block is located from the data table entry, and obtain the offset address corresponding to the next second data block from the data table entry; wherein, the offset address represents the offset address corresponding to the linked list entry in the address linked list;

[0152] For a non-first second data block of the second serial port, the linked list entry of the second data block is determined from the address linked list based on the offset address corresponding to the second data block;

[0153] Obtain the offset position of the basic storage unit where the second data block is located from the linked list item, and obtain the offset address of the next second data block from the linked list item.

[0154] In one example, the framing module 1202 is further configured to, after obtaining the offset position of the basic storage unit where the second data block is located from the data table entry and obtaining the offset address corresponding to the next second data block from the data table entry, delete the offset position and offset address recorded in the data table entry; the framing module 1202 is further configured to, after obtaining the offset position of the basic storage unit where the second data block is located from the linked list entry and obtaining the offset address corresponding to the next second data block from the linked list entry, delete the offset position and offset address recorded in the linked list entry.

[0155] In one example, the framing module 1202 obtains the offset position of the basic storage unit where the second data block is located from the mapping table, and when reading the second data block from the basic storage unit of the internal storage medium based on this offset position, it is specifically used for:

[0156] After each second data block is read from a basic storage unit of the internal storage medium, a first number of second data blocks read from the internal storage medium is determined;

[0157] The remaining readable quantity is determined based on the first quantity and the second quantity, where the second quantity represents the total number of data blocks stored for the second serial port through the internal storage medium.

[0158] If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port has not been completed. The offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position.

[0159] If the remaining readable quantity is equal to 0, then it is determined that the data reading for the second serial port has been completed.

[0160] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0161] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A message transmission method, characterized in that, Applied to a processing device, wherein the target interface corresponding to the processing device is divided into multiple wide area network (WAN) interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot, the method includes: For the data writing process, each first serial port is traversed sequentially, and M first data blocks of the first serial port are read from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port. For each first data block, a basic storage unit for the first data block is selected from the internal storage medium of the processing device, and the first data block is stored through the basic storage unit. The offset position of the basic storage unit in the internal storage medium is recorded in a mapping table. The mapping table includes a fixed relationship table and an address linked list. The fixed relationship table includes data table entries corresponding to each serial port, and the address linked list includes multiple linked list entries shared by all serial ports. For the first first data block of the first serial port, a target data table entry corresponding to the first serial port is determined from the fixed relationship table. The offset position of the basic storage unit where the first data block is located is recorded in the target data table entry, and the offset address of the target linked list entry for the next first data block is recorded in the address linked list. For non-first first data blocks of the first serial port, a target linked list entry corresponding to the first data block is selected from the address linked list. The offset position of the basic storage unit where the first data block is located is recorded in the target linked list entry, and the offset address of the target linked list entry for the next first data block is recorded in the address linked list. For the data transmission process, each second serial port is traversed sequentially. For each second data block of the second serial port, the offset position of the basic storage unit where the second data block is located is obtained from the mapping table. Based on the offset position, the second data block is read from the basic storage unit of the internal storage medium. Each second data block of the second serial port is transmitted in the time slot occupied by the second serial port.

2. The method according to claim 1, characterized in that, The step of selecting the basic storage unit of the first data block from the internal storage medium of the processing device includes: Select the offset position of the basic storage unit from the address queue, determine the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and delete the offset position from the address queue; wherein, the address queue is used to record the offset positions of unoccupied basic storage units; After reading the second data block from the basic storage unit of the internal storage medium based on the offset position, the method further includes: determining the offset position of the basic storage unit where the second data block is located, and recording the offset position of the basic storage unit in the address queue.

3. The method according to claim 1, characterized in that, Obtaining the offset position of the basic storage unit where the second data block is located from the mapping table includes: For the first second data block of the second serial port, determine the data table entry corresponding to the second serial port from the fixed relationship table, obtain the offset position of the basic storage unit where the second data block is located from the data table entry, and obtain the offset address corresponding to the next second data block from the data table entry; wherein, the offset address represents the offset address corresponding to the linked list entry in the address linked list; For a non-first second data block of the second serial port, the linked list entry of the second data block is determined from the address linked list based on the offset address corresponding to the second data block; Obtain the offset position of the basic storage unit where the second data block is located from the linked list item, and obtain the offset address of the next second data block from the linked list item.

4. The method according to claim 3, characterized in that, After obtaining the offset position of the basic storage unit where the second data block is located from the data table entry and obtaining the offset address corresponding to the next second data block from the data table entry, the method further includes: deleting the offset position and offset address recorded in the data table entry. After obtaining the offset position of the basic storage unit where the second data block is located from the linked list item, and obtaining the offset address corresponding to the next second data block from the linked list item, the method further includes: deleting the offset position and offset address recorded in the linked list item.

5. The method according to claim 1, characterized in that, The step of obtaining the offset position of the basic storage unit where the second data block is located from the mapping table, and reading the second data block from the basic storage unit of the internal storage medium based on the offset position, includes: After each second data block is read from a basic storage unit of the internal storage medium, a first number of second data blocks read from the internal storage medium is determined; The remaining readable quantity is determined based on the first quantity and the second quantity, where the second quantity represents the total number of data blocks stored for the second serial port through the internal storage medium. If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port has not been completed. The offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position. If the remaining readable quantity is equal to 0, then it is determined that the data reading for the second serial port has been completed.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: The cache space of the internal storage medium is determined based on the number of WAN interfaces divided by the target interface, the number of time slots corresponding to each WAN interface, and the number of bytes sent in each time slot. Wherein, the cache space is greater than or equal to K*P*U; Where K represents the number of WAN interfaces divided by the target interface, P represents the number of time slots corresponding to each WAN interface, and U represents the number of bytes sent in each time slot; The target interface includes a channelized POS interface.

7. A message transmission device, characterized in that, Applied to a processing device, wherein the target interface corresponding to the processing device is divided into multiple wide area network (WAN) interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and one serial port occupies at least one time slot, the device includes: The message buffer module is used to sequentially traverse each first serial port and read M first data blocks from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port. For each first data block, a basic storage unit for the first data block is selected from the internal storage medium of the processing device, and the first data block is stored through the basic storage unit. The offset position of the basic storage unit in the internal storage medium is recorded in a mapping table. The mapping table includes a fixed relationship table and an address linked list. The fixed relationship table includes data table entries corresponding to each serial port, and the address linked list includes multiple linked list entries shared by all serial ports. Specifically, when the message buffer module records the offset position of the basic storage unit in the internal storage medium in the mapping table, it performs the following: For the first data block of the first serial port, select a basic storage unit from the fixed relationship table... The system determines the target data table entry corresponding to the first serial port in the system table. The target data table entry records the offset position of the basic storage unit where the first data block is located. The target data table entry also records the offset address of the target linked list entry of the next first data block in the address linked list. For a non-first first data block of the first serial port, the system selects the target linked list entry corresponding to the first data block from the address linked list. The target linked list entry records the offset position of the basic storage unit where the first data block is located. The target linked list entry also records the offset address of the target linked list entry of the next first data block in the address linked list. The framing module is used to sequentially traverse each second serial port, and for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position; An interface sending module is used to send each second data block of the second serial port in the time slot occupied by the second serial port after the framing module reads the second data block.

8. The apparatus according to claim 7, characterized in that, When the message caching module selects the basic storage unit of the first data block from the internal storage medium of the processing device, it is specifically used for: Select the offset position of the basic storage unit from the address queue, determine the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and delete the offset position from the address queue; wherein, the address queue is used to record the offset positions of unoccupied basic storage units; The framing module is further configured to, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, determine the offset position of the basic storage unit where the second data block is located, and record the offset position of the basic storage unit in the address queue.

9. The apparatus according to claim 7, characterized in that, When the framing module obtains the offset position of the basic storage unit where the second data block is located from the mapping table, it is specifically used for: For the first second data block of the second serial port, determine the data table entry corresponding to the second serial port from the fixed relationship table, obtain the offset position of the basic storage unit where the second data block is located from the data table entry, and obtain the offset address corresponding to the next second data block from the data table entry; wherein, the offset address represents the offset address corresponding to the linked list entry in the address linked list; For a non-first second data block of the second serial port, the linked list entry of the second data block is determined from the address linked list based on the offset address corresponding to the second data block; Obtain the offset position of the basic storage unit where the second data block is located from the linked list item, and obtain the offset address of the next second data block from the linked list item.

10. The apparatus according to claim 9, characterized in that, The framing module is further configured to, after obtaining the offset position of the basic storage unit where the second data block is located from the data table entry and obtaining the offset address corresponding to the next second data block from the data table entry, delete the offset position and offset address recorded in the data table entry. The framing module is further configured to, after obtaining the offset position of the basic storage unit where the second data block is located from the linked list item and obtaining the offset address corresponding to the next second data block from the linked list item, delete the offset position and offset address recorded in the linked list item.

11. The apparatus according to claim 7, characterized in that, The framing module obtains the offset position of the basic storage unit where the second data block is located from the mapping table, and when reading the second data block from the basic storage unit of the internal storage medium based on this offset position, it is specifically used for: After each second data block is read from a basic storage unit of the internal storage medium, a first number of second data blocks read from the internal storage medium is determined; The remaining readable quantity is determined based on the first quantity and the second quantity, where the second quantity represents the total number of data blocks stored for the second serial port through the internal storage medium. If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port has not been completed. The offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position. If the remaining readable quantity is equal to 0, then it is determined that the data reading for the second serial port has been completed.

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