Image pickup apparatus, control method thereof, storage medium, and program product

Abstract

The invention provides an imaging apparatus, a control method thereof, a storage medium, and a program product. An image pickup apparatus includes: a pixel section in which a plurality of pixels each including a plurality of photoelectric conversion elements are arranged in a matrix; at least three sample hold circuits; a voltage-current conversion section configured to output a difference between the two sample-and-hold circuits as a current signal; an AD converter configured to convert an output signal of the voltage-current conversion section into a digital signal; and a control unit configured to perform control such that in a period in which a first pixel signal obtained from the pixel is held in one sample-and-hold circuit and AD conversion is performed on the first pixel signal, an operation becoming to hold a second pixel signal obtained from the pixel in another sample-and-hold circuit is started.

Description

Technical Field

[0001] The present invention relates to an imaging device and a control method thereof. Background Art

[0002] Hitherto, there has been known a technique in which a plurality of photoelectric conversion elements are provided in one pixel of an image sensor and focus detection is performed using output signals from the plurality of photoelectric conversion elements.

[0003] Japanese Patent No. 5755111 discloses an image pickup device that can perform focus detection using an image sensor, wherein each pixel in the image sensor includes a microlens and a plurality of photoelectric conversion elements. In Japanese Patent No. 5755111, after a reset signal of a pixel is read out, a signal based on the charge of at least one photoelectric conversion element is read out from the pixel, and then a signal based on the charge of a plurality of photoelectric conversion elements is read out from the pixel.

[0004] In addition, in Japanese Patent Laid-Open No. 2022-119484, the following configuration of a photoelectric conversion device is disclosed. That is, two sample-and-hold circuits are set in parallel for one output line, one sample-and-hold circuit holds a reset signal of one pixel, and the other sample-and-hold circuit holds a photodetection signal. Then, a current based on the difference between the photodetection signal and the reset signal is output to an AD conversion unit, and correction processing is performed using correlated double sampling between the photodetection signal and the reset signal.

[0005] However, using the configuration described in Japanese Patent Laid-Open No. 2022-119484, when two sample-and-hold circuits connected to signal lines are to be used to sample and hold a reset signal read out from a pixel, a signal based on the charge of at least one photoelectric conversion element, and a signal based on the charge of multiple photoelectric conversion elements, the following processing is required.

[0006] First, one sampling and holding circuit holds a reset signal of one pixel, and another sampling and holding circuit holds a signal based on the charge of at least one photoelectric conversion element in the one pixel. After AD conversion is performed on the signal based on the difference, the sampling and holding circuit that holds the signal based on the charge of at least one photoelectric conversion element holds a signal based on the charge of multiple photoelectric conversion elements in the one pixel. Then, AD conversion is performed on the signal based on the difference from the reset signal. As described above, after performing AD conversion once, AD conversion needs to be performed again, so there is a problem of increased readout time. Summary of the invention

[0007] The present invention has been made in view of the above-mentioned problems, and provides an image pickup apparatus capable of shortening a signal readout time when one pixel includes a plurality of photoelectric conversion elements.

[0008] According to a first aspect of the present invention, there is provided an image pickup device, comprising: a pixel section, in which a plurality of pixels each including a plurality of photoelectric conversion elements are arranged in a matrix; at least three sampling and holding circuits arranged for a pixel signal output from one pixel; a voltage-current conversion section, configured to output a difference between two sampling and holding circuits of the at least three sampling and holding circuits as a current signal; an AD converter, configured to convert the output signal of the voltage-current conversion section into a digital signal; and a control unit, configured to control so that during a period in which a first pixel signal obtained from the pixel is held in one of the at least three sampling and holding circuits and the first pixel signal is AD-converted, an operation of starting to hold a second pixel signal obtained from the pixel in the other sampling and holding circuits of the at least three sampling and holding circuits is performed.

[0009] According to a second aspect of the present invention, there is provided a control method for an imaging device, the imaging device comprising a pixel unit, at least three sampling and holding circuits, a voltage-current conversion unit and an AD converter, wherein a plurality of pixels in the pixel unit, each of which comprises a plurality of photoelectric conversion elements, are arranged in a matrix, the at least three sampling and holding circuits are arranged for a pixel signal output from one pixel, the voltage-current conversion unit is configured to output a difference between two sampling and holding circuits of the at least three sampling and holding circuits as a current signal, the AD converter is configured to convert the output signal of the voltage-current conversion unit into a digital signal, and the control method comprises: controlling so that during a period in which a first pixel signal obtained from the pixel is maintained in one of the at least three sampling and holding circuits and the first pixel signal is AD-converted, an operation is started to maintain a second pixel signal obtained from the pixel in other sampling and holding circuits of the at least three sampling and holding circuits.

[0010] According to a third aspect of the present invention, there is provided a non-transitory computer-readable medium storing a program for causing a computer to execute the above-mentioned control method of the imaging apparatus.

[0011] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a block diagram of a camera device.

[0013] Figure 2 is a simplified configuration diagram of an image sensor.

[0014] Figure 3 It is the equivalent circuit diagram of a unit pixel.

[0015] Figure 4 is a simplified block diagram of the column circuit.

[0016] Figure 5 is a diagram showing an exemplary configuration of a column circuit.

[0017] Figure 6 is a timing diagram of the read operation.

[0018] Figure 7 is a simplified block diagram of the column circuit of the second embodiment.

[0019] Figure 8 is a timing chart of the second embodiment.

[0020] Fig. 9 is an equivalent circuit diagram of a unit pixel of the third embodiment.

[0021] Fig.10 is a simplified block diagram of the column circuit of the third embodiment.

[0022] Fig.11 is a timing chart of the third embodiment.

[0023] Fig.12 is an equivalent circuit diagram of a unit pixel of the fourth embodiment.

[0024] Fig.13 is a simplified block diagram of the column circuit of the fourth embodiment.

[0025] Fig.14 is a timing chart of the fourth embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the present invention. A plurality of features are described in the embodiments, but are not limited to the invention requiring all of these features, and these features may be appropriately combined. In addition, in the accompanying drawings, the same reference numerals are given to the same or similar configurations, and their redundant descriptions will be omitted.

[0027] (First embodiment)

[0028] Figure 1 1 is a block diagram showing a configuration of an image pickup apparatus according to an embodiment of the present invention. The image pickup apparatus 100 is an image pickup apparatus capable of performing focus detection on an image pickup plane.

[0029] The lens unit 101 collects incident light from a subject and forms a subject image on the image sensor 102. The lens unit 101 is composed of, for example, a plurality of lenses, an aperture, etc., and is controlled by a lens driving device 103 to perform zoom control, focus control, and aperture control.

[0030] The control circuit 112 partially controls the image processing of the image processing circuit 109 and the driving of the image sensor 102. In addition, the control circuit 112 controls the reception of instructions from the display unit 113 and the console unit 116, and the data transmission with respect to the memory circuit 111 and the recording unit 110. In addition, the control circuit 112 performs focus detection calculation based on the image data from the image processing circuit 109, and causes the lens driving device 103 to perform focus adjustment through the lens unit 101. Note that the control circuit 112 may be included in the image sensor 102 or the image processing circuit 109, for example.

[0031] The image processing circuit 109 performs development processing such as color matrix processing and gamma processing on the image data from the image sensor 102. In this processing, the image processing circuit 109 causes the memory circuit 111 to retain the image data as needed. In addition, the image processing circuit 109 outputs the processed image data to the display unit 113 or the recording unit 110. The display unit 113 includes a display device for displaying the processed image data, etc. The console unit 116 generates an operation signal according to an operation performed by a user. The bus 120 is a common path for exchanging data between the image sensor 102, the image processing circuit 109, the display unit 113, the console unit 116, the recording unit 110, and the memory circuit 111.

[0032] Figure 2 is a simplified configuration diagram of the image sensor 102. Figure 2 As shown, the image sensor 102 includes a pixel array section 201, a vertical scanning unit 202, a column circuit unit 210, and a digital memory unit 211. In addition, the image sensor 102 includes a horizontal scanning unit 212, a digital signal processing unit 215 (also referred to as a digital front end (DFE)), an output unit 216, and a control unit 203.

[0033] In the pixel array section 201, a plurality of pixels 21 are arranged in a matrix, lines in the vertical direction are referred to as "columns", and lines in the horizontal direction are referred to as "rows". For convenience, Figure 2 2 shows a part of the plurality of pixels 21 constituting the pixel array section 201 .

[0034] Control signal lines 22 are arranged in each row of the pixel array section 201. The control signal lines 22 each include a plurality of control signal lines for supplying a plurality of types of control signals to a plurality of pixels 21. The control signal lines 22 in each row are connected to the vertical scanning unit 202.

[0035] A column output line 23 is arranged in each column of the pixel array section 201 . In the pixel array, the number of column output lines 23 for one column does not have to be one, and may be two or more. The column output line 23 is connected to the column circuit unit 210 .

[0036] The vertical scanning unit 202 receives a control signal output from the control unit 203, generates a control signal for driving the plurality of pixels 21, and supplies the control signal to the plurality of pixels 21 through the control signal line 22. A logic circuit such as a shift register or an address decoder is used in the vertical scanning unit 202. The vertical scanning unit 202 performs control so that signals are read out by selecting the plurality of pixels 21 in the pixel array section 201 in units of rows, and outputs the signals of the plurality of pixels 21 to the column circuit unit 210 through the column output line 23.

[0037] The column circuit unit 210 includes a plurality of sample-and-hold circuits for holding signals of output lines, a plurality of voltage-current conversion circuits, and a plurality of AD converters, and performs signal processing including correlated double sampling and AD conversion. A specific configuration of the column circuit unit 210 will be described later.

[0038] The digital memory unit 211 is connected to the column circuit unit 210, and has a function of retaining a digital signal for each column obtained by AD conversion in the column circuit unit 210. The digital memory unit 211 is connected to the control unit 203, and receives a control signal for retaining the digital signal output from the column circuit unit 210 from the control unit 203.

[0039] The horizontal scanning unit 212 is connected to the control unit 203, and generates a control signal for reading out the digital signal retained in the digital memory unit 211 based on the control signal from the control unit 203. Then, the horizontal scanning unit 212 causes the digital signal retained in the digital memory unit 211 to be output to the digital signal processing unit 215.

[0040] The digital signal processing unit 215 performs signal processing such as amplification processing and correction processing on the digital signal output from the digital memory unit 211 .

[0041] The output unit 216 is controlled by a control signal from the control unit 203, and is an external interface circuit for outputting a signal input from the digital signal processing unit 215 to an external device. The control unit 203 supplies control signals to the vertical scanning unit 202, the column circuit unit 210, the digital memory unit 211, the horizontal scanning unit 212, and the output unit 216 to control each unit. Note that these control signals do not have to be supplied from the control unit 203, and may be supplied from the outside of the image sensor 102.

[0042] Figure 3is a simplified equivalent circuit of the pixel 21. Figure 3 As shown, the pixel 21 includes a first photoelectric converter 301, a second photoelectric converter 302, a first transfer transistor 303, and a second transfer transistor 304. The pixel 21 also includes a reset transistor 32, an amplifying transistor 33, a selection transistor 34, and a floating diffusion 31.

[0043] For example, the first transfer transistor 303 , the second transfer transistor 304 , the reset transistor 32 , the amplification transistor 33 , and the selection transistor 34 are each configured by an NMOS transistor, but may be configured by other transistors.

[0044] Each pixel 21 includes a microlens and a color filter (not shown) on an optical path through which incident light is guided to the first photoelectric converter 301 and the second photoelectric converter 302. The first photoelectric converter 301 and the second photoelectric converter 302 are photodiodes, for example.

[0045] The first transfer transistor 303 and the second transfer transistor 304 are respectively connected to the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302. In addition, each of these transfer transistors is used to transfer the signal of the corresponding photoelectric conversion element to the floating diffusion unit 31 (ie, the input node of the amplifier transistor 33).

[0046] The floating diffusion 31 includes a capacitance component (floating diffusion capacitance) formed of interconnect capacitance and the like, and has a function as a charge holding portion.

[0047] The reset transistor 32 is connected to the floating diffusion 31 (ie, the input node of the amplifier transistor 33), and supplies a reset voltage thereto. The drains of the reset transistor 32 and the amplifier transistor 33 are connected to a power supply voltage node.

[0048] The amplifier transistor 33 amplifies the signal transmitted to the floating diffusion 31 (ie, the input node), and outputs the amplified signal to the column output line 23. The selection transistor 34 controls the electrical conduction between the amplifier transistor 33 and the column output line 23.

[0049] The current source 35 is electrically connected to the column output line 23. The current source 35 supplies a bias current to the amplifier transistor 33, and the amplifier transistor 33 and the current source 35 constitute a source follower.

[0050] The control signal line 22 of the vertical scanning unit 202 is connected to the first transfer transistor 303, the second transfer transistor 304, the reset transistor 32, the amplification transistor 33 and the selection transistor 34. The control signal line 22 includes four signal lines to which control signals PTXA, PTXB, PRES and PSEL are respectively provided. These four signal lines are signal lines shared by the pixels 21 belonging to the corresponding row.

[0051] Among the four signal lines of each row, the signal line of the control signal PTXA is connected to the gate of the first transfer transistor 303 in the pixel 21 of the corresponding row. The signal line of the control signal PTXB is connected to the gate of the second transfer transistor 304. The signal line of the control signal PRES is connected to the gate of the reset transistor 32. The signal line of the control signal PSEL is connected to the gate of the selection transistor 34.

[0052] Figure 4 4 is a simplified block diagram of the column circuit 41. The column circuit unit 210 is composed of a plurality of column circuits 41. Each column circuit 41 is connected to at least one of the plurality of column output lines 23 of the pixel array section 201. Figure 4 , the column output line 23 is connected to a first sample-and-hold circuit (S&H(N)) 42, a second sample-and-hold circuit (S&H(A)) 43, and a third sample-and-hold circuit (S&H(A+B)) 44. The first sample-and-hold circuit 42, the second sample-and-hold circuit 43, and the third sample-and-hold circuit 44 each hold the potential of the column output line 23 at a predetermined time, and these operations are controlled by a plurality of control signals (not shown) provided by the control unit 203. In addition, these sample-and-hold circuits can each provide the held potential to a voltage-current conversion circuit (V to I) 45. The first sample-and-hold circuit 42 holds an N signal described later. The second sample-and-hold circuit 43 holds an A signal described later. The third sample-and-hold circuit 44 holds an A+B signal described later.

[0053] The voltage-current conversion circuit 45 switches the current signal between a current signal based on the potential difference between the first sampling and holding circuit 42 and the second sampling and holding circuit 43, and a current signal based on the potential difference between the first sampling and holding circuit 42 and the third sampling and holding circuit through a control signal (not shown) provided by the control unit 203, and outputs the resulting current signal to the AD converter (ADC) 46.

[0054] The AD converter 46 is an AD converter that converts the output current signal of the voltage-current conversion circuit 45 into a digital signal, but it can also be connected to the voltage-current conversion circuit of another column circuit and perform AD conversion on the signal output therefrom. For example, the AD converter 46 is a Delta-Sigma (ΔΣ) type AD conversion circuit, but it is not limited to this.

[0055] Figure 5is a circuit diagram showing an exemplary configuration of the column circuit 41. The first sample-and-hold circuit 42, the second sample-and-hold circuit 43, and the third sample-and-hold circuit 44 are connected to the column output line 23 via switches 501, 502, and 503, respectively. The switches 501, 502, and 503 are controlled by a control signal (not shown) from the control unit 203, and are used to select which sample-and-hold circuit holds the potential of the column output line 23.

[0056] The first sample-and-hold circuit 42, the second sample-and-hold circuit 43, and the third sample-and-hold circuit 44 respectively include capacitors 504, 505, and 506 to hold signals. One end of these capacitors is respectively connected to switches 501, 502, and 503, and the other end is respectively connected to inverting amplifiers 510, 511, and 512.

[0057] The switches 507, 508, and 509 are connected between the input nodes and output nodes of the respective inverting amplifiers 510, 511, and 512, respectively. The switches 513, 514, and 515 are respectively provided between the nodes of the switches 501, 502, and 503 on the opposite side to the column output line 23 and the voltage-current conversion circuit 45. The switch 513 is connected to the interconnection line 51, and the switches 514 and 515 are connected to the interconnection line 52. The switches 516, 517, and 518 are respectively provided between the output nodes of the inverting amplifiers 510, 511, and 512 and the voltage-current conversion circuit 45. The switch 516 is connected to the PMOS transistor 521, and the switches 517 and 518 are connected to the PMOS transistor 522.

[0058] The voltage-current conversion circuit 45 includes a current source 520, a resistor 523, a PMOS transistor 521, a PMOS transistor 522, an interconnection line 51, an interconnection line 52, and an interconnection line 53. The current source 520 is arranged between the power supply voltage node and the interconnection line 51, and the resistor 523 is arranged between the interconnection line 51 and the interconnection line 52. The PMOS transistor 522 used as a source follower is arranged between the interconnection line 53 and the interconnection line 52, and the PMOS transistor 521 used as a source follower is arranged between the interconnection line 51 and the ground. The voltage-current conversion circuit 45 performs a process of converting the potential difference between the interconnection line 51 and the interconnection line 52 into a current signal, and transmits the current signal to the AD converter 46.

[0059] Figure 6 2 is a timing chart showing an example of a pixel signal readout operation from the pixel 21 to the AD converter 46 .

[0060] exist Figure 6, control signals PSEL, PRES, PTXA, and PTXB output from the vertical scanning unit 202 to the pixels 21 on one row and output potentials Vout from the pixels 21 to the column output lines 23 of the corresponding columns are shown. In the period before time T1, the control signals PSEL, PRES, PTXA, and PTXB are assumed to be at a low level (hereinafter indicated as "L level"). In addition, it is assumed that charges corresponding to the amount of incident light are accumulated in the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302. In addition, it is assumed that switches 507, 508, and 509 in the column circuit 41 are in a closed state, and the other switches in the column circuit 41 are in an open state.

[0061] At time T1, the vertical scanning unit 202 controls the control signal PSEL to transition from the L level to the high level (hereinafter referred to as "H level"). Therefore, the selection transistor 34 is turned on, and the source of the amplifier transistor 33 is connected to the column output line 23 via the selection transistor 34. Here, the number of pixels connected to the column output line 23 is not limited to one, and a plurality of pixels on different columns or rows to be subjected to the same operation may be connected simultaneously.

[0062] In the next predetermined period from time T2, the vertical scanning unit 202 controls the control signal PRES to transition from the L level to the H level. Therefore, the reset transistor 32 is turned on, and the floating diffusion 31 is reset to a predetermined potential (reset potential) according to the reference potential. This state is the reset state of the pixel 21. In this way, the output potential Vout of the column output line 23 becomes a potential corresponding to the reset potential of the floating diffusion 31. During the period until time T3 after the reset transistor 32 is turned off and the potential of the column output line 23 is stabilized, the potential becomes a reset signal (also represented as "N signal") due to the turning on and off of the switch 501, the switch 502 and the switch 503. The period from time T2 to time T3 includes the stabilization time of the column output line 23 and the writing time of the N signal to the capacitor 504, the capacitor 505 and the capacitor 506, and is represented as an "N signal sampling and holding period".

[0063] In the next predetermined period from time T3, the vertical scanning unit 202 controls the control signal PTXA to transition from the L level to the H level. Therefore, the first transfer transistor 303 is turned on, the charge accumulated in the first photoelectric conversion unit 301 is transferred to the floating diffusion unit 31, and the potential of the floating diffusion unit 31 becomes a potential corresponding to the amount of charge transferred from the photoelectric conversion unit. Therefore, the output potential Vout of the column output line 23 becomes a potential corresponding to the amount of charge transferred to the floating diffusion unit 31. During the period until time T4 after the first transfer transistor 303 is turned off and the potential of the column output line 23 is stabilized, the potential becomes a photodetection signal (also represented as "A signal") for focus detection due to the turning on and off of the switch 502 and is held in the capacitor 505. The period from time T3 to time T4 includes the stabilization time of the column output line 23 and the writing time of the A signal to the capacitor 505, and is represented as an "A signal sampling and holding period".

[0064] In the next predetermined period from time T4, by a control signal (not shown) output from the control unit 203, the switches 507 and 508 are turned off, and the switches 513, 516, 514, and 517 are turned on. Here, the potential of the interconnection line 51 becomes a potential based on the N signal held in the capacitor 504, and the potential of the interconnection line 52 becomes a potential based on the A signal held in the capacitor 505. A current corresponding to the potential difference between the interconnection line 51 and the interconnection line 52 flows through the resistor 523, and a current signal corrected by correlated double sampling based on the A signal and the N signal is taken out to the interconnection line 53 connected to the AD converter 46. The current signal of the interconnection line 53 is input to the AD converter 46 and converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211.

[0065] The period from time T4 until the converted digital signal is obtained is represented as an “A signal AD conversion period”.

[0066] In a predetermined period from time T5 in the A signal AD conversion period, the vertical scanning unit 202 controls the control signal PTXA to transition from the L level to the H level. In addition, the vertical scanning unit 202 controls the control signal PTXB to transition from the L level to the H level so that the control signal PTXB is at the H level in at least a portion of the H level period of the control signal PTXA. In this way, the first transfer transistor 303 and the second transfer transistor 304 are turned on. In addition, the charge accumulated in the first photoelectric conversion unit 301 and the charge accumulated in the second photoelectric conversion unit 302 can be transferred to the floating diffusion unit 31 at the same time. That is, the potential of the floating diffusion unit 31 becomes a potential corresponding to the amount of charge transferred from the two photoelectric conversion units. Therefore, the output potential Vout of the column output line 23 becomes a potential corresponding to the amount of charge transferred to the floating diffusion unit 31. In the period until time T6 after the first transfer transistor 303 and the second transfer transistor 304 are turned off and the potential of the column output line 23 is stabilized, due to the on and off of the switch 503, the potential becomes a photodetection signal (also represented as "A+B signal") for image formation and is held in the capacitor 506. The period from time T5 to time T6 is represented as the "A+B signal sampling and holding period". The A+B signal sampling and holding period starts in the A signal AD conversion period, so the AD conversion of the A signal and the sampling and holding operation of the A+B signal are performed in parallel. In this way, the speed of the readout operation of the pixel signal can be increased. Here, time T5 can be the same as time T4.

[0067] At the next time T6, the switch 514, the switch 517, and the switch 509 are turned off by a control signal (not shown) output from the control unit 203, and the switch 515 and the switch 518 are turned on. Here, the potential of the interconnection line 51 becomes the potential based on the N signal held in the capacitor 504, and the potential of the interconnection line 52 becomes the potential based on the A+B signal held in the capacitor 506. A current corresponding to the potential difference between the interconnection line 51 and the interconnection line 52 flows through the resistor 523. Therefore, the current signal corrected by the correlated double sampling based on the A+B signal and the N signal is taken out to the interconnection line 53 connected to the AD converter 46. The current signal of the interconnection line 53 is input to the AD converter 46 and converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211. The period from the time T6 until the converted digital signal is obtained is expressed as "A+B signal AD conversion period". Since there is one AD converter 46, the A+B signal AD conversion period needs to start after the A signal AD conversion period ends.

[0068] At the next time T7, the vertical scanning unit 202 controls the control signal PSEL to transition from the H level to the L level. In this way, the selection transistor 34 is turned off, and the source of the amplification transistor 33 is disconnected from the column output line 23. When the operation of the time T7 and the A+B signal AD conversion period are completed, the operation of reading out the signals of the pixels 21 belonging to the row to the corresponding AD converter 46 via the respective column output lines 23 is completed.

[0069] In the first embodiment, three sampling and holding circuits are included. Therefore, during the period of AD conversion of the A signal using the first sampling and holding circuit and the second sampling and holding circuit, the sampling and holding operation of the A+B signal using the third sampling and holding circuit can be started. Therefore, the readout time of the signal from the pixel can be shortened.

[0070] (Second embodiment)

[0071] In the first embodiment described above, one voltage-current conversion circuit and one AD converter are connected to three sample-and-hold circuits, but in this configuration, since there is only one AD converter, AD conversion of the A+B signal needs to be performed after AD conversion of the A signal. Therefore, if the AD conversion period of the A signal is long, the waiting time from the end of the sample-and-hold operation of the A+B signal until the start of AD conversion of the A+B signal increases, and the readout time increases. The second embodiment is different from the first embodiment in that two voltage-current conversion circuits and two AD converters are provided, so that AD conversion can be performed in parallel even when the AD conversion period is long.

[0072] Will use Figure 7 and Figure 8 A second embodiment of the present invention will be described.

[0073] exist Figure 7 and Figure 8 In the present invention, constituent elements similar to those of the first embodiment will be given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0074] Figure 7 7 is a simplified block diagram showing an example of a column circuit in the second embodiment. A voltage-current conversion circuit (V to I) 71 and an AD converter (ADC) 72 are added to the arrangement of the pixel configuration of the first embodiment. The voltage-current conversion circuit 71 is connected to the sample-and-hold circuit 42 that holds the N signal and the sample-and-hold circuit 44 that holds the A+B signal. The voltage-current conversion circuit 71 outputs a current signal based on the difference between the potential held in the sample-and-hold circuit 42 and the potential held in the sample-and-hold circuit 44 to the AD converter 72.

[0075] The voltage-current conversion circuit 45 is connected to the sample-hold circuit 42 holding the N signal and the sample-hold circuit 43 holding the A signal. The voltage-current conversion circuit 45 outputs a current signal based on the difference between the potential held in the sample-hold circuit 42 and the potential held in the sample-hold circuit 43 to the AD converter 46.

[0076] The AD converter 46 and the AD converter 72 each convert the input analog current signal into a digital signal, and output the converted digital signal to the digital memory unit 211 .

[0077] Figure 8 2 is a timing chart showing an example of the readout operation of the pixel signal from the pixel to the AD converter in the second embodiment. The operation before time T1 and from time T1 to time T4 is the same as that of the first embodiment, so the description thereof will be omitted.

[0078] At time T4, the N signal and the A signal are held in the sample-hold circuit 42 and the sample-hold circuit 43, respectively. From time T4, the output of the current signal based on the potential difference between the A signal and the N signal in the voltage-current conversion circuit 45 to the AD converter 46 and the conversion operation of the digital signal in the AD converter 46 are started. The period from time T4 until the A signal is converted into a digital signal is expressed as an "A signal AD conversion period".

[0079] At the next time T5, the first transfer transistor 303 and the second transfer transistor 304 are turned on. After Vout is stabilized at the potential of the A+B signal, a holding operation of the A+B signal is performed in the sample and hold circuit 44. The time when the holding operation of the A+B signal is completed in the sample and hold circuit 44 is time T6, and the period from time T5 to time T6 is expressed as an "A+B signal sampling and holding period".

[0080] At the next time T6, in the voltage-current conversion circuit 71, conversion of the current signal based on the potential difference between the N signal held in the sample-and-hold circuit 42 and the A+B signal held in the sample-and-hold circuit 44 is performed. In addition, the conversion operation of the digital signal is started in the AD conversion circuit 72. The period from the time T6 until the completion of the conversion operation of the digital signal in the AD conversion circuit 72 is expressed as an "A+B signal conversion period".

[0081] At the next time T7, the selection transistor 34 is turned off, and the source of the amplification transistor 33 is disconnected from the column output line 23. When the operation at time T7 and the A signal AD conversion period and the A+B signal AD conversion period are completed, the operation of reading out the signals of the pixels 21 belonging to the row to the corresponding AD converters 46 via the respective column output lines 23 is completed.

[0082] In the second embodiment, even if the A signal AD conversion period is not completed at time T6, since two voltage-current conversion circuits and AD converters are provided, AD conversion of the A+B signal can be started. Therefore, in the period after time T6, AD conversion of the A signal and AD conversion of the A+B signal can be performed in parallel, and the read operation period can be shortened relative to the first embodiment.

[0083] (Third Embodiment)

[0084] In the above-mentioned second embodiment, the following example is shown: since two voltage-current conversion circuits and two AD conversion circuits are arranged for three sample-and-hold circuits, AD conversion is performed in parallel. When this configuration is used, even if the number of signals to be read out from the pixel has increased, AD conversion can be performed in parallel in two AD converters, and similarly to the second embodiment, the readout time can be shortened.

[0085] As is well known, when the number of photoelectric conversion elements included in one pixel increases, focus detection can be performed with higher accuracy, and in the third embodiment, an example is shown in which three types of photodetection signals are read out from the pixel portion in addition to the reset signal.

[0086] Will use Figures 9 to 11 A third embodiment of the present invention is described. Figures 9 to 11 In the present invention, constituent elements similar to those of the first and second embodiments will be given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0087] Fig. 9 is an equivalent circuit diagram of a unit pixel in the third embodiment.

[0088] In addition to the pixel configuration in the first embodiment, it also includes a third photoelectric conversion unit 901, a fourth photoelectric conversion unit 902, a third transfer transistor 903, a fourth transfer transistor 904 and a signal line for providing a control signal PTXC (i.e., a control signal line 22 connected to the vertical scanning unit 202).

[0089] Unlike the first and second embodiments, since the number of photoelectric conversion elements is increased to four, for example, when the photoelectric conversion elements are arranged in a 2×2 matrix, signals for focus detection corresponding to the vertical direction and the horizontal direction can be obtained. The third transfer transistor 903 is arranged between the third photoelectric conversion portion 901 and the floating diffusion portion 31, and the fourth transfer transistor 904 is arranged between the fourth photoelectric conversion portion 902 and the floating diffusion portion 31. The gates of the third transfer transistor 903 and the fourth transfer transistor 904 are connected to the signal line PTXC, and when the control signal is at an H level, the signal of the corresponding photoelectric conversion element is transferred to the floating diffusion portion 31.

[0090] Fig.10 : is a simplified block diagram of a column circuit in the third embodiment. A sample and hold circuit (S&H (A, A+B+C)) 10 holds an A signal and thereafter holds an A+B+C signal described later.

[0091] Fig.11 3 is a timing chart showing an example of a pixel signal readout operation from a pixel to an AD converter in the third embodiment. The operation before time T1 and from time T1 to time T6 is the same as that of the second embodiment, so a description thereof will be omitted.

[0092] It is assumed that the A signal AD conversion period ends at time T6, which is different from the second embodiment. Here, since the AD conversion of the previously held A signal has been completed, the sample-and-hold circuit 10 can hold a new signal. At time T6, the control signals PTXA, PTXB, and PTXC are turned to the H level for the new signal holding operation. Therefore, the charges accumulated in the first photoelectric conversion unit 301, the second photoelectric conversion unit 302, the third photoelectric conversion unit 901, and the fourth photoelectric conversion unit 902 are transferred to the floating diffusion unit 31. In addition, the potential of the floating diffusion unit 31 becomes a potential corresponding to the transferred charge.

[0093] Even after the control signals PTXA, PTXB, and PTXC transition to the L level, the potential of the floating diffusion 31 is maintained, and the potential Vout of the column output line 23 is stabilized to a potential corresponding to the potential of the floating diffusion 31 through the amplification transistor 33. After Vout is stabilized, the third photodetection signal (also represented as “A+B+C signal”) is held in the sample-and-hold circuit 10 by the sample-and-hold operation of the sample-and-hold circuit 10. The period from time T6 until the sample-and-hold operation of the A+B+C signal is completed is represented as “A+B+C signal sample-and-hold period”.

[0094] On the other hand, time T6 is also the time when the A+B signal sampling and holding period ends, and from time T6, AD conversion of the A+B signal is performed in the voltage-current conversion circuit 71 and the AD converter 72. The period from time T6 until the AD conversion of the A+B signal is completed is represented as the "A+B signal AD conversion period". Here, even if the number of signals to be read out from the pixel has increased relative to the first embodiment as in the case of the third photodetection signal, the readout time can be shortened because the sampling and holding and AD conversion of the signals are processed in parallel as in the period after time T6. The period from the end of the A+B+C signal sampling and holding period until the AD conversion of the A+B+C signal is completed is represented as the "A+B+C signal AD conversion period".

[0095] In addition, if Fig.11 As shown, when the A+B+C signal sampling and holding period ends in the A+B signal AD conversion period, since two voltage-current conversion circuits and two AD converters are provided in the column circuit, AD conversion of the A+B+C signal can be started using the voltage-current conversion circuit 45 and the AD converter 46. As described above, even if the number of signals to be read out from the pixel has increased, since AD ​​conversion is performed in parallel using two AD converters as in the second embodiment, the readout time can be shortened.

[0096] In the third embodiment, even if the number of signals to be read out from the pixel is 3, the readout time can be shortened by using the configuration of the column circuit of the second embodiment. Specifically, after the AD conversion of the first pixel signal (A signal AD conversion period) is completed and the sampling and holding operation of the second pixel signal (A+B signal sampling and holding period) is completed, the third pixel signal becomes held in the sampling and holding capacitor (A+B+C signal sampling and holding period). Then, by overlapping the A+B+C signal sampling and holding period and the A+B signal AD conversion period, and by overlapping the A+B signal AD conversion period and the A+B+C signal AD conversion period, the readout time can be shortened.

[0097] (Fourth embodiment)

[0098] The fourth embodiment is an example in which four sample-and-hold circuits, two voltage-current conversion circuits, and two AD converters are provided for one pixel, and the readout time is shortened by performing readout operations of signals from photoelectric conversion elements in parallel.

[0099] The following will refer to Figure 12 to Figure 14 A readout operation of a signal from a photoelectric conversion element in a fourth embodiment of the present invention is described. Descriptions of portions similar to those of the first to third embodiments will be omitted or simplified.

[0100] Fig.12 3 is an equivalent circuit diagram of a unit pixel in the fourth embodiment. Reset transistor 332 and reset transistor 322 are connected to floating diffusion 331 and floating diffusion 321, respectively, and reset the floating diffusion to the power supply voltage by control signal PRES. The signal output nodes of the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302 are connected to transfer transistor 330 and transfer transistor 320, respectively. In addition, these signals (from the signal output nodes) are transmitted to different floating diffusions 331 and floating diffusions 321, respectively, by control signal PTXA output from vertical scanning unit 202.

[0101] The amplifier transistor 333 is used to amplify the signal accumulated in the floating diffusion 331 and output it to the column output line 23B. The selection transistor 334 is located between the amplifier transistor 333 and the column output line 23B, and is used to control electrical conduction by the control signal PSEL output from the vertical scanning unit 202. The amplifier transistor 323 is used to amplify the signal accumulated in the floating diffusion 321 and output it to the column output line 23A. The selection transistor 324 is located between the amplifier transistor 323 and the column output line 23A, and is used to control electrical conduction by the control signal PSEL output from the vertical scanning unit 202.

[0102] The current source 35B is electrically connected to the column output line 23B. The current source 35B supplies a bias current to the amplifier transistor 333, and the amplifier transistor 333 and the current source 35B constitute a source follower.

[0103] The current source 35A is electrically connected to the column output line 23A. The current source 35A supplies a bias current to the amplifier transistor 323, and the amplifier transistor 323 and the current source 35A constitute a source follower.

[0104] Fig.13 2 is a simplified block diagram of a column circuit 141 in the fourth embodiment. A plurality of column circuits 141 are arranged in the column circuit unit 210, and each column circuit 141 is connected to a corresponding output line of the pixel array section.

[0105] The sampling and holding circuit (S&H(NB)) 144 and the sampling and holding circuit (S&H(B)) 145 are connected to the column output line 23B. The voltage-current conversion circuit (V to I) 147 is connected to the output nodes of the sampling and holding circuit 144 and the sampling and holding circuit 145, and the output node of the voltage-current conversion circuit 147 is connected to the AD converter (ADC) 149.

[0106] The sample-and-hold circuit (S&H(NA)) 142 and the sample-and-hold circuit (S&H(A)) 143 are connected to the column output line 23A. The voltage-current conversion circuit (V to I) 146 is connected to the output nodes of the sample-and-hold circuit 142 and the sample-and-hold circuit 143, and the output node of the voltage-current conversion circuit 146 is connected to the AD converter (ADC) 148. The output nodes of the AD converter 148 and the AD converter 149 are connected to the digital memory unit 211.

[0107] Fig.14 1 is a timing chart showing a readout operation in a period in which a signal is output from a pixel and AD-converted in the fourth embodiment. Fig.14 , control signals PSEL, PRES, and PTXA output from the vertical scanning unit 202 to one row, and output potentials VoutA and VoutB output to the column output lines 23A and 23B, respectively, are shown.

[0108] It is assumed that the control signals PSEL, PRES, and PTXA are at the L level in the period before time T11. In addition, it is assumed that charges corresponding to the amount of incident light are accumulated in each of the first photoelectric conversion portion 301 and the second photoelectric conversion portion 302.

[0109] At time T11, the vertical scanning unit 202 controls the control signal PSEL to change from the L level to the H level. In this way, the selection transistor 334 and the selection transistor 324 are turned on. In addition, the source of the amplifier transistor 333 is connected to the column output line 23B via the selection transistor 334, and the source of the amplifier transistor 323 is connected to the column output line 23A via the selection transistor 324.

[0110] In the next predetermined period from time T12, the vertical scanning unit 202 controls the control signal PRES to transition from the L level to the H level. In this way, the reset transistor 332 and the reset transistor 322 are turned on, and the potentials of the floating diffusion 331 and the floating diffusion 321 are reset to a predetermined potential (reset potential) according to the reference potential.

[0111] This state is the reset state of the pixel 21. Therefore, the output potentials VoutA and VoutB of each column output line 23A and column output line 23B become potentials corresponding to the reset potentials of the floating diffusion 331 and floating diffusion 321, respectively. In the period from the reset transistor 332 and the reset transistor 322 are turned off and the potentials of the column output line 23B and the column output line 23A have stabilized until time T13, these potentials are sampled and held. Therefore, the reset signal (expressed as "NA signal") based on the reset potential of the floating diffusion 321 is held in the sample-hold circuit 142 and the sample-hold circuit 143. The period from time T12 to time T13 includes the stabilization time of the column output line 23A and the time for sampling and holding the NA signal, and is expressed as "NA signal sample-hold period".

[0112] In addition, a reset signal (expressed as “NB signal”) based on the reset potential of the floating diffusion 331 is held in the sample-hold circuit 144 and the sample-hold circuit 145. The period from time T12 to time T13 also includes the stabilization time of the column output line 23B and the time for sampling and holding the NB signal, and is also expressed as “NB signal sampling and holding period”.

[0113] In the next predetermined period from time T13, the vertical scanning unit 202 controls the control signal PTXA to transition from the L level to the H level. In this way, the transfer transistor 330 is turned on, and the charge accumulated in the first photoelectric conversion unit 301 is transferred to the floating diffusion 331. In addition, the potential of the floating diffusion 331 becomes a potential corresponding to the amount of charge transferred from the photoelectric conversion unit. Therefore, the output potential VoutB of the column output line 23B becomes a potential corresponding to the amount of charge transferred to the floating diffusion 331. In the period from the transfer transistor 330 to the end and the potential of the column output line 23B has stabilized until time T14, the potential is sampled and held by the sample and hold circuit 145. The signal is held in the sample and hold circuit 145 as a first photodetection signal (also represented as a "B signal"). The period from time T13 to time T14 includes the stabilization time of the column output line 23B and the writing time of the B signal to the sample and hold circuit 145, and is represented as a "B signal sample and hold period".

[0114] On the other hand, by controlling the control signal PTXA to change from the L level to the H level, the transfer transistor 320 is also turned on, and the charge accumulated in the second photoelectric conversion unit 302 is transferred to the floating diffusion unit 321. In addition, the potential of the floating diffusion unit 321 becomes a potential corresponding to the amount of charge transferred from the photoelectric conversion unit. Therefore, the output potential VoutA of the column output line 23A becomes a potential corresponding to the amount of charge transferred to the floating diffusion unit 321. In the period until time T14 after the transfer transistor 320 is turned off and the potential of the column output line 23A has stabilized, the potential is sampled and held by the sample and hold circuit 143. The signal is held in the sample and hold circuit 143 as a second photodetection signal (also represented as "A signal"). The period from time T13 to time T14 includes the stabilization time of the column output line 23A and the writing time of the A signal to the sample and hold circuit 143, and is represented as the "A signal sample and hold period".

[0115] In the next predetermined period from time T14, the signals held in the sample and hold circuits 142 and 143 are sent to the voltage-current conversion circuit 146 by a control signal (not shown) output from the control unit 203. A current signal based on the difference between the A signal and the NA signal is output from the voltage-current conversion circuit 146 to the AD converter 148 as a signal subjected to correction processing by correlated double sampling.

[0116] The current signal input to the AD converter 148 is converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211. The period from time T14 until the converted digital signal is obtained is represented as an "A signal AD conversion period".

[0117] Here, also in the voltage-current conversion circuit 147, after time T14, the signals held in the sample-and-hold circuit 144 and the sample-and-hold circuit 145 are sent to the voltage-current conversion circuit 147. In addition, the current signal based on the potential difference between the B signal and the NB signal is output to the AD converter 149 as a signal subjected to correction processing by correlated double sampling.

[0118] The current signal input to the AD converter 149 is converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211. The period from time T14 until the converted digital signal is obtained is also represented as a "B signal AD conversion period".

[0119] At the next time T15, the vertical scanning unit 202 controls the control signal PSEL to change from the H level to the L level. Therefore, the selection transistor 334 and the selection transistor 324 are turned off. Then, the source of the amplifier transistor 333 is disconnected from the column output line 23B, and the source of the amplifier transistor 323 is disconnected from the column output line 23A. When the operation at time T15, the A signal AD conversion period, and the B signal AD conversion period end, the readout operation until the signal of the pixel 21 belonging to the row is AD converted ends.

[0120] In the fourth embodiment, four sample-and-hold circuits, two voltage-current conversion circuits, and two AD converters are provided for one pixel. Therefore, the period during which the A signal is sampled and held and AD-converted can overlap with the period during which the B signal is sampled and held and AD-converted, thereby shortening the readout operation period.

[0121] Other embodiments

[0122] The embodiments of the present invention may also be implemented by providing software (program) for performing the functions of the above-described embodiments to a system or device via a network or various storage media, and a computer or a central processing unit (CPU) or a microprocessing unit (MPU) of the system or device reads and executes the program.

[0123] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A camera device, comprising: a pixel portion in which a plurality of pixels each including a plurality of photoelectric conversion elements are arranged in a matrix; at least three sample-and-hold circuits arranged for a pixel signal output from one pixel; a voltage-current conversion section configured to output a difference between two sample-and-hold circuits of the at least three sample-and-hold circuits as a current signal; An AD converter configured to convert an output signal of the voltage-current conversion unit into a digital signal; as well as A control unit is configured to control so that during a period in which a first pixel signal obtained from the pixel is held in one of the at least three sampling and holding circuits and AD conversion is performed on the first pixel signal, an operation of holding a second pixel signal obtained from the pixel in another sampling and holding circuit among the at least three sampling and holding circuits is started.

2. The imaging device according to claim 1, wherein: The control unit causes the at least three sample-and-hold circuits to hold a reset signal of the pixel.

3. The imaging device according to claim 1, wherein: The first pixel signal is a signal based on the charge of at least one photoelectric conversion element of the one pixel, and the second pixel signal is a signal based on the charge of a plurality of photoelectric conversion elements of the one pixel.

4. The imaging device according to claim 1, wherein: The first pixel signal is a signal based on the charge of at least one photoelectric conversion element of the one pixel, and the second pixel signal is a signal based on the charge of the other photoelectric conversion elements of the one pixel.

5. The imaging device according to claim 4, wherein: The AD converter includes a first AD converter and a second AD converter, and the control unit performs control so that the second AD converter performs AD conversion of the first pixel signal when the first AD converter performs AD conversion of the first pixel signal.

6. The imaging device according to claim 1, wherein: The AD converter includes a first AD converter and a second AD converter, and the control unit controls so that the second AD converter starts converting the second pixel signal into a digital signal during a period in which the first AD converter is converting the first pixel signal into a digital signal.

7. The imaging device according to claim 1, wherein: The control unit controls to start an operation of causing the sample-and-hold circuit that has held the first pixel signal to hold a third pixel signal after AD conversion of the first pixel signal is completed and the second pixel signal is sampled and held.

8. The imaging device according to claim 1, wherein: The AD converter includes a Delta-Sigma type AD converter.

9. The imaging device according to claim 1, wherein: The pixel signal is a signal based on signals output from a plurality of pixels.

10. A control method for an imaging device, the imaging device comprising a pixel unit, at least three sample-and-hold circuits, a voltage-to-current conversion unit, and an AD converter, wherein: In the pixel section, a plurality of pixels each including a plurality of photoelectric conversion elements are arranged in a matrix, the at least three sample-and-hold circuits are arranged for a pixel signal output from one pixel, the voltage-to-current conversion section is configured to output a difference between two sample-and-hold circuits of the at least three sample-and-hold circuits as a current signal, the AD converter is configured to convert an output signal of the voltage-to-current conversion section into a digital signal, and the control method includes: Control is performed so that during a period in which a first pixel signal obtained from the pixel is held in one of the at least three sampling and holding circuits and AD conversion is performed on the first pixel signal, an operation of holding a second pixel signal obtained from the pixel in another sampling and holding circuit among the at least three sampling and holding circuits is started. 11 . A non-transitory computer-readable storage medium storing a program for causing a computer to execute the control method of the imaging apparatus according to claim 10 . 12 . A computer program product comprising a program for causing a computer to execute the control method of the imaging apparatus according to claim 10 .

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