Composite dielectric gate double-transistor reading method for realizing HDR (High Dynamic Range) based on variable slope

Abstract

The invention discloses a composite dielectric gate double-transistor reading method for realizing HDR based on a variable slope, and belongs to the field of integrated circuits. A specific nonlinear ramp voltage (the slope of the ramp voltage at the front section is small, the slope of the ramp voltage at the middle section is large, and the slope of the ramp voltage at the rear section is reduced) is added to the gate of the composite dielectric gate double-transistor photosensitive detector, so that the comparator overturning time of pixel points in low-brightness and high-brightness intervals is prolonged, namely, the gray value ranges of the two intervals are widened, and the sensitivity of the composite dielectric gate double-transistor photosensitive detector is improved. The pixel in the middle gray value is not enlarged, so that the HDR imaging effect is achieved at the circuit end, the problems of high power consumption and high complexity caused by processing at the algorithm end are avoided, multiple exposure imaging and additional algorithm processing are not needed, and the implementation method is simple.

Description

Technical Field

[0001] The invention relates to a composite dielectric gate dual transistor readout method for realizing HDR based on a variable slope, and belongs to the field of integrated circuits. Background Art

[0002] An image sensor is a device that uses photoelectric devices to perform imaging. The image is formed by converting the light signal on the photosensitive surface into an electrical signal that is proportional to the light signal, and then quantizing the changed analog signal into a digital signal through a designed circuit. Among the existing image sensors, CCD and CMOS-APS have been widely used. The Chinese invention patent with the publication number CN102938409A discloses a composite dielectric gate dual-transistor photosensitive detector. The photosensitive detector has a dual-transistor structure, which is a photosensitive transistor and a reading transistor that respectively realize the photosensitive function and the reading function. The composite structure makes it unnecessary to make a source and drain for the photosensitive transistor part; compared with traditional photodetectors, it has the advantages of low dark current, no interference between photosensitive units, and high quantum efficiency. When reading out the composite dielectric gate dual-transistor photosensitive detector, different light responses will cause different threshold voltages of the reading transistor. Therefore, the light signal can be read out by fixing the gate voltage to quantize the drain current or fixing the current to quantize the gate voltage.

[0003] The quantization method of the traditional readout circuit is linear quantization, that is, the light response intensity and the converted electrical signal correspond linearly. For the readout of the composite dielectric gate dual transistor, the Chinese invention patent with the publication number CN111147078A proposes an analog-to-digital conversion circuit based on a composite dielectric gate dual transistor photosensitive detector. Through an off-chip ramp voltage source, the device light response can be converted into a digital readout; in addition, the Chinese invention patents with the publication numbers CN116017184A and CN117135478A respectively propose a composite dielectric gate dual transistor pixel readout circuit based on an inverter chain transimpedance amplifier and a composite dielectric gate transistor pixel readout circuit based on a dual transimpedance amplifier. The former uses a ramp voltage applied to the gate of the composite dielectric gate dual transistor for readout, and the latter uses a ramp current source plus a cross-group amplifier for readout. In the above scheme, whether it is a ramp voltage source or a ramp current source, a ramp signal with a fixed slope is used, and the different light responses of each pixel are linearly quantized. Therefore, for an image with a large range of light and dark, if the exposure time is short, the darker pixels will not get a good imaging effect; if the exposure time is long, the brighter pixels will not get a good imaging effect.

[0004] In order to improve the imaging effect of images with a large range of light and dark, High Dynamic Range Imaging (HDR) can be used. By increasing the image brightness range, the range of highlights and shadows in the image is wider, which will make the image details fuller and correctly represent the brightness range from direct sunlight to the darkest shadow in the real world. The traditional method of implementing HDR is to use the time domain multi-frame synthesis method, that is, to take multiple pictures with different exposure times (for example, take three frames, respectively, short exposure time frame, medium exposure time frame, long exposure time frame), and then synthesize them. This method usually needs to be processed on the algorithm side, resulting in high power consumption and higher complexity. Summary of the invention

[0005] In order to improve the imaging effect of images with a large range of light and dark without increasing power consumption and complexity, the present invention provides a composite dielectric gate dual transistor readout circuit and a readout method for realizing HDR based on a variable slope. By improving the readout circuit framework provided by the Chinese invention patent with publication number CN111147078A, HDR imaging is realized at the circuit end without the need for multiple exposure imaging and additional algorithm processing. The implementation method is simple and does not cause additional power consumption.

[0006] A composite dielectric gate dual transistor readout method for realizing HDR based on a variable slope, wherein the method performs nonlinear readout of the composite dielectric gate dual crystal threshold voltage by applying a ramp voltage with a variable slope to the gate of the composite dielectric gate dual crystal; the slope of the ramp voltage is small at both ends and large in the middle.

[0007] Optionally, the method is implemented based on a composite dielectric gate dual transistor readout circuit that implements HDR with a variable slope, the circuit comprising a composite dielectric gate dual transistor photodetector, a slope-controllable slope generating circuit, a clamping circuit, an integrating capacitor, a comparator circuit and a counter; wherein the slope-controllable slope generating circuit is connected to the gate of the composite dielectric gate dual transistor photodetector, the source of the composite dielectric gate dual transistor photodetector is grounded, and the drain is connected to the output of the clamping circuit to keep the drain voltage constant; the drain of the composite dielectric gate dual transistor photodetector is also connected to the integrating capacitor to convert the current signal into a voltage signal connected to the positive input of the comparator circuit, and the negative input of the comparator circuit is connected to a reference voltage Vrefcomp; and the counter is connected to the output of the comparator circuit.

[0008] Optionally, the slope-controllable ramp generation circuit includes a transconductance operational amplifier, an integrating capacitor, and a current mirror circuit. The upper and lower plates of the integrating capacitor are respectively connected to the negative input terminal and the output terminal of the transconductance operational amplifier. The positive input terminal of the transconductance operational amplifier is connected to the reference voltage Vhold. The current mirror circuit is used to generate an integrating current, and the current mirror circuit is connected to the negative input terminal of the transconductance operational amplifier through a switch.

[0009] Optionally, the current mirror circuit includes N current mirrors, and each current mirror is connected to a switch below. The switch is controlled by a digital circuit to adjust the magnitude of the integrating current.

[0010] Optionally, the currents generated by the N current mirrors are respectively 2 0 I, 2 1 I, 2 2 I, ……, 2 N-1 I, where I represents the unit current.

[0011] Optionally, the three slopes of the ramp voltage are respectively denoted as k1, k2, k1, where k1 < k2; the lowest and highest voltages of the ramp voltage are VL and VH respectively, and the ramp voltages at the slope turning points are respectively denoted as V1 and V2;

[0012] For the pixel points with the threshold voltage range from VL to V1, the time for the comparator to flip is equal to The count value is

[0013]

[0014] For the pixel points with the threshold voltage range from V1 to V2, the time for the comparator to flip is equal to The count value is

[0015] For the pixel points with the threshold voltage range from V2 to VH, the time for the comparator to flip is equal to The count value is

[0016] VTH is the threshold voltage of the composite dielectric gate bipolar transistor.

[0017] Optionally, the method includes:

[0018] Step 1, applying a ramp voltage with a variable slope to the gate of the composite dielectric gate bipolar transistor by controlling the magnitude of the integrating current through a digital circuit;

[0019] Step 2, when the magnitude of the ramp voltage reaches the threshold of the composite dielectric gate bipolar transistor, the drain current of the composite dielectric gate bipolar transistor charges the integrating capacitor to reach the comparator reference voltage Vrefcomp, and the comparator flips;

[0020] Step 3, the counter starts counting from the time when the comparator flips, and the final count value is the quantification of the threshold voltage of the composite dielectric gate dual transistor;

[0021] Step 4, obtaining the quantization of the threshold voltage of the composite dielectric gate dual transistor according to the final count value of the counter, and reading the gray value of each pixel according to the quantization value.

[0022] The present application also provides a composite dielectric gate dual transistor readout circuit for realizing HDR based on a variable slope, the circuit comprising a composite dielectric gate dual transistor photosensitive detector, a slope controllable slope generating circuit, a clamping circuit, an integrating capacitor, a comparator circuit and a counter; wherein the slope controllable slope generating circuit is connected to the gate of the composite dielectric gate dual transistor photosensitive detector, the source of the composite dielectric gate dual transistor photosensitive detector is grounded, and the drain is connected to the output of the clamping circuit to keep the drain voltage constant; the drain of the composite dielectric gate dual transistor photosensitive detector is also connected to the integrating capacitor to convert the current signal into a voltage signal connected to the positive input of the comparator circuit, and the negative input of the comparator circuit is connected to the reference voltage Vrefcomp; the counter is connected to the output of the comparator circuit.

[0023] Optionally, the slope-controllable ramp generating circuit includes a transconductance operational amplifier, an integrating capacitor and a current mirror circuit, wherein the upper and lower plates of the integrating capacitor are respectively connected to the negative input and output ends of the transconductance operational amplifier, and the positive input end of the transconductance operational amplifier is connected to a reference voltage Vhold; the current mirror circuit is used to generate an integral current, and the current mirror circuit is connected to the negative input end of the transconductance operational amplifier through a switch.

[0024] Optionally, the current mirror circuit includes N current mirrors, each current mirror is connected to a switch, and the switch is controlled by a digital circuit to adjust the magnitude of the integral current; the magnitudes of the currents generated by the N current mirrors are 2 0 I.2 1 I.2 2 I, ..., 2 N-1 I, I represents unit current.

[0025] The beneficial effects of the present invention are:

[0026] By adding a specific nonlinear ramp voltage to the gate of the composite dielectric gate dual-transistor photosensitive detector (the slope of the ramp voltage is small in the front section, large in the middle section, and decreases in the back section), the comparator flipping time of the pixels in the low-brightness and high-brightness intervals is lengthened, that is, the grayscale value range of these two intervals is enlarged, but the pixels in the middle grayscale value are not enlarged, thereby achieving the HDR imaging effect at the circuit end and avoiding the problems of high power consumption and high complexity caused by processing at the algorithm end. The present application scheme does not require multiple exposure imaging and additional algorithm processing, and the implementation method is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 Schematic diagram of a variable slope ramp voltage used in the present invention.

[0029] Figure 2 It is a structural diagram of the readout circuit used in the present invention.

[0030] Figure 3 1 is a circuit diagram of a ramp generator for generating the ramp voltage according to the present invention.

[0031] Figure 4 It is a comparison diagram of the effect of the present invention on processing underexposed pictures.

[0032] Figure 5 It is a comparison diagram of the effects of the present invention on processing overexposed images. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0034] Embodiment 1

[0035] This embodiment provides a composite dielectric gate dual transistor readout circuit for implementing HDR based on a variable ramp, wherein the ramp voltage used is as follows: Figure 1 As shown in the figure, the ramp voltage has the characteristics of a small slope in the front section, a large slope in the middle section, and a decreasing slope in the back section. The ramp voltage is applied to the gate of the composite dielectric gate dual transistor, and the drain current of the composite dielectric gate dual transistor is read out, that is, the grayscale value corresponding to each pixel. The image obtained by quantizing the ramp voltage with a nonlinear slope shown in the figure has a high dynamic range and has a better display effect for darker and brighter pixels.

[0036] The architecture of the composite dielectric gate dual transistor readout circuit for implementing HDR based on a variable slope provided in this embodiment is as follows: Figure 2 As shown, the readout structure includes a composite dielectric gate dual transistor photosensitive detector, a slope controllable ramp generating circuit, a clamping circuit, an integrating capacitor, a comparator circuit and a counter;

[0037] The source end of the composite dielectric gate dual transistor photodetector is grounded, the drain end is connected to the output of the clamping circuit to keep the drain voltage constant, the gate end is connected to the ramp voltage output by the ramp generating circuit, and the drain current is connected to the integrating capacitor to be converted into a voltage signal, which is then converted into a digital quantity by the subsequent comparator and counter.

[0038] Will Figure 1 The ramp voltage is applied to the gate terminal of the composite dielectric gate dual transistor. When the ramp voltage reaches the composite dielectric gate dual transistor threshold voltage (VTH), the drain current charges the capacitor to reach the readout circuit comparator reference voltage Vrefcomp, and the comparator flips. The comparator output is connected to a counter, and the time from the start to the flipping of the comparator is recorded. The final count value is the quantification of the composite dielectric gate dual transistor threshold voltage.

[0039] Since the composite dielectric gate dual transistor photosensitive detector can convert light intensity into transistor threshold voltage, the grayscale value of the pixel point can be obtained by quantifying the threshold voltage of the composite dielectric gate dual transistor, that is, the grayscale value of each pixel can be read out by the counting value.

[0040] To generate Figure 1 The ramp voltage with the characteristics shown in the figure requires the design of a ramp generator with an adjustable ramp slope, such as Figure 3 As shown. The designed ramp generator consists of a transconductance operational amplifier, an integrating capacitor and a current mirror circuit. The upper and lower plates of the integrating capacitor are connected to the negative input and output of the transconductance operational amplifier respectively, and the positive input of the transconductance operational amplifier is connected to the reference voltage Vhold. The integrating current is generated by the current mirror circuit, and the generated current size is adjustable. The method is to add a switch under each current mirror, and the switch can be controlled by a digital circuit. If a 4-bit control switch is used, the 4 current sizes are I, 2I, 4I, and 8I respectively, so the generated current size ranges from 0 to 15I.

[0041] According to the principle of constant current charging of capacitors, the slope of the ramp voltage is proportional to the charging current, that is, the adjustable range of the slope is 0 to 15I / C. Therefore, to generate a ramp voltage with a slope, for example, the digital terminal can input a 4-bit current control code in sequence of 1, 4, and 1, and the slopes of the three ramps are I / C, 4I / C, and I / C respectively.

[0042] In order to control the ramp up and down, it is necessary to add a switch to control the charging and discharging of the capacitor. Figure 3 In this case, a switch S1 is added between the capacitor and the charging current, and a switch S2 is added across the capacitor. When S1 is closed and S2 is open, the current charges the capacitor, so the output voltage obtained is a linearly rising ramp voltage; when S1 is open and S2 is closed, the output voltage rapidly slopes down and remains stable after dropping to the magnitude of the reference voltage Vhold.

[0043] Embodiment 2

[0044] This embodiment provides a composite dielectric gate dual-transistor readout method for implementing HDR based on a variable ramp. This method is implemented based on the circuit provided in Embodiment 1. Different from the conventional linear ramp quantization method, this method sets different quantization coefficients for pixel points in different brightness ranges through a non-linear ramp to achieve a high-dynamic-range imaging effect.

[0045] A composite dielectric gate dual-transistor readout method for implementing HDR based on a variable ramp includes:

[0046] Step 1: Controlling the magnitude of the integration current through a digital circuit to apply a ramp voltage with a variable slope to the gate of the composite dielectric gate dual-transistor;

[0047] Step 2: When the magnitude of the ramp voltage reaches the threshold of the composite dielectric gate dual-transistor, the drain current of the composite dielectric gate dual-transistor charges the integration capacitor to reach the comparator reference voltage Vrefcomp, and the comparator flips;

[0048] Step 3: The counter starts counting from the time when it starts to flip until it flips, and the final count value is the quantization of the threshold voltage of the composite dielectric gate dual-transistor;

[0049] Step 4: Obtaining the quantization of the threshold voltage of the composite dielectric gate dual-transistor according to the final count value of the counter, and reading out the gray values of each pixel according to the quantization value to implement.

[0050] The specific quantization method involved is:

[0051] If the three slopes of the ramp voltage are set as k1, k2, k1 (where k1 < k2), the lowest and highest voltages of the ramp voltage are VL and VH respectively, the ramp voltages at the slope turning points are set as V1 and V2 respectively, and the counter clock frequency is f.

[0052] For pixel points with a threshold voltage range from VL to V1, the time when the comparator flips is equal to The count value is For pixel points with a threshold voltage range from V1 to V2, the time when the comparator flips is equal to The count value is For pixel points with a threshold voltage range from V2 to VH, the time when the comparator flips is equal to The count value is

[0053] For the method of fixed slope ramp voltage quantization, if the slope of the ramp voltage is fixed as k2, then for each pixel, the time when the comparator flips is equal to The count value range is Low precision and small dynamic range; if the slope of the ramp voltage is fixed as k1, then for each pixel, the time when the comparator flips is equal to (where k1 < k2), the count value range is High precision, but requires a higher-bit counter and cannot improve the contrast in darker and brighter regions.

[0054] Therefore, by comparison, the ramp voltage with segmented slopes lengthens the comparator flip time of the pixels in the low-brightness and high-brightness intervals, that is, expands the gray value range of these two intervals, but does not expand the pixels with intermediate gray values, thus achieving the HDR imaging effect.

[0055] Using the above variable slope segmented ramp quantization method to process an underexposed picture:

[0056] As Figure 4 shown, the left figure is an underexposed Lena picture. The overall picture is dark and some black details are difficult to distinguish. Performing the segmented slope mapping as Figure 1 shown, the result shown in the right figure is obtained. Since the gray value range of the dark pixels is expanded, more details can be shown in the dark areas (such as the hair area shown in the box), improving the dynamic range. Figure 4

[0057] Using the above variable slope segmented ramp quantization method to process an overexposed picture:

[0058] As Figure 5 shown, the left figure is an overexposed Lena picture. The overall picture is bright, resulting in the details in the bright part being submerged. Performing the segmented slope mapping as Figure 1 shown, the result shown in the right figure is obtained. Since the gray value range of the bright pixels is expanded, more details can be shown in the bright areas (such as the hat area shown in the box), also improving the dynamic range. Figure 5

[0059] Some steps in the embodiments of the present invention can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as a CD or a hard disk, etc.

[0060] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.​​

Claims

1. A composite dielectric gate dual transistor readout method for implementing HDR based on a variable slope, characterized in that: The method non-linearly reads out the threshold voltage of the composite dielectric gate bipolar transistor by applying a ramp voltage with a variable slope to the gate of the composite dielectric gate bipolar transistor; the slope of the ramp voltage is small at both ends and large in the middle.

2. The method according to claim 1, characterized in that The method is implemented based on a variable ramp to realize the readout circuit of the composite dielectric gate bipolar transistor for HDR. The circuit includes a composite dielectric gate bipolar transistor photosensitive detector, a ramp generation circuit with controllable slope, a clamping circuit, an integrating capacitor, a comparator circuit, and a counter. Among them, the ramp generation circuit with controllable slope is connected to the gate of the composite dielectric gate bipolar transistor photosensitive detector. The source of the composite dielectric gate bipolar transistor photosensitive detector is grounded, and the drain is connected to the output of the clamping circuit to keep the drain voltage constant. The drain of the composite dielectric gate bipolar transistor photosensitive detector is also connected to the integrating capacitor to convert the current signal into a voltage signal and connect it to the positive input terminal of the comparator circuit. The negative input terminal of the comparator circuit is connected to the reference voltage Vrefcomp. The counter is connected to the output terminal of the comparator circuit.

3. The method according to claim 2, characterized in that The ramp generation circuit with controllable slope includes a transconductance operational amplifier, an integrating capacitor, and a current mirror circuit. The upper and lower plates of the integrating capacitor are respectively connected to the negative input terminal and the output terminal of the transconductance operational amplifier. The positive input terminal of the transconductance operational amplifier is connected to the reference voltage Vhold. The current mirror circuit is used to generate an integrating current, and the current mirror circuit is connected to the negative input terminal of the transconductance operational amplifier through a switch.

4. The method according to claim 3, characterized in that The current mirror circuit includes N current mirrors, and each current mirror is connected to a switch below. The switch is controlled by a digital circuit to adjust the magnitude of the integrating current.

5. The method according to claim 4, characterized in that The currents generated by the N current mirrors are respectively 2 0 I.2 1 I.2 2 I, ..., 2 N-1 I, I represents unit current.

6. The method according to claim 5, characterized in that The three slopes of the ramp voltage are respectively denoted as k1, k2, k1, and k1 < k2. The lowest and highest voltages of the ramp voltage are VL and VH respectively, and the ramp voltages at the slope turning points are respectively denoted as V1 and V2. For pixels with a threshold voltage range of VL to V1, the comparator flip time is equal to The count value is For pixels with a threshold voltage range of V1 to V2, the comparator flip time is equal to The count value is For pixels with a threshold voltage range of V2 to VH, the comparator flip time is equal to The count value is VTH is the threshold voltage of the composite dielectric gate bipolar transistor.

7. The method according to claim 6, characterized in that The method includes: Step 1, controlling the magnitude of the integrating current through a digital circuit to apply a ramp voltage with a variable slope to the gate of the composite dielectric gate bipolar transistor. Step 2, when the magnitude of the ramp voltage reaches the threshold of the composite dielectric gate bipolar transistor, the drain current of the composite dielectric gate bipolar transistor charges the integrating capacitor to reach the comparator reference voltage Vrefcomp, and the comparator flips. Step 3, the counter starts counting from the time when the comparator flips, and the final count value is the quantization of the threshold voltage of the composite dielectric gate bipolar transistor. Step 4, obtaining the quantization of the threshold voltage of the composite dielectric gate bipolar transistor according to the final count value of the counter, and reading out the gray value of each pixel according to the quantization value.

8. A composite dielectric gate dual transistor readout circuit for implementing HDR based on a variable slope, characterized in that: The circuit includes a composite dielectric gate dual-transistor photosensitive detector, a slope-controllable ramp generating circuit, a clamping circuit, an integrating capacitor, a comparator circuit and a counter; wherein the slope-controllable ramp generating circuit is connected to the gate of the composite dielectric gate dual-transistor photosensitive detector, the source of the composite dielectric gate dual-transistor photosensitive detector is grounded, and the drain is connected to the output of the clamping circuit to keep the drain voltage constant; the drain of the composite dielectric gate dual-transistor photosensitive detector is also connected to the integrating capacitor to convert the current signal into a voltage signal connected to the positive input of the comparator circuit, and the negative input of the comparator circuit is connected to a reference voltage Vrefcomp; the counter is connected to the output of the comparator circuit.

9. The circuit according to claim 8, characterized in that The slope generating circuit with controllable slope includes a transconductance operational amplifier, an integrating capacitor and a current mirror circuit, wherein the upper and lower plates of the integrating capacitor are respectively connected to the negative input terminal and the output terminal of the transconductance operational amplifier, and the positive input terminal of the transconductance operational amplifier is connected to the reference voltage Vhold; the current mirror circuit is used to generate an integrating current, and the current mirror circuit is connected to the negative input terminal of the transconductance operational amplifier through a switch.

10. The circuit according to claim 9, characterized in that The current mirror circuit comprises N current mirrors, each of which is connected to a switch, and the switch is controlled by a digital circuit to adjust the magnitude of the integral current; the magnitudes of the currents generated by the N current mirrors are respectively 2 0 I.2 1 I.2 2 I, ..., 2 N-1 I, I represents unit current.

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