Image sensor, control method, device, electronic device, and storage medium thereof

Abstract

The present application discloses an image sensor and its control method, device, electronic device, and storage medium. The image sensor includes: a pixel chip, the pixel chip including a pixel array, the pixel array including N pixel circuits and N registers, the N registers corresponding one-to-one to the N pixel circuits, the registers connected to the corresponding pixel circuits, the pixel circuits including single-photon avalanche transistors, where N is a positive integer; a signal transmission structure, the first end of the signal transmission structure connected to the pixel chip, the first end of the signal transmission structure located on the periphery of the pixel array, the signal transmission structure including X first transmission structures and Y second transmission structures; and a logic chip, the logic chip provided with a column scanning circuit and a row clock control circuit, the column scanning circuit connected to X column registers via X first transmission structures, and the row clock control circuit connected to Y row pixel circuits via Y second transmission structures.

Description

Technical Field

[0001] The present application belongs to the technical field of image processors, and specifically relates to an image sensor and a control method, device, electronic device, and storage medium thereof. Background Art

[0002] SPAD (Single-Photon Avalanche Diode) is currently widely used in dToF (direct Time-of-Flight) image sensor chips. In recent years, researchers have begun to study the use of SPAD to replace PPD (Pinned Photodiode) as the pixel photosensitive element of ordinary visible light RGB (Red, Green, Blue) camera CIS (Contact Image Sensor).

[0003] The pixel circuit architecture of the CMOS (complementary metal-oxide-semiconductor) single-photon image sensor based on SPAD devices has undergone significant changes compared to the current mainstream CMOS image sensor based on PPD pixels.

[0004] In the related art, the pixels of CMOS single-photon image sensors based on SPAD pixels have the problem of excessively large chip stacking size due to complex circuit structures and numerous components. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide an image sensor and its control method, device, electronic device and storage medium, which solve the problem of chip stacking size being too large.

[0006] In a first aspect, embodiments of the present application provide an image sensor, comprising: a pixel chip, the pixel chip including a pixel array, the pixel array including N pixel circuits and N registers, the N registers corresponding one-to-one to the N pixel circuits, the registers connected to corresponding pixel circuits, the pixel circuits including single-photon avalanche transistors, where N is a positive integer; a signal transmission structure, a first end of the signal transmission structure connected to the pixel chip, the first end of the signal transmission structure being located on a peripheral side of the pixel array, the signal transmission structure including X first transmission structures and Y second transmission structures, the X first transmission structures corresponding one-to-one to X columns of pixel circuits in the pixel array, the Y second transmission structures corresponding one-to-one to Y rows of pixel circuits in the pixel array, X and Y being positive integers, and X×Y=N; and a logic chip, disposed opposite the pixel chip, the logic chip connected to the second end of the signal transmission structure, the logic chip provided with a column scanning circuit and a row clock control circuit, the column scanning circuit connected to the X column registers via the X first transmission structures, and the row clock control circuit connected to the Y row of pixel circuits via the Y second transmission structures.

[0007] In a second aspect, embodiments of the present application provide a control method, applied to the above-mentioned image sensor, the control method comprising: a row clock control circuit in a logic chip transmits a row clock signal to Y rows of pixel circuits via Y second transmission structures; the Y rows of pixel circuits in a pixel array, in response to the row clock signal, synchronously expose during a first time period, and store image signals obtained by the exposure in corresponding registers during a second time period; and X column registers transmit the image signals to a column scanning circuit in the logic chip via X first transmission structures during a third time period.

[0008] In a third aspect, an embodiment of the present application provides a control device for use with the above-mentioned image sensor, the control device comprising: a transmission module configured to cause a row clock control circuit in a logic chip to transmit a row clock signal to Y rows of pixel circuits via Y second transmission structures; an exposure module configured to cause Y rows of pixel circuits in a pixel array to be synchronously exposed within a first time period in response to the row clock signal; a storage module configured to store image signals obtained by exposure in corresponding registers within a second time period; and a transmission module configured to cause X column registers to transmit image signals to a column scanning circuit in the logic chip via X first transmission structures within a third time period.

[0009] In a fourth aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method of the second aspect are implemented.

[0010] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method of the second aspect are implemented.

[0011] In a sixth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the steps of the method of the second aspect.

[0012] In a seventh aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the method of the second aspect.

[0013] In the embodiment of the present application, by providing only the pixel array and the registers corresponding to each pixel circuit in the pixel chip, and providing logic circuits such as the column scanning circuit and the row clock control circuit in the logic chip, there is no need to provide additional logic circuits in the pixel chip, and there is no need to provide pixel circuits on the logic chip. As a result, the stack size of the logic chip and the pixel chip is consistent, thereby reducing the size of the overall architecture of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 shows a schematic structural diagram of an image sensor provided in some embodiments of the present application;

[0015] Figure 2 shows a schematic structural diagram of a pixel chip provided in some embodiments of the present application;

[0016] Figure 3 shows a schematic structural diagram of a logic chip provided in some embodiments of the present application;

[0017] Figure 4 FIG2 shows a time diagram of an operating mode of an image sensor provided in some embodiments of the present application;

[0018] Figure 5 shows a flow chart of a control method provided in some embodiments of the present application;

[0019] Figure 6 shows an operating timing diagram of an image sensor provided in some embodiments of the present application;

[0020] Figure 7 One of the register working period diagrams provided in some embodiments of the present application is shown;

[0021] Figure 8 FIG2 shows a second schematic diagram of a register working period provided in some embodiments of the present application;

[0022] Figure 9 shows a schematic diagram of the arrangement of sub-pixel arrays provided in some embodiments of the present application;

[0023] Figure 10 FIG3 shows a third schematic diagram of a register working period provided in some embodiments of the present application;

[0024] Figure 11 shows a schematic block diagram of a control device provided in some embodiments of the present application;

[0025] Figure 12 shows a structural block diagram of an electronic device according to an embodiment of the present application;

[0026] Figure 13 A schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application is shown.

[0027] Figures 1 to 3 The reference numerals in the figures are as follows:

[0028] 100 image sensor, 110 pixel chip, 112 pixel array, 1122 pixel circuit, 1124 register, 120 signal transmission structure, 122 first transmission structure, 124 second transmission structure, 126 third transmission structure, 130 logic chip, 131 column scanning circuit, 132 row clock control circuit, 133 column clock control circuit, 134 image signal processing circuit, 135 port circuit, 136 auxiliary circuit, 137 communication pin. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0030] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0031] The following is combined with Figures 1 to 13 , the image sensor and its control method, device, electronic device and storage medium provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0032] In some embodiments of the present application, an image sensor is provided. Figure 1 shows a schematic structural diagram of an image sensor provided in some embodiments of the present application, Figure 2 shows a schematic structural diagram of a pixel chip provided in some embodiments of the present application, Figure 3 Schematic diagram of the structure of the logic chip provided in some embodiments of the present application is shown in FIG. Figure 1 、 Figure 2 and Figure 3 As shown, the image sensor 100 includes: a pixel chip 110, the pixel chip 110 includes a pixel array 112, the pixel array 112 includes N pixel circuits 1122 and N registers 1124, the N registers 1124 correspond to the N pixel circuits 1122 one by one, the registers 1124 are connected to the corresponding pixel circuits 1122, the pixel circuits 1122 include single photon avalanche transistors, N is a positive integer; a signal transmission structure 120, a first end of the signal transmission structure 120 is connected to the pixel chip 110, the first end of the signal transmission structure 120 is located on the peripheral side of the pixel array 112, and the signal transmission structure 120 includes X first transmission structures 122 and Y second transmission structures 124. 4. X first transmission structures 122 correspond one-to-one to X columns of pixel circuits 1122 in the pixel array 112, and Y second transmission structures 124 correspond one-to-one to Y rows of pixel circuits 1122 in the pixel array 112, where X and Y are both positive integers and X×Y=N. A logic chip 130 is disposed opposite the pixel chip 110 and connected to the second end of the signal transmission structure 120. The logic chip 130 is provided with a column scanning circuit 131 and a row clock control circuit 132. The column scanning circuit 131 is connected to the X column register 1124 via the X first transmission structures 122, and the row clock control circuit 132 is connected to the Y row of pixel circuits 1122 via the Y second transmission structures 124.

[0033] In an embodiment of the present application, the image sensor 100 includes a pixel chip 110, a logic chip 130, and a signal transmission structure 120 arranged between the pixel chip 110 and the logic chip 130, and the first end and the second end of the signal transmission structure 120 are respectively connected to the pixel chip 110 and the logic chip 130.

[0034] Pixel chip 110 includes a pixel array 112, which includes N pixel circuits 1122 and N registers 1124. Each register 1124 is connected to each pixel circuit 1122. Pixel circuits 1122 are single-photon avalanche transistor (SPAT) circuits. After exposure, pixel circuits 1122 store image signals in corresponding registers 1124. Logic chip 130 is stacked below pixel chip 110 and includes a column scanning circuit 131 and a row clock control circuit 132. Column scanning circuit 131 is used to read image signals stored in N registers 1124 in pixel chip 110. Row clock control circuit 132 is used to transmit a row clock signal to pixel chip 110. This row clock signal is used to provide timing and control for pixel circuits 1122 in pixel array 112.

[0035] For example, the row clock control circuit 132 sends a row clock signal to the pixel chip 110. The pixel chip 110 can control the pixel array 112 to expose in response to the row clock signal and control the register 1124 to transmit the image signal obtained by exposure according to the first clock information in the row clock signal.

[0036] In the embodiment of the present application, the signal transmission structure 120 includes a first transmission structure 122 and a second transmission structure 124. The first transmission structure 122 is used to transmit the image signal stored in the register 1124 to the logic chip 130. The second transmission structure 124 is used to transmit the row clock signal of the row clock control circuit 132 in the logic chip 130 to the pixel chip 110.

[0037] Specifically, the number of pixel circuits 1122 in the pixel array 112 is N, and the N pixel circuits 1122 are arranged in a Y×X arrangement, i.e., the N pixel circuits 1122 include X columns of pixel circuits 1122 and Y rows of pixel circuits 1122. The number of first transmission structures 122 in the signal transmission structure 120 is X, and each first transmission structure 122 corresponds to a single column of pixel circuits 1122. That is, each first transmission structure 122 is used to transmit image signals from a column of registers 1124 corresponding to a column of pixel circuits 1122. The number of second transmission structures 124 in the signal transmission structure 120 is Y, and each second transmission structure 124 corresponds to a single row of pixel circuits 1122. That is, each second transmission structure 124 is used to transmit a row clock signal to a corresponding row of pixel circuits 1122, thereby controlling the exposure of a row of pixel circuits 1122 and the transmission of image signals from a row of registers 1124.

[0038] like Figure 2 and Figure 3As shown, illustratively, the first end of the signal transmission structure 120 is spaced apart from the pixel array 112, and the first end of the signal transmission structure 120 is located on the periphery of the pixel array 112, and the first end of the signal transmission structure 120 surrounds at least a portion of the pixel array 112. The second end of the signal transmission structure 120 is connected to the periphery of the logic chip 130.

[0039] It should be noted that in the related art, there is an architecture in which transmission circuits such as registers 1124 are set on other chips outside the pixel chip 110, making the pixel chip 110 smaller, but circuits such as registers 1124 are set on other chips, causing the other chips to be larger. There is an inconsistency in the stack sizes of the individual chips in the image sensor 100 structure in which the pixel chip 110 and other chips are stacked, resulting in a larger volume of the image sensor 100 architecture.

[0040] In the embodiment of the present application, by providing only the pixel array 112 and the register 1124 corresponding to each pixel circuit 1122 in the pixel chip 110, and providing logic circuits such as the column scanning circuit 131 and the row clock control circuit 132 in the logic chip 130, there is no need to provide additional logic circuits in the pixel chip 110, and there is no need to provide the pixel circuit 1122 on the logic chip 130. As a result, the stack size of the logic chip 130 and the pixel chip 110 is consistent, thereby reducing the size of the overall architecture of the image sensor 100.

[0041] In some embodiments of the present application, the Y registers 1124 in each column of registers 1124 are respectively connected to corresponding first transmission structures 122 .

[0042] In the embodiment of the present application, the pixel array 112 includes Y rows and X columns of pixel circuits 1122, and each pixel circuit 1122 is provided with a corresponding register 1124. Therefore, the registers 1124 are also arranged in Y rows and X columns. There are X registers 1124 in each row of registers 1124, and Y registers 1124 in each column of registers 1124.

[0043] In the embodiment of the present application, the Y registers 1124 in each column of registers 1124 are connected in parallel to the first end of the first transmission structure 122. Specifically, the first transmission structures 122 in the signal transmission structure 120 are used to transmit image signals in the registers 1124. The number of first transmission structures 122 is set to X, and the first end of each first transmission structure 122 is corresponding to each column of pixel circuits 1122. Each first transmission structure 122 is connected one by one to the registers 1124 corresponding to a single column of pixel circuits 1122. That is, the Y registers 1124 in a column are connected in parallel to the first end of the first transmission structure 122. When the X first transmission structures 122 synchronously transmit image signals, the image signals in a row of registers 1124 can be transmitted to the logic chip 130 at a time.

[0044] It should be noted that the number of the first transmission structures 122 may be an integer multiple of X. When there are 2X first transmission structures 122 , the image signals in two rows of registers 1124 can be transmitted each time through the 2X transmission structures.

[0045] Exemplarily, after pixel array 112 is exposed and obtains an image signal, the image signal is stored in register 1124 corresponding to each pixel circuit 1122. At this point, image signals are stored in each of Y×X registers 1124, and each register 1124 in a column of registers 1124 is connected in parallel to the first end of the corresponding first transmission structure 122. After pixel chip 110 receives a row clock signal, it transmits the image signal for row 1 to column scanning circuit 131 at time 1, transmits the image signal for row 2 to column scanning circuit 131 at time 2, and so on, transmits the image signal for row Y to column scanning circuit 131 at time y.

[0046] In an embodiment of the present application, by connecting Y registers 1124 in each column of registers 1124 in parallel on the first transmission structure 122, the first transmission structure 122 can transmit the image signals in one row of registers 1124 at a time, thereby improving the transmission efficiency of the image signals between the pixel chip 110 and the logic chip 130.

[0047] In some embodiments of the present application, the Y registers 1124 in each column of registers 1124 are connected in series, and the Y registers 1124 are connected to the first transmission structure 122 .

[0048] In the embodiment of the present application, the pixel array 112 includes Y rows and X columns of pixel circuits 1122, and each pixel circuit 1122 is provided with a corresponding register 1124. Therefore, the registers 1124 are also arranged in Y rows and X columns. There are X registers 1124 in each row of registers 1124, and Y registers 1124 in each column of registers 1124.

[0049] In the embodiment of the present application, the Y registers 1124 in each column of registers 1124 are connected in series, and the Y serially connected registers 1124 are connected to the first end of the first transmission structure 122. Specifically, the first transmission structures 122 in the signal transmission structure 120 are used to transmit image signals in the registers 1124. The number of first transmission structures 122 is set to X, and the first end of each first transmission structure 122 is corresponding to each column of pixel circuits 1122. Each first transmission structure 122 is connected to the nearest register 1124 in a single column of pixel circuits 1122. Since the registers 1124 corresponding to a column of pixel circuits 1122 are connected in series, that is, the Y registers 1124 in a column are connected in series to the first end of the first transmission structure 122, the first transmission structure 122 can transmit the image signals in the registers 1124 in a column. When the X first transmission structures 122 synchronously transmit image signals, at each moment, the image signals flow through the Y registers 1124 connected in series to the first transmission structures 122 until all image signals are transmitted to the column scanning circuit 131 of the logic chip 130 through the first transmission structures 122 .

[0050] Exemplarily, after the pixel array 112 is exposed and obtains an image signal, the image signal is stored in the register 1124 corresponding to each pixel circuit 1122. At this point, each of the Y×X registers 1124 stores an image signal, and each register 1124 in a column of registers 1124 is connected in parallel to the first end of the corresponding first transmission structure 122. After the pixel chip 110 receives the row clock signal, at time 1, the image signal of the first row register 1124 is transmitted to the column scanning circuit 131, and the image signal of the second row register 1124 is transmitted to the image signal of the first row, ..., the image signal of the Yth row register 1124 is transmitted to the Y-1th row register 1124. The above steps are repeated at the next time until all image signals are transmitted to the logic chip 130 via the first transmission structure 122.

[0051] In the embodiment of the present application, by connecting Y registers 1124 in each column of registers 1124 in series on the first transmission structure 122, during the image signal transmission process, the image signal can flow in the series-connected registers 1124, so that the first transmission structure 122 can transmit the image signal in one row of registers 1124 at a time, thereby improving the transmission efficiency of the image signal between the pixel chip 110 and the logic chip 130.

[0052] like Figure 1 and Figure 3 As shown, in some embodiments of the present application, the signal transmission structure 120 further includes X third transmission structures 126 , and the X third transmission structures 126 correspond one-to-one to the X columns of pixel circuits 1122 in the pixel array 112 ;

[0053] The logic chip 130 further includes a column clock control circuit 133 connected to the X third transmission structures 126 . The column clock control circuit 133 is connected to the X column registers 1124 in the pixel array 112 through the X third transmission structures 126 .

[0054] In the embodiment of the present application, the signal transmission structure 120 further includes X third transmission structures 126, and the logic chip 130 further includes a column clock control circuit 133. The column clock control circuit 133 can transmit a column clock signal to the logic chip 130 through the third transmission structure 126, and perform timing and control on the logic chip 130 through the column clock signal. The third transmission structure 126 is used to transmit the column clock signal from the column clock control circuit 133 to the pixel chip 110.

[0055] Specifically, the number of pixel circuits 1122 in the pixel array 112 is N, and the N pixel circuits 1122 are arranged in a Y×X manner, that is, the N pixel circuits 1122 include X columns of pixel circuits 1122 and Y rows of pixel circuits 1122. The number of third transmission structures 126 in the signal transmission structure 120 is set to X, and each third transmission structure 126 corresponds to a single column of pixel circuits 1122. That is, each third transmission structure 126 is used to transmit a column clock signal to a column register 1124.

[0056] For example, if a column clock control circuit 133 is provided on the logic chip 130, the column clock control circuit 133 controls the operation of each register 1124 and the transmission of image signals. After all pixel circuits 1122 on all rows have completed signal reading and buffering, all rows synchronously enter a signal transmission period. The signal transmission period is divided into multiple column signal transmission periods. If the pixel array 112 has X columns and the register 1124 is a shift register 1124, the signal transmission period is divided into X column signal transmission periods, where the X signal transmission periods include: C1, C2, C3, ..., CX. During each column signal transmission period, a column of pixel circuits 1122, driven by the column clock and control circuit module, shifts and transmits the output registered image signal to the column scanning circuit 131 on the logic chip 130 until the image signals registered in all registers on that column are transmitted out of the pixel array 112 and to the column scanning circuit 131 on the logic chip 130.

[0057] In the embodiment of the present application, a column clock control circuit 133 is provided in the logic chip 130, and a third transmission structure 126 for transmitting the column clock signal of the column clock control circuit 133 is provided in the signal transmission structure. The number of the third transmission structures 126 is set to be the same as the number of columns of the pixel array 112. Therefore, the column clock signal output by the logic chip 130 can be synchronously transmitted to each column register 1124, thereby improving the signal transmission efficiency between the logic chip 130 and the pixel chip 110.

[0058] like Figure 3 As shown, in some embodiments of the present application, the logic chip 130 further includes: an image signal processing circuit 134, a first end of the image signal processing circuit 134 is connected to the column scanning circuit 131; and a port circuit 135, the port circuit 135 is connected to a second end of the image signal processing circuit 134.

[0059] In an embodiment of the present application, the logic chip 130 further includes an image signal processing circuit 134 and a port circuit 135. The image signal processing circuit 134 is arranged between the column scanning circuit 131 and the port circuit 135. The image signal processing circuit 134 can process the image signal transmitted from the pixel chip 110 to the logic chip 130.

[0060] Specifically, the column scanning circuit 131 in the logic chip 130 is connected to the register 1124 in the pixel chip 110 through the signal transmission structure 120. The column scanning circuit 131 is also connected to the image signal processing circuit 134 in the logic chip 130. After acquiring the image signal from the pixel chip 110, the column scanning circuit 131 can transmit the image signal to the image signal processing circuit 134 for processing. The processed image signal is transmitted to the outside of the logic chip 130 through the port circuit 135.

[0061] Figure 4 FIG. 1 shows a time diagram of an operating mode of the image sensor 100 provided in some embodiments of the present application, such as FIG. Figure 4As shown, a frame time includes K subframes, each of which is independent of each other. The length and number of subframes can be adjusted according to different applications. A frame time begins with the start of the first subframe, and after the completion of the Kth subframe, the signal processing period begins. That is, the image signal is processed by the image signal processing circuit 134. When the image signal processing is completed, the frame is considered complete and the next frame time begins. All subframes of each row of pixel circuits 1122 within each frame time are completely aligned in time sequence. Therefore, the pixel circuits 1122 on all rows have the same number of subframes and the subframe completion time is consistent. The image signal processing period of each row of pixel circuits 1122 is consistent in length. The signal processing period mainly takes the time for the image signal processing circuit 134, auxiliary circuit 136, and port circuit 135 at the logic layer to perform the final image signal processing within the frame, reset the circuit, and prepare for the start of the next frame. All pixel circuits 1122 in the pixel chip 110 can be effectively operated and read within one frame time. At the same time, the operation mode similar to the global shutter can effectively eliminate the jello effect of moving objects caused by the rolling shutter of the traditional image sensor 100.

[0062] In an embodiment of the present application, an image signal processing circuit 134 and a port circuit 135 are provided in the logic chip 130 , so that the logic chip 130 can process the image signal transmitted by the pixel chip 110 through the image signal processing circuit 134 and transmit the processed image signal to the outside through the port circuit 135 .

[0063] In some embodiments of the present application, the signal transmission structure 120 includes at least one of the following: copper-copper bonding, and through-silicon via.

[0064] In the embodiment of the present application, the signal transmission structure 120 can be selected from copper-copper bonding (Cu-Cu bonding), TSV (Trans-Silicon Via), or a combination thereof.

[0065] In some embodiments of the present application, the logic chip 130 further includes a communication pin 137 (I / O pin), and the signal input outside the chip and the signal output inside the chip are both carried out through the communication pin 137 on the logic chip 130 .

[0066] In some embodiments of the present application, a control method is provided, which is applied to the image sensor in any of the above embodiments. Figure 5 1 shows a flow chart of the control method provided in some embodiments of the present application, such as Figure 5 As shown, the control method includes:

[0067] Step 502: The row clock control circuit in the logic chip transmits a row clock signal to Y rows of pixel circuits via Y second transmission structures.

[0068] In an embodiment of the present application, the image sensor includes a pixel chip, a logic chip, and a signal transmission structure arranged between the pixel chip and the logic chip, and the signal transmission structure transmits signals between the logic chip and the pixel chip. The pixel chip includes a pixel array, and the pixel array includes N pixel circuits and N registers. Each register is connected to each pixel circuit. The pixel circuit is a pixel circuit of a single-photon avalanche transistor. After the pixel circuit is exposed, the image signal is stored in the corresponding register. The logic chip is stacked below the pixel chip. The logic chip includes a column scanning circuit and a row clock control circuit. The column scanning circuit is used to read the image signal stored in the N registers in the pixel chip. The row clock control circuit is used to transmit a row clock signal to the pixel chip. The row clock signal can be used to time and control the pixel circuits in the pixel array.

[0069] Step 504: the pixel circuits in the Y row in the pixel array respond to the row clock signal, perform synchronous exposure in a first period, and store the image signals obtained by exposure in corresponding registers in a second period;

[0070] In the embodiment of the present application, after receiving the row clock signal, the pixel circuits in the Y row in the pixel array perform exposure in response to the row clock signal within a first period of time. After the exposure is completed, the image signals obtained by the exposure of the pixel circuits are stored in corresponding registers within a second period of time.

[0071] Step 506 : The X column registers transmit the image signal to the column scanning circuit in the logic chip through the X first transmission structures during the third period.

[0072] In an embodiment of the present application, during a third time period, registers corresponding to X columns of pixel circuits transmit image signals to a column scanning circuit of a logic chip via X first transmission structures. The number of pixel circuits in the pixel array is N, and the N pixel circuits are arranged in a Y×X arrangement, i.e., the N pixel circuits include X columns of pixel circuits and Y rows of pixel circuits. The number of first transmission structures in the signal transmission structure is set to X, and each first transmission structure corresponds to a single column of pixel circuits. That is, each first transmission structure is used to transmit image signals from a column of registers corresponding to a column of pixel circuits.

[0073] Specifically, the first period is the pixel circuit's exposure period, the second period is the register's signal reading period, and the third period is the signal transmission period. During the first period, the pixel circuit performs exposure to acquire an image signal. During the second period, the pixel circuit transfers the exposed image signal to the register for storage. During the third period, the register transmits the image signal to the column scanning circuit in the logic chip via the first transmission structure.

[0074] Figure 6 FIG. 4 shows an operation timing diagram of an image sensor provided in some embodiments of the present application, such as Figure 6 As shown, each subframe includes a pixel circuit exposure period, i.e., a first period. This exposure period is followed by a register operating period, which includes a second period during which the image signal is transferred to the register for storage, and a third period during which the image signal is transferred to the column scanning circuit in the logic chip.

[0075] In the embodiments of the present application, by providing only the pixel array and corresponding registers for each pixel circuit in the pixel chip, and providing logic circuits such as the column scanning circuit and row clock control circuit in the logic chip, no additional logic circuits are required in the pixel chip, and no pixel circuits are required on the logic chip. This allows the logic chip and pixel chip stacks to be the same size, reducing the overall size of the image sensor architecture. Furthermore, each pixel circuit starts and ends exposure synchronously within each frame. This global shutter-like operation prevents the image sensor from experiencing the rolling shutter effect typical of moving objects when capturing images, improving the image sensor's capture quality.

[0076] In some embodiments of the present application, the Y registers in each column of registers are respectively connected to corresponding first transmission structures;

[0077] During a third period, the X columns of pixel circuits in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures, including:

[0078] The Y row registers sequentially transmit the image signals to the column scanning circuit in Y second sub-periods of the third period, wherein each second sub-period corresponds to the transmission of the image signals in a row of registers.

[0079] In an embodiment of the present application, the Y registers in each column of registers are connected in parallel to the first end of the first transmission structure. The first transmission structure in the signal transmission structure is used to transmit image signals in the registers. The number of first transmission structures is set to X, and the first end of each first transmission structure is set to correspond to each column of pixel circuits. Each first transmission structure is connected one by one to the registers corresponding to a single column of pixel circuits, that is, the Y registers in a column are connected in parallel to the first end of the first transmission structure. When the X first transmission structures synchronously transmit image signals, the image signals in a row of registers can be transmitted to the logic chip at a time.

[0080] Specifically, the third period includes Y second sub-periods, each of which is used to transmit the image signal from a row of registers to the column scanning circuit of the logic chip. Before the pixel circuit begins exposure, the pixel chip receives a first clock signal from the row clock control circuit. The first clock signal is used to determine the first period, the second period, and the third period, as well as the Y second periods within the third period. After the pixel circuit exposure is completed and the image signal obtained by the exposure is stored in the corresponding register, the image signal from the Y registers in each column of registers is sequentially transmitted to the column scanning circuit of the logic chip according to the Y second sub-periods in the third period.

[0081] It should be noted that the number of the first transmission structures may be an integer multiple of X. When the number of the first transmission structures is 2X, the image signals in two rows of registers can be transmitted each time through the 2X transmission structures.

[0082] Exemplarily, after the pixel array is exposed and obtains an image signal, the image signal is stored in the register corresponding to each pixel circuit. At this point, each of the Y×X registers stores an image signal, and each register in a column of registers is connected in parallel to the first end of the corresponding first transmission structure. After the pixel chip receives the row clock signal, the image signal for row 1 is transmitted to the column scanning circuit at time 1, the image signal for row 2 is transmitted to the column scanning circuit at time 2, and so on. At time y, the image signal for row Y is transmitted to the column scanning circuit.

[0083] In an embodiment of the present application, by connecting Y registers in each column of registers in parallel on the first transmission structure, the first transmission structure can transmit the image signals in one row of registers at a time, thereby improving the transmission efficiency of the image signals between the pixel chip and the logic chip.

[0084] In some embodiments of the present application, the Y registers in each column of registers are connected in series, and the Y registers are connected to the first transmission structure;

[0085] During a third period, the X columns of pixel circuits in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures, including:

[0086] During the M second sub-periods within the third period, each row of registers receives the image signal transmitted by the previous row of registers and transmits the image signal to the next row of registers until all the image signals in the Y row of registers are transmitted to the column scanning circuit, where M is a positive integer and M=Y-1.

[0087] In an embodiment of the present application, the Y registers in each column of registers are connected in series, and the Y registers connected in series are connected to the first end of a first transmission structure. Specifically, the first transmission structure in the signal transmission structure is used to transmit image signals in the registers. The number of first transmission structures is set to X, and the first end of each first transmission structure is set to correspond to each column of pixel circuits. Each first transmission structure is connected to the nearest register in a single column of pixel circuits. Since the registers corresponding to a column of pixel circuits are connected in series, that is, the Y registers in a column are connected in series to the first end of the first transmission structure, the first transmission structure is able to transmit the image signals in the column of registers. When the X first transmission structures synchronously transmit image signals, at each moment, the image signal flows from the Y registers in series to the first transmission structure until all image signals are transmitted to the column scanning circuit of the logic chip through the first transmission structure.

[0088] In an embodiment of the present application, the third time period includes M second sub-time periods, and the second sub-time period is used to transmit the image signal in the current row register to the next row register. The register closest to the first transmission structure transmits the stored image signal to the column scanning circuit of the logic chip.

[0089] Specifically, after the pixel array is exposed and obtains an image signal, the image signal is stored in the register corresponding to each pixel circuit. At this point, each of the Y×X registers stores an image signal, and each register in a column of registers is connected in parallel to the first end of the corresponding first transmission structure. After the pixel chip receives the row clock signal, at time 1, the image signal from the first row register is transmitted to the column scanning circuit, and the image signal from the second row register is transmitted to the image signal of the first row, ... The image signal from the Yth row register is transmitted to the Y-1th row register. The above steps are repeated at the next time until all image signals are transmitted to the logic chip via the first transmission structure.

[0090] Figure 7 FIG. 1 shows one of the register working period diagrams provided in some embodiments of the present application, such as Figure 7As shown, during the signal transmission period, the image signal generated by the pixel circuit in the first row will be shifted one by one to the register in the next column of pixels. After M shifts, it is finally transferred out of the pixel chip and reaches the column scanning circuit on the logic chip. Similarly, for the image signal generated by the pixel circuit in the second row, it needs to be shifted M-1 times before it is finally transferred out of the pixel chip and reaches the column scanning circuit on the logic chip. For the image signal generated by the pixel circuit in the Yth row, it only needs to be shifted once to be transferred out of the pixel chip. It should be noted that after the image signal generated by each row of pixel circuits is transferred out of the pixel chip and reaches the column scanning circuit on the logic chip, the column scanning circuit immediately performs a column scanning operation to scan and output the image signal generated by the pixel circuit in this row to the image signal processing circuit for subsequent processing. Only after this step is completed will the next round of pixel signal shifting be performed. Among them, the image signal can be a digital signal.

[0091] In an embodiment of the present application, by connecting Y registers in each column of registers in series on the first transmission structure, during the image signal transmission process, the image signal can flow in the series-connected registers, so that the first transmission structure can transmit the image signal in one row of registers at a time, thereby improving the transmission efficiency of the image signal between the pixel chip and the logic chip.

[0092] In some embodiments of the present application, the signal transmission structure further includes X third transmission structures, and the X third transmission structures correspond one-to-one to X columns of pixel circuits in the pixel array; the logic chip further includes: a column clock control circuit connected to the X third transmission structures, and the column clock control circuit is connected to X columns of registers in the pixel array through the X third transmission structures;

[0093] During a third period, the X columns of pixel circuits in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures, including:

[0094] The column clock control circuit transmits a column clock signal to N registers to determine X third sub-periods within the third period;

[0095] The X column registers transmit the image signal to the column scanning circuit in sequence in X third sub-periods in response to the column clock signal, wherein each third sub-period corresponds to the transmission of the image signal in one column register.

[0096] In an embodiment of the present application, the signal transmission structure also includes X third transmission structures, and the logic chip also includes a column clock control circuit. The column clock control circuit can transmit a column clock signal to the logic chip through the third transmission structure, and perform timing and control on the logic chip through the column clock signal. The third transmission structure is used to transmit the column clock signal from the column clock control circuit to the pixel chip.

[0097] Specifically, the number of pixel circuits in the pixel array is N, and the N pixel circuits are arranged in a Y×X manner, i.e., the N pixel circuits include X columns of pixel circuits and Y rows of pixel circuits. The number of third transmission structures in the signal transmission structure is set to X, and each third transmission structure corresponds to a single column of pixel circuits. i.e., each third transmission structure is used to transmit a column clock signal to a column register.

[0098] In the embodiment of the present application, the third period includes X third sub-periods, and each third sub-period is a signal transmission period for a column of registers.

[0099] Figure 8 FIG2 shows a second schematic diagram of a register working period provided in some embodiments of the present application, such as Figure 8 As shown, when a column clock control circuit is provided on the logic chip, the column clock control circuit controls the operation of each register and the transmission of image signals. When all pixel circuits on all rows have completed signal reading and caching, all rows synchronously enter the signal transmission period. The signal transmission period is divided into multiple column signal transmission periods. If the pixel array has X columns and the register is a shift register, the signal transmission period is divided into X column signal transmission periods, and the X signal transmission periods include: C1, C2, C3...CX. During each column signal transmission period, a column of pixel circuits, driven by the column clock and control circuit module, shifts and transmits the output registered image signal to the column scanning circuit on the logic chip until the image signals registered by all registers on this column are transmitted outside the pixel array to the column scanning circuit on the logic chip.

[0100] In an embodiment of the present application, a column clock control circuit is provided in the logic chip, and a third transmission structure for transmitting the column clock signal of the column clock control circuit is provided in the signal transmission structure. The number of the third transmission structures is set to be the same as the number of columns of the pixel array. This enables the column clock signal output by the logic chip to be synchronously transmitted to each column register, thereby improving the signal transmission efficiency between the logic chip and the pixel chip.

[0101] In some embodiments of the present application, the pixel circuit includes a sub-pixel array, the register corresponding to the pixel circuit includes a sub-register, each sub-pixel in the sub-pixel array is correspondingly provided with a sub-register, and the sub-pixel array includes Q columns of sub-pixels, where Q is a positive integer;

[0102] During a third period, the X columns of pixel circuits in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures, including:

[0103] The column clock control circuit transmits a third clock signal to the N registers to determine Z fourth sub-periods within the third period, where Z=X×Q;

[0104] The Q column sub-registers in the X column register respond to the third clock signal and sequentially transmit the image signal to the column scanning circuit in Z fourth sub-periods, wherein each fourth sub-period corresponds to the transmission of the image signal in one column sub-register.

[0105] In an embodiment of the present application, the pixel circuit is an all-in-one pixel circuit, which includes a sub-pixel array, and each sub-pixel array includes multiple sub-pixels. When the pixel circuit is an all-in-one pixel circuit, a sub-register is set corresponding to each sub-pixel. In the process of transmitting image signals by the all-in-one pixel circuit, it is necessary to combine the arrangement of the sub-pixel array in the all-in-one pixel circuit. Based on the number of columns of the sub-pixel array, the number of fourth time periods within the third time period is determined, and each fourth time period is used to transmit the image signal in the sub-register corresponding to each sub-pixel in the sub-pixel array to the logic chip.

[0106] Specifically, there are X columns of pixel circuits, and each pixel circuit includes Q columns of sub-pixels, so the third period of signal transmission needs to be divided into X×Q segments.

[0107] Figure 9 Schematic diagrams of the arrangement of sub-pixel arrays provided in some embodiments of the present application are shown. Figure 9 As shown, the sub-pixel array includes 4 sub-pixels, which are SPAD1, SPAD2, SPAD3 and SPAD4, and the arrangement of the 4 sub-pixels is 2×2.

[0108] Figure 10 FIG3 shows a third schematic diagram of a register working period provided in some embodiments of the present application, such as Figure 9 and Figure 10 As shown, for a sub-pixel array comprising four sub-pixels, the third signal transmission period is divided into 2X column signal transmission periods, including C11, C12, C21…CX1, CX2. During each column signal transmission period, a column of sub-pixels, driven by the column clock and control circuit module, shifts and transmits the output registered image signals to the column scanning circuit module on the logic chip until the digital signals registered in the pixel circuit registers of all pixels in this column are transmitted out of the pixel chip to the column scanning circuit module on the logic chip.

[0109] In an embodiment of the present application, when the pixel circuit is an all-in-one pixel circuit, the number of third sub-periods included in the third period of signal transmission is set in combination with the number of columns of the sub-pixel array in the all-in-one pixel circuit, and the column clock control signal is transmitted through the column clock control circuit to control the pixel chip to transmit the image signal to the column scanning circuit in the logic chip, thereby further improving the signal transmission efficiency.

[0110] In some embodiments of the present application, the logic chip further includes: an image signal processing circuit, wherein a first terminal of the image signal processing circuit is connected to the column scanning circuit;

[0111] After the X columns of pixel circuits in the pixel array transmit the image signals to the column scanning circuit in the logic chip through the X first transmission structures during the third time period, the control method further includes:

[0112] The column scanning circuit transmits image signals of K subframes to the image signal processing circuit for processing, where the subframes include a first period, a second period, and a third period, and K is a positive integer.

[0113] In an embodiment of the present application, the logic chip also includes an image signal processing circuit and a port circuit. The image signal processing circuit is arranged between the column scanning circuit and the port circuit. The image signal processing circuit can process the image signal transmitted from the pixel chip to the logic chip to improve the imaging effect of the output image.

[0114] Specifically, the column scanning circuit in the logic chip is connected to the register in the pixel chip through a signal transmission structure. The column scanning circuit is also connected to the image signal processing circuit in the logic chip. After acquiring the image signal in the pixel chip, the column scanning circuit can transmit the image signal to the image signal processing circuit for processing. The processed image signal is transmitted to the outside of the logic chip through the port circuit.

[0115] like Figure 4 As shown, a frame time consists of K subframes, each independent of the others. The length and number of subframes can be adjusted based on different applications. A frame time begins with the start of the first subframe. After the Kth subframe completes, the signal processing period begins. This involves processing the image signal via the image signal processing circuit. Upon completion, the frame is considered complete and the next frame time begins. All subframes within each frame time for each row of pixel circuits are perfectly aligned in time sequence. Therefore, all rows of pixel circuits have the same number of subframes and the subframe completion times are consistent. The image signal processing period for each row of pixel circuits is consistent in duration. This period primarily involves the image signal processing circuitry, auxiliary circuitry, and port circuitry at the logic layer performing the final image signal processing within the frame, resetting the circuitry, and preparing for the next frame. This allows all pixel circuits in the pixel chip to operate and read effectively within a single frame timeframe. Furthermore, this global shutter-like operation effectively eliminates the rolling shutter effect of moving objects often seen in traditional image sensors.

[0116] The control method provided in the embodiment of the present application can be executed by a control device. In the embodiment of the present application, the control method provided in the embodiment of the present application is described by taking the control device executing the control method as an example.

[0117] In some embodiments of the present application, a control device is provided, which is applied to the image sensor in any of the above embodiments. Figure 11 Schematic block diagram of the control device provided in some embodiments of the present application is shown. Figure 11 As shown, the control device 1100 includes:

[0118] A transmission module 1102 is used for the row clock control circuit in the logic chip to transmit the row clock signal to Y rows of pixel circuits through Y second transmission structures;

[0119] An exposure module 1104 is configured to synchronously expose pixel circuits in a Y row in the pixel array in response to a row clock signal within a first time period;

[0120] The storage module 1106 is configured to store the image signal obtained by exposure in the second time period in a corresponding register;

[0121] The transmission module 1102 is configured to transmit the image signal from the X column registers to the column scanning circuit in the logic chip via the X first transmission structures during the third period.

[0122] In the embodiments of the present application, by providing only the pixel array and corresponding registers for each pixel circuit in the pixel chip, and providing logic circuits such as the column scanning circuit and row clock control circuit in the logic chip, no additional logic circuits are required in the pixel chip, and no pixel circuits are required on the logic chip. This allows the logic chip and pixel chip stacks to be the same size, reducing the overall size of the image sensor architecture. Furthermore, each pixel circuit starts and ends exposure synchronously within each frame. This global shutter-like operation prevents the image sensor from experiencing the rolling shutter effect typical of moving objects when capturing images, improving the image sensor's capture quality.

[0123] In some embodiments of the present application, the Y registers in each column of registers are respectively connected to corresponding first transmission structures;

[0124] The transmission module 1102 is configured to transmit the image signal from the Y row registers to the column scanning circuit in sequence in Y second sub-periods of the third period, wherein each second sub-period corresponds to the transmission of the image signal in one row of registers.

[0125] In an embodiment of the present application, by connecting Y registers in each column of registers in parallel on the first transmission structure, the first transmission structure can transmit the image signals in one row of registers at a time, thereby improving the transmission efficiency of the image signals between the pixel chip and the logic chip.

[0126] In some embodiments of the present application, the Y registers in each column of registers are connected in series, and the Y registers are connected to the first transmission structure;

[0127] The transmission module 1102 is used to receive the image signal transmitted by the register in the previous row in each row of registers and transmit the image signal to the register in the next row of registers in M ​​second sub-periods within the third time period, until all the image signals in the Y row of registers are transmitted to the column scanning circuit, where M is a positive integer and M=Y-1.

[0128] In an embodiment of the present application, by connecting Y registers in each column of registers in series on the first transmission structure, during the image signal transmission process, the image signal can flow in the series-connected registers, so that the first transmission structure can transmit the image signal in one row of registers at a time, thereby improving the transmission efficiency of the image signal between the pixel chip and the logic chip.

[0129] In some embodiments of the present application, the signal transmission structure further includes X third transmission structures, and the X third transmission structures correspond one-to-one to X columns of pixel circuits in the pixel array; the logic chip further includes: a column clock control circuit connected to the X third transmission structures, and the column clock control circuit is connected to X columns of registers in the pixel array through the X third transmission structures;

[0130] The control device 1100 further includes:

[0131] A determination module, configured for the column clock control circuit to transmit a column clock signal to N registers, and determine X third sub-periods within the third period;

[0132] The transmission module 1102 is configured to transmit the image signal to the column scanning circuit in X third sub-periods in response to the column clock signal from the X column registers, wherein each third sub-period corresponds to the transmission of the image signal in one column register.

[0133] In an embodiment of the present application, a column clock control circuit is provided in the logic chip, and a third transmission structure for transmitting the column clock signal of the column clock control circuit is provided in the signal transmission structure. The number of the third transmission structures is set to be the same as the number of columns of the pixel array. This enables the column clock signal output by the logic chip to be synchronously transmitted to each column register, thereby improving the signal transmission efficiency between the logic chip and the pixel chip.

[0134] In some embodiments of the present application, the pixel circuit includes a sub-pixel array, the register corresponding to the pixel circuit includes a sub-register, each sub-pixel in the sub-pixel array is correspondingly provided with a sub-register, and the sub-pixel array includes Q columns of sub-pixels, where Q is a positive integer;

[0135] A determination module is configured to transmit a third clock signal from a column clock control circuit to N registers, and determine Z fourth sub-periods within a third period, where Z=X×Q;

[0136] The transmission module 1102 is configured to transmit the image signal from the Q column sub-register in the X column register to the column scanning circuit in sequence in Z fourth sub-intervals in response to the third clock signal, wherein each fourth sub-interval corresponds to the transmission of the image signal in one column sub-register.

[0137] In an embodiment of the present application, when the pixel circuit is an all-in-one pixel circuit, the number of third sub-periods included in the third period of signal transmission is set in combination with the number of columns of the sub-pixel array in the all-in-one pixel circuit, and the column clock control signal is transmitted through the column clock control circuit to control the pixel chip to transmit the image signal to the column scanning circuit in the logic chip, thereby further improving the signal transmission efficiency.

[0138] In some embodiments of the present application, the logic chip further includes: an image signal processing circuit, wherein a first terminal of the image signal processing circuit is connected to the column scanning circuit;

[0139] The transmission module 1102 is used for the column scanning circuit to transmit the image signals of K subframes to the image signal processing circuit for processing. The subframe includes a first period, a second period and a third period, and K is a positive integer.

[0140] In an embodiment of the present application, the logic chip also includes an image signal processing circuit and a port circuit. The image signal processing circuit is arranged between the column scanning circuit and the port circuit. The image signal processing circuit can process the image signal transmitted from the pixel chip to the logic chip to improve the imaging effect of the output image.

[0141] In an embodiment of the present application, an image signal processing circuit and a port circuit are provided in the logic chip, so that the logic chip can process the image signal transmitted by the pixel chip through the image signal processing circuit.

[0142] The control device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., and the embodiment of the present application does not specifically limit it.

[0143] The control device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0144] The control device provided in the embodiment of the present application can implement each process implemented in the above method embodiment. To avoid repetition, it will not be described here.

[0145] Optionally, an embodiment of the present application further provides an electronic device, which includes a control device as in any of the above embodiments, and thus has all the beneficial effects of the control method in any of the embodiments, which will not be described in detail here.

[0146] Optionally, an embodiment of the present application further provides an electronic device, Figure 12 FIG. 1 shows a structural block diagram of an electronic device according to an embodiment of the present application. Figure 12 As shown, the electronic device 1200 includes a processor 1202, a memory 1204, and a program or instruction stored in the memory 1204 and executable on the processor 1202. When the program or instruction is executed by the processor 1202, the various processes of the above-mentioned control method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, they will not be described here.

[0147] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0148] Figure 13 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0149] The electronic device 1300 includes but is not limited to: a radio frequency unit 1301, a network module 1302, an audio output unit 1303, an input unit 1304, a sensor 1305, a display unit 1306, a user input unit 1307, an interface unit 1308, a memory 1309 and a processor 1310.

[0150] Those skilled in the art will understand that the electronic device 1300 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 1310 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 13 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0151] The processor 1310 is used for the row clock control circuit in the logic chip to transmit the row clock signal to the Y row pixel circuits through the Y second transmission structures;

[0152] Processor 1310, configured to synchronize exposure of Y-row pixel circuits in a pixel array in response to a row clock signal within a first time period;

[0153] The processor 1310 is configured to store the image signal obtained by exposure in a corresponding register during the second period of time;

[0154] The processor 1310 is configured to transmit the image signal to the column scanning circuit in the logic chip through the X column registers and the X first transmission structures during the third time period.

[0155] In the embodiments of the present application, by providing only the pixel array and corresponding registers for each pixel circuit in the pixel chip, and providing logic circuits such as the column scanning circuit and row clock control circuit in the logic chip, no additional logic circuits are required in the pixel chip, and no pixel circuits are required on the logic chip. This allows the logic chip and pixel chip stacks to be the same size, reducing the overall size of the image sensor architecture. Furthermore, each pixel circuit starts and ends exposure synchronously within each frame. This global shutter-like operation prevents the image sensor from experiencing the rolling shutter effect typical of moving objects when capturing images, improving the image sensor's capture quality.

[0156] Furthermore, the Y registers in each column of registers are respectively connected to corresponding first transmission structures;

[0157] The processor 1310 is configured to transmit the image signal from the Y row registers to the column scanning circuit in sequence in Y second sub-periods of the third period, wherein each second sub-period corresponds to the transmission of the image signal in one row of registers.

[0158] In an embodiment of the present application, by connecting Y registers in each column of registers in parallel on the first transmission structure, the first transmission structure can transmit the image signals in one row of registers at a time, thereby improving the transmission efficiency of the image signals between the pixel chip and the logic chip.

[0159] Furthermore, the Y registers in each column of registers are connected in series, and the Y registers are connected to the first transmission structure;

[0160] Processor 1310 is configured to receive, in each row of registers, an image signal transmitted by a previous row of registers and transmit the image signal to a next row of registers during M second sub-periods within a third period, until all image signals in Y rows of registers are transmitted to the column scanning circuit, where M is a positive integer and M=Y-1.

[0161] In an embodiment of the present application, by connecting Y registers in each column of registers in series on the first transmission structure, during the image signal transmission process, the image signal can flow in the series-connected registers, so that the first transmission structure can transmit the image signal in one row of registers at a time, thereby improving the transmission efficiency of the image signal between the pixel chip and the logic chip.

[0162] Furthermore, the signal transmission structure further includes X third transmission structures, and the X third transmission structures correspond one-to-one to X columns of pixel circuits in the pixel array; the logic chip further includes: a column clock control circuit connected to the X third transmission structures, and the column clock control circuit is connected to X columns of registers in the pixel array through the X third transmission structures;

[0163] Processor 1310 is configured to transmit a column clock signal to N registers via a column clock control circuit to determine X third sub-periods within a third period;

[0164] The processor 1310 is configured to transmit the image signal to the column scanning circuit in sequence in X third sub-periods in response to the column clock signal via the X column registers, wherein each third sub-period corresponds to the transmission of the image signal in one column register.

[0165] In an embodiment of the present application, a column clock control circuit is provided in the logic chip, and a third transmission structure for transmitting the column clock signal of the column clock control circuit is provided in the signal transmission structure. The number of the third transmission structures is set to be the same as the number of columns of the pixel array. This enables the column clock signal output by the logic chip to be synchronously transmitted to each column register, thereby improving the signal transmission efficiency between the logic chip and the pixel chip.

[0166] Furthermore, the pixel circuit includes a sub-pixel array, the register corresponding to the pixel circuit includes sub-registers, each sub-pixel in the sub-pixel array is correspondingly provided with a sub-register, the sub-pixel array includes Q columns of sub-pixels, and Q is a positive integer;

[0167] Processor 1310 is configured to transmit a third clock signal to N registers via a column clock control circuit, and determine Z fourth sub-intervals within a third period, where Z=X×Q.

[0168] The processor 1310 is configured to transmit the image signal to the column scanning circuit in sequence in Z fourth sub-intervals in response to the third clock signal via the Q column sub-register in the X column register, wherein each fourth sub-interval corresponds to the transmission of the image signal in one column sub-register.

[0169] In an embodiment of the present application, when the pixel circuit is an all-in-one pixel circuit, the number of third sub-periods included in the third period of signal transmission is set in combination with the number of columns of the sub-pixel array in the all-in-one pixel circuit, and the column clock control signal is transmitted through the column clock control circuit to control the pixel chip to transmit the image signal to the column scanning circuit in the logic chip, thereby further improving the signal transmission efficiency.

[0170] Furthermore, the logic chip further includes: an image signal processing circuit, wherein a first terminal of the image signal processing circuit is connected to the column scanning circuit;

[0171] The processor 1310 is configured to transmit the image signals of K subframes from the column scanning circuit to the image signal processing circuit for processing, where the subframe includes a first period, a second period, and a third period, and K is a positive integer.

[0172] In an embodiment of the present application, the logic chip also includes an image signal processing circuit and a port circuit. The image signal processing circuit is arranged between the column scanning circuit and the port circuit. The image signal processing circuit can process the image signal transmitted from the pixel chip to the logic chip to improve the imaging effect of the output image.

[0173] It should be understood that in an embodiment of the present application, the input unit 1304 may include a graphics processing unit (GPU) 13041 and a microphone 13042, and the graphics processor 13041 processes the image data of a static picture or a motion file obtained by an image capture device (such as a camera) in an action file capture mode or an image capture mode. The display unit 1306 may include a display panel 13061, and the display panel 13061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1307 includes a touch panel 13071 and at least one of other input devices 13072. The touch panel 13071 is also called a touch screen. The touch panel 13071 may include two parts: a touch detection device and a touch controller. Other input devices 13072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0174] The memory 1309 can be used to store software programs and various data. The memory 1309 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 1309 may include a volatile memory or a non-volatile memory, or the memory 1309 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DRRAM). The memory 1309 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0175] Processor 1310 may include one or more processing units. Optionally, processor 1310 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 1310.

[0176] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0177] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0178] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned control method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0179] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0180] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned control method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0181] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, device, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, device, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, device, article or device comprising the element. In addition, it should be noted that the scope of the devices and apparatus in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described apparatus may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0182] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment devices can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the devices of each embodiment of the present application.

[0183] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An image sensor, characterized in that: include: A pixel chip, wherein the pixel chip includes a pixel array, the pixel array includes N pixel circuits and N registers, the N registers correspond one-to-one to the N pixel circuits, the registers are connected to the corresponding pixel circuits, the pixel circuits include single-photon avalanche transistors, and N is a positive integer; a signal transmission structure, wherein a first end of the signal transmission structure is connected to the pixel chip, the first end of the signal transmission structure being located on a peripheral side of the pixel array, the signal transmission structure including X first transmission structures and Y second transmission structures, the X first transmission structures corresponding one-to-one to the pixel circuits in columns X of the pixel array, and the Y second transmission structures corresponding one-to-one to the pixel circuits in rows Y of the pixel array, where X and Y are both positive integers, and X×Y=N; a logic chip disposed opposite to the pixel chip, the logic chip being connected to the second end of the signal transmission structure, the logic chip being provided with a column scanning circuit and a row clock control circuit, the column scanning circuit being connected to the registers in X columns via X first transmission structures, and the row clock control circuit being connected to the pixel circuits in Y rows via Y second transmission structures.

2. The image sensor according to claim 1, wherein The Y registers in each column of registers are respectively connected to corresponding first transmission structures.

3. The image sensor according to claim 1, wherein The Y registers in each column of the registers are connected in series, and the Y registers are connected to the first transmission structure.

4. The image sensor according to any one of claims 1 to 3, characterized in that The signal transmission structure further includes X third transmission structures, and the X third transmission structures correspond one-to-one to the X columns of pixel circuits in the pixel array; The logic chip further includes: A column clock control circuit is connected to the X third transmission structures. The column clock control circuit is connected to the registers in X columns in the pixel array through the X third transmission structures.

5. The image sensor according to any one of claims 1 to 3, characterized in that The logic chip further includes: an image signal processing circuit, wherein a first terminal of the image signal processing circuit is connected to the column scanning circuit; A port circuit is connected to the second end of the image signal processing circuit.

6. The image sensor according to any one of claims 1 to 3, characterized in that The signal transmission structure includes at least one of the following: copper-copper bonding and through-silicon via.

7. A control method, characterized in that: Applied to the image sensor according to any one of claims 1 to 6, the control method comprises: The row clock control circuit in the logic chip transmits a row clock signal to Y rows of pixel circuits through Y second transmission structures; The pixel circuits of row Y in the pixel array are synchronously exposed in a first time period in response to the row clock signal, and store image signals obtained by exposure in corresponding registers in a second time period; During a third time period, the X columns of registers transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures.

8. The control method according to claim 7, characterized in that: The Y registers in each column of the registers are respectively connected to corresponding first transmission structures; The pixel circuits of the X columns in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures within a third time period, including: The registers in the Y rows transmit the image signals to the column scanning circuit in sequence in Y second sub-periods of the third period, wherein each second sub-period corresponds to the transmission of the image signals in a row of the registers.

9. The control method according to claim 7, characterized in that: The Y registers in each column of the registers are connected in series, and the Y registers are connected to the first transmission structure; The pixel circuits of the X columns in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures within a third time period, including: During the M second sub-periods within the third time period, each row of the registers receives the image signal transmitted by the registers in the previous row, and transmits the image signal to the registers in the next row, until the image signals in the registers in Y rows are all transmitted to the column scanning circuit, M is a positive integer, and M=Y-1.

10. The control method according to claim 7, characterized in that: The signal transmission structure further includes X third transmission structures, and the X third transmission structures correspond one-to-one to the pixel circuits in the X columns in the pixel array; the logic chip further includes: a column clock control circuit connected to the X third transmission structures, and the column clock control circuit is connected to the registers in the X columns in the pixel array through the X third transmission structures; The pixel circuits of the X columns in the pixel array transmit image signals to the column scanning circuit in the logic chip through the X first transmission structures within a third time period, including: The column clock control circuit transmits a column clock signal to the N registers to determine X third sub-periods within the third period; The X columns of registers transmit the image signals to the column scanning circuit in sequence in X third sub-periods in response to the column clock signal, wherein each third sub-period corresponds to the transmission of the image signals in one column of the registers.

11. A control device, characterized in that: The image sensor according to any one of claims 1 to 6, wherein the control device comprises: A transmission module, configured for a row clock control circuit in a logic chip to transmit a row clock signal to Y rows of pixel circuits via Y second transmission structures; An exposure module, configured to synchronously expose the pixel circuits of the Y rows in the pixel array in response to the row clock signal within a first time period; A storage module, configured to store the image signal obtained by exposure in a corresponding register during the second period; The transmission module is configured to transmit image signals from the X columns of registers to the column scanning circuit in the logic chip via the X first transmission structures within a third time period.

12. An electronic device, characterized in that: include: A processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 7 to 10 are implemented.

13. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method according to any one of claims 7 to 10 are implemented.

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