Photoacid generator, photoresist composition and lithography method

Abstract

The invention relates to a photoacid generator, a photoresist composition and a lithography method. The photoacid generator comprises a photoactive cation and an anion. The photoactive cation includes a portion and one or more EUV absorbing atoms. The moiety comprises an onium salt, a selenium salt, a phosphonium salt, an iodine salt, or a sulfonium salt. The one or more EUV absorbing atoms are attached to the portion. The anion is attached to the photoactive cation.

Description

Technical Field

[0001] The present disclosure relates to a photoacid generator, a photoresist composition and a lithography method. Background Art

[0002] As consumer devices become smaller and smaller in response to consumer demand, the individual components of these devices must also decrease in size. Semiconductor devices that constitute the primary components of devices such as mobile phones, tablet computers, and the like have been forced to become smaller and smaller, while corresponding pressures on individual devices within the semiconductor devices (e.g., transistors, resistors, capacitors, etc.) have also been reduced in size.

[0003] One enabling technique used in the fabrication of semiconductor devices is the use of lithographic materials. Such materials are applied to the surface of the layer to be patterned and then exposed to an energy that is itself patterned. This exposure changes the chemical and physical properties of the exposed areas of the photosensitive material. This change, along with not reducing the extreme ultraviolet (EUV) dose used to develop the pattern in the photoresist and not reducing the line width roughness (LWR) of the pattern on the unexposed areas of the photosensitive material, can be used to remove one area without removing another area.

[0004] However, as the size of individual devices decreases, the process window of lithography becomes increasingly tighter. Thus, advances in the field of lithography are necessary to maintain the ability to scale down devices, and further improvements are needed to keep moving toward smaller and smaller components in order to meet the required design standards.

[0005] As the semiconductor industry has progressed to nanometer technology process nodes in pursuit of higher device density, higher performance and lower cost, there are challenges in reducing semiconductor feature sizes. Extreme ultraviolet lithography (EUVL) has been developed to form smaller semiconductor device feature sizes and increase device density on semiconductor wafers. Summary of the invention

[0006] In some embodiments, a photoacid generator includes a photoactive cation and an anion attached to the photoactive cation. The photoactive cation includes a moiety and one or more EUV absorbing atoms attached to the moiety. The moiety includes an onium salt, a selenium salt, a phosphonium salt, an iodonium salt, or a sulfonium salt.

[0007] In some embodiments, a photoresist composition includes a polymer, a photoacid generator, and a solvent. The photoacid generator includes a cation. The cation is made of one or more electron donor materials and an electron acceptor material attached to the one or more electron donor materials. The one or more electron donor materials can absorb radiation.

[0008] In some embodiments, a lithography method includes the following steps: depositing a photoresist composition on a substrate to form a photoresist layer, wherein the photoresist composition includes a polymer, a photoacid generator, and a solvent. The photoresist layer is exposed to light so that the photoacid generator decomposes via a plurality of charge transfer mechanisms having different types, and the charge transfer mechanism includes intramolecular charge transfer. The photoresist layer is developed. The substrate is etched using the developed photoresist layer as an etch mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1A is a schematic diagram of an EUV lithography tool with an LPP-based EUV radiation source according to some embodiments of the present disclosure;

[0011] Figure 1B is a simplified schematic diagram of details of an EUV lithography tool according to an embodiment of the present disclosure, showing exposure of a photoresist-coated substrate using a patterned EUV beam;

[0012] Figure 2 is a cross-sectional view of an EUV mask constructed according to some embodiments of the present disclosure;

[0013] Figure 3 is a schematic partial cross-sectional side view of a semiconductor device at various stages of manufacture according to various aspects of the present disclosure;

[0014] Figure 4 is a schematic diagram of a photoactive cation of a PAG according to some embodiments;

[0015] Figure 5 is an example structural formula (A1) of a photoactive cation of a PAG according to some embodiments;

[0016] Figure 6 is a schematic partial cross-sectional side view of a semiconductor device at various stages of manufacture according to various aspects of the present disclosure;

[0017] Fig. 7A shows electron generation of a polymer of a photoresist composition under EUV radiation according to some embodiments;

[0018] Figure 7B shows the formation of an acid "precursor" of a polymer of a photoresist composition according to some embodiments;

[0019] Fig. 8A shows the intermolecular charge transfer mechanism of PAG according to some embodiments;

[0020] Figure 8B shows the intramolecular charge transfer mechanism of PAG according to some embodiments;

[0021] Figure 8C illustrates acid release according to some embodiments;

[0022] Fig. 9A Graph showing EUV absorption of CH3-I groups of PAGs according to some embodiments;

[0023] Fig. 9B is a schematic diagram of the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) under UV absorption of PAG according to some embodiments;

[0024] Fig. 10A and Fig. 10B are diagrams of a first mechanism and a second mechanism, respectively, of intramolecular charge transfer between a donor and an acceptor by EUV according to some embodiments;

[0025] Fig.11 , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B is a schematic partial cross-sectional side view of a semiconductor device at various stages of manufacture according to various aspects of the present disclosure;

[0026] Figures 14 to 19 is a schematic partial cross-sectional side view of a semiconductor device at various stages of manufacture according to various aspects of the present disclosure;

[0027] Fig. 20 , Fig.21 and Fig.22A A perspective view illustrating an additive manufacturing process for forming a semiconductor device on a substrate according to some embodiments of the present disclosure;

[0028] Fig. 22B , Fig.23 , Fig.24 and Fig.25A cross-sectional view illustrating an additive manufacturing process for forming a semiconductor device using a substrate according to some embodiments of the present disclosure.

[0029]

Explanation of symbols

[0030] 10: EUV lithography system

[0031] 12, 13, 30, 210: substrate

[0032] 14: STI area

[0033] 15, 215: Photoresist layer

[0034] 32: Conductive layer

[0035] 34:ML Structure

[0036] 36: Covering layer

[0037] 38: Buffer layer

[0038] 40: absorbent layer

[0039] 45, 45a, 400: semiconductor device

[0040] 47: First material layer

[0041] 49: Second material layer

[0042] 50: Exposure area

[0043] 52: Unexposed area

[0044] 57: Developer

[0045] 62: Allocator

[0046] 100: EUV radiation source

[0047] 102: Semiconductor Strip

[0048] 104: Fins

[0049] 105: Chamber

[0050] 106: dummy gate structure

[0051] 108: dummy gate dielectric layer

[0052] 109: dummy gate electrode

[0053] 110: Collector

[0054] 112: Bottom cover

[0055] 114: Top cover

[0056] 115: Target droplet generator

[0057] 116: Gate spacer

[0058] 120: Nozzle

[0059] 122: Source / drain epitaxial structure

[0060] 123:CESL

[0061] 125: Droplet catcher

[0062] 126:ILD layer

[0063] 128: Gate structure

[0064] 130: Gate dielectric layer

[0065] 132: Work function metal layer

[0066] 134: Filler Metal

[0067] 200: Exposure device

[0068] 205a, 205b: Optical device

[0069] 205c: Reflective hood

[0070] 205d, 205e: Reduced projection optics

[0071] 208: substrate stage

[0072] 300: Excitation laser source

[0073] 310: Laser Generator

[0074] 320:Laser Guided Optics

[0075] 330: Focusing Equipment

[0076] 500, 500a: Photoactive cation

[0077] 502A, 502A_1, 502A_2: Part

[0078] 502D, 502D_1, 502D_2: High EUV absorption group

[0079] 504:Polymer

[0080] 506: Acid "precursor"

[0081] 508: Anion

[0082] 510:Acid

[0083] 512: First Mechanism

[0084] 514: Second Mechanism

[0085] A1: Example structure

[0086] BB:Line

[0087] BF: Grassroots

[0088] DP: Target droplet

[0089] DP1, DP2: damper

[0090] LR1: Laser

[0091] LR2: Laser Pulse

[0092] MF: Main Layer

[0093] PP1, PP2: base plate

[0094] S100: Operation

[0095] S102: Actinic Radiation

[0096] ZE: Excitation zone DETAILED DESCRIPTION

[0097] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of the components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0098] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0099] As used herein, "approximately," "about," "approximately," or "substantially" may refer to within 20%, or within 10%, or within 5% of a given value or range. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the specification are merely examples and may decrease as integrated circuits shrink. The numerical quantities given herein are approximate, meaning that the terms "approximately," "about," "approximately," or "substantially" may be inferred in the absence of explicit provisions.

[0100] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0101] Figure 1A Schematic diagram of an EUV lithography system 10 constructed according to some embodiments. The EUV lithography system 10 may also be collectively referred to as a scanner for performing a lithography exposure process using a respective radiation source and an exposure mode. The EUV lithography system 10 is designed to expose a photoresist layer by EUV light or EUV radiation. The photoresist layer is a material that is sensitive to EUV light. The EUV lithography system 10 uses a radiation source 100 to generate EUV light, such as EUV light having a wavelength ranging from about 1 nm to about 100 nm. In a specific example, the radiation source 100 generates EUV light having a wavelength centered at about 13.5 nm. Therefore, the radiation source 100 is also referred to as an EUV radiation source 100. Extreme ultraviolet (EUV) lithography has been widely used due to its ability to achieve small semiconductor device sizes (e.g., 20 nanometer (nm) technology nodes).

[0102] The present disclosure provides a novel photo acid generator (PAG). PAG can contain high EUV absorbing groups and donor-acceptor design in the same molecule. PAG has multiple charge transfer mechanisms. In addition to the intermolecular charge transfer of PAG, the high EUV absorbing groups can absorb EUV photons due to their inner shell electrons and have fast intramolecular charge transfer from donor to acceptor. Therefore, the decomposition of PAG can occur easily and quickly via intramolecular charge transfer. Since PAG contains both intermolecular charge transfer and intramolecular charge transfer, the acid generation efficiency is improved, which is beneficial to improve the performance of lithography.

[0103] The following will refer to Figures 1A to 13BThe various aspects of the present disclosure are discussed in more detail. First, the following reference is made to Figure 1A , Figure 1B and Figure 2 Next, we will refer to the EUV lithography system. Figures 3 to 13B Details of novel PAGs and lithography processes employing photoresists including the novel PAGs are discussed.

[0104] The advanced lithography processes, methods, and materials described in this disclosure can be used in many applications, including fin-type field effect transistors (FinFETs), gate-all-around (GAA) FETs. For example, fins can be patterned to produce relatively tight spacing between features, and the above disclosure is particularly suitable for this situation. In addition, spacers used to form fins of FinFETs can be processed according to the above disclosure.

[0105] In order to cope with the trend of Moore's Law for reducing the size of chip elements and the demand for higher computing power chips for mobile electronic devices (such as smart phones with computer functions, multitasking capabilities or even workstation capabilities), smaller wavelength lithography exposure systems are desirable. Extreme ultraviolet (EUV) lithography technology uses an EUV radiation source to emit EUV light with a wavelength of about 13.5nm. Because this wavelength is also in the x-ray radiation wavelength region, the EUV radiation source is also called a soft x-ray radiation source. The EUV light emitted from the laser-produced plasma (LPP) is collected by a condenser and reflected toward a patterned mask.

[0106] Figure 1A FIG. 1 is a schematic diagram of an EUV lithography tool having an EUV radiation source based on LPP according to some embodiments of the present disclosure. The EUV lithography system includes an EUV radiation source 100 for generating EUV radiation, an exposure device 200 such as a scanner, and an excitation laser source 300. Figure 1A As shown in , in some embodiments, the EUV radiation source 100 and the exposure device 200 are installed on the main layer MF of the clean room, and the excitation laser source 300 is installed in the base layer BF located below the main layer MF. Each of the EUV radiation source 100 and the exposure device 200 is placed above the base plates PP1 and PP2 via dampers DP1 and DP2, respectively. The EUV radiation source 100 and the exposure device 200 are coupled to each other by a coupling mechanism, which may include a focusing unit.

[0107] The EUV lithography tool is designed to expose a resist layer to EUV light (also interchangeably referred to herein as EUV radiation). The resist layer is a material that is sensitive to EUV light. The EUV lithography system uses an EUV radiation source 100 to generate EUV light, such as EUV light having a wavelength ranging from about 1 nm to about 100 nm. In a specific example, the EUV radiation source 100 generates EUV light having a wavelength centered at about 13.5 nm. In a specific embodiment, the EUV radiation source 100 generates EUV radiation using a laser-produced plasma (LPP) mechanism.

[0108] The exposure device 200 includes various reflective optical elements, such as convex mirrors / concave mirrors / plane mirrors, a mask holding mechanism including a mask stage, and a wafer holding mechanism. The EUV radiation EUV generated by the EUV radiation source 100 is guided by the reflective optical elements to a mask fixed on the mask stage. In some embodiments, the mask stage includes an electrostatic chuck (electronic chuck) for fixing the mask.

[0109] Figure 1B A simplified schematic diagram of details of an extreme ultraviolet lithography tool according to an embodiment of the present disclosure is shown, showing a photoresist-coated substrate 210 fixed on a substrate stage 208 of an exposure device 200 being exposed using a patterned EUV beam. The exposure device 200 is an integrated circuit lithography tool such as a stepper, a scanner, a step-and-scan system, a direct write system, a device using a contact and / or proximity mask, etc., which is provided with, for example, one or more optical devices 205a, 205b for irradiating a patterned optical device 205c such as a reduction mask with an EUV beam to produce a patterned beam and one or more reduction projection optical devices 205d, 205e for projecting the patterned beam onto the photoresist-coated substrate 210. A mechanical component (not shown) may be provided for producing controlled relative motion between the photoresist-coated substrate 210 and the patterned optical device 205c. As Figure 2 As further shown in , the EUVL tool comprises an EUV radiation source 100 comprising an EUV light radiator ZE emitting EUV light in a chamber 105 , which is reflected by a collector 110 along a path into an exposure device 200 to irradiate a substrate 210 coated with photoresist.

[0110] As used herein, the term "optical device" is intended to be broadly interpreted to include, but not necessarily limited to, one or more elements that reflect and / or transmit and / or act on incident light, and include, but are not limited to, one or more lenses, windows, filters, wedges, prisms, gratings, transmission fibers, etalons, diffusers, homogenizers, detectors and other instrument elements, apertures, axicons, and mirrors, including multilayer mirrors, near normal incidence mirrors, grazing incidence mirrors, specular reflectors, diffuse reflectors, and combinations of the foregoing. Furthermore, unless otherwise specified, the term "optical device" as used herein refers to, but is not limited to, elements that operate alone or advantageously in one or more specific wavelength ranges, such as at EUV output light wavelengths, irradiation laser wavelengths, wavelengths suitable for measurement methods, or any other specific wavelengths.

[0111] In various embodiments of the present disclosure, the substrate 210 coated with photoresist is a semiconductor wafer, such as a silicon wafer or other types of wafers to be patterned. In some embodiments, the EUVL tool further includes other modules or is integrated (or coupled) with other modules.

[0112] like Figure 1A As shown in FIG. 1 , an EUV radiation source 100 includes a target droplet generator 115 and a collector 110 enclosed by a chamber 105. For example, the collector 110 is a laser-produced plasma (LPP) collector. In various embodiments, the target droplet generator 115 includes a reservoir for holding a source material and a nozzle 120, and the target droplets DP of the source material are supplied into the chamber 105 via the nozzle 120.

[0113] In some embodiments, the target droplets DP are metal droplets of tin (Sn), lithium (Li), or an alloy of Sn and Li. In some embodiments, the target droplets DP each have a diameter in the range of about 10 microns (μm) to about 100 μm. For example, in an embodiment, the target droplets DP are tin droplets having a diameter of about 10 μm to about 100 μm. In other embodiments, the target droplets DP are tin droplets having a diameter of about 25 μm to about 50 μm. In some embodiments, the target droplets DP are supplied via the nozzle 120 at a rate in the range of about 50 droplets per second (i.e., a spraying frequency of about 50 Hz) to about 50,000 droplets per second (i.e., a spraying frequency of about 50 kHz).

[0114] Return to reference Figure 1A, the excitation laser LR2 generated by the excitation laser source 300 is a pulsed laser. The laser pulse LR2 is generated by the excitation laser source 300. The excitation laser source 300 may include a laser generator 310, a laser guiding optical device 320, and a focusing device 330. In some embodiments, the laser generator 310 includes a carbon dioxide (CO2) or a neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source, whose wavelength is in the infrared region of the electromagnetic spectrum. For example, in an embodiment, the laser generator 310 has a wavelength of about 9.4 μm to about 10.6 μm. The laser light LR1 generated by the laser generator 310 is guided by the laser guiding optical device 320 and focused by the focusing device 330 into the excitation laser light LR2, and then introduced into the EUV radiation source 100.

[0115] In some embodiments, the excitation laser LR2 comprises a preheating laser and a main laser. In such embodiments, a given target droplet is heated (or preheated) using a preheating laser pulse (interchangeably referred to herein as a "pre-pulse") to produce a low-density target plume with multiple smaller droplets, which is then heated (or reheated) by a pulse from the main laser to produce increased EUV light emission.

[0116] In various embodiments, the preheating laser pulse has a spot size of about 100 μm or less, and the main laser pulse has a spot size in the range of about 150 μm to about 300 μm. In some embodiments, the preheating laser and the main laser pulse have a pulse duration in the range of about 10 ns to about 50 ns and a pulse frequency in the range of about 1 kHz to about 100 kHz. In various embodiments, the preheating laser and the main laser have an average power in the range of about 1 kilowatt (kW) to about 50 kW. In an embodiment, the pulse frequency of the excitation laser LR2 is matched (e.g., synchronized) with the ejection frequency of the target droplets DP.

[0117] The excitation laser LR2 is directed into the excitation region ZE located in front of the collector 110 via a window (or lens). The window is made of a suitable material that is substantially transparent to the laser beam. The generation of the pulsed laser is synchronized with the ejection of the target droplets DP via the nozzle 120. As the target droplets move through the excitation region, the pre-pulse heats the target droplets and transforms them into a low-density target plume. The delay between the pre-pulse and the main pulse is controlled to allow the target plume to form and expand to an optimal size and geometry. In various embodiments, the pre-pulse and the main pulse have the same pulse duration and peak power. When the main pulse heats the target plume, a high-temperature plasma is generated. The plasma emits EUV radiation EUV that is collected by the collector 110. The collector 110 further reflects and focuses the EUV radiation for use in a lithography exposure process performed via the exposure device 200. The droplet catcher 125 is used to capture excess target droplets. For example, some target droplets may be intentionally missed by the laser pulse.

[0118] In some embodiments, the collector 110 is designed with appropriate coating materials and shapes to act as a reflector for EUV collection, reflection, and focusing. In some embodiments, the collector 110 is designed to have an elliptical geometry. In some embodiments, the coating material of the collector 110 is similar to the reflective multilayer of the EUV mask. In some examples, the coating material of the collector 110 includes a ML (such as a plurality of Mo / Si film pairs) and may further include a capping layer (such as Ru) coated on the ML to substantially reflect EUV light. In some embodiments, the collector 110 may further include a grating structure designed to effectively scatter a laser beam directed onto the collector 110. For example, a silicon nitride layer is coated on the collector 110 and patterned to have a grating pattern.

[0119] In the present disclosure, the terms mask, reticle, and retractor are used interchangeably. In the present disclosure, the patterned optical device 205c is a reflective mask 205c. The reflective mask 205c also includes a reflective ML deposited on the substrate. The ML includes a plurality of film pairs, such as a molybdenum-silicon (Mo / Si) film pair (e.g., a molybdenum layer above or below the silicon layer in each film pair). Alternatively, the ML may include a molybdenum-beryllium (Mo / Be) film pair or other suitable materials that can be used to highly reflect EUV light.

[0120] The mask 205c may further include a capping layer, such as ruthenium (Ru), disposed on the ML for protection. The mask 205c further includes an absorber layer deposited over the ML. The absorber layer is patterned to define an integrated circuit (IC) layer, and the absorber layer is discussed in more detail below according to various aspects of the present disclosure. Alternatively, another reflective layer may be deposited over the ML and patterned to define an integrated circuit layer, thereby forming an EUV phase transfer mask.

[0121] The mask 205c and its manufacturing method are further described according to some embodiments. In some embodiments, the mask manufacturing process includes two operations: a blank mask manufacturing process and a mask patterning process. During the blank mask manufacturing process, a blank mask is formed by depositing a suitable layer (e.g., a reflective multilayer) on a suitable substrate. The blank mask is then patterned during the mask patterning process to achieve the desired design of an integrated circuit (IC) layer. The patterned mask is then used to transfer the circuit pattern (e.g., the design of the IC layer) to a semiconductor wafer. The pattern can be transferred over and over to multiple wafers via various lithography processes. A set of masks is used to construct a complete IC.

[0122] An example of a reflective mask 205c is shown in Figure 2 . The reflective mask 205c in the illustrated embodiment is an EUV mask and includes a substrate 30 made of LTEM. The LTEM material may include SiO2 doped with TiO2 and / or other low thermal expansion materials known in the art. In some embodiments, a conductive layer 32 is additionally disposed under the back side of the LTEM substrate 30 for electrostatic clamping purposes. In one example, the conductive layer 32 includes chromium nitride (CrN), but other suitable compositions are also possible.

[0123] The reflective mask 205c includes a reflective multilayer (ML) structure 34 disposed above the LTEM substrate 30. The ML structure 34 may be selected such that it provides high reflectivity for the selected radiation type / wavelength. The ML structure 34 includes a plurality of film pairs, such as a Mo / Si film pair (e.g., a molybdenum layer above or below the silicon layer in each film pair). Alternatively, the ML structure 34 may include a Mo / Be film pair or any material with a refractive index difference that is highly reflective at EUV wavelengths.

[0124] Still refer to Figure 2The EUV mask 205c also includes a capping layer 36 disposed over the ML structure 34 to prevent oxidation of the ML. The EUV mask 205c may further include a buffer layer 38 disposed over the capping layer 36 to serve as an etch stop layer in a patterning or repair process of the absorber layer, which will be described later. The buffer layer 38 has different etching characteristics from the absorber layer disposed over it. In various examples, the buffer layer 38 includes ruthenium (Ru), a Ru compound such as RuB, RuSi, chromium (Cr), chromium oxide, and chromium nitride.

[0125] The EUV mask 205c also includes an absorber layer 40 (also referred to as an absorber layer) formed over the buffer layer 38. In some embodiments, the absorber layer 40 absorbs EUV radiation directed onto the mask. In various embodiments, the absorber layer can be made of tantalum boron nitride (TaBN), tantalum boron oxide (TaBO), or a suitable oxide or nitride (or alloy) of chromium (Cr), radium (Ra), or one or more of the following materials: actinium, radium, tellurium, zinc, copper, and aluminum.

[0126] Figure 3 , Figure 6 , Fig.11 , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B 4 is a schematic partial cross-sectional side view of a semiconductor device 45 at various stages of manufacture according to various aspects of the present disclosure. In some embodiments, the semiconductor device 45 may include an integrated circuit (IC) chip, a system on chip (SoC), or a portion thereof, and may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high-power MOS transistors, or other types of transistors.

[0127] refer to Figure 3. In operation S100, a photoresist layer 15 is coated on the surface of a layer to be patterned (or a target layer) or a substrate. For example, a semiconductor device 45 including a substrate 13 is described. In some embodiments, the substrate 13 is a silicon substrate doped with a p-type dopant such as boron (e.g., a p-type substrate). Alternatively, the substrate 13 may be another suitable semiconductor material. For example, the substrate 13 may be a silicon substrate doped with an n-type dopant such as phosphorus or arsenic (n-type substrate). The substrate 13 may include other elemental semiconductors, such as germanium and diamond. The substrate 13 may optionally include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 13 may include an epitaxial layer (epi layer), may be strained to achieve performance enhancement, and may include a silicon-on-insulator (SOI) structure.

[0128] In some embodiments, the substrate 13 is substantially conductive or semi-conductive. The resistance may be less than about 103 ohm-meter. In some embodiments, the substrate 13 contains a ribbon MX a The substrate 13 may be a metal, a metal alloy, or a metal nitride / sulfide / selenide / oxide / silicide, wherein M is a metal, and X is N, S, Se, O, Si, and wherein "a" is in the range of about 0.4 to about 2.5. For example, the substrate 13 may contain Ti, Al, Co, Ru, TiN, WN2, or TaN.

[0129] In some other embodiments, the substrate 13 contains a dielectric material having a dielectric constant ranging from about 1 to about 40. In some other embodiments, the substrate 13 contains Si, a metal oxide, or a metal nitride, wherein the formula is MX b , wherein M is a metal or Si, and X is N or O, wherein "b" is in the range of about 0.4 to 2.5. For example, the substrate 13 may contain SiO2, silicon nitride, aluminum oxide, hafnium oxide, or lanthanum oxide.

[0130] The photoresist layer 15 may be formed by a spin coating process. When exposed to actinic radiation, the photoresist layer 15 undergoes one or more chemical reactions, thereby causing a change in solubility in the developer composition. Forming the photoresist layer 15 may include depositing the photoresist composition on the substrate 13 to form the photoresist layer 15. In certain embodiments, the photoresist composition includes a polymer, a photo acid generator (PAG), a quencher, and a solvent. The quencher may include a base that removes trace acids without excessively affecting the performance of the photoresist composition. In some other embodiments, the photoresist composition may include a surfactant, a chromophore, a cross-linking agent, the like, or a combination thereof. In some embodiments, the polymer has a molecular weight in the range of about 1000 to about 10000.

[0131] Figure 4 Schematic diagram of a photoactive cation 500 of a PAG according to some embodiments. In some embodiments, the PAG comprises a photoactive cation 500 and an anion. The photoactive cation 500 comprises one or more high EUV absorbing groups 502D for EUV absorption and a donor-acceptor (DA) type structure for EUV induced intramolecular charge transfer. For example, the PAG has a portion 502A attached to the high EUV absorbing group 502D, wherein the high EUV absorbing group 502D acts as a donor and the portion 502A acts as an acceptor. In other words, the high EUV absorbing group 502D and the donor-acceptor design are included in the same molecule of the PAG. The high EUV absorbing group 502D may include one or more atoms having a high EUV absorption cross section. In some embodiments, the high EUV absorbing group 502D comprises I, Sn, Xe, Te, Sb, In, Cs, At, Bi, Po, or an anion having a cross section greater than about 1×10 7 cm 2 / mol of EUV cross-section. If the EUV cross-section of the high EUV absorption group 502D is less than about 1×10 7 cm 2 / mol, the required EUV sensitivity of PAG cannot be achieved. Figure 5 is an example structural formula (A1) of a photoactive cation 500 of a PAG according to some embodiments. The I atom in formula (A1) acts as a high EUV absorbing group 502D_1, and the onium salt in formula (A1) acts as a moiety 502A_1. Because iodine (I) has a strong ability to push electrons after excitation, it acts as an electron donor. In other words, iodine (I) is an electron-pushing group, and moiety 502A_1 is an electron-withdrawing group.

[0132] Portion 502A attached to high EUV absorbing group 502D is used for photoacid generation, wherein portion 502A is selected from the group consisting of onium salts, selenium salts, phosphonium salts, iodonium salts, and sulfonium salts. Portion 502A may be a non-cyclic structure or a cyclic structure, wherein the cyclic structure may be an aromatic ring or a non-aromatic ring. The cyclic structure of portion 502A may be an aromatic ring or a non-aromatic ring having a substituted carbon group or a functionalized group, wherein the substituted carbon group or the functionalized group includes -H, -F, -CF3, -I, -Br, -Cl, -NH2, -COOH, -OH, -SH, -N3, -S(=O)-, olefins, alkynes, imines, ethers, esters, aldehydes, ketones, amides, sulfones, acetic acid, cyanide, allene, alcohols, amines, phosphines, phosphites, anilines, pyridines, or pyrroles. Examples of PAGs include formulas (A1) to (A12):

[0133]

[0134]

[0135] and

[0136] The highly EUV absorbing group 502D can absorb EUV photons due to its inner shell electrons and have a fast intramolecular charge transfer from itself to the moiety 502A, which will be discussed in more detail below.

[0137] In some embodiments, the photoresist composition may be organic or inorganic. For example, the photoresist composition may be inorganic and at least include a metal complex, a metal cluster, a PAG, a quencher (or a base) and a solvent. The photoresist composition may include a metal photoresist as a negative photoresist. In some embodiments, the metal photoresist may include a surfactant, a chromophore, a ligand and a counter ion. For example, the polymer of the negative metal photoresist includes at least one of the metal complexes having a plurality of ligands and counter ions. The ligand may dissociate after exposure, and further complexation or condensation may occur via treatment with oxygen such as H2O, O2 or a combination of the above. After the polymer is cross-linked or undergoes complexation or condensation, the polymer becomes more hydrophobic.

[0138] refer to Figure 6 After forming the photoresist layer 15, the photoresist layer 15 is exposed to actinic radiation S102. For example, the photoresist layer 15 has an exposed area 50 and an unexposed area 52. In some embodiments, the photoresist layer 15 is exposed to actinic radiation S102 having a wavelength substantially less than about 250 nm, and the actinic radiation S102 includes KrF, ArF, EUV, electron beam, or a combination thereof. Due to the actinic radiation S102, the PAG generates a strong acid, which may be a sulfonic acid, a fluorosulfonic acid, or other strong acid with a pKa<0. The PAG may generate an acid via a variety of reactions, such as electron generation, acid "precursor" formation, anion release, and acid release.

[0139] Fig. 7A Electron generation of a polymer 504 of a photoresist composition under EUV radiation is shown according to some embodiments. Figure 7B The formation of an acid "precursor" 506 of a polymer of a photoresist composition according to some embodiments is shown. PAG can decompose to release anions via at least two charge transfer mechanisms. The at least two charge transfer mechanisms include an intermolecular charge transfer mechanism and an intramolecular charge transfer mechanism. Since PAG includes both intermolecular charge transfer and intramolecular charge transfer, the acid generation efficiency is improved, which is beneficial to improving lithography performance.

[0140] Fig. 8A The intermolecular charge transfer mechanism of PAGs according to some embodiments is shown. Figure 8BFIG. 4 shows the intramolecular charge transfer mechanism of PAG according to some embodiments. Fig. 8A , the PAG comprises a photoactive cation 500a attached to an anion 508. Fig. 7A , Figure 7B and Fig. 8A In the intermolecular charge transfer mechanism, when the photoresist composition is irradiated by EUV, the polymer 504 can generate secondary electrons, and then form an acid "precursor" 506. Since the initially formed secondary electrons with high energy (e.g., in the range of about 78 eV to about 86 eV) cannot be transferred to the photoactive cations 500 of the PAG (see Figure 4 ) are used directly, so these secondary electrons require some energy loss mechanism to reduce their energy to below about 20 eV, which is called hot electrons (see Fig. 7A ). When the secondary electrons have sufficiently low energy, they can react and combine with the photoactive cation 500a to decompose the photoactive cation 500a and release the anion 508. Figure 8C Acid release according to some embodiments is shown. Figure 8C , the released anions 508 can trigger the acid "precursor" 506 to release the acid 510, and the acid 510 can be further used for chemical amplification reactions.

[0141] Return to reference Figure 8B In the intramolecular charge transfer mechanism, when the PAG is irradiated by EUV (where the absorption energy is represented by E=hv (E: energy, h: Planck constant, v: wavelength)), since the photoactive cation 500a includes one or more high EUV absorption groups for EUV absorption (in this example, it is an I atom) and a donor-acceptor (DA) type structure for EUV-induced intramolecular charge transfer, EUV-induced electron transition is more efficiently achieved. PAG can be decomposed via at least two charge transfer mechanisms to release anions, wherein at least two charge transfer mechanisms include an intermolecular charge transfer mechanism and an intramolecular charge transfer mechanism. The intramolecular charge transfer mechanism is faster than the intermolecular charge transfer mechanism, which is conducive to improving the efficiency of anion release. Therefore, the acid production of PAG by EUV increases. Secondary electron loss is reduced by the intramolecular charge transfer mechanism.

[0142] Fig. 9A Graph showing EUV absorption of CH3-I groups of PAGs according to some embodiments. Figure 8B and Fig. 9A. For example, the highly EUV absorbing group is iodine (I), where iodine has 4d orbital electrons and can absorb EUV light. Iodine can generate a large number of secondary electrons including 4d and Auger electrons. After iodine absorbs EUV light, intramolecular electronic transitions may occur in the CH3-I (or CI) group by EUV light. Molecular electronic transitions occur when electrons in a molecule are excited from one energy level to a higher energy level. For example, the electrons occupying the EUV sensitive molecular orbital are 4d orbitals for iodine (I) and can be excited to the antibonding molecular orbital of a σ bond (σ). In some embodiments, the intramolecular charge transfer includes d─σ* transitions and d─D*─σ* transitions, where d represents a 4d orbital, σ* represents a σ bond excited state, and D* represents a donor excited state.

[0143] Fig. 9B is a schematic diagram of the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) under UV absorption of PAG according to some embodiments. In some embodiments, when actinic radiation S102 (see Figure 6 ) is UV light, the PAG can have n─π* transition under UV light. The high EUV absorption group 502D_2 is iodine (I) and can be an electron-pushing group, while the portion 502A_2 is an electron-withdrawing group. Because the PAG has a high EUV absorption group, a large amount of secondary electrons can be generated. Due to the donor-acceptor (DA) type structure, efficient EUV-induced electron transition can be achieved.

[0144] Fig. 10A and Fig. 10B 5 are diagrams of a first mechanism 512 and a second mechanism 514, respectively, for intramolecular charge transfer between a donor and an acceptor by EUV according to some embodiments. Fig. 10A In the first mechanism 512, electrons are directly excited by EUV light from the ground state of the donor to the excited state of the acceptor. Fig. 10B In the second mechanism 514, electrons are directly excited from the donor's ground state to the donor's excited state, and then undergo intersystem crossing (ISC) to transfer the electrons from the donor's excited state to the acceptor's excited state.

[0145] In some embodiments, after the photoresist layer 15 is exposed to actinic radiation S102, a post exposure bake (PEB) process is performed on the photoresist layer 15. In some embodiments, the photoresist composition is a positive photoresist, and its polymer is an acid-cleavable polymer. The PAG releases acid after the actinic radiation S102, and the acid cleaves the polymer in the post exposure bake process. After the acid cleaves the polymer, the polymer becomes more hydrophilic. In more detail, after the PEB process, a strong acid (e.g. Figure 8C The acid in the photoresist layer 15 can deprotect the acid-labile groups (ALG) in the exposed areas 50 of the photoresist layer 15, and the polarity of the polymer changes from hydrophobic to hydrophilic.

[0146] In some embodiments where the photoresist composition includes a metal polymer, after actinic radiation S102, the metal polymer dissociates some ligands and gives some active vacancies. After PEB, the vacancies are complexed with H2O or O2 in the exposed area 50, and the structure of the metal polymer becomes a giant metal oxide.

[0147] In some embodiments, the photoresist layer 15 is a negative photoresist. For example, the negative photoresist includes at least one of an acid-catalyzed crosslinkable polymer or a polymer pinacol. The PAG releases an acid after actinic radiation S102, and the acid-catalyzed crosslinkable polymer crosslinks or causes the polymer pinacol to undergo a pinacol rearrangement. After the polymer crosslinks or undergoes a pinacol rearrangement, the polymer becomes more hydrophobic.

[0148] The photoresist layer 15 is then developed by applying a developer to the photoresist layer 15, such as Fig.11 As shown in FIG. 1 , developer 57 is supplied from dispenser 62 to photoresist layer 15. In some embodiments, as shown in FIG. Fig. 12A As shown in FIG. 1 , the exposed areas 50 of the photoresist layer 15 are removed by the developer 57. For example, in some embodiments where the photoresist composition is a positive photoresist, after the polymer becomes more hydrophilic, the polymer can be dissolved by the developer 57 made of an alkaline solution (e.g., an aqueous solution of tetramethylammonium hydroxide (TMAH), such as 2.38% TMAH). In some embodiments, the developer 57 is made of an organic solvent, such as normal butyl acetate (also known as n-butyl acetate). Fig. 12B As shown in , after the polymer becomes more hydrophilic, the polymer cannot be dissolved by the organic solvent, so that the exposed area 50 remains on the substrate 13 and the unexposed area 52 is removed. Fig. 12BIn some embodiments where the photoresist composition is a negative photoresist, the developer 57 (see Fig.11 ) may be an alkaline solution. After the polymer becomes more hydrophobic, the polymer cannot be dissolved by an alkaline solution (e.g., an aqueous solution of tetramethylammonium hydroxide (TMAH), such as 2.38% TMAH). In some other embodiments, the developer 57 (see Fig.11 ) can be made from an organic solvent, such as normalbutyl acetate (also known as n-butyl acetate). After the polymer becomes a polymer with an increased molecular weight (MW), the polymer cannot be dissolved in the organic solvent.

[0149] In some embodiments, Fig.13A and Fig. 13B As shown in , the pattern of the developed photoresist layer 15 extends into the layer to be patterned or the substrate 13 to produce a pattern in the substrate 13, thereby transferring the pattern in the photoresist layer 15 into the substrate 13. The pattern is extended into the substrate 13 by an etching operation using one or more suitable etchants. In some embodiments, the remaining portion of the photoresist layer 15 is at least partially removed during the etching operation. In other embodiments, the remaining photoresist layer 15 is removed after etching the substrate 13 by using a suitable photoresist stripping solvent or by a photoresist ashing operation.

[0150] Figures 14 to 19 is a schematic partial cross-sectional side view of a semiconductor device 45a at various stages of manufacture according to various aspects of the present disclosure. Fig.14 The semiconductor device 45a is similar to the semiconductor device 45a described previously except that the semiconductor device 45a further includes a first material layer 47 and a second material layer 49. Figure 3The semiconductor device 45 discussed. A first material layer 47, a second material layer 49, and a photoresist layer 15 are sequentially formed on a substrate 13. In some embodiments, the semiconductor device 45a may include other additional layers (not shown) on the substrate 13. In some embodiments, the first material layer 47 has different optical properties from the silicon hard mask, the additional layers, and the photoresist layer 15. For example, the first material layer 47 has n, k, T values ​​substantially different from n, k, T values ​​(thickness) of the photoresist layer 15. In some embodiments, the first material layer 47 may be a CVD or PVD deposited film. In some embodiments, the first material layer 47 includes at least one of a different polymer structure, an acid-sensitive molecule, a PAG load, a quencher load, a chromophore, a cross-linking agent, or a solvent, which produces a different n value from the photoresist layer 15. The first material layer 47 and the photoresist layer 15 are etch-resistant. The first material layer 47 and the photoresist layer 15 may contain at least one of etching-resistant molecules, such as molecules including a low Ohnishi number structure, double bonds, triple bonds, silicon, silicon nitride, Ti, TiN, Al, aluminum oxide, SiON, or the like.

[0151] In some embodiments, the second material layer 49 includes at least a silicon-containing polymer, a metal polymer, an organic polymer, a metal complex, a metal oxide, a metal nanoparticle, a cross-linking agent, a chromophore, a PAG, a quencher (or a base), a fluorine additive, and a solvent. In some embodiments, the second material layer 49 may be referred to as a silicon hard mask layer. The second material layer 49 may have different optical properties from the first material layer 47 and the photoresist layer 15. The second material layer 49 has a substantially different n, k, or T value from the first material layer 47 and the photoresist layer 15. For example, compared to the photoresist layer 15 and the first material layer 47, the second material layer 49 includes at least one of a different silicon-containing polymer structure, an acid-sensitive molecule, a PAG loading, a quencher loading, a chromophore, a cross-linking agent, or a solvent, which produces a different n value from the photoresist layer 15. In some embodiments, the first material layer 47, the second material layer 49, and the photoresist layer 15 have different etching resistances. The second material layer 49 contains at least one of etching-resistant molecules, such as molecules including a low Ohnishi number structure, a double bond, a triple bond, silicon, silicon nitride, Ti, TiN, Al, aluminum oxide, SiON, or the like.

[0152] In some embodiments where the second material layer 49 is a silicon-containing polymer, the silicon-containing polymer has at least one silicon-containing monomer, such as a silicon-containing monomer containing 0 to about 4 oxygen atoms on the silicon atom, and a silicon-containing monomer having 0 to about 4 alkyl groups on the silicon atom, wherein the alkyl groups attached to the silicon atom may be aliphatic or aromatic groups.

[0153] In some embodiments, the second material layer 49 is a blend of a silicon-containing polymer and a metal polymer, wherein the metal polymer has at least one metal atom that can absorb EUV light. For example, the metal atom of the metal polymer may be Hf, Zr, Ti, Cr, W, Mo, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Al, Ga, Tl, Ge, Sn, Pb, Sb, or Bi. In some embodiments, the second material layer 49 is a silicon polymer blended with a metal complex, a metal oxide, and metal nanoparticles. In some embodiments, the metal atom of the metal complex, the metal oxide, and the metal nanoparticles may be Hf, Zr, Ti, Cr, W, Mo, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Al, Ga, Tl, Ge, Sn, Pb, Sb, or Bi.

[0154] refer to Fig.15 For example, the photoresist layer 15 is patterned by exposure and development processes, as previously described. Figure 6 and Figures 11 to 12B Therefore, the description thereof is omitted in this article. Fig.16 The first etching process is performed on the second material layer 49 using the patterned photoresist layer 15 as an etching mask, thereby transforming the pattern from the photoresist layer 15 to the second material layer 49, thereby forming the patterned second material layer 49. The first etching process is performed using an etchant to selectively etch the second material layer 49, but terminate on the first material layer 47. The first etching process can be dry etching, wet etching, or a combination thereof. After the first etching process, the photoresist layer 15 is removed by wet stripping or plasma ashing.

[0155] refer to Fig.17 . The first material layer 47 is subjected to a second etching process using the patterned second material layer 49 as an etching mask, thereby transforming the pattern from the patterned second material layer 49 to the first material layer 47, thereby forming the patterned first material layer 47. Due to the etching selectivity between the second material layer 49 and the first material layer 47, an etchant is used to perform the second etching process to selectively etch the first material layer 47 without significantly removing the patterned second material layer 49. The second etching process may be dry etching, wet etching, or a combination thereof. After the second etching process, the patterned second material layer 49 may be removed by an appropriate technique such as wet etching. The resulting structure is shown in FIG. Fig.18 middle.

[0156] refer to Fig.19 Using a patterned first material layer (see Fig.18) as a mask, an additional manufacturing process such as etching or implantation may be performed on the substrate 13. For example, the substrate 13 is etched. Thereafter, the patterned first material layer 47 may be removed by a suitable removal process.

[0157] Fig. 20 , Fig.21 and Fig.22A A perspective view illustrating an additive manufacturing process for forming a semiconductor device 400 on a substrate 12 according to some embodiments of the present disclosure. Fig. 22B , Fig.23 , Fig.24 and Fig.25 A cross-sectional view illustrating an additive manufacturing process for forming a semiconductor device 400 using a substrate 12 according to some embodiments of the present disclosure. Fig.21 . Fig.21 A perspective view illustrating an initial structure. The initial structure includes a substrate 12. The substrate 12 is similar to the substrate 13 in terms of composition and formation, such as being patterned by a photoresist layer 15, as previously described with respect to Figure 3 and Fig. 13B Isolation regions such as shallow trench isolation (STI) regions 14 may be formed to extend into substrate 12 . Portions of substrate 12 between adjacent STI regions 14 are referred to as semiconductor strips 102 .

[0158] The STI regions 14 may include a pad oxide (not shown). The pad oxide may be formed by a thermal oxide formed by thermal oxidation of a surface layer of the substrate 12. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 14 may also include a dielectric material located above the pad oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0159] refer to Fig.21 , the STI region 14 is recessed so that the top portion of the semiconductor strip 102 protrudes higher than the top surface of the adjacent STI region 14 to form a protruding fin 104. The etching may be performed using a dry etching process or a wet etching process.

[0160] The material of the fin 104 may also be replaced with a material different from that of the substrate 12. For example, if the fin 104 is used for an n-type transistor, the protruding fin 104 may be formed of Si, SiP, SiC, SiPC, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like. On the other hand, if the fin 104 is used for a p-type transistor, the protruding fin 104 may be formed of Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor such as InSb, GaSb, InGaSb, or the like.

[0161] refer to Fig.22A and Fig. 22B , a dummy gate structure 106 is formed on the top surface and sidewalls of the fin 104 . Fig. 22B Description Fig.22A BB in FIG. 1 . Forming the dummy gate structure 106 includes sequentially depositing a blank-formed gate dielectric layer and a blank-formed dummy gate electrode layer across the fin 104, followed by patterning the blanket-formed gate dielectric layer and the blank-formed dummy gate electrode layer. As a result of the patterning, the dummy gate structure 106 includes a dummy gate dielectric layer 108 and a dummy gate electrode 109 located above the dummy gate dielectric layer 108. The dummy gate dielectric layer 108 may be any acceptable dielectric layer, such as silicon oxide, silicon nitride, the like, or a combination thereof, and may be formed using any acceptable process such as thermal oxidation, a spin-on process, CVD, or the like. The dummy gate electrode 109 may be any acceptable electrode layer, such as including polysilicon, metal, the like, or a combination thereof. The gate electrode layer may be deposited by any acceptable deposition process such as CVD, plasma enhanced CVD (PECVD), or the like. Each of the dummy gate structures 106 spans across a single or multiple fins 104. The dummy gate structures 106 may have a longitudinal direction that is perpendicular to the longitudinal direction of the respective fins 104.

[0162] A three-layer structure can be used to pattern the blank-formed dummy gate electrode layer and the blank-formed gate dielectric layer. A bottom mask 112, a top mask 114, and a photoresist layer 215 are sequentially formed above the blank-formed dummy gate electrode layer, wherein the photoresist layer 215 is similar to the composition and formation method of the Figure 3 Unless otherwise mentioned, the above discussion on the photoresist layer 15 is applicable to the photoresist layer 215. By using the photoresist layer 215 as a mask, the pattern size accuracy of the underlying layers (eg, the dummy gate electrode 109 and the dummy gate dielectric layer 108) can be improved.

[0163] In alternative embodiments, the bottom mask 112 and the top mask 114 are made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN or other suitable materials. In some embodiments, the bottom mask 112 includes silicon nitride and the top mask 114 includes silicon oxide.

[0164] Next, if Fig.23 , a gate spacer 116 is formed on the sidewall of the dummy gate structure 106. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 12. The spacer material layer may be a conformal layer, which is then etched back to form the gate spacer 116. The spacer material layer is made of a low-k dielectric material. The low-k dielectric material has a dielectric constant (k value) of less than about 3.5. Suitable materials for the low-k dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, or the like. By way of example and not limitation, the spacer material layer may be formed using a process such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, or other suitable processes. The deposited spacer material layer is then subjected to an anisotropic etching process to expose portions of the fin 104 that are not covered by the dummy gate structure 106 (e.g., in the source / drain region of the fin 104). The portion of the spacer material layer directly above the dummy gate structure 106 may be completely removed by the anisotropic etching process. For simplicity, portions of the spacer material layer on the sidewalls of the dummy gate structure 106 may remain to form gate spacers, which are represented as gate spacers 116. In some embodiments, the gate spacers 116 may be used to offset subsequently formed doped regions such as source / drain regions. The gate spacers 116 may further be used to design or modify the source / drain region profile.

[0165] exist Fig.24 In the embodiment, after the formation of the gate spacer 116 is completed, a source / drain epitaxial structure 122 is formed on the source / drain region of the protruding fin 104 that is not covered by the dummy gate structure 106 and the gate spacer 116. In some embodiments, forming the source / drain epitaxial structure 122 includes recessing the source / drain region of the fin 104, followed by epitaxially growing a semiconductor material in the recessed source / drain region of the fin 104. The source / drain epitaxial structure 122 is located on the opposite side of the dummy gate structure 106.

[0166] The source / drain regions of the fins 104 may be recessed using a suitable selective etching process that erodes the fins 104 but does little to erode the gate spacers 116 and the top mask 114 of the dummy gate structure 106. For example, the recessing of the fins 104 may be performed by dry chemical etching using a plasma source and an etchant gas. The plasma source may be an inductively coupled plasma (ICR) etch, a transformer coupled plasma (TCP) etch, an electron cyclotron resonance (ECR) etch, a reactive ion etch (RIE), or the like, and the etchant gas may be fluorine, chlorine, bromine, a combination thereof, or the like, which etches the protruding fins 104 at a faster etching rate than it etches the gate spacers 116 and the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the protruding fins 104 may be performed by wet chemical etching that etches the fins 104 at a faster etching rate than it etches the gate spacers 116 and the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the protruding fins 104 may be performed by a combination of dry chemical etching and wet chemical etching.

[0167] Once the recesses are created in the source / drain regions of the fins 104, source / drain epitaxial structures 122 are formed in the source / drain recesses in the fins 104 using one or more epitaxial or epitaxial (epi) processes that provide one or more epitaxial materials on the protruding fins 104. During the epitaxial growth process, the gate spacers 116 confine the one or more epitaxial materials to the source / drain regions in the fins 104. In some embodiments, the lattice constant of the source / drain epitaxial structures 122 is different from the lattice constant of the fins 104, so that the channel regions in the fins 104 and between the source / drain epitaxial structures 122 can be strained or stressed by the source / drain epitaxial structures 122 to improve carrier mobility of the semiconductor device and enhance device performance. Epitaxy processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy and / or other suitable processes. Epitaxy processes may use gaseous and / or liquid precursors that interact with the composition of the fin 104 .

[0168] In some embodiments, the source / drain epitaxial structure 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure 122 may be in-situ doped during the epitaxy process by introducing doping species, which include p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drain epitaxial structure 122 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 122. In some exemplary embodiments, the source / drain epitaxial structure 122 in the n-type transistor includes SiP, and the source / drain epitaxial structure in the p-type includes GeSnB and / or SiGeSnB. In embodiments with different device types, a mask such as a photoresist may be formed over the n-type device region while exposing the p-type device region, and a p-type epitaxial structure may be formed on the exposed fins 104 in the p-type device region. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type device region while exposing the n-type device region, and an n-type epitaxial structure may be formed on the exposed fins 104 in the n-type device region. The mask may then be removed.

[0169] Once the source / drain epitaxial structures 122 are formed, an annealing process may be performed to activate the p-type dopants or n-type dopants in the source / drain epitaxial structures 122. The annealing process may be, for example, a rapid thermal annealing (RTA), laser annealing, millisecond thermal annealing (MSA) process, or the like.

[0170] Next, in Fig.25In the embodiment, a contact etch stop layer (CESL) 123 and an interlayer dielectric (ILD) layer 126 are sequentially formed on the substrate 12. In some examples, the CESL 123 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having different etching selectivity from the ILD layer 126. The CESL 123 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 includes materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials having different etch selectivity from the CESL 123. The ILD layer 126 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 126, the wafer may be subjected to a high thermal budget process to anneal the ILD layer 126.

[0171] In some examples, after forming the ILD layer 126, a planarization process may be performed to remove excess material of the ILD layer 126 and the CESL 123. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 126 and the CESL 123 that overlie the dummy gate structure 106. In some embodiments, the CMP process also removes the bottom mask 112 and the top mask 114 (e.g., Fig.25 ) and expose the dummy gate electrode 109.

[0172] An etching process is performed to remove the dummy gate electrode 109 and the dummy gate dielectric layer 108, thereby creating gate trenches between corresponding gate spacers 116. The dummy gate structure 106 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the dummy gate structure 106 at a faster etching rate than it etches other materials (e.g., the gate spacers 116 and / or the ILD layer 126).

[0173] Thereafter, replacement gate structures 128 are formed in the gate trenches, respectively. The gate structure 128 may be the final gate of the FinFET. In the FinFET, the fins may be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) may be used to pattern the fins. In general, the double patterning or multi-patterning process combines lithography and self-alignment processes, thereby allowing the formation of patterns having, for example, a smaller pitch than that which can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and a lithography process is used to pattern the sacrificial layer. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. The final gate structures may each be a high-k / metal gate (HKMG) stack, however, other compositions are also possible. In some embodiments, each of the gate structures 128 forms a gate associated with three sides of the channel region provided by the fin 104. In other words, each of the gate structures 128 surrounds the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 128 includes a gate dielectric layer 130 lining the gate trench, a work function metal layer 132 formed over the gate dielectric layer 130, and a fill metal 134 formed over the work function metal layer 132 and filling the remaining portion of the gate trench. The gate dielectric layer 130 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer over the interface layer. As used and described herein, a high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermal silicon oxide (about 3.9)). The work function metal layer 132 and / or the fill metal 134 used within the high-k / metal gate structure 128 may include a metal, a metal alloy, or a metal silicide. Forming the high-k / metal gate structure 128 may include multiple deposition processes for forming various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material.

[0174] In some embodiments, the interface layer of the gate dielectric layer 130 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 130 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 130 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), nitride oxide (SiON) and combinations thereof.

[0175] The work function metal layer 132 may include a work function metal for providing a suitable work function for the high-k / metal gate structure 128. For n-type FinFETs, the work function metal layer 132 may include one or more n-type work function metals (N metals). The n-type work function metal may illustratively include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for p-type FinFETs, the work function metal layer 132 may include one or more p-type work function metals (P metals). The p-type work function metal may illustratively include but is not limited to titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides and / or other suitable materials.

[0176] In some embodiments, the fill metal 134 may illustratively include but is not limited to tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0177] In some embodiments, the semiconductor device 400 includes other layers or features not specifically described. In some embodiments, the semiconductor device 400 is subjected to a back end of line (BEOL) process. In some embodiments, the semiconductor device 400 is formed by a non-replacement metal gate process or a gate first process.

[0178] Based on the above discussion, it can be seen that the present disclosure provides advantages over conventional methods. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and not all embodiments require specific advantages. One advantage is that by including a high EUV absorbing group and a donor-acceptor design in the same molecule of a PAG, the high EUV absorbing group can absorb EUV photons due to its inner shell electrons and have a fast intramolecular charge transfer from the donor to the acceptor. Another advantage is that the decomposition of the PAG can occur easily and quickly via intramolecular charge transfer. Yet another advantage is that since the PAG includes both intermolecular charge transfer and intramolecular charge transfer, the acid production efficiency is improved, which is beneficial to improving lithography performance.

[0179] In some embodiments, a photoacid generator includes a photoactive cation and an anion attached to the photoactive cation. The photoactive cation includes a moiety and one or more EUV absorbing atoms attached to the moiety. The moiety includes an onium salt, a selenium salt, a phosphonium salt, an iodine salt, or a sulfonium salt. In some embodiments, the one or more EUV absorbing atoms include I, Sn, Xe, Te, Sb, In, Cs, At, Bi, Po, or a combination thereof. In some embodiments, the moiety is an aromatic or non-aromatic ring having a substituted carbon group or a functionalized group, the substituted carbon group or the functionalized group including -H, -F, -CF3, -I, -Br, -Cl, -NH2, -COOH, -OH, -SH, -N3, -S(=O)-, olefins, alkynes, imines, ethers, esters, aldehydes, ketones, amides, sulfones, acetic acid, cyanide, allene, alcohols, amines, phosphines, phosphites, anilines, pyridines, or pyrroles. In some embodiments, the photoacid generator has formula (A1) to (A12):

[0180]

[0181]

[0182] and In some embodiments, one or more EUV absorbing atoms are UV absorbing. In some embodiments, one or more EUV absorbing atoms are electron donating groups, while some are electron withdrawing groups.

[0183] In some embodiments, a photoresist composition includes a polymer, a photoacid generator, and a solvent. The photoacid generator includes a cation. The cation is made of one or more electron donor materials and an electron acceptor material attached to the one or more electron donor materials. The one or more electron donor materials are radiation absorbing. In some embodiments, the one or more electron donor materials include I, Sn, Xe, Te, Sb, In, Cs, At, Bi, Po, or a combination of the foregoing. In some embodiments, the one or more electron donor materials are UV absorbing, EUV absorbing, or UV absorbing and EUV absorbing. In some embodiments, the cation of the photoacid generator has formula (A1) to (A12):

[0184]

[0185]

[0186] and In some embodiments, one or more electron donor materials have at least one 4d orbital electron. In some embodiments, one or more electron donor materials have an EUV sensitive molecular orbital that is a 4d orbital. In some embodiments, the cationic electron acceptor material comprises an onium salt, a selenium salt, a phosphonium salt, an iodonium salt, or a sulfonium salt. In some embodiments, the cationic electron acceptor material is an aromatic ring or a non-aromatic ring having a substituted carbon group or a functionalized group, wherein the substituted carbon group or the functionalized group comprises -H, -F, -CF3, -I, -Br, -Cl, -NH2, -COOH, -OH, -SH, -N3, -S(=O)-, olefins, alkynes, imines, ethers, esters, aldehydes, ketones, amides, sulfones, acetic acid, cyanide, allene, alcohols, amines, phosphines, phosphites, anilines, pyridines, or pyrroles.

[0187] In some embodiments, a lithography method includes the following steps. A photoresist composition is deposited on a substrate to form a photoresist layer, wherein the photoresist composition includes a polymer, a photoacid generator, and a solvent. The photoresist layer is exposed to light so that the photoacid generator decomposes via a charge transfer mechanism having different types, and the charge transfer mechanism includes intramolecular charge transfer. The photoresist layer is developed. The substrate is etched using the developed photoresist layer as an etching mask. In some embodiments, the charge transfer mechanism further includes intermolecular charge transfer. In some embodiments, the photoacid generator includes a cation and an anion attached to the cation. The cation includes a cation having a charge transfer mechanism greater than about 1×10 7 cm 2 / mol of EUV cross-section. In some embodiments, the at least one atom is I, Sn, Xe, Te, Sb, In, Cs, At, Bi, Po, or a combination thereof. In some embodiments, the at least one atom is an electron-pushing group. In some embodiments, the cation further includes an electron-withdrawing group attached to the at least one atom.

[0188] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A photoacid generator, characterized in that: include: A photoactive cation, wherein the photoactive cation comprises: a part comprising a plurality of onium salts, a plurality of selenium salts, a plurality of phosphonium salts, a plurality of iodine salts or a plurality of sulfonium salts; and one or more extreme ultraviolet absorbing atoms attached to the portion; and An anion is attached to the photoactive cation.

2. The photoacid generator according to claim 1, wherein The one or more extreme ultraviolet absorbing atoms include I, Sn, Xe, Te, Sb, In, Cs, At, Bi, Po or a combination thereof.

3. The photoacid generator according to claim 1, wherein The moiety is an aromatic ring or a non-aromatic ring having a substituted carbon group or a functionalized group, wherein the substituted carbon group or the functionalized group comprises -H, -F, -CF3, -I, -Br, -Cl, -NH2, -COOH, -OH, -SH, -N3, -S(=O)-, olefins, alkynes, imines, ethers, esters, aldehydes, ketones, amides, sulfones, acetic acid, cyanide, allene, alcohols, amines, phosphines, phosphites, anilines, pyridines or pyrroles.

4. The photoacid generator according to claim 1, wherein Wherein the photoacid generator has formula (A1) to (A12):

5. A photoresist composition, characterized in that: include: A polymer; A photoacid generator, wherein the photoacid generator comprises a cation, and the cation is made of: one or more electron donor materials, the one or more electron donor materials being radiation absorbing; and an electron acceptor material attached to the one or more electron donor materials; and A solvent.

6. The photoresist composition according to claim 5, wherein: The one or more electron donor materials include I, Sn, Xe, Te, Sb, In, Cs, At, Bi, Po or a combination thereof.

7. The photoresist composition according to claim 5, wherein: The one or more electron donor materials are ultraviolet absorbing, extreme ultraviolet absorbing, or ultraviolet absorbing and extreme ultraviolet absorbing.

8. A lithography method, characterized in that: The following steps are involved: A photoresist composition is deposited on a substrate to form a photoresist layer, wherein the photoresist composition comprises: A polymer; a photoacid generator; and A solvent; exposing the photoresist layer to decompose the photoacid generator via a plurality of charge transfer mechanisms having a plurality of different types, wherein the plurality of charge transfer mechanisms include an intramolecular charge transfer; developing the photoresist layer; and The substrate is etched using the developed photoresist layer as an etch mask.

9. The method according to claim 8, characterized in that The multiple charge transfer mechanisms further include intermolecular charge transfer.

10. The method according to claim 8, characterized in that The photoacid generator comprises: A cation, wherein the cation comprises a cation having a 7 cm 2 at least one atom of an extreme ultraviolet cross section per mol; and An anion is attached to the cation.

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