A super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices and a preparation method thereof

Abstract

The present invention provides a super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafer for power devices and a preparation method thereof: S1: siliconizing a graphite base in a silicon epitaxial furnace; S2: placing a silicon substrate on the graphite base; S3: using hydrogen to carry trichlorosilane as a silicon growth source to grow an undoped silicon epitaxial layer on the silicon substrate; S4: feeding doped phosphine gas, hydrogen, and trichlorosilane into a reaction chamber through a first doping pipeline; S5: feeding doped phosphine gas, hydrogen, and trichlorosilane into a reaction chamber through a second doping pipeline to obtain a super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafer for power devices. The method can be used for industrialized mass production of super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafers.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor silicon epitaxial wafer preparation, and in particular relates to an ultra-heavy phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices and a preparation method thereof. Background Art

[0002] In the technical field, power devices such as MOS, SBD, and FRD are developing in the direction of high breakdown voltage and low on-resistance. Since the breakdown voltage and on-voltage drop of power devices are mutually restrictive, that is, if the breakdown voltage is increased, the on-voltage drop will also increase, and vice versa. The traditional planar device structure is based on a single-layer silicon epitaxial wafer, which consists of a heavily doped silicon substrate and a high-resistance silicon epitaxial layer. In recent years, with the continuous progress in the field of technology, in order to ensure the low on-resistance requirements of power devices, ultra-heavily doped silicon substrates have gradually replaced heavily doped silicon substrates as the substrate material of power devices. The adverse effect is that the silicon epitaxial layer faces a stronger self-doping effect during growth, which is more unfavorable for the control of the resistivity stability and consistency of the high-resistance silicon epitaxial layer. In order to ensure the high breakdown voltage requirements of power devices, a thick and high-resistance silicon epitaxial layer is required, but this leads to high on-resistance.

[0003] In recent years, in order to further reduce the on-resistance, designers have adopted a large number of double-layer silicon epitaxial wafers based on the optimization and adjustment of the device structure, shifting the location of the breakdown voltage from the surface to the body of the silicon material. By growing a doped epitaxial inner layer on a heavily doped silicon substrate as a buffer layer, and then growing the second doped outer layer required for the breakdown voltage, both the reverse breakdown voltage and the forward high current characteristics can be improved, but more stringent control requirements are imposed on the stability and consistency of the epitaxial structure. At the same time, the resistivity difference between the first and second silicon epitaxial layers of the double-layer epitaxial generally reaches more than 10 times, and the resistivity of the second high-resistance silicon epitaxial layer has been tightened from <3% to ≤1.2% based on the tolerance requirements of the application field, which places higher requirements on the process control method.

[0004] The process methods used in traditional double-layer silicon epitaxial wafers are as follows: the Chinese patent with publication number CN 110349841 B discloses: using a method of alternating high-temperature, high-flow H2 and normal-flow H2 to blow away impurities in the near-surface layer of the silicon wafer, so that the impurities adsorbed on the silicon wafer and the base have enough energy to escape, thereby realizing the preparation of double-layer silicon epitaxial wafers. However, this patent is applicable to double-layer silicon epitaxial wafers with a resistivity of 0.001~0.004Ω·cm for silicon substrates and a target resistivity of 2.9~3.1Ω·cm for the outer layer of the epitaxial layer. For silicon substrates with lower resistivity, the preparation of double-layer silicon epitaxial wafers with a higher target resistivity of the outer layer of the epitaxial layer is not applicable, and the difficulty of implementing its preparation process will be significantly increased when the substrate resistivity is lower and the epitaxial resistivity is higher. The Chinese patent with the publication number CN111463116A discloses a method for preparing a double-layer epitaxial film for a MOS device structure. By setting comprehensive conditions such as the main process hydrogen flow rate, the heating power of the infrared bulbs in the inner and outer zones, and the precise distribution of the doping flow rate, the overall thickness and resistivity uniformity of the double-layer epitaxial film are controlled, and the inhomogeneity within the film is significantly improved from the current technical level of 2% to 3% to a well-controlled level of <1.5%. However, the technical solution of this patent is not suitable for the preparation of super-heavy phosphorus-doped substrates with lower substrate resistivity. If the traditional flat-plate monolithic silicon epitaxial furnace growth process is used to grow multi-layer silicon epitaxial wafers on super-heavy phosphorus-doped substrates, the substrate self-doping effect will lead to a more serious problem of unstable resistivity of the outer doped silicon epitaxial layer during the growth process. In addition, in this patent, the control of resistivity uniformity still needs to be improved. In addition, the above patents all have complex process steps, and the first silicon epitaxial layer and the second silicon epitaxial layer share a common doping pipeline. Due to the large difference in doping flow rates, there is a problem of mutual interference. Ultimately, the optimal effect of the non-uniformity of the outer high-resistance silicon epitaxial layer is <1.5%.

[0005] Therefore, there is a need for a method for preparing a multilayer silicon epitaxial wafer that has good parameter stability and is adaptable to the requirements of industrial continuous production. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices and a preparation method thereof, which overcomes the problem that the resistivity of the outer doped silicon epitaxial layer is unstable during the growth of the multilayer silicon epitaxial layer due to the high-temperature self-doping effect of the heavily doped substrate and the mutual interference caused by the shared doping pipelines of the inner and outer silicon epitaxial layers when growing the super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer in a traditional flat-plate single-wafer silicon epitaxial furnace.

[0007] In order to solve the above problems, the first aspect of the present invention provides a method for preparing a multilayer silicon epitaxial wafer with an ultra-heavy phosphorus-doped substrate for a power device, comprising the following steps in sequence:

[0008] S1: Siliconizing the graphite susceptor in the silicon epitaxial furnace;

[0009] S2: placing a silicon substrate sheet on the graphite base;

[0010] S3: using hydrogen to carry trichlorosilane as a silicon growth source, growing an undoped silicon epitaxial layer on the polished surface of the silicon substrate, the flow rate of trichlorosilane is 7-8 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.5-0.6 μm;

[0011] S4: doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber through the first doping pipeline configured in the reaction chamber, and a doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer; wherein the flow rate of trichlorosilane is 7-8 g / min, the flow rate of doping phosphine is 220-250 sccm, and the growth rate is 3.0-3.5 μm / min;

[0012] S5: doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber through the second doping pipeline configured in the reaction chamber, and a doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, wherein the flow rate of trichlorosilane is 10-12 g / min, the flow rate of doping phosphine is 110-120 sccm, and the growth rate is 3.6-4.0 μm / min, to obtain a super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices.

[0013] Preferably, in step S1, the thickness of the silicon coating on the graphite base is 5-6 μm.

[0014] Preferably, the process further includes cleaning the reaction chamber and the graphite susceptor of the silicon epitaxial furnace before step S1; the cleaning specifically includes the following steps: introducing hydrogen into the reaction chamber of the silicon epitaxial furnace and heating it up, and then introducing hydrogen chloride gas to clean the reaction chamber and the graphite susceptor, wherein the reaction chamber of the silicon epitaxial furnace is heated to 1160-1180°C, the hydrogen flow rate is 3-5 L / min, the hydrogen chloride flow rate is 15-20 L / min, and the cleaning time is 125-150 sec.

[0015] Preferably, the step S1 specifically includes the following steps: introducing hydrogen to carry trichlorosilane into the reaction chamber, growing a polysilicon coating layer on the graphite base in the reaction chamber, and completing the silicon coating of the graphite base, wherein the flow rate of hydrogen is 45-50 L / min, and the flow rate of trichlorosilane is 10-12 g / min.

[0016] Preferably, the step S2 further comprises cooling the reaction chamber to 600-650° C. before placing the silicon substrate sheet on the graphite susceptor.

[0017] Preferably, before step S3, the reaction chamber is first purged; the first purging specifically includes the following steps: heating the reaction chamber of the silicon epitaxial furnace to 1130-1150°C, maintaining for 3-5 min, baking the silicon substrate, and simultaneously introducing hydrogen to purge the reaction chamber.

[0018] Preferably, in step S3, the hydrogen flow rate is 45-50 L / min.

[0019] Preferably, before step S4, the reaction chamber is subjected to a second purge; the second purge specifically comprises the following steps: hydrogen is introduced to purge the reaction chamber, and the temperature of the reaction chamber is reduced to 1110-1120°C, and the hydrogen purge time of the reaction chamber is 5-8 min; in step S4, before the doping phosphine gas, hydrogen and trichlorosilane are introduced into the reaction chamber, the first doping pipeline is emptied by introducing the doping phosphine gas, hydrogen and trichlorosilane.

[0020] Preferably, before step S5, the reaction chamber is subjected to a third purge; the third purge specifically comprises the following steps: hydrogen is introduced to purge the reaction chamber for 3 to 5 minutes; in step S5, before the doping phosphine gas, hydrogen and trichlorosilane are introduced into the reaction chamber, the second doping pipeline is emptied by introducing the doping phosphine gas, hydrogen and trichlorosilane.

[0021] The second aspect of the present invention provides a super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices prepared by the above-mentioned preparation method.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The method for preparing a multilayer silicon epitaxial wafer with an ultra-heavy phosphorus-doped substrate for a power device of the present invention realizes batch preparation of multilayer silicon epitaxial wafer with an ultra-heavy phosphorus-doped substrate under the condition of simple process and batch repetition by comprehensively designing the process parameters such as the base silicon thickness, the growth thickness of the undoped silicon epitaxial layer, the doping and growth rate of the doped silicon epitaxial inner layer and the doped silicon epitaxial outer layer of the ultra-heavy phosphorus-doped substrate multilayer silicon epitaxial wafer grown in a flat-plate monolithic silicon epitaxial furnace. The method avoids the problem of unstable resistivity of the outer doped silicon epitaxial layer during the growth of the multilayer silicon epitaxial layer due to the high-temperature self-doping effect of the heavily doped substrate and the shared doping pipeline of the inner and outer silicon epitaxial layers when the ultra-heavy phosphorus-doped substrate multilayer silicon epitaxial wafer is grown in a conventional flat-plate monolithic silicon epitaxial furnace. The method can be applied to the industrialized batch production of multilayer silicon epitaxial wafer with an ultra-heavy phosphorus-doped substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1is a schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Example 1 of the present invention;

[0025] Figure 2 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Example 2 of the present invention;

[0026] Figure 3 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Example 3 of the present invention;

[0027] Figure 4 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Example 4 of the present invention;

[0028] Figure 5 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Example 5 of the present invention;

[0029] Figure 6 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Comparative Example 1 of the present invention;

[0030] Figure 7 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Comparative Example 2 of the present invention;

[0031] Figure 8 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Comparative Example 3 of the present invention;

[0032] Fig. 9 A schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Comparative Example 4 of the present invention;

[0033] Fig.10 This is a schematic diagram of the resistivity distribution of the doped silicon epitaxial outer layer produced in Comparative Example 5 of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] A first aspect of an embodiment of the present invention provides a method for preparing a multi-layer silicon epitaxial wafer with an ultra-heavy phosphorus-doped substrate for a power device, comprising the following steps in sequence:

[0036] S1: Siliconizing the graphite susceptor in the silicon epitaxial furnace;

[0037] S2: placing a silicon substrate sheet on the graphite base;

[0038] S3: using hydrogen to carry trichlorosilane as a silicon growth source, growing an undoped silicon epitaxial layer on the polished surface of the silicon substrate, the flow rate of trichlorosilane is 7-8 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.5-0.6 μm;

[0039] S4: doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber through the first doping pipeline configured in the reaction chamber, and a doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer; wherein the flow rate of trichlorosilane is 7-8 g / min, the flow rate of doping phosphine is 220-250 sccm, and the growth rate is 3.0-3.5 μm / min;

[0040] S5: doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber through the second doping pipeline configured in the reaction chamber, and a doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, wherein the flow rate of trichlorosilane is 10-12 g / min, the flow rate of doping phosphine is 110-120 sccm, and the growth rate is 3.6-4.0 μm / min, to obtain a super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices.

[0041] The method for preparing a super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafer for power devices in an embodiment of the present invention realizes batch preparation of super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafers under the condition of simple process and batch repetition by comprehensively designing the base silicon thickness of the super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafer grown in a flat-plate monolithic silicon epitaxial furnace, the growth thickness of the undoped silicon epitaxial layer, the doping and growth rate of the doped silicon epitaxial inner layer and the doped silicon epitaxial outer layer and other process parameters. The method avoids the problem of unstable resistivity of the outer doped silicon epitaxial layer during the growth of the multi-layer silicon epitaxial layer caused by the high-temperature self-doping effect of the heavily doped substrate and the shared doping pipeline of the inner and outer silicon epitaxial layers in the traditional flat-plate monolithic silicon epitaxial furnace growth of super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafers. The method can be applied to the industrial batch production of super-heavy phosphorus-doped substrate multi-layer silicon epitaxial wafers.

[0042] In some embodiments, in step S1, the thickness of the silicon coating on the graphite base is 5-6 μm.

[0043] In some embodiments, the process further includes cleaning the reaction chamber and the graphite susceptor of the silicon epitaxial furnace before step S1; the cleaning specifically includes the following steps: introducing hydrogen into the reaction chamber of the silicon epitaxial furnace and heating it up, and then introducing hydrogen chloride gas to clean the reaction chamber and the graphite susceptor, wherein the reaction chamber of the silicon epitaxial furnace is heated to 1160~1180°C, the hydrogen flow rate is 3~5 L / min, the hydrogen chloride gas flow rate is 15~20 L / min, and the cleaning time is 125~150 sec.

[0044] In some embodiments, the step S1 specifically includes the following steps: introducing hydrogen to carry trichlorosilane into the reaction chamber, growing a polysilicon coating on the graphite base in the reaction chamber, and completing the silicon coating of the graphite base, wherein the flow rate of hydrogen is 45~50 L / min, and the flow rate of trichlorosilane is 10~12 g / min.

[0045] In some embodiments, the step S2 further includes cooling the reaction chamber to 600-650° C. before placing the silicon substrate on the graphite susceptor.

[0046] In some embodiments, before step S3, the reaction chamber is first purged; the first purging specifically includes the following steps: heating the reaction chamber of the silicon epitaxial furnace to 1130-1150°C, maintaining for 3-5 minutes, baking the silicon substrate, and simultaneously introducing hydrogen to purge the reaction chamber.

[0047] In some embodiments, in step S3, the hydrogen flow rate is 45-50 L / min.

[0048] In some embodiments, the process further includes performing a second purge on the reaction chamber before step S4; the second purge specifically includes the following steps: introducing hydrogen to purge the reaction chamber, and reducing the temperature of the reaction chamber to 1110-1120°C, and the hydrogen purge time of the reaction chamber is 5-8 min; in step S4, before introducing doping phosphine gas, hydrogen, and trichlorosilane into the reaction chamber, the first doping pipeline is emptied by introducing doping phosphine gas, hydrogen, and trichlorosilane.

[0049] In some embodiments, the process further includes performing a third purge on the reaction chamber before step S5; the third purge specifically includes the following steps: introducing hydrogen to purge the reaction chamber for 3 to 5 minutes; in step S5, before introducing doping phosphine gas, hydrogen, and trichlorosilane into the reaction chamber, the second doping pipeline is emptied by introducing doping phosphine gas, hydrogen, and trichlorosilane.

[0050] A second aspect of the embodiments of the present invention provides a super heavily phosphorus-doped substrate multi-layer silicon epitaxial wafer for power devices prepared by the above-mentioned preparation method.

[0051] Example 1

[0052] The method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for a power device of this embodiment comprises the following steps:

[0053] (1) Hydrogen gas was introduced into the reaction chamber of the silicon epitaxial furnace to increase the temperature, and hydrogen chloride gas was introduced to clean the reaction chamber and the graphite susceptor. The reaction chamber of the silicon epitaxial furnace was heated to 1180°C, the hydrogen flow rate was set to 5 L / min, the hydrogen chloride flow rate was set to 15 L / min, and the cleaning time was set to 150 sec.

[0054] (2) Hydrogen gas carrying trichlorosilane is introduced into the reaction chamber to grow a polysilicon coating on the graphite susceptor in the reaction chamber to complete the silicon coating of the susceptor. The hydrogen flow rate is set to 45 L / min, and the trichlorosilane flow rate is set to 10 g / min. A polysilicon coating with a thickness of 6 μm is deposited on the graphite susceptor in the reaction chamber.

[0055] (3) The reaction chamber is cooled to 600°C, and the silicon substrate is placed in the center of the sheet pit of the graphite base of the reaction chamber;

[0056] (4) Hydrogen is introduced into the reaction chamber and the temperature is raised to 1130°C again to bake the surface of the silicon substrate and purge the reaction chamber for 3 min;

[0057] (5) Hydrogen carries trichlorosilane as a silicon growth source to grow an undoped silicon epitaxial layer on the polished surface of a silicon substrate. The hydrogen flow rate is set to 45 L / min, the trichlorosilane flow rate is set to 7 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.5 μm.

[0058] (6) The reaction chamber was re-purged with hydrogen for 5 min and the temperature was reduced to 1110 °C;

[0059] (7) The first doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer. The flow rate of trichlorosilane is set to 7 g / min, the flow rate of doped phosphine is 220 sccm, and the growth rate is set to 3.0 μm / min.

[0060] (8) Re-purge the reaction chamber with hydrogen for 5 min;

[0061] (9) The second doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, forming a multilayer silicon epitaxial wafer. The flow rate of trichlorosilane is set to 10 g / min, the flow rate of doped phosphine is 110 sccm, and the growth rate is set to 3.6 μm / min.

[0062] (10) The reaction chamber is re-purged with hydrogen and the temperature is lowered to 600° C. The multilayer silicon epitaxial wafer is removed from the reaction chamber;

[0063] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Example 1 is shown in FIG. Figure 1 As shown, the thicknesses of the doped silicon epitaxial inner layer of the multilayer silicon epitaxial wafer prepared in Example 1 at 5 points of the test were 5.552 μm, 5.255 μm, 5.356 μm, 5.275 μm, and 5.331 μm, respectively, with an average value of 5.354 μm, and the resistivity of the doped silicon epitaxial inner layer at 5 points of the test was 0.218 Ω·cm, 0.215 Ω·cm, 0.217 Ω·cm, 0.212 Ω·cm, and 0.214 Ω·cm, with an average value of 0.215 Ω·cm; The thicknesses of the doped silicon epitaxial outer layer of the silicon epitaxial wafer tested at 5 points were 17.224 μm, 17.353 μm, 17.374 μm, 17.387 μm, and 17.432 μm, respectively, with an average value of 17.354 μm. The resistivity of the doped silicon epitaxial outer layer tested at 5 points was 8.076 Ω·cm, 7.989 Ω·cm, 7.995 Ω·cm, 7.978 Ω·cm, and 7.968 Ω·cm, with an average value of 8.001 Ω·cm, which meets the requirements of the present invention.

[0064] Example 2

[0065] The method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for a power device of this embodiment comprises the following steps:

[0066] (1) Hydrogen gas was introduced into the reaction chamber of the silicon epitaxial furnace to increase the temperature, and hydrogen chloride gas was introduced to clean the reaction chamber and the graphite susceptor. The reaction chamber of the silicon epitaxial furnace was heated to 1160°C, the hydrogen flow rate was set to 3 L / min, the hydrogen chloride flow rate was set to 15 L / min, and the cleaning time was set to 150 sec.

[0067] (2) Hydrogen gas carrying trichlorosilane is introduced into the reaction chamber to grow a polysilicon coating on the graphite susceptor in the reaction chamber to complete the silicon coating of the susceptor. The hydrogen flow rate is set to 45 L / min, and the trichlorosilane flow rate is set to 10 g / min. A polysilicon coating with a thickness of 6 μm is deposited on the graphite susceptor in the reaction chamber.

[0068] (3) The reaction chamber is cooled to 600°C, and the silicon substrate is placed in the center of the sheet pit of the graphite base of the reaction chamber;

[0069] (4) Hydrogen is introduced into the reaction chamber and the temperature is raised to 1150°C again to bake the surface of the silicon substrate and purge the reaction chamber for 5 minutes;

[0070] (5) Hydrogen carries trichlorosilane as a silicon growth source to grow an undoped silicon epitaxial layer on the polished surface of a silicon substrate. The hydrogen flow rate is set to 45 L / min, the trichlorosilane flow rate is set to 7 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.6 μm.

[0071] (6) The reaction chamber was re-purged with hydrogen for 6 min, and the temperature was reduced to 1120 °C;

[0072] (7) The first doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer. The flow rate of trichlorosilane is set to 8 g / min, the flow rate of doped phosphine is 230 sccm, and the growth rate is set to 3.2 μm / min.

[0073] (8) Re-purge the reaction chamber with hydrogen for 3 min;

[0074] (9) The second doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, forming a multilayer silicon epitaxial wafer. The flow rate of trichlorosilane is set to 12 g / min, the flow rate of doped phosphine is 115 sccm, and the growth rate is set to 3.8 μm / min.

[0075] (10) The reaction chamber is re-purged with hydrogen and the temperature is lowered to 600° C. The multilayer silicon epitaxial wafer is removed from the reaction chamber;

[0076] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Example 2 is shown in FIG. Figure 2As shown, the thicknesses of the doped silicon epitaxial inner layer of the multilayer silicon epitaxial wafer prepared in Example 2 at 5 points of the test were 5.683 μm, 5.557 μm, 5.679 μm, 5.621 μm, and 5.646 μm, respectively, with an average value of 5.637 μm, and the resistivity of the doped silicon epitaxial inner layer at 5 points of the test was 0.215 Ω·cm, 0.211 Ω·cm, 0.208 Ω·cm, 0.205 Ω·cm, and 0.207 Ω·cm, with an average value of 0.209 Ω·cm; The thicknesses of the doped silicon epitaxial outer layer of the silicon epitaxial wafer tested at 5 points were 17.767 μm, 17.482 μm, 17.565 μm, 17.641 μm, and 17.574 μm, respectively, with an average value of 17.606 μm. The resistivity of the doped silicon epitaxial outer layer tested at 5 points was 7.995 Ω·cm, 7.932 Ω·cm, 7.925 Ω·cm, 7.955 Ω·cm, and 7.943 Ω·cm, with an average value of 7.950 Ω·cm, which meets the requirements of the present invention.

[0077] Example 3

[0078] The method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for a power device of this embodiment comprises the following steps:

[0079] (1) Hydrogen gas was introduced into the reaction chamber of the silicon epitaxial furnace to increase the temperature, and hydrogen chloride gas was introduced to clean the reaction chamber and the graphite susceptor. The reaction chamber of the silicon epitaxial furnace was heated to 1180°C, the hydrogen flow rate was set to 5 L / min, the hydrogen chloride flow rate was set to 20 L / min, and the cleaning time was set to 150 sec.

[0080] (2) Hydrogen gas carrying trichlorosilane is introduced into the reaction chamber to grow a polysilicon coating on the graphite susceptor in the reaction chamber to complete the silicon coating of the susceptor. The hydrogen flow rate is set to 50 L / min, and the trichlorosilane flow rate is set to 12 g / min. A polysilicon coating with a thickness of 6 μm is deposited on the graphite susceptor in the reaction chamber.

[0081] (3) The reaction chamber is cooled to 600°C, and the silicon substrate is centered in the sheet pit of the graphite base of the reaction chamber;

[0082] (4) Hydrogen is introduced into the reaction chamber and the temperature is raised to 1130°C again to bake the surface of the silicon substrate and purge the reaction chamber for 3 minutes;

[0083] (5) Hydrogen carries trichlorosilane as a silicon growth source to grow an undoped silicon epitaxial layer on the polished surface of a silicon substrate. The hydrogen flow rate is set to 50 L / min, the trichlorosilane flow rate is set to 8 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.6 μm.

[0084] (6) The reaction chamber was purged again with hydrogen for 8 min, and the temperature was reduced to 1110 °C;

[0085] (7) The first doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer. The flow rate of trichlorosilane is set to 7 g / min, the flow rate of doped phosphine is 225 sccm, and the growth rate is set to 3.1 μm / min.

[0086] (8) Re-purge the reaction chamber with hydrogen for 3 min;

[0087] (9) The second doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, forming a multilayer silicon epitaxial wafer. The flow rate of trichlorosilane is set to 12 g / min, the flow rate of doped phosphine is 115 sccm, and the growth rate is set to 3.9 μm / min.

[0088] (10) The reaction chamber is re-purged with hydrogen and the temperature is lowered to 600° C. The multilayer silicon epitaxial wafer is removed from the reaction chamber;

[0089] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Example 3 is shown in FIG. Figure 3 As shown, the thicknesses of the doped silicon epitaxial inner layer of the multilayer silicon epitaxial wafer prepared in Example 3 at 5 points of the test are 5.667μm, 5.621μm, 5.533μm, 5.587μm, and 5.592μm, respectively, with an average value of 5.600μm, and the resistivity of the doped silicon epitaxial inner layer at 5 points of the test is 0.212Ω·cm, 0.209Ω·cm, 0.207Ω·cm, 0.209Ω·cm, and 0.208Ω·cm, with an average value of 0.209Ω·cm; The thicknesses of the doped silicon epitaxial outer layer of the silicon epitaxial wafer tested at 5 points were 17.817 μm, 17.762 μm, 17.675 μm, 17.774 μm, and 17.823 μm, respectively, with an average value of 17.770 μm. The resistivity of the doped silicon epitaxial outer layer tested at 5 points was 7.964 Ω·cm, 7.925 Ω·cm, 7.945 Ω·cm, 7.936 Ω·cm, and 7.941 Ω·cm, with an average value of 7.942 Ω·cm, which meets the requirements of the present invention.

[0090] Example 4

[0091] The method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for a power device of this embodiment comprises the following steps:

[0092] (1) Hydrogen gas was introduced into the reaction chamber of the silicon epitaxial furnace to increase the temperature, and hydrogen chloride gas was introduced to clean the reaction chamber and the graphite susceptor. The reaction chamber of the silicon epitaxial furnace was heated to 1180°C, the hydrogen flow rate was set to 5 L / min, the hydrogen chloride flow rate was set to 20 L / min, and the cleaning time was set to 150 sec.

[0093] (2) Hydrogen gas carrying trichlorosilane is introduced into the reaction chamber to grow a polysilicon coating on the graphite susceptor in the reaction chamber to complete the silicon coating of the susceptor. The hydrogen flow rate is set to 50 L / min, and the trichlorosilane flow rate is set to 12 g / min. A polysilicon coating with a thickness of 6 μm is deposited on the graphite susceptor in the reaction chamber.

[0094] (3) The reaction chamber is cooled to 600°C, and the silicon substrate is centered in the sheet pit of the graphite base of the reaction chamber;

[0095] (4) Hydrogen is introduced into the reaction chamber and the temperature is raised to 1140°C again to bake the surface of the silicon substrate and purge the reaction chamber for 4 min.

[0096] (5) Hydrogen carries trichlorosilane as a silicon growth source to grow an undoped silicon epitaxial layer on the polished surface of a silicon substrate. The hydrogen flow rate is set to 50 L / min, the trichlorosilane flow rate is set to 8 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.6 μm.

[0097] (6) The reaction chamber was re-purged with hydrogen for 8 min, and the temperature was reduced to 1120 °C;

[0098] (7) The first doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer. The flow rate of trichlorosilane is set to 7 g / min, the flow rate of doped phosphine is 230 sccm, and the growth rate is set to 3.3 μm / min.

[0099] (8) Re-purge the reaction chamber with hydrogen for 4 min;

[0100] (9) The second doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, forming a multilayer silicon epitaxial wafer. The flow rate of trichlorosilane is set to 11 g / min, the flow rate of doped phosphine is 110 sccm, and the growth rate is set to 3.9 μm / min.

[0101] (10) The reaction chamber is re-purged with hydrogen and the temperature is lowered to 600° C. The multilayer silicon epitaxial wafer is removed from the reaction chamber;

[0102] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Example 4 is shown in FIG. Figure 4 As shown, the thicknesses of the doped silicon epitaxial inner layer of the multilayer silicon epitaxial wafer prepared in Example 4 at 5 points of the test were 5.778 μm, 5.825 μm, 5.814 μm, 5.819 μm, and 5.826 μm, respectively, with an average value of 5.812 μm, and the resistivity of the doped silicon epitaxial inner layer at 5 points of the test was 0.209 Ω·cm, 0.205 Ω·cm, 0.203 Ω·cm, 0.204 Ω·cm, and 0.206 Ω·cm, with an average value of 0.205 Ω·cm; The thicknesses of the doped silicon epitaxial outer layer of the silicon epitaxial wafer tested at 5 points were 17.955 μm, 17.813 μm, 17.775 μm, 17.821 μm, and 17.909 μm, respectively, with an average value of 17.854 μm. The resistivity of the doped silicon epitaxial outer layer tested at 5 points was 8.034 Ω·cm, 7.987 Ω·cm, 7.982 Ω·cm, 7.979 Ω·cm, and 7.991 Ω·cm, with an average value of 7.995 Ω·cm, which meets the requirements of the present invention.

[0103] Example 5

[0104] The method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for a power device of this embodiment comprises the following steps:

[0105] (1) Hydrogen gas was introduced into the reaction chamber of the silicon epitaxial furnace to increase the temperature, and hydrogen chloride gas was introduced to clean the reaction chamber and the graphite susceptor. The reaction chamber of the silicon epitaxial furnace was heated to 1160°C, the hydrogen flow rate was set to 5 L / min, the hydrogen chloride flow rate was set to 15 L / min, and the cleaning time was set to 125 sec.

[0106] (2) Hydrogen gas carrying trichlorosilane is introduced into the reaction chamber to grow a polysilicon coating on the graphite susceptor in the reaction chamber to complete the silicon coating of the susceptor. The hydrogen flow rate is set to 50 L / min, and the trichlorosilane flow rate is set to 12 g / min. A polysilicon coating with a thickness of 6 μm is deposited on the graphite susceptor in the reaction chamber.

[0107] (3) The reaction chamber is cooled to 600°C, and the silicon substrate is centered in the sheet pit of the graphite base of the reaction chamber;

[0108] (4) Hydrogen is introduced into the reaction chamber and the temperature is raised to 1140°C again to bake the surface of the silicon substrate and purge the reaction chamber for 5 minutes;

[0109] (5) Hydrogen carries trichlorosilane as a silicon growth source to grow an undoped silicon epitaxial layer on the polished surface of a silicon substrate. The hydrogen flow rate is set to 50 L / min, the trichlorosilane flow rate is set to 8 g / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.5 μm.

[0110] (6) The reaction chamber was re-purged with hydrogen for 5 min and the temperature was reduced to 1120 °C;

[0111] (7) The first doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer. The flow rate of trichlorosilane is set to 8 g / min, the flow rate of doped phosphine is 235 sccm, and the growth rate is set to 3.5 μm / min.

[0112] (8) Re-purge the reaction chamber with hydrogen for 5 min;

[0113] (9) The second doping pipeline configured in the reaction chamber is introduced with doped phosphine gas, which is mixed with hydrogen and trichlorosilane and the pipeline is emptied for 1 min. The doped silicon epitaxial outer layer is grown on the surface of the doped silicon epitaxial inner layer to achieve the target thickness and resistivity of the doped silicon epitaxial outer layer, forming a multilayer silicon epitaxial wafer. The flow rate of trichlorosilane is set to 12 g / min, the flow rate of doped phosphine is 120 sccm, and the growth rate is set to 4.0 μm / min.

[0114] (10) The reaction chamber is re-purged with hydrogen and the temperature is lowered to 600° C. The multilayer silicon epitaxial wafer is removed from the reaction chamber;

[0115] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Example 5 is shown in FIG. Figure 5As shown, the thicknesses of the doped silicon epitaxial inner layer of the multilayer silicon epitaxial wafer prepared in Example 5 at 5 points of the test are 5.995 μm, 5.878 μm, 5.876 μm, 5.775 μm, and 5.779 μm, respectively, with an average value of 5.861 μm, and the resistivity of the doped silicon epitaxial inner layer at 5 points of the test are 0.215 Ω·cm, 0.209 Ω·cm, 0.211 Ω·cm, 0.213 Ω·cm, and 0.212 Ω·cm, with an average value of 0.212 Ω·cm; the thicknesses of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer tested at 5 points are 17.968 μm, 17.925 μm, and 17.856 μm, respectively. μm, 17.867μm, 17.914μm, with an average value of 17.906μm, and the resistivity of the doped silicon epitaxial outer layer tested at 5 points is 8.076Ω·cm, 8.035Ω·cm, 8.026Ω·cm, 8.015Ω·cm, 8.053Ω·cm, with an average value of 8.041Ω·cm, which meets the requirements of the present invention.

[0116] Comparative Example 1

[0117] The difference between this comparative example and Example 1 is: the thickness of the silicon coating; in this comparative example, a polysilicon coating layer with a thickness of 4 μm is deposited on the graphite susceptor in the reaction chamber.

[0118] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 1 is shown in FIG. Figure 6 As shown, the resistivity of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 1 was 7.945Ω·cm, 7.821Ω·cm, 7.802Ω·cm, 7.815Ω·cm, and 7.803Ω·cm at 5 points, with an average value of 7.837Ω·cm, which does not meet the range of 7.9~8.1Ω·cm and does not meet the requirements of the present invention.

[0119] Comparative Example 2

[0120] The difference between this comparative example and Example 1 is the use of doping pipelines; the doping pipeline used for the growth of the doped silicon epitaxial outer layer in this comparative example is the same as the doping pipeline used for the growth of the doped silicon epitaxial inner layer, and both use the first doping pipeline, while Example 1 uses the first doping pipeline for the inner layer doping and the second doping pipeline for the outer layer.

[0121] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 2 is shown in FIG. Figure 7 As shown, the resistivity of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 2 was 7.778Ω·cm, 7.671Ω·cm, 7.682Ω·cm, 7.655Ω·cm, and 7.661Ω·cm at 5 points, with an average value of 7.689Ω·cm, which does not meet the range of 7.9~8.1Ω·cm and does not meet the requirements of the present invention.

[0122] Comparative Example 3

[0123] The difference between this comparative example and Example 1 is: the growth thickness of the undoped silicon epitaxial layer; the target growth thickness of the undoped silicon epitaxial layer in this comparative example is 0.4 μm.

[0124] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 3 is shown in FIG. Figure 8 As shown, the resistivity of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 3 was 7.865Ω·cm, 7.776Ω·cm, 7.781Ω·cm, 7.767Ω·cm, and 7.773Ω·cm at 5 points, with an average value of 7.792Ω·cm, which does not meet the range of 7.9~8.1Ω·cm and does not meet the requirements of the present invention.

[0125] Comparative Example 4

[0126] The difference between this comparative example and Example 1 is: epitaxial layer growth temperature; in this comparative example, the epitaxial layer growth temperature is maintained at 1130° C. and is not reduced.

[0127] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 4 is shown in FIG. Fig. 9 As shown, the resistivity of the doped silicon epitaxial outer layer of the multi-layer silicon epitaxial wafer prepared in Comparative Example 4 was 8.089Ω·cm, 7.908Ω·cm, 7.913Ω·cm, 7.882Ω·cm, and 7.886Ω·cm at 5 test points, with an average value of 7.935Ω·cm. Some test positions no longer meet the range of 7.9~8.1Ω·cm, and do not meet the requirements of the present invention.

[0128] Comparative Example 5

[0129] The difference between this comparative example and Example 1 is that the growth flow rate of trichlorosilane is different, and the corresponding growth rate is different; in this comparative example, the flow rate of trichlorosilane in step 9 is set to 9 g / min, and the growth rate is set to 3.0 μm / min, which is lower than the growth rate within the scope of the present invention.

[0130] The resistivity distribution diagram of the doped silicon epitaxial outer layer of the multilayer silicon epitaxial wafer prepared in Comparative Example 5 is shown in FIG. Fig.10 As shown, the resistivity of the doped silicon epitaxial outer layer of the multi-layer silicon epitaxial wafer prepared in Comparative Example 5 was 7.934Ω·cm, 7.919Ω·cm, 7.892Ω·cm, 7.906Ω·cm, and 7.885Ω·cm at 5 test points, with an average value of 7.907Ω·cm. Some test positions no longer meet the range of 7.9~8.1Ω·cm, and do not meet the requirements of the present invention.

[0131] Table 1 Related performance tests of multilayer silicon epitaxial wafers with super heavily phosphorus-doped substrates for power devices

[0132] Silicon coating thickness Outer doping pipeline Growth thickness of undoped silicon epitaxial layer Epitaxial layer growth temperature The flow rate of trichlorosilane during the growth of the epitaxial outer layer Five-point value of outer layer resistivity Example 1 6 2 0.5 1110 10 8.076Ω·cm, 7.989Ω·cm, 7.995Ω·cm, 7.978Ω·cm, 7.968Ω·cm Example 2 6 2 0.6 1120 12 7.995Ω·cm, 7.932Ω·cm, 7.925Ω·cm, 7.955Ω·cm, 7.943Ω·cm Example 3 6 2 0.6 1110 12 7.964Ω·cm, 7.925Ω·cm, 7.945Ω·cm, 7.936Ω·cm, 7.941Ω·cm Example 4 6 2 0.6 1120 11 8.034Ω·cm, 7.987Ω·cm, 7.982Ω·cm, 7.979Ω·cm, 7.991Ω·cm Example 5 6 2 0.5 1120 12 8.076Ω·cm, 8.035Ω·cm, 8.026Ω·cm, 8.015Ω·cm, 8.053Ω·cm Comparative Example 1 0 2 0.5 1110 10 7.945Ω·cm, 7.821Ω·cm, 7.802Ω·cm, 7.815Ω·cm, 7.803Ω·cm, Comparative Example 2 6 1 0.5 1110 10 7.778Ω·cm, 7.671Ω·cm, 7.682Ω·cm, 7.655Ω·cm, 7.661Ω·cm Comparative Example 3 6 2 0 1110 10 7.865Ω·cm, 7.776Ω·cm, 7.781Ω·cm, 7.767Ω·cm, 7.773Ω·cm Comparative Example 4 6 2 0.5 1130 10 8.089Ω·cm, 7.908Ω·cm, 7.913Ω·cm, 7.882Ω·cm, 7.886Ω·cm Comparative Example 5 6 2 0.5 1110 7 7.934Ω·cm, 7.919Ω·cm, 7.892Ω·cm, 7.906Ω·cm, 7.885Ω·cm

[0133] From the experimental results of Examples 1-5 and Comparative Examples 1-5, it can be concluded in Table 1 that the target resistivity of the outer layer of the epitaxial layer grown using the preparation technology of Examples 1-5 of the present invention is all in the range of 7.9~8.1Ω·cm, that is, the resistivity control rate reaches a difference of ≤1.2%, which reflects a significant improvement in the stability and consistency of its epitaxial structure and meets the purpose of the present invention. However, some test positions of the silicon epitaxial wafers grown by the preparation technology of Comparative Examples 1-5 no longer meet the range of 7.9~8.1Ω·cm, do not meet the requirements of the present invention, and do not meet the purpose of the present invention.

[0134] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for power devices, characterized in that: The method comprises the following steps: S1: coating the graphite susceptor in the silicon epitaxial furnace with silicon, wherein the thickness of the silicon coating on the graphite susceptor is 5-6 μm; the step S1 specifically comprises the following steps: introducing hydrogen gas carrying trichlorosilane into the reaction chamber, growing a polysilicon coating layer on the graphite susceptor in the reaction chamber, and completing the silicon coating on the graphite susceptor, wherein the flow rate of hydrogen gas is 45-50 L / min, and the flow rate of trichlorosilane is 10-12 g / min; S2: placing a silicon substrate sheet on the graphite base; S3: using hydrogen to carry trichlorosilane as a silicon growth source, growing an undoped silicon epitaxial layer on the polished surface of the silicon substrate, the flow rate of trichlorosilane is 7-8 g / min, the flow rate of hydrogen is 45-50 L / min, and the target growth thickness of the undoped silicon epitaxial layer is 0.5-0.6 μm; S4: doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber through the first doping pipeline configured in the reaction chamber, and a doped silicon epitaxial inner layer is grown on the surface of the undoped silicon epitaxial layer to achieve the target thickness and resistivity of the doped silicon epitaxial inner layer; wherein the flow rate of trichlorosilane is 7-8 g / min, the flow rate of doping phosphine is 220-250 sccm, and the growth rate is 3.0-3.5 μm / min; S5: introducing doped phosphine gas, hydrogen gas and trichlorosilane into the reaction chamber through the second doping pipeline configured in the reaction chamber, growing a doped silicon epitaxial outer layer on the surface of the doped silicon epitaxial inner layer, and achieving the target thickness and resistivity of the doped silicon epitaxial outer layer, wherein the flow rate of trichlorosilane is 10-12 g / min, the flow rate of doped phosphine is 110-120 sccm, and the growth rate is 3.6-4.0 μm / min, to obtain a super-heavy phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices; Before step S3, the reaction chamber is first purged; the first purging specifically comprises the following steps: heating the reaction chamber of the silicon epitaxial furnace to 1130-1150° C., maintaining the temperature for 3-5 min, baking the silicon substrate, and simultaneously introducing hydrogen to purge the reaction chamber; Before step S4, the reaction chamber is subjected to a second purge; the second purge specifically comprises the following steps: introducing hydrogen to purge the reaction chamber, and lowering the temperature of the reaction chamber to 1110-1120° C., and the hydrogen purge time of the reaction chamber is 5-8 minutes; In step S4, before the doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber, the first doping pipeline is emptied by introducing the doping phosphine gas, hydrogen gas and trichlorosilane; Before step S5, the reaction chamber is purged for the third time; the third purge specifically comprises the following steps: introducing hydrogen to purge the reaction chamber for 3 to 5 minutes; In step S5, before the doping phosphine gas, hydrogen gas and trichlorosilane are introduced into the reaction chamber, the second doping pipeline is emptied by introducing the doping phosphine gas, hydrogen gas and trichlorosilane.

2. The method for preparing a super heavily phosphorus-doped substrate multilayer silicon epitaxial wafer for power devices according to claim 1, characterized in that: The method also includes cleaning the reaction chamber and the graphite susceptor of the silicon epitaxial furnace before step S1; the cleaning specifically includes the following steps: introducing hydrogen into the reaction chamber of the silicon epitaxial furnace and heating it up, and then introducing hydrogen chloride gas to clean the reaction chamber and the graphite susceptor, wherein the reaction chamber of the silicon epitaxial furnace is heated to 1160-1180°C, the hydrogen flow rate is 3-5 L / min, the hydrogen chloride flow rate is 15-20 L / min, and the cleaning time is 125-150 sec.

3. The method for preparing a multilayer silicon epitaxial wafer with a super heavily phosphorus-doped substrate for power devices according to claim 1, characterized in that: The step S2 also includes cooling the reaction chamber to 600-650° C. before placing the silicon substrate on the graphite susceptor.

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