A data processing method and related device

Abstract

The present application discloses a data processing method and related devices, belonging to the field of computer technology. The disclosed related devices include a storage device, which includes: a data storage unit for storing data; a first instruction storage unit for obtaining and storing multiple data processing instructions transmitted by an external device in a batch transmission mode; a processing unit for executing an operation corresponding to the data processing instruction in the first instruction storage unit in response to first indication information for indicating the execution of the data processing instruction to process the data in the storage unit.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and in particular, relates to a data processing method and related devices. Background Art

[0002] Current memory chips such as LP-DDR (Low Power Double Data Rate SDRAM) are locally provided with a PIM (Process in memory) processing unit, which can be used to perform local operations on data in the memory chip. In the known technology, when data processing instructions are transmitted to the memory chip so that the memory chip performs local data operations based on the PIM processing unit, the transmission of the data processing instructions suffers from bandwidth efficiency loss, resulting in low bandwidth efficiency and affecting the execution efficiency of the LP-PIM data processing instructions. Summary of the invention

[0003] To this end, this application discloses the following technical solutions:

[0004] A storage device, comprising:

[0005] A data storage unit, used for storing data;

[0006] A first instruction storage unit, used for obtaining and storing a plurality of data processing instructions transmitted by an external device in a batch transmission mode;

[0007] The processing unit is used to execute the operation corresponding to the data processing instruction in the first instruction storage unit in response to the first indication information for instructing the execution of the data processing instruction to perform data processing on the data in the storage unit.

[0008] Optionally, the storage device further includes a storage unit and a control unit;

[0009] The storage unit includes a first sub-storage unit and a second sub-storage unit;

[0010] The control unit is used to control the processing unit to execute the operation corresponding to the data processing instruction in the first instruction storage unit in response to detecting that the first indication information for instructing the execution of the data processing instruction is written in the first sub-register unit; and to determine the execution status of the data processing instruction in the first instruction storage unit, and write the execution status to the second sub-register unit, so as to provide the execution status to the external device other than the storage device.

[0011] Optionally, the control unit is further configured to: in response to detecting that second indication information for indicating data access to the storage device is written in the first sub-registering unit, perform a data access operation indicated by the second indication information on the data storage unit;

[0012] The second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit is in a non-access state according to the execution state of the data processing instruction stored in the second sub-register unit.

[0013] Optionally, the first instruction storage unit includes a first queue, which is used to store multiple data processing instructions transmitted in batch transmission based on the execution order between the data processing instructions.

[0014] A control chip, comprising:

[0015] A second instruction storage unit, used for storing a plurality of data processing instructions to be sent to the storage device;

[0016] A storage controller is used to obtain multiple data processing instructions in the second instruction storage unit, and transmit the multiple data processing instructions to the storage device based on a batch transmission method, so that the processing unit in the storage device responds to the first indication information used to instruct the execution of the data processing instruction, and executes the operation corresponding to each received data processing instruction to process the data stored in the data storage unit of the storage device.

[0017] Optionally, when the storage controller transmits the plurality of data processing instructions to the storage device based on a batch transmission method, it is specifically configured to:

[0018] Obtaining the execution status of the data processing instructions in the storage device;

[0019] In response to the execution status satisfying a status condition, the plurality of data processing instructions in the control chip are transmitted to the storage device based on a batch transmission method.

[0020] Optionally, the storage controller is further configured to perform at least one of the following:

[0021] Sending first instruction information to the storage device to instruct the storage device to execute each received data processing instruction;

[0022] Sending second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit;

[0023] The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

[0024] Optionally, the second instruction storage unit includes a second queue, which is used to store multiple data processing instructions to be sent to the storage device based on the execution order between the data processing instructions.

[0025] An electronic device comprises a storage controller and a storage device, wherein the storage device comprises a first instruction storage unit, a processing unit and a data storage unit;

[0026] The storage controller is used to obtain a plurality of data processing instructions and transmit the plurality of data processing instructions to the storage device based on a batch transmission method;

[0027] The storage device is used to receive and store multiple data processing instructions transmitted by the storage controller based on the first instruction storage unit, and in response to first indication information used to instruct the execution of data processing instructions, execute operations corresponding to the data processing instructions based on the processing unit to perform data processing on the data stored in the data storage unit.

[0028] A data processing method, applied to a storage device, comprising:

[0029] Acquire and store a plurality of data processing instructions transmitted by an external device based on a batch transmission mode;

[0030] In response to first indication information for instructing the execution of data processing instructions, the processing unit of the storage device is used to execute operations corresponding to the multiple data processing instructions, so as to process the data stored in the data storage unit of the storage device by executing the operation corresponding to each data processing instruction.

[0031] A data processing method is applied to a control chip, the method comprising:

[0032] obtaining a plurality of data processing instructions to be sent to a storage device;

[0033] Based on a batch transmission method, multiple data processing instructions are transmitted to the storage device so that the processing unit in the storage device responds to the first indication information used to instruct the execution of the data processing instructions, and executes the operations corresponding to each received data processing instruction to process the data stored in the data storage unit of the storage device.

[0034] A data processing method, applied to an electronic device, comprising:

[0035] The storage controller obtains a plurality of data processing instructions, and transmits the plurality of data processing instructions to the storage device based on a batch transmission method;

[0036] The storage device receives and stores the multiple data processing instructions transmitted based on a batch transfer method based on a first instruction storage unit included therein, and in response to first indication information used to instruct the execution of the data processing instructions, executes operations corresponding to the data processing instructions based on the included processing unit to perform data processing on the data in the included data storage unit.

[0037] Optionally, the transmitting the plurality of data processing instructions to the storage device based on a batch transmission method includes:

[0038] The storage controller obtains the execution status of the data processing instructions in the storage device, and in response to the execution status satisfying the status condition, transmits multiple data processing instructions in the control chip to the storage device based on a batch transmission method.

[0039] Optionally, the data processing method further includes at least one of the following:

[0040] The storage controller sends first instruction information to the storage device to instruct the storage device to execute each received data processing instruction;

[0041] The storage controller sends second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit;

[0042] The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0044] Figure 1 It is a schematic diagram of a composition structure of a storage device provided by the present application;

[0045] Figure 2 is another schematic diagram of the composition structure of the storage device provided by the present application;

[0046] Figure 3It is a schematic diagram of the composition structure of the control chip provided by this application;

[0047] Figure 4 is an exemplary implementation structure diagram of the storage device and the control chip provided in this application;

[0048] Figure 5 It is a schematic diagram of the composition structure of LP-DDR and SOC in the known technology provided by this application;

[0049] Figure 6 It is a schematic diagram of the composition structure of the electronic device provided by this application;

[0050] Figure 7 is a flow chart of a data processing method provided by the present application for application to a storage device;

[0051] Figure 8 is a flow chart of a data processing method for a control chip provided by the present application;

[0052] Fig. 9 It is a flow chart of a data processing method provided by the present application for application in electronic devices. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] The embodiments of the present application provide a data processing method and related devices, which are used to solve the problem that when the processing unit in the memory chip in the known technology needs to realize local processing of memory data by executing instructions, the transmission efficiency of the existing data processing instructions is low, there is a loss in bandwidth efficiency, and the execution efficiency of the data processing instructions is affected. The solution of the embodiments of the present application can be applied to electronic devices in many general or special computing device environments or configurations, such as: personal computers, server computers, handheld devices or portable devices, tablet devices, multi-processor devices, etc.

[0055] The related device provided in the embodiment of the present application includes a storage device, a control chip and an electronic device.

[0056] Among them, the storage device can be a storage chip with local computing capability of an electronic device, and can specifically be but not limited to a memory chip with local computing capability or a chip in a non-memory storage scenario, such as an HBM (High Bandwidth Memory) with an HBM-PIM processing unit, and an LP DDR, low power DDR, etc. with an LP DDR-PIM processing unit suitable for mobile terminals. The embodiment of the present application will mainly take the storage device as a memory chip with local computing capability as an example to illustrate the solution.

[0057] For ease of description, the embodiments of the present application refer to memory chips with local computing capabilities, such as those with a PIM processing unit, as integrated storage and computing chips.

[0058] The control chip may be, but is not limited to, a SOC (System on Chip) of an electronic device.

[0059] See also Figure 1 As shown in the schematic diagram of the composition structure of the storage device, in the embodiment of the present application, the storage device at least includes a data storage unit 11, a first instruction storage unit 12 and a processing unit 13.

[0060] The data storage unit 11 is used to store data.

[0061] The number of data storage units 11 included in the storage device is not limited and may be one or more.

[0062] Optionally, the data storage unit 11 may be a bank in a storage-computing integrated chip. A storage-computing integrated chip usually includes multiple banks, each bank is composed of multiple memory cells, and a memory cell is a basic unit for storing data in a memory. However, it is not limited thereto, and the data storage unit may also correspond to a memory particle, and each memory particle includes multiple banks.

[0063] The first instruction storage unit 12 is used to obtain and store a plurality of data processing instructions transmitted by an external device in a batch transmission manner.

[0064] Optionally, the first instruction storage unit includes a first queue, which can be specifically used to store multiple data processing instructions transmitted in a batch transmission manner based on the execution order between the data processing instructions.

[0065] The external device may be, but is not limited to, a control chip such as a SOC.

[0066] The storage device such as the integrated storage and computing chip in the known technology does not include the first instruction storage unit 12. The embodiment of the present application adds a first instruction storage unit 12 in the storage device, such as adding a first queue, so that based on the added first instruction storage unit 12, the storage device has the ability to store multiple data processing instructions transmitted in batch transmission. Based on this capability, data processing instructions can be transmitted between the storage device and an external device such as a control chip such as an SOC based on a batch transmission method.

[0067] Among them, the multiple data processing instructions transmitted based on the batch transmission method may include data processing instructions involved in AI operations in AI (Artificial Intelligence) application scenarios, and / or data processing instructions involved in data operations in non-AI application scenarios (i.e., conventional application scenarios).

[0068] The data processing instructions in the first instruction storage unit 12 may include data transfer instructions for instructing data transfer between the data storage unit 11 and the processing unit 13 of the storage device, and data operation instructions for instructing the processing unit 13 to perform data operations.

[0069] Further, the data handling instructions can be subdivided into data read instructions and data write instructions, wherein the data read instructions are used to instruct the processing unit 13 to read data from the data storage unit 11 for data operation, and the data write instructions are used to instruct the processing unit 13 to write data (such as operation result data, intermediate data, etc.) into the data storage unit 11 for data storage. The data operation instructions may include but are not limited to instructions for instructing multiplication and accumulation operations (i.e., sum operations) on data, which may be determined according to actual operation requirements.

[0070] The processing unit 13 is used to execute the operation corresponding to the data processing instruction in the first instruction storage unit 12 in response to the first instruction information for instructing to execute the data processing instruction, so as to perform data processing on the data in the storage unit 11.

[0071] Optionally, the processing unit 13 may be a PIM processing unit in the storage-computing integrated chip, such as a programmable computing unit (PCU), which can be used to perform local operations on the data in the storage-computing integrated chip. By performing local operations on the data in the storage-computing integrated chip, the computing pressure of external devices of the storage-computing integrated chip, such as control chips such as SOC, can be reduced. At the same time, the amount of data transmission between external devices such as SOC can be reduced, thereby saving bandwidth and reducing data latency.

[0072] Optionally, multiple processing units may correspond to one first instruction storage unit, and each or multiple data storage units may correspond to one processing unit.

[0073] For the case where the storage device is a DDR, the data storage unit is a Bank within the DDR, the processing unit is a PIM processing unit (or called a PIM processor) within the DDR, and the first instruction storage unit is an additional first queue, in an optional implementation, a number of DDR modules may be set for each Channel (memory channel), and each corresponding Channel includes multiple Banks, each or multiple Banks corresponds to a PIM processing unit, and a first queue may be configured in each Channel, and a first queue configured in each Channel corresponds to each PIM processing unit in the Channel, and is used to store operation instructions corresponding to each PIM processing unit.

[0074] For example, assuming that the system of an electronic device supports dual-channel memory and there are four memory slots on the motherboard, each channel can have two slots, which can correspond to two integrated storage and computing chips.

[0075] The PIM processing unit on each channel usually executes the same instruction at the same time and performs synchronous calculations.

[0076] In addition, a register group can be set in each Channel to store relevant information (such as first indication information for indicating the execution of data processing instructions, or second indication information for indicating data access). And for multiple Channels, a local memory controller (Control) can be set for the integrated memory and computing chip with PIM processing unit. The memory controller, i.e., Control, can be used as an interface to connect multiple Channels and provide the required control functions for the processing unit, data storage unit, etc. on each Channel.

[0077] In some implementations, the storage-computing integrated chip, when it comes to local PIM operations, can transmit data processing instructions to the storage-computing integrated chip one by one, and will not transmit another instruction until one instruction operation is completed, so as to avoid instruction conflicts; this method obviously has a loss in bandwidth efficiency, which will lead to low bandwidth efficiency and affect the execution efficiency of data processing instructions.

[0078] In the embodiment of the present application, by adding a first instruction storage unit such as a first queue in the storage device, the storage device is equipped with the ability to store multiple data processing instructions transmitted by batch transmission, and supports the transmission of data processing instructions between the storage device and its external devices such as control chips such as SOC based on batch transmission. Based on this design, when a storage device such as a storage-computing integrated chip involves local calculations such as local PIM calculations, data processing instructions can be transmitted to the storage device by batch transmission, without having to transmit the data processing instructions one by one, thereby improving the transmission efficiency of the data processing instructions, avoiding bandwidth efficiency loss, and avoiding affecting the execution efficiency of the data processing instructions in the storage device, thereby improving the execution efficiency of the data processing instructions.

[0079] In an alternative embodiment, see Figure 2 As shown in the schematic diagram of the composition structure of the storage device, the storage device provided in the present application also includes a storage unit 14 and a control unit 15.

[0080] The storage unit 14 includes a first sub-storage unit 141 for storing indication information and a second sub-storage unit 142 for storing status information.

[0081] The indication information stored in the first sub-registering unit may include, but is not limited to, first indication information sent by an external device of the storage device such as a SOC for indicating the execution of a data processing instruction, and second indication information sent by the external device for indicating data access to the storage device.

[0082] The status information stored in the second sub-registering unit may include, but is not limited to, the execution status information of the data processing instructions in the first instruction storage unit 12 (such as the first queue).

[0083] Optionally, the register unit 14 may be a register (Memory Register, MR) in a memory-computing integrated chip, and the register unit 14 may include at least a first sub-register unit and a second sub-register unit, which may be different register areas of the MR respectively.

[0084] Exemplarily, this embodiment adds DB Register (Doorbell Register) and CQRegister (Status Register) in the MR area of ​​the storage device to serve as the first sub-register unit and the second sub-register unit, respectively, to store the indication information and the status information, respectively. DB is the abbreviation of Doorbell, which indicates a doorbell mechanism for giving relevant indications to the storage device (such as indicating the execution of a data processing instruction, or indicating data access to the storage device); CQ is the abbreviation of Completion Queue, which indicates the execution / completion status of the data processing instruction in the first queue.

[0085] The control unit 15 may be a local memory controller of the storage-computing integrated chip.

[0086] In an embodiment of the present application, the control unit 15 is used to execute the data processing instruction in the first instruction storage unit 12 in response to detecting that the first indication information for indicating the execution of the data processing instruction is written in the first sub-register unit, such as reading the data processing instruction and decoding the read data processing instruction, etc., and then generate a control signal, and based on the control signal, control the processing unit 13 corresponding to the data processing instruction to execute the specific operation corresponding to the data processing instruction, such as reading data, performing a multiplication operation or an accumulation operation on the read data, etc.

[0087] In actual applications, when an external device of the storage device, such as a control chip such as an SOC, needs to perform local data processing inside the storage device based on application requirements, in addition to uploading multiple data processing instructions to the storage device in batch transmission, a first indication information for indicating the execution of the data processing instruction can also be sent to the storage device as needed (the external device can specifically send the first indication information after uploading multiple data processing instructions to the storage device, or can also send the first indication information at the same time when uploading the multiple data processing instructions to the storage device), and the first indication information sent is specifically stored in the first sub-register unit of the register unit 14 in the storage device. Once the control unit 15 detects the first indication information in the first sub-register unit, it reads the data processing instructions in the first instruction storage unit 12 such as the first queue and executes them, and controls the processing unit to perform data processing based on the instruction execution process.

[0088] Taking the storage device as a storage-computing integrated chip as an example, when an external device such as SOC needs the storage-computing integrated chip to perform local processing on its data based on application requirements (such as AI computing requirements), after uploading multiple data processing to the storage-computing integrated chip through batch transmission, a first indication information for indicating the execution of data processing instructions can be further sent to the storage-computing integrated chip as needed. The first indication information sent is stored in the DB Register (first sub-register unit) of the storage-computing integrated chip. Once the local memory controller of the storage-computing integrated chip detects the first indication information in the DB Register, it reads and executes the data processing instructions in the first instruction storage unit 12 such as the first queue, and controls the corresponding PIM processing unit of the storage-computing integrated chip based on the instruction execution process to execute the specific data processing corresponding to the data processing instructions.

[0089] The processing unit 13 in the storage device, under the control of the control unit 15, specifically executes the operations corresponding to the data processing instructions based on the execution order of the data processing instructions in the first instruction storage unit 12. Among them, the multiple data processing instructions received based on the batch transmission mode are stored in the first instruction storage unit 12 in sequence based on the execution order between different data processing instructions. Therefore, the control unit 15 directly reads and executes the data processing instructions stored in the first instruction storage unit 12 in sequence, such as reading and executing the data processing instructions in the first queue in sequence, and controls the corresponding processing unit 13 such as the PIM processing unit to execute the specific operations corresponding to the data processing instructions during the execution process, so as to ensure that the execution order of each data processing instruction meets the actual order requirements of its operation logic.

[0090] In addition, optionally, the control unit 15 is also used to determine the execution status of the data processing instruction in the first instruction storage unit 12, and write the execution status to the second sub-register unit, so as to provide the execution status to an external device other than the storage device.

[0091] Optionally, the execution status of the data processing instructions in the first instruction storage unit 12 includes the execution progress of the data processing instructions in the first instruction storage unit 12 and the instruction type of the data processing instructions currently being executed. For example, for a first queue containing a total of N data processing instructions, the execution progress may include, but is not limited to, which data processing instruction in the first queue is currently being executed, or the proportion of the currently executed data processing instructions to the total number of instructions in the first queue, etc. The type of the data processing instruction may be, but is not limited to, a data handling instruction or a data operation instruction.

[0092] The N is an integer greater than 1.

[0093] Subsequently, an external device other than the storage device may determine whether to transmit the data processing instruction to the storage device based on the execution status stored in the second sub-register unit.

[0094] In summary, on the basis of adding a first instruction storage unit in the storage device, this embodiment further adds a first sub-register unit for storing indication information and a second sub-register unit for storing status information in the storage device, and designs a matching control function for the control unit of the storage device, so as to realize organic organization and coordination of the entire process of data processing instruction transmission, reception, execution, and status recording based on the first sub-register unit, the second sub-register unit, and the first instruction storage unit, and realizes a sequence mechanism based on Doorbell, and provides the execution status of the data processing instruction in the storage device to the external device through the second sub-register unit, so that the external device can send relevant instructions or instructions such as the second indication information for indicating data access based on the execution status of the data processing instruction in the storage device, effectively avoiding conflicts and improving the instruction execution efficiency of the processing unit in the storage device, such as improving the instruction execution efficiency of the LP-PIM, so as to improve the transmission efficiency of the data processing instruction and avoid the loss of bandwidth efficiency, and also avoid conflicts and further improve the instruction execution efficiency of the processing unit in the storage device.

[0095] In an optional embodiment, the control unit 15 in the storage device is further used to: in response to detecting that second indication information for indicating data access to the storage device is written in the first sub-register unit, perform a data access operation indicated by the second indication information on the data storage unit in the storage device.

[0096] The second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction stored in the second sub-register unit.

[0097] When an external device of the storage device, such as a control chip such as an SOC, has a need to access the data stored in the storage device, it can be determined whether the data storage unit in the storage device is in a window period according to the execution status of the data processing instruction in the storage device stored in the second sub-register unit of the storage device. If it is in the window period, it indicates that the data in the data storage unit is in a non-access state. Conversely, if it is not in the window period, it indicates that the data in the data storage unit is in an access state. In addition, when the data storage unit is in the window period, that is, the data in the data storage unit is in a non-access state, second indication information for indicating data access can be issued to the storage device. In an embodiment of the present application, the second indication information issued is stored in the first sub-register unit of the register unit 14. The control unit 15 in the storage device can detect and respond to the second indication information in the first sub-register unit to perform corresponding data access operations on the data storage unit 11 of the storage device, such as a read operation to read data from the data storage unit 11 or a write operation to write data to the data storage unit 11, so as to meet the data access needs of the external device to the storage device.

[0098] In some implementations, when the storage-computing chip needs to perform local data processing, it is necessary to first switch the mode of the storage-computing chip from the conventional data read-write mode to the internal processing mode, such as switching the storage-computing chip from normal LP (a conventional mode that can be used to read and write data in the storage-computing chip) to PIM operation mode (a mode for the PIM processing unit in the storage-computing chip to perform local data processing). After switching to the internal processing mode such as the PIM operation mode, the external device cannot access the data of the storage-computing chip to avoid conflicts with the data access of the PIM processing unit to the storage-computing chip. If the external device needs to access the data of the storage-computing chip, it needs to switch back to the conventional data read-write mode such as the normal LP mode, that is, the data read and write needs of the external device need to wait during the internal processing mode of the storage-computing chip such as the PIM operation period, which obviously increases the data access delay of the external device to the storage-computing chip and affects the data access efficiency of the storage-computing chip. Other storage chips with local processing capabilities also have similar characteristics.

[0099] In response to the above problems, the applicant discovered that during the execution of the instruction sequence in the first instruction storage unit 12, due to the execution cycle of the processing unit 13 such as the PIM processing unit, there is a window period for operating the data storage unit in the storage device such as the storage-computing integrated chip. For example, when the PIM processing unit executes the data operation instruction (such as the multiplication or addition operation instruction) in the instruction sequence of the first queue, the data operation is only performed inside the PIM processing unit without accessing the Bank of the storage-computing integrated chip, thereby generating a window period for the Bank operation. Accordingly, the Bank can be placed in a window period state, that is, the bank is not accessed by the PIM processing unit at this time. In response to the above problems existing in the known technology, the embodiment of the present application utilizes the window period feature of the operation of the processing unit 13 on the data storage unit 11 in the storage device such as the storage-computing integrated chip, and executes the data access operation required by an external device such as a SOC chip on the data storage unit 11 in the storage device during the window period when the data storage unit 11 is in the window period.

[0100] Specifically, when an external device such as a control chip such as an SOC has a need to access data stored in a storage device, it can determine whether the data storage unit in the storage device is in a window period based on the execution status of the data processing instruction in the storage device stored in the second sub-register unit of the storage device, and when the data storage unit is in the window period, that is, the data in the data storage unit is in a non-access state, the control unit 15 sends second indication information for indicating data access to the storage device. In response to detecting that the second indication information for indicating data access to the storage device is written in the first sub-register unit, the control unit 15 executes the data access operation indicated by the second indication information for the corresponding data processing unit.

[0101] However, it is not limited to this. In actual applications, when there is a need to access data stored in the storage device, the external device can also directly send second indication information for indicating data access to the storage device, and write the second indication information into the first sub-register unit. In response to detecting that the second indication information for indicating data access to the storage device is written in the first sub-register unit, the control unit 15 determines whether the data storage unit 11 is in a window period according to the execution status of the data processing instruction stored in the second sub-register unit, wherein specifically, it can be determined whether the data storage unit 11 is in the window period according to the type of the data processing instruction currently executed in the execution status; if the type of the data processing instruction currently executed is a data transfer instruction, the data storage unit 11 is not in the window period; if the type of the data processing instruction currently executed is a data operation instruction, the data storage unit 11 is in the window period. When the data storage unit 11 is in a window period, the data access operation indicated by the second indication information, such as a read operation or a write operation, can be performed on the data storage unit 11. If the data storage unit 11 is not in a window period, continuous detection can be performed, and when the window period is detected, the data access operation indicated by the second indication information is performed to meet the external device's access requirements to the data in the storage device.

[0102] For example, in response to detecting that second indication information for indicating data access is written in the DB Register, the local memory controller of the storage-computing chip determines whether the Bank in the storage-computing chip is in a window period according to the execution status of the instruction sequence in the CQ Register (such as the type of data processing instruction currently being executed). If so, the data access operation indicated by the second indication information is performed on the Bank. If not, the detection is continued, and when a window period is detected, the data access operation indicated by the second indication information is performed on the Bank to meet the read / write requirements of external devices such as SOC chips for data in the storage-computing chip.

[0103] This embodiment utilizes the window period feature of the processing unit's operation on the data storage unit in the storage device. During the window period, the data access operation required by the external device such as the SOC chip on the data storage unit in the storage device is performed. This can meet the data reading and writing requirements of the external device such as the SOC chip on the storage device during the local data processing (such as PIM processing) of the storage device, and will not affect the local data processing in the storage device. Therefore, there is no need to switch the mode of the storage device such as the storage and computing integrated chip such as LP-DDR, and accordingly there is no need to wait before switching back to the normal read and write mode such as normalLP. This improves the data access efficiency of the external device to the storage device in the local data processing (internal data processing) scenario of the storage device and reduces the data access latency of the external device.

[0104] Specifically, this embodiment is based on the execution status information of the data processing instructions stored in the second sub-register unit in the storage device, which allows the external device to know the execution status of the data processing instructions in the storage device, and then know the access status of the data storage unit in the storage device (such as whether it is in a window period / whether it is in an accessed state). When it is known that the data storage unit such as Bank is in a window period / non-access state, the corresponding data storage unit can be accessed, which effectively utilizes the window period characteristics of the processing unit's operation on the data storage unit in the storage device, improves the data access efficiency of the external device to the storage device, and reduces the data access delay of the external device.

[0105] See also Figure 3 As shown in the composition structure diagram of the control chip, the control chip provided in the embodiment of the present application at least includes a second instruction storage unit 21 and a storage controller 22.

[0106] The second instruction storage unit 21 is used to store a plurality of data processing instructions to be sent to the storage device at the control chip end.

[0107] Optionally, the second instruction storage unit 21 may include a second queue, which is specifically used to store a plurality of data processing instructions to be sent to the storage device based on the execution order between the data processing instructions at the control chip end.

[0108] This embodiment supports batch storage of multiple data processing instructions in the control chip by adding a second instruction storage unit 21 on the control chip, such as adding a second queue, and further supports batch transmission of the data processing instructions.

[0109] The storage controller 22 is used to obtain multiple data processing instructions in the second instruction storage unit 21, and transmit the multiple data processing instructions to the storage device based on a batch transmission method, so that the processing unit in the storage device responds to the first indication information used to instruct the execution of the data processing instruction, and executes the operations corresponding to the received data processing instructions to process the data stored in the data storage unit of the storage device.

[0110] Optionally, the control chip may be a SOC, and the storage controller 22 may be a DDRC (DDR Controller) in the SOC.

[0111] In addition to the second instruction storage unit 21 and the storage controller 22, the control chip may optionally further include a processor, such as a neural network processor (Neural Processing Unit, NPU), a deep learning processor (Deep Learning Processing Unit, DPU), etc. The number of processors included may be one or more without limitation.

[0112] In actual applications, when the processor inside the control chip (such as NPU / DPU) and / or the external processor (such as CPU) has data processing requirements and needs to use a storage device to perform local data processing inside the storage device (such as local PIM processing needs to be performed in a storage-computing integrated chip), the generated data processing instructions can be stored in the second instruction storage unit 21 added inside the control chip as needed. For example, when the NPU / DPU inside the SOC generates a series of AI operator instructions that require PIM processing based on AI computing requirements (such as a series of multiplication instructions and accumulation instructions involved in matrix multiplication operations), each AI operator instruction can be stored in the second queue added to the SOC in the order of execution.

[0113] On this basis, the storage controller 22 can obtain multiple data processing instructions in the second instruction storage unit 21, and transmit the multiple data processing instructions to the storage device based on a batch transmission method. After the subsequent storage device receives the multiple data processing instructions transmitted based on the batch transmission method, it stores them in the first instruction storage unit 12 added in the storage device in the execution order (such as the transmission order), and under the control of the control unit 15 in the storage device, the processing unit 13 is used to execute the operations corresponding to each data processing instruction in the first instruction storage unit 12, thereby realizing local processing of the data stored in the data storage unit 11 of the storage device.

[0114] For example, the DDRC in the SOC obtains each AI operator instruction in the second queue and transmits it in batches to the storage-computing integrated chip. The storage-computing integrated chip stores each received AI operator instruction in the first queue in the order of execution. Subsequently, under the control of the local memory controller of the storage-computing integrated chip, the PIM processing unit of the storage-computing integrated chip executes the operations corresponding to each AI operator instruction in the first queue to implement the required processing of the data in the Bank of the storage-computing integrated chip, such as executing the multiplication and accumulation operations respectively indicated by multiple AI operator instructions. After that, the PIM processing unit can write its operation results to the Bank so that the SOC and other external devices can read and use the operation results. By performing local data processing inside a storage device such as a storage-computing integrated chip, the data processing pressure of an external device such as a SOC can be reduced, and the amount of data transmission between a storage device such as a storage-computing integrated chip and an external device such as a SOC can be reduced, and bandwidth can be saved. For data processing tasks with the characteristics of heavy handling (large data volume, high transmission time, high bandwidth demand) and light operation (simple operation, such as addition and multiplication), this advantage will be more obvious.

[0115] This embodiment can support batch storage of multiple data processing instructions in the control chip by adding a second instruction storage unit in the control chip, such as adding a second queue, and further supports the control chip to transmit the data processing instructions based on the batch transmission mode. The improvement of the control chip end in this embodiment, combined with the improvement of the storage device end in the above text (such as adding a first instruction storage unit, a first sub-register unit, and a second sub-register unit in the storage device, and matching the functional design of the control unit in the storage device), can realize the transmission of data processing instructions from the control chip to the storage device (such as LP-DDR and other storage and computing integrated chips) through batch transmission, overcome the bandwidth efficiency loss problem existing in the known technology of issuing instructions one by one, improve the transmission efficiency of data processing instructions, avoid bandwidth efficiency loss, and avoid affecting the execution efficiency of data processing instructions in the storage device, thereby improving the execution efficiency of data processing instructions in the storage device.

[0116] In an optional embodiment, the storage controller 22 in the control chip, when transmitting the plurality of data processing instructions to the storage device based on a batch transmission method, is specifically configured to:

[0117] Obtaining the execution status of the data processing instructions in the storage device;

[0118] In response to the execution status satisfying a status condition, the plurality of data processing instructions in the control chip are transmitted to the storage device based on a batch transmission method.

[0119] Optionally, the status condition may be, but is not limited to, set to any one of the following:

[0120] Condition 1: The first instruction storage unit (such as the first queue) is idle.

[0121] If PIM processing is not performed in the storage-computing integrated chip, the first queue does not contain data processing instructions to be executed.

[0122] Condition 2: the number of executed data processing instructions in the first instruction storage unit reaches a preset number, thereby indicating that the first instruction storage unit needs to be further supplemented with data processing instructions to be executed.

[0123] Condition three: the ratio of the number of executed data processing instructions in the first instruction storage unit to the total number of instructions that can be stored in the first instruction storage unit reaches a preset ratio, thereby indicating that the first instruction storage unit needs to be further supplemented with data processing instructions to be executed.

[0124] In this embodiment, when the storage controller 22 such as DDRC needs to transmit the data processing instruction to the storage device, it can first obtain the execution status of the data processing instruction in the storage device from the second sub-register unit of the storage device, and determine whether the execution status of the data processing instruction meets the status condition. If the status condition is met, the multiple data processing instructions in the second instruction storage unit of the control chip are transmitted to the storage device based on the batch transmission method. Otherwise, the detection can be continued until the execution status of the data processing instruction in the storage device meets the status condition, and the multiple data processing instructions in the second instruction storage unit of the control chip are transmitted to the storage device based on the batch transmission method.

[0125] For example, when the DDRC in the SOC needs to transmit data processing instructions to the storage-computing integrated chip, it can first obtain the execution status of the data processing instructions in the first queue from the CQ Register of the storage-computing integrated chip, such as which data processing instruction in the first queue is currently being executed or the proportion of the currently executed data processing instructions to the total number of instructions in the first queue, and determine whether the execution status of the data processing instructions meets the status conditions. If the status conditions are met, multiple data processing instructions in the second queue of the SOC are transmitted to the storage-computing integrated chip based on the batch transmission method. Otherwise, continuous detection can be performed until the execution status of the data processing instructions in the first queue of the storage-computing integrated chip meets the status conditions, and then multiple data processing instructions in the second queue of the SOC are transmitted to the storage-computing integrated chip based on the batch transmission method.

[0126] In this embodiment, the storage controller in the control chip is functionally designed so that when the data processing instruction needs to be transmitted to the storage device, the execution status of the data processing instruction in the storage device is obtained, and in response to the execution status satisfying the status condition, multiple data processing instructions are transmitted to the storage device based on a batch transmission method. In combination with the improvement of the storage device end in this application, the data transmission between the control chip and the storage device can be controlled based on the Completion Queue (CQ) sequence mechanism. While the transmission efficiency of the data processing instructions can be improved based on the batch transmission method and the loss of bandwidth efficiency can be avoided, the appropriate transmission timing of the data processing instructions such as the LP-PIM instructions can be effectively controlled, thereby ensuring the orderly and efficient execution of the data processing instructions in the storage device.

[0127] In an optional embodiment, the storage controller 22 in the control chip is further configured to perform at least one of the following processes 11) and 12):

[0128] 11) Sending first instruction information to the storage device to instruct the storage device to execute each received data processing instruction.

[0129] In addition to sending multiple data processing instructions to storage devices such as storage and computing integrated chips, control chips such as SOCs can also send first indication information for instructing the execution of each data processing instruction to storage devices such as storage and computing integrated chips as needed.

[0130] Specifically, the first indication information sent can be stored in the first sub-register unit of the storage device, such as in DBRegister, so that the control unit in the storage device can control the processing unit in the storage device based on the first indication information to execute operations corresponding to each data processing instruction in the first instruction storage unit such as the first queue.

[0131] 12) Sending second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit. The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

[0132] When a control chip such as SOC has a need to access data stored in a storage device, the storage controller can specifically determine whether the data storage unit in the storage device is in a window period according to the execution status of the data processing instruction stored in the second sub-register unit in the storage device. The data storage unit being in the window period indicates that the data in the data storage unit is in a non-access state, and when the data storage unit is in the window period, that is, the data in the data storage unit is in a non-access state, second indication information for indicating data access can be sent to the storage device. In response to detecting the second indication information for indicating data access to the storage device, the control unit in the storage device executes the data access operation indicated by the second indication information for the corresponding data processing unit.

[0133] However, the present invention is not limited to this. In other embodiments, when a control chip such as SOC has a need to access data stored in a storage device, the storage controller in the control chip can also be used to directly send second indication information for instructing data access to the storage device. In response to detecting the second indication information, the control unit in the storage device determines whether the data storage unit in the storage device is in a window period based on the execution status of the data processing instruction in the storage device, and when it is in the window period, that is, the data in the data storage unit is in a non-access state, the data access operation indicated by the second indication information is performed on the data storage unit.

[0134] The second indication information sent by the SOC and other control chips to the storage device can be specifically stored in the first sub-register unit of the storage device, such as in the DB Register of the storage-computing integrated chip. After detecting the second indication information in the first sub-register unit such as the DB Register, the control unit in the storage device executes the data access operation indicated by the second indication information on the data storage unit, specifically during the window period of the data storage unit in the storage device, so as to meet the data access requirements of the SOC and other control chips to the storage devices such as the storage-computing integrated chip.

[0135] This embodiment ensures the coordination of instruction processing inside the storage device and the interaction between the storage device and the control chip by sending corresponding indication information to the storage device as needed through the control chip, and combining corresponding improvements on the storage device side (such as adding corresponding sub-register units in the storage device, improving the function of the control unit in the storage device, etc.), thereby ensuring the efficiency of instruction (data processing instruction) processing inside the storage device and the efficiency of interaction between the storage device and the control chip.

[0136] See also Figure 4 , provides an application example of the present application scheme.

[0137] In this application example, the storage device is LP-DDR and the control chip is SOC. Figure 5 A schematic diagram of the composition structure of LP-DDR and SOC in the known technology is provided. Compared with the known technology, this example adds a first queue SQ_LP for storing multiple data processing instructions, a first sub-register unit MR (DB) for storing indication information, and a second sub-register unit MR (CQ) for storing status information at the LP-DDR end. Optionally, when the first queue SQ_LP is added at the LP-DDR end, one SQ_LP can be added in each Channel of the LP-DDR end, such as Figure 4 As shown in the figure, the memory control unit (control) of the LP-DDR local memory has been improved accordingly. The memory controller Control can be used as an interface to connect multiple channels and can provide the required control functions for chips such as LP DDR on each channel.

[0138] At the same time, a second queue SQ_SOC for storing multiple data processing instructions is added to the SOC, and the corresponding functions of the DDRC in the SOC are improved. Among them, the XPU in the SOC may include but is not limited to the NPU and / or DPU, and the DDR phy (Double Data Rate PHY) in the SOC is a physical layer interface for controlling and managing the DDR memory interface.

[0139] Based on the above improvements to LP-DDR and SOC, this example can implement batch transmission of data processing instructions from SOC to LP-DDR, without the need to transmit data processing instructions one by one, thereby improving the transmission efficiency of data processing instructions and avoiding bandwidth efficiency loss. At the same time, it avoids affecting the execution efficiency of data processing instructions in LP-DDR, thereby improving the execution efficiency of data processing instructions.

[0140] In addition, in response to the SOC chip's data access requirements for LP-DDR, the PIM processing unit can utilize the window period characteristics of the Bank operation in LP-DDR. During the Bank's window period, the data access operation required by the SOC chip is performed, thereby improving the SOC's data access efficiency to LP-DDR in the PIM operation scenario of LP-DDR and reducing data access latency.

[0141] Regarding the functions of the components in LP-DDR and SOC, and the interaction process between LP-DDR and SOC, please refer to the description of the corresponding embodiments of the storage device and the control chip in the previous text, which will not be repeated here.

[0142] See also Figure 6A composition structure diagram of an electronic device is provided. The electronic device provided in an embodiment of the present application includes a storage device 10 and a storage controller 20.

[0143] The storage device 10 includes a data storage unit 11 , a first instruction storage unit 12 and a processing unit 13 .

[0144] The storage controller 20 is used to obtain a plurality of data processing instructions and transmit the plurality of data processing instructions to the storage device 10 based on a batch transmission method.

[0145] The storage device 10 is used to receive and store multiple data processing instructions transmitted by the storage controller 20 based on the first instruction storage unit 12, and in response to the first indication information used to instruct the execution of the data processing instruction, execute the operation corresponding to the data processing instruction based on the processing unit 13 to process the data stored in the data storage unit 11.

[0146] The first instruction storage unit 12 may be a first queue, which may be specifically used to store a plurality of data processing instructions transmitted in a batch transmission manner in the order of execution of the data processing instructions at the storage device end.

[0147] In an optional implementation, the storage device 10 further includes a storage unit and a control unit;

[0148] The storage unit includes a first sub-storage unit and a second sub-storage unit;

[0149] The control unit is used to control the processing unit to execute the operation corresponding to the data processing instruction in the first instruction storage unit in response to detecting that the first indication information for indicating the execution of the data processing instruction is written in the first sub-register unit; and to determine the execution status of the data processing instruction in the first instruction storage unit, and write the execution status to the second sub-register unit, so as to provide the execution status to an external device other than the storage device.

[0150] In an optional embodiment, the control unit is further used to: in response to detecting that second indication information for indicating data access to the storage device is written in the first sub-registering unit, perform a data access operation indicated by the second indication information on a data storage unit in the storage device;

[0151] The second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction stored in the second sub-register unit.

[0152] In an optional implementation, the electronic device further includes a control chip, the storage controller 20 is included in the control chip, and the control chip may further include but is not limited to a second instruction storage unit and a processor.

[0153] Optionally, the second instruction storage unit may be a second queue, which is specifically used to store a plurality of data processing instructions based on the execution order between the data processing instructions at the control chip end.

[0154] The processor in the control chip may include but is not limited to an NPU and / or a DPU, and the control chip may include one or more processors.

[0155] For a more detailed description of the various components and functions of the storage device in the electronic device and the various components and functions of the control chip, please refer to the description of the corresponding embodiments of the storage device and the control chip in the previous text, which will not be repeated here.

[0156] The present application also provides a data processing method for use in a storage device. Figure 7 The method flow chart shown in the figure, the data processing method comprises:

[0157] Step 701, obtaining and storing a plurality of data processing instructions transmitted by an external device based on a batch transmission mode;

[0158] Step 702: In response to first indication information for instructing the execution of data processing instructions, use the processing unit of the storage device to execute operations corresponding to the multiple data processing instructions, so as to process the data stored in the data storage unit of the storage device by executing the operation corresponding to each data processing instruction.

[0159] In an optional implementation, the using a processing unit in the storage device to execute the plurality of data processing instructions includes:

[0160] In response to detecting that first instruction information for instructing to execute a data processing instruction is stored in the first sub-register unit, controlling the processing unit to execute operations corresponding to the plurality of data processing instructions;

[0161] The first sub-registering unit is a sub-registering unit included in a registering unit in the storage device.

[0162] In an optional implementation manner, the data processing method for a storage device may further include at least one of the following:

[0163] determining an execution status of the data processing instruction, and writing the execution status into a second sub-register unit for providing the execution status to an external device other than the storage device;

[0164] In response to detecting that second indication information for instructing data access to the storage device is written in the first sub-register unit, performing a data access operation indicated by the second indication information on a data storage unit in the storage device;

[0165] Wherein, the second indication information is written to the first sub-register unit by the external device when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction stored in the second sub-register unit; the second sub-register unit is a sub-register unit included in the register unit, and the second sub-register unit is different from the first sub-register unit.

[0166] The data processing method provided in this embodiment corresponds to the storage device disclosed in this application. The relevant similarities can be found in the description of the corresponding embodiment of the storage device above, which will not be repeated here.

[0167] The present application also provides a data processing method for a control chip. Figure 8 The method flow chart shown in the figure, the data processing method comprises:

[0168] Step 801, obtaining a plurality of data processing instructions to be sent to a storage device;

[0169] Step 802: Based on a batch transmission method, multiple data processing instructions are transmitted to the storage device, so that the processing unit in the storage device responds to the first indication information for instructing the execution of the data processing instruction, and executes the operation corresponding to each received data processing instruction to process the data stored in the data storage unit of the storage device.

[0170] In an optional implementation manner, transmitting the plurality of data processing instructions to a storage device includes:

[0171] Obtaining the execution status of the data processing instructions in the storage device;

[0172] In response to the execution status satisfying a status condition, the plurality of data processing instructions are transmitted to the storage device based on a batch transmission method.

[0173] In an optional implementation manner, the data processing method for applying to a control chip may further include at least one of the following:

[0174] Sending first instruction information to the storage device to instruct the storage device to control the processing unit to perform operations corresponding to each received data processing instruction;

[0175] Sending second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the included data storage unit;

[0176] The second indication information is sent to the storage device by the storage controller in the control chip when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

[0177] The data processing method provided in this embodiment corresponds to the control chip disclosed in this application. The relevant similarities can be found in the description of the corresponding embodiment of the control chip above, which will not be repeated here.

[0178] The present application also provides a data processing method for electronic equipment. Fig. 9 The method flow chart shown in the figure, the data processing method comprises:

[0179] Step 901: The storage controller obtains a plurality of data processing instructions, and transmits the plurality of data processing instructions to the storage device based on a batch transmission method;

[0180] Step 902: The storage device receives and stores the multiple data processing instructions transmitted based on a batch transmission method based on the first instruction storage unit included therein, and in response to the first indication information used to instruct the execution of the data processing instructions, executes the operations corresponding to the data processing instructions based on the included processing unit to perform data processing on the data in the included data storage unit.

[0181] In an optional implementation manner, the step of transmitting the plurality of data processing instructions to a storage device in a batch transmission manner includes:

[0182] The storage controller obtains the execution status of the data processing instructions in the storage device, and in response to the execution status satisfying the status condition, transmits multiple data processing instructions in the control chip to the storage device based on a batch transmission method.

[0183] In an optional implementation manner, the data processing method of this embodiment further includes at least one of the following:

[0184] The storage controller sends first instruction information to the storage device to instruct the storage device to execute each received data processing instruction;

[0185] The storage controller sends second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit;

[0186] The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

[0187] The data processing method provided in this embodiment corresponds to the electronic device disclosed in the present application. Furthermore, the data processing method essentially corresponds to the storage device and the control chip included in the electronic device disclosed in the present application. The relevant similarities can be found in the description of the corresponding embodiments of the storage device and the control chip in the above text, which will not be repeated here.

[0188] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0189] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0190] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or the part that makes a creative contribution can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application or some parts of the embodiments.

[0191] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0192] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A storage device, comprising: A data storage unit, used for storing data; A first instruction storage unit, used for obtaining and storing a plurality of data processing instructions transmitted by an external device in a batch transmission mode; a processing unit, configured to execute, in response to first instruction information for instructing to execute a data processing instruction, an operation corresponding to the data processing instruction in the first instruction storage unit to perform data processing on the data in the data storage unit; The storage device further comprises: a storage unit and a control unit; The storage unit comprises: a first sub-storage unit and a second sub-storage unit; The control unit is used for: in response to detecting that second indication information for indicating data access to the storage device is written in the first sub-register unit, executing the data access operation indicated by the second indication information on the data storage unit; The second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit is in a non-access state according to the execution state of the data processing instruction stored in the second sub-register unit.

2. According to the storage device of claim 1, the control unit is further used to control the processing unit to execute the operation corresponding to the data processing instruction in the first instruction storage unit in response to detecting that the first indication information for instructing the execution of the data processing instruction is written in the first sub-register unit; and to determine the execution status of the data processing instruction in the first instruction storage unit, and write the execution status to the second sub-register unit, so as to provide the execution status to the external device outside the storage device. 3 . The storage device according to claim 1 , wherein the first instruction storage unit comprises a first queue for storing a plurality of data processing instructions transmitted in a batch transmission manner based on an execution order between the data processing instructions.

4. A control chip, comprising: A second instruction storage unit, used for storing a plurality of data processing instructions to be sent to the storage device; a storage controller, configured to obtain a plurality of data processing instructions in the second instruction storage unit, and transmit the plurality of data processing instructions to a storage device based on a batch transmission method, so that a processing unit in the storage device executes an operation corresponding to each received data processing instruction in response to first instruction information for instructing execution of the data processing instruction to perform data processing on the data stored in the data storage unit of the storage device; The storage controller is further used to send second instruction information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit; The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

5. The control chip according to claim 4, wherein the storage controller, when transmitting the plurality of data processing instructions to the storage device in a batch transmission manner, is specifically configured to: Obtaining the execution status of the data processing instructions in the storage device; In response to the execution status satisfying a status condition, the plurality of data processing instructions in the control chip are transmitted to the storage device based on a batch transmission method.

6. The control chip according to claim 4, wherein the storage controller is further configured to execute: Sending first instruction information to the storage device to instruct the storage device to execute each received data processing instruction. 7 . The control chip according to claim 4 , wherein the second instruction storage unit comprises a second queue for storing a plurality of data processing instructions to be sent to the storage device based on an execution order between the data processing instructions.

8. An electronic device, comprising a storage controller and a storage device, wherein the storage device comprises a first instruction storage unit, a processing unit and a data storage unit; The storage controller is used to obtain a plurality of data processing instructions and transmit the plurality of data processing instructions to the storage device based on a batch transmission method; The storage device is used to receive and store a plurality of data processing instructions transmitted by the storage controller based on the first instruction storage unit, and in response to first instruction information for instructing to execute the data processing instructions, execute the operations corresponding to the data processing instructions based on the processing unit to perform data processing on the data stored in the data storage unit; The storage controller is further used to send second instruction information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit; in, The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

9. A data processing method, applied to a storage device, wherein the storage device comprises a register unit; The register unit comprises: a first sub-register unit and a second sub-register unit; the method comprises: Acquire and store a plurality of data processing instructions transmitted by an external device based on a batch transmission mode; In response to first instruction information for instructing to execute a data processing instruction, using a processing unit of the storage device to execute operations corresponding to the plurality of data processing instructions, so as to process data stored in a data storage unit of the storage device by executing the operation corresponding to each data processing instruction; In response to detecting that second indication information for instructing data access to the storage device is written in the first sub-register unit, performing a data access operation indicated by the second indication information on a data storage unit in the storage device; The second indication information is written into the first sub-register unit by the external device when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction stored in the second sub-register unit.

10. A data processing method, applied to a control chip, comprising: obtaining a plurality of data processing instructions to be sent to a storage device; Based on a batch transmission mode, the plurality of data processing instructions are transmitted to the storage device, so that the processing unit in the storage device executes the operation corresponding to each received data processing instruction in response to the first instruction information for instructing to execute the data processing instruction, so as to perform data processing on the data stored in the data storage unit of the storage device; Sending second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the included data storage unit; The second indication information is sent to the storage device by the storage controller in the control chip when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

11. A data processing method, applied to an electronic device, comprising: The storage controller obtains a plurality of data processing instructions, and transmits the plurality of data processing instructions to the storage device based on a batch transmission method; The storage device receives and stores the plurality of data processing instructions transmitted based on a batch transmission mode based on a first instruction storage unit included therein, and executes operations corresponding to the data processing instructions based on a processing unit included therein in response to first instruction information for instructing to execute the data processing instructions, so as to perform data processing on the data in the data storage unit included therein; The storage controller sends second indication information to the storage device to instruct the storage device to perform a data access operation on the data in the corresponding data storage unit; The second indication information is sent to the storage device by the storage controller when it is determined that the data in the data storage unit in the storage device is in a non-access state according to the execution state of the data processing instruction in the storage device.

12. The data processing method according to claim 11, wherein the step of transmitting the plurality of data processing instructions to a storage device in batch transmission comprises: The storage controller obtains the execution status of the data processing instructions in the storage device, and in response to the execution status satisfying the status condition, transmits multiple data processing instructions in the control chip to the storage device based on a batch transmission method.

13. The data processing method according to claim 11, further comprising: The storage controller sends first instruction information to the storage device to instruct the storage device to execute each received data processing instruction.

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