Code running method and device, electronic equipment and readable medium
By comparing the running speeds of microcontrollers and Flash memory, selecting the appropriate reading strategy to read the code directly from the Flash memory, solving the problem of limited code running speed in the prior art and improving the running efficiency.
Patent Information
- Application Number
- CN202411261372.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2024-12-27
AI Technical Summary
In the prior art, the operating state of Flash memory and microcontroller cannot be flexibly adapted, resulting in the code running speed being affected.
By comparing the code running speed of the microcontroller with the code reading speed of the Flash memory, select an appropriate reading strategy based on the comparison results, and directly read and run the code data from the Flash memory to avoid pre-reading operations.
It improves the running efficiency of Flash memory code data, flexibly adapts to the running state of Flash memory and microcontrollers, and improves the running speed of code.
Smart Images
Figure CN119201272A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of computer technology, and in particular to a code running method, a running device, an electronic device, and a readable medium. Background Art
[0002] Flash memory is a non-volatile storage technology used to store code data. In the related art, the corresponding code data is usually pre-read from the Flash memory and stored in the RAM (Random Access Memory), so that the microcontroller unit (MCU) can directly read the code data from the RAM when running the code. However, the above method cannot flexibly adapt to the operating state of the Flash memory and the microcontroller, which affects the code running speed. Summary of the invention
[0003] To this end, the embodiments of the present disclosure provide a code running method, a running device, an electronic device, and a readable medium to solve the problem of affecting the code running speed in the prior art.
[0004] In order to achieve the above-mentioned purpose, the first aspect of the embodiment of the present disclosure provides a code running method, including:
[0005] Obtaining the code running speed of the microcontroller;
[0006] Comparing the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result;
[0007] In the case where the comparison result meets the preset condition, selecting a first reading strategy corresponding to the preset condition from the preset reading strategies, and directly reading and running the code data from the Flash memory through the first reading strategy;
[0008] The preset read strategy further includes: a second read strategy for pre-reading the code data in the Flash memory to a preset storage space when the comparison result does not meet the preset condition, so as to read and run the code data from the preset storage space.
[0009] In some embodiments, the comparison result satisfies a preset condition including: a difference between the code running speed of the microcontroller and the code reading speed of the Flash memory is within a preset threshold range;
[0010] The directly reading and running code data from the Flash memory by using the first reading strategy includes:
[0011] In the case where the code reading speed is greater than the code running speed, the first code data corresponding to the current read cycle is directly read from the Flash memory and run through the first reading strategy, and the reading operation of the second code data corresponding to the next read cycle stored in the Flash memory is controlled through the reading control information.
[0012] In some embodiments, controlling the read operation of the second code data corresponding to the next read cycle stored in the Flash memory by reading the control information includes:
[0013] Before the first code data is executed, a pause type of read control information is sent to the SPI bus used to read the Flash memory, so as to control the SPI bus to pause the operation of reading the second code data corresponding to the next read cycle from the Flash memory;
[0014] After the first code data is executed, read control information of a recovery type is sent to the SPI bus to control the SPI bus to resume the operation of reading the second code data corresponding to the next read cycle from the Flash memory.
[0015] In some embodiments, the sending of pause-type read control information to the SPI bus for reading the Flash memory includes: configuring a first read clock of the SPI control to be in an off state so that the SPI control turns off a second read clock corresponding to the SPI bus; wherein the SPI control is provided in the microcontroller and is used to control a data read operation of the SPI bus;
[0016] The sending of the recovery type read control information to the SPI bus includes: configuring a first read clock of the SPI control to be in an on state so that the SPI control can start a second read clock corresponding to the SPI bus.
[0017] In some embodiments, directly reading and running code data from the Flash memory using the first reading strategy specifically includes:
[0018] After the first code data transmitted in the current read cycle is directly read from the Flash memory by the first read strategy and executed, if the comparison result between the data address of the first code data transmitted in the current read cycle and the data address of the target code data to be read in the next read cycle satisfies the preset address jump condition, the target code data to be read in the next read cycle is read and executed in combination with the preset cache space;
[0019] The preset cache space is used to store the first code data that has been read and executed and the data address of the first code data in the Flash memory.
[0020] In some embodiments, the step of reading and executing the target code data to be read in the next read cycle in combination with the preset cache space includes:
[0021] Determine a matching result between a data address of the target code data to be read in the next read cycle and a preset cache space;
[0022] When the matching result is a successful match, reading and executing the target code data from the preset cache space;
[0023] When the matching result is a matching failure, the target code data is directly read from the Flash memory and executed.
[0024] In some embodiments, directly reading and running code data from the Flash memory using the first read strategy includes:
[0025] In the case where the code data is the starting code data corresponding to a data acquisition cycle, the address information corresponding to the data acquisition cycle is sent to the Flash memory through the first reading strategy, so as to sequentially read and run the code data corresponding to the address information fed back by the Flash memory according to the reading cycle within the data acquisition cycle.
[0026] In a second aspect, an embodiment of the present disclosure provides a code execution device, wherein the code execution device is arranged in a microcontroller, and the code execution device comprises:
[0027] An acquisition unit, used for acquiring a code running speed of the microcontroller;
[0028] A comparison unit, used for comparing the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result;
[0029] An operating unit is used to select a first reading strategy corresponding to the preset condition from the preset reading strategies when the comparison result satisfies the preset condition, and directly read and run the code data from the Flash memory through the first reading strategy; wherein the preset reading strategy also includes: a second reading strategy, used to pre-read the code data in the Flash memory to a preset storage space when the comparison result does not satisfy the preset condition, so as to read and run the code data from the preset storage space.
[0030] In a third aspect, an embodiment of the present disclosure provides an electronic device, including:
[0031] One or more processors; a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the above-mentioned code running method;
[0032] One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.
[0033] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein the program implements the above-mentioned code running method when executed by a processor.
[0034] When the embodiment of the present disclosure runs the code, first, the code running speed of the microcontroller is obtained, so as to compare the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result, and then, when the comparison result meets the preset condition, a first reading strategy corresponding to the preset condition is selected from the preset reading strategy, and the code data is directly read and run from the Flash memory through the first reading strategy. It can be seen that when the embodiment of the present disclosure runs the code, the code running speed of the microcontroller and the code reading speed of the Flash memory can be comprehensively considered, so as to directly read and run the code data from the Flash memory when the comparison result meets the preset condition, thereby avoiding the pre-reading operation of the code data of the Flash memory and improving the running efficiency of the code data of the Flash memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The accompanying drawings are used to provide further understanding of the present disclosure and constitute a part of the specification. They are used to explain the present disclosure together with the following detailed description, but do not constitute a limitation of the present disclosure.
[0036] Figure 1 A flowchart of a code running method provided in an embodiment of the present disclosure;
[0037] Figure 2 A flowchart of some steps in a code running method provided in an embodiment of the present disclosure;
[0038] Figure 3 A flowchart of some steps in a code running method provided in an embodiment of the present disclosure;
[0039] Figure 4 A flowchart of some steps in a code running method provided in an embodiment of the present disclosure;
[0040] Figure 5A flowchart of some steps in a code running method provided in an embodiment of the present disclosure;
[0041] Figure 6 A flowchart of some steps in a code running method provided in an embodiment of the present disclosure;
[0042] Figure 7 A flowchart of some steps in a code running method provided in an embodiment of the present disclosure;
[0043] Figure 8 A schematic diagram of a code running method provided in an embodiment of the present disclosure;
[0044] Fig. 9 A schematic diagram of a code running device provided in an embodiment of the present disclosure;
[0045] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0046] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0047] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0048] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure.As used in the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
[0049] When the terms “comprising” and / or “made of…” are used in the present disclosure, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.
[0050] The embodiments described in the present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic diagrams of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.
[0051] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.
[0052] In some related technologies, when the code is running, the corresponding code data is pre-read from the Flash memory and stored in the RAM, so that the microcontroller can directly read the code data from the RAM when running the code. However, the above code method cannot flexibly adapt to the running state of the Flash memory and the microcontroller, which affects the code running speed.
[0053] In a first aspect, an embodiment of the present disclosure provides a code execution method, which is applied to a microcontroller. Figure 1 A flowchart of a code running method provided by an embodiment of the present disclosure is shown. Figure 1 As shown, the method specifically includes:
[0054] Step S1: Get the code running speed of the microcontroller.
[0055] The code running speed of a microcontroller is used to characterize how fast the microcontroller runs the code data. The code running speed of a microcontroller depends on many factors, such as the architecture of the microcontroller, the instruction set, the system clock frequency, etc.
[0056] It should be noted that when obtaining the code running speed of the microcontroller, a timer can be set to measure the execution time interval required for the microcontroller to execute a preset amount of code data, thereby obtaining the code running speed of the microcontroller based on the ratio of the preset data amount to the execution time.
[0057] It should also be noted that the embodiments of the present disclosure do not limit the number of times the code running speed of the microcontroller is obtained. The code running speed of the microcontroller can be obtained only once. For example, for a certain section of code data, the code running speed of the microcontroller is obtained before reading and running the code data. The code running speed of the microcontroller can also be obtained multiple times. For example, for a certain section of code data, after reading and running part of the data of the code data each time according to the reading cycle, the corresponding code running speed is obtained.
[0058] Step S2: Compare the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result.
[0059] The code reading speed of the Flash memory refers to the speed at which the microcontroller reads code data from the Flash memory through the SPI bus (Serial Peripheral Interface), which is used to characterize how fast the microcontroller reads code data.
[0060] It should be noted that the disclosed embodiments do not impose any specific restrictions on the method for determining the code reading speed of the Flash memory. For example, the code reading speed of the Flash memory can be determined based on the SPI clock frequency (i.e., the number of clock cycles corresponding to the SPI per second) and the number of lines used for SPI data transmission. Exemplarily, the SPI clock frequency is 50 MHz (megahertz), and the data transmission uses 4-line reading, then its code speed is 50 MHz × 4 bits (bits) = 23.84 MB / s. For another example, a timer can be set to measure the reading time required to read a preset amount of code data from the Flash memory, thereby obtaining the code reading speed of the Flash memory through the ratio of the preset amount of data to the reading time.
[0061] Among them, by comparing the code running speed of the microcontroller with the code reading speed of the Flash memory, the relative speed between the code running speed and the code reading speed can be determined, thereby obtaining a comparison result.
[0062] The comparison result is expressed in numerical form, which may be the difference between the code running speed and the code reading speed, or the ratio between the code running speed and the code reading speed, which is not limited in the embodiments of the present disclosure.
[0063] Step S3: When the comparison result meets the preset condition, a first read strategy corresponding to the preset condition is selected from the preset read strategies, and the code data is directly read and executed from the Flash memory through the first read strategy; wherein the preset read strategy also includes: a second read strategy, which is used to pre-read the code data in the Flash memory to a preset storage space when the comparison result does not meet the preset condition, so as to read and execute the code data from the preset storage space.
[0064] The preset condition is used to indicate that the comparison result satisfies a preset relative speed relationship between the code running speed and the code reading speed.
[0065] In some possible implementations, when the comparison result is the difference between the code running speed and the code reading speed, the preset condition may be that the comparison result is within a preset threshold range, that is, the difference between the code running speed of the microcontroller and the code reading speed of the Flash memory is within the preset threshold range.
[0066] It should be noted that the preset threshold range can be adaptively set according to actual application needs, and the embodiments of the present disclosure are not limited to this.
[0067] Exemplarily, the preset threshold range is set to [-A, A], so that when the difference between the code running speed and the code reading speed of the Flash memory is within the preset threshold range, it is determined that the comparison result meets the preset condition.
[0068] Among them, the first reading strategy corresponding to the preset condition can also be called a direct reading strategy. When the comparison result meets the preset condition, it indicates that the speed difference between the code running speed and the code reading speed is small. Therefore, through the first reading strategy, the code data is directly read and run from the Flash memory, avoiding the pre-reading operation of the code data of the Flash memory, thereby improving the code execution efficiency.
[0069] The second read strategy can also be called a pre-read strategy. When the comparison result does not meet the preset condition, it indicates that the speed difference between the code running speed and the code reading speed is large. Therefore, based on the second read strategy, the code data in the Flash memory can be pre-read to the preset storage space, so as to read and run the code data in the preset storage space.
[0070] It should also be noted that the preset storage space can be adaptively set according to actual application needs, and the embodiments of the present disclosure do not limit this. Exemplarily, the preset storage space can be a cache space Cache or a random access memory RAM.
[0071] In the embodiments of the present disclosure, when the code is running, the code running speed of the microcontroller and the code reading speed of the Flash memory can be comprehensively considered, so that when the comparison result meets the preset conditions, the code data is directly read and run from the Flash memory, avoiding the pre-reading operation of the code data of the Flash memory and improving the running efficiency of the code data of the Flash memory.
[0072] In addition, in order to achieve better technical effects, those skilled in the art may also make various changes and modifications to the above embodiments:
[0073] In an optional implementation, in order to avoid the situation where the code reading speed is greater than the code running speed, resulting in code running errors, when the code data is read and run directly from the Flash memory through the first read strategy, when reading and running the first code data corresponding to the current read cycle, the reading operation of the second code data corresponding to the next read cycle stored in the Flash memory can be controlled by reading control information.
[0074] Figure 2 is a flowchart of step S3 in the embodiment of the present disclosure, refer to Figure 2 , step S3 comprises:
[0075] Step S31: When the difference between the code running speed of the microcontroller and the code reading speed of the Flash memory is within a preset threshold range, a first reading strategy corresponding to the preset condition is selected from the preset reading strategies, and when the code reading speed is greater than the code running speed, the first code data corresponding to the current reading cycle is directly read and run from the Flash memory through the first reading strategy, and the reading operation of the second code data corresponding to the next reading cycle stored in the Flash memory is controlled by reading the control information.
[0076] in, Figure 2 The methods used in steps S1 and S2 are the same as those in the above-mentioned steps S1 and S2, and are not described in detail here.
[0077] Among them, when the difference between the code running speed of the microcontroller and the code reading speed of the Flash memory is within the preset threshold range, it indicates that the comparison result between the code running speed and the code reading speed at this time meets the preset conditions. Therefore, the first reading strategy can be used to read the code data.
[0078] When reading and running the code data, due to the limitation of the amount of the code data, the microcontroller needs to read and run part of the code data in sequence according to the reading cycle.
[0079] Exemplarily, the data addresses corresponding to the code data in the Flash memory are addresses 0, 1, and 2. Therefore, when reading and running the code data, the code data corresponding to address 0 can be read and run first, and then the code data corresponding to addresses 1 and 2 can be read and run in sequence according to the address order.
[0080] The current read cycle refers to the time corresponding to the microcontroller performing the current code data read operation from the Flash memory. The next read cycle refers to the time corresponding to the microcontroller performing the next code data read operation from the Flash memory after the current code data read operation is completed.
[0081] It should be noted that the current read cycle and the next read cycle are only used to characterize the order in which the microcontroller reads from the Flash memory. The time lengths corresponding to the two are the same, and the time values corresponding to the current read cycle and the next read cycle change dynamically.
[0082] For example, if the current read cycle is the time corresponding to reading the code data at address 0, the next read cycle is the time corresponding to reading the code data at address 1. Correspondingly, after the code data at address 0 is read, when the code data at address 1 is read, the read time corresponding to the code data is the current read cycle, and the next read cycle is the time corresponding to reading the code data at address 2.
[0083] It should also be noted that the length of time between the current read cycle and the next read cycle depends on the amount of code data read corresponding to the data read operation. For example, when the microcontroller reads code data from the Flash memory via the SPI bus, if the number of lines used for SPI data transmission is 4-line reading, and 1 byte of code data is read each time, the current read cycle and the next read cycle both correspond to two SPI clock cycles.
[0084] The first code data corresponding to the current reading cycle refers to the code data read by the microcontroller from the Flash memory in the current reading cycle.
[0085] The second code data refers to the code data corresponding to the next read cycle stored in the Flash memory.
[0086] Exemplarily, the data addresses in the Flash memory corresponding to the code data are addresses 0, 1, and 2. Therefore, if the current read operation needs to read the code data corresponding to address 0, the code data is the first code data corresponding to the current read cycle, and the code data corresponding to address 1 is the second code data corresponding to the next read cycle.
[0087] Among them, whether the code reading speed is greater than the code running speed can be judged by the positive or negative value of the difference between the code running speed and the code reading speed.
[0088] The inventor discovered in the process of implementing the present invention that, when the code reading speed is greater than the code running speed, the microcontroller may have read the second code data corresponding to the next read cycle from the Flash memory, but the microcontroller has not yet executed the first code data corresponding to the current read cycle. At this time, if the microcontroller continues to read the code data from the Flash memory, the read code data will not match the code data to be run, thereby causing a code execution exception.
[0089] Therefore, in order to solve the above problem, in the present application, if it is necessary to read the second code data corresponding to the next read cycle from the Flash memory, the reading operation of the second code data corresponding to the next read cycle stored in the Flash memory can be controlled by reading the control information to avoid the situation where the code data read by the microcontroller does not match the code data to be run.
[0090] When the code reading speed is less than or equal to the code running speed, if the second code data corresponding to the next reading cycle needs to be read from the Flash memory, the reading operation of the first code data can be directly performed without controlling the reading operation.
[0091] In an optional implementation, in order to effectively control the reading operation of the second code data, a preset type of reading control information may be sent to the SPI bus to control the data reading operation of the SPI bus.
[0092] Figure 3 FIG. 1 is a flowchart of controlling the reading operation of the second code data corresponding to the next reading cycle stored in the Flash memory by reading the control information in step S31 in the embodiment of the present disclosure, referring to FIG. Figure 3 Step S31 controls the reading operation of the second code data corresponding to the next reading cycle stored in the Flash memory by reading the control information, specifically including:
[0093] Step S311: before the first code data is executed, a pause type of read control information is sent to the SPI bus for reading the Flash memory, so as to control the SPI bus to pause the operation of reading the second code data corresponding to the next read cycle from the Flash memory.
[0094] Among them, before the first code data is completed, it can be defined in many ways. For example, before the first code data is completed, it can be: after reading the first code data corresponding to the current read cycle from the Flash memory, or it can be during the operation of the first code data corresponding to the current read cycle. The embodiment of the present disclosure does not limit this.
[0095] Among them, the pause type reading control information is used to configure the data transmission signal related to the SPI bus to a signal state corresponding to pausing data transmission, so that the SPI bus suspends the operation of reading the second code data corresponding to the next read cycle from the Flash memory according to the signal state of the data transmission signal.
[0096] Step S312: After the first code data is executed, the read control information of the recovery type is sent to the SPI bus to control the SPI bus to resume the operation of reading the second code data corresponding to the next read cycle from the Flash memory.
[0097] Among them, the recovery type read control information is used to configure the data transmission signal related to the SPI bus to restore the signal state corresponding to the data transmission, so that the SPI bus resumes the operation of reading the second code data corresponding to the next read cycle from the Flash memory according to the signal state of the data transmission signal.
[0098] In an optional implementation, in order to improve the control efficiency of the operation of the SPI bus reading the second code data corresponding to the next read cycle from the Flash memory, the read clock corresponding to the SPI bus may be configured by reading the control information.
[0099] Figure 4 Flow chart of steps S311 and S312 in the present disclosure embodiment sending read control information to the SPI bus for reading the Flash memory, refer to Figure 4 , step S311 sends a pause type of read control information to the SPI bus used to read the Flash memory, specifically including:
[0100] Step S311′: configure the first read clock of the SPI control to be in a closed state, so that the SPI control can close the second read clock corresponding to the SPI bus.
[0101] Step S312 sends the read control information of the recovery type to the SPI bus, specifically including:
[0102] Step S312′: configure the first read clock of the SPI control to be in an on state, so that the SPI control can start the second read clock corresponding to the SPI bus.
[0103] The SPI control is also called the Spi Ctrl register, which is a register used to configure and control the SPI bus. The SPI control is set in the microcontroller, which can be used to control the data reading operation, clock signal, data frame format, etc. of the SPI bus.
[0104] The first read clock of the SPI control is used to control the second read clock of the SPI bus. When the first read clock of the SPI control is in a paused state, the second read clock of the SPI bus is also in a paused state, and when the first read clock of the SPI control is in a resumed state, the second read clock of the SPI bus is also in a resumed state.
[0105] The second read clock of the SPI bus is used to synchronize data transmission and control the operation state of the SPI bus.
[0106] When the second read clock of the SPI bus is in the pause state, the SPI bus pauses the operation of reading the second code data corresponding to the next read cycle from the Flash memory. When the first read clock of the SPI control is in the resume state, the SPI bus resumes the operation of reading the second code data corresponding to the next read cycle from the Flash memory.
[0107] In an optional implementation, when reading code data from the Flash memory, address jumps are likely to occur. At this time, in order to improve the efficiency of reading code data in the case of address jumps, the code data can be further read in combination with a preset cache space, wherein the preset cache space is used to store the first code data that has been read and run and the data address of the first code data in the Flash memory.
[0108] Figure 5 is a flowchart of step S3 in the embodiment of the present disclosure, refer to Figure 5 , step S3 comprises:
[0109] Step S41: When the comparison result satisfies the preset condition, a first read strategy corresponding to the preset condition is selected from the preset read strategies, and after the first code data transmitted in the current read cycle is directly read from the Flash memory and executed through the first read strategy, if the comparison result between the data address of the first code data transmitted in the current read cycle and the data address of the target code data to be read in the next read cycle satisfies the preset address jump condition, the target code data to be read in the next read cycle is read and executed in combination with the preset cache space.
[0110] in, Figure 5 The methods used in steps S1 and S2 are the same as those in the above-mentioned steps S1 and S2, and are not described in detail here.
[0111] The data address of the first code data is the data address corresponding to the first code data in the Flash memory.
[0112] The target code data refers to the code data to be read by the microcontroller in the next read cycle. The data address of the target code data is the data address corresponding to the code data in the Flash memory.
[0113] It should be noted that the target code data is similar to the second code data mentioned above, and both are used to refer to the code data to be read by the microcontroller in the next read cycle. Therefore, the data content of the two is the same. The main difference between the two is that the target code data refers to the code data to be read by the microcontroller in the next read cycle, which may be stored in the Flash memory or in a preset cache space; while the second code data is stored in the Flash memory, which may not be read by the microcontroller in the next read cycle.
[0114] The preset cache space is used to store the first code data that has been read and run and the data address of the first code data in the Flash memory. Since the time of the current read cycle changes dynamically, each time the microcontroller performs a code data read operation, the corresponding time is the current read cycle. Therefore, after each code data read operation of the microcontroller, the code data, i.e., the first code data transmitted in the current read cycle, will be stored in the preset cache space, so that all the first code data that has been read and run and their data addresses are stored in the preset cache space.
[0115] Correspondingly, if the target code data to be read by the microcontroller in the next read cycle is the code data that has been read and run by the microcontroller in the previous read cycle, at this time, the target code data is stored in both the Flash memory and the preset cache space. Therefore, the microcontroller can choose to read the code data in the Flash memory or the preset cache space, so that when the microcontroller chooses to read the code data in the preset cache space, the second code data stored in the Flash memory will not be read by the microcontroller.
[0116] The comparison result between the data address of the first code data transmitted in the current read cycle and the data address of the target code data to be read in the next read cycle satisfies the preset address jump condition, which means that the data address of the target code data is a non-continuous address of the data address of the first code data.
[0117] For example, the data address of the first code data is address 12, and the data address of the target code data is address 5. At this time, the data address of the target code data is a non-continuous address of the data address of the first code data, and the comparison result between the data address of the first code data and the data address of the target code data satisfies the preset address jump condition.
[0118] For another example, the data address of the first code data is address 12, and the data address of the target code data is address 13. At this time, the data address of the target code data is a continuous address of the data address of the first code data, and the comparison result between the data address of the first code data and the data address of the target code data does not meet the preset address jump condition.
[0119] When the comparison result between the data address of the first code data and the data address of the target code data satisfies the preset address jump condition, the target code data to be read in the next read cycle can be read and executed in combination with the preset cache space.
[0120] In an optional implementation, when reading and executing the target code data to be read in the next read cycle in combination with the preset cache space, it can be determined whether to read and execute the target code data from the preset cache space based on the matching result between the data address of the target code data to be read in the next read cycle and the preset cache space.
[0121] Figure 6 This is a flowchart of step S41 in the embodiment of the present disclosure, which combines the preset cache space to read and run the target code data to be read in the next read cycle, with reference to Figure 6 Step S41 reads and runs the target code data to be read in the next read cycle in combination with the preset cache space, specifically including:
[0122] Step S411: Determine a matching result between a data address of target code data to be read in a next read cycle and a preset cache space.
[0123] Step S412: When the matching result is successful, the target code data is read and executed from the preset cache space.
[0124] Step S413: When the matching result is a match failure, the target code data is directly read and executed from the Flash memory.
[0125] The matching result between the data address of the target code data to be read in the next read cycle and the preset cache space is used to indicate whether the target code data is stored in the preset cache space. The matching result between the data address of the target code data and the preset cache space is obtained by matching the data address of the target code data with the data address of the code data stored in the preset cache space.
[0126] When the matching result is a successful match, it indicates that the target code data has been stored in the preset cache space. At this time, the target code data can be directly read and run from the preset cache space to improve the code data reading efficiency. When the matching result is a failed match, it indicates that the target code data is not stored in the preset cache space. At this time, the target code data still needs to be read and run from the Flash memory.
[0127] In an optional implementation, when reading code data from a Flash memory, the code data corresponds to a continuous storage address. At this time, in order to improve the efficiency of reading code data from the Flash memory, the address information corresponding to the data acquisition cycle can be sent to the Flash memory, so that the code data can be read and run in sequence according to the read cycle within the data acquisition cycle.
[0128] Figure 7 is a flowchart of step S3 in the embodiment of the present disclosure, refer to Figure 7 , step S3 comprises:
[0129] Step S51: When the comparison result satisfies the preset condition, a first read strategy corresponding to the preset condition is selected from the preset read strategies, and when the code data is the starting code data corresponding to the data acquisition cycle, the address information corresponding to the data acquisition cycle is sent to the Flash memory through the first read strategy, so as to read and run the code data corresponding to the address information fed back by the Flash memory in sequence according to the read cycle within the data acquisition cycle.
[0130] in, Figure 7 The methods used in steps S1 and S2 are the same as those in the above-mentioned steps S1 and S2, and are not described in detail here.
[0131] The fetch cycle refers to the time period for reading a segment of code data with continuous addresses. The fetch cycle includes at least one read cycle. The start code data refers to the first code data to be read corresponding to the fetch cycle.
[0132] It should be noted that when determining that the code data is the starting code data corresponding to the data acquisition cycle, the data address of the code data can be compared with the data address of the first code data corresponding to the current read cycle to see if they are continuous. In the case of discontinuous addresses, it can be determined that the code data is the starting code data corresponding to the data acquisition cycle.
[0133] Among them, the address information corresponding to the data acquisition cycle is determined in the following manner: the data address corresponding to the code data is used as the starting address of the address information and the data address to be compared, starting from the code data, it is determined in sequence whether the data address to be compared is continuous with the data address of the code data in the next reading sequence. If the data addresses are continuous, the data address of the code data in the next reading sequence is used as the new data address to be compared and added to the address information. If the data addresses are not continuous, the above-mentioned address information determination step is stopped.
[0134] Therefore, the embodiment of the present disclosure can divide the code data with continuous addresses into the same data acquisition cycle for data reading according to the address continuity of the data address of the data to be read, so that only by sending the address information corresponding to the data acquisition cycle to the Flash memory once, multiple code data corresponding to the data acquisition cycle can be read sequentially, thereby improving the reading efficiency of the code data.
[0135] To facilitate understanding, an example is used below to introduce the implementation of the above embodiment.
[0136] In the related art, when the code is running, the corresponding code data will be pre-read from the Flash memory and stored in the storage space, so that the microcontroller can directly read the code data from the storage space when running the code. For example, there is a Flash pre-read operation inside the single-chip microcomputer, so that the Flash code segment is read in advance and placed in the cache. When the MCU runs the code, it reads directly from the cache, thereby speeding up the reading and running speed of the single-chip microcomputer. For another example, in a computer / linux embedded system, the code must first be read from the Flash, copied to the RAM, and then the execution code is read in the RAM.
[0137] However, the above code method cannot flexibly adapt to the running status of the Flash memory and the microcontroller, which affects the code running speed. Therefore, in order to solve the above problem, this example proposes a code running method. When the code reading speed of the Flash memory is close to the code running speed of the MCU, the MCU directly reads the running code from the Flash memory without the need for code pre-reading operation.
[0138] Figure 8 A schematic diagram of the code running method in this example is shown, where Figure 8 The meanings of the signals involved are as follows:
[0139] Cache: A preset cache space used to store the code data and its address that have been read and run;
[0140] memaddr[15:0]: data address of the code data that the MCU needs to access;
[0141] memdata[7:0]: code data corresponding to the data address obtained by MCU;
[0142] mempsack: MCU program address read response signal;
[0143] miss: MCU checks whether the corresponding code address exists in the cache space;
[0144] flash_ack: SPI bus reads the valid signal of each byte of code data in the Flash memory;
[0145] 1'b1: The preset cache space Cache transmits a valid signal of 1 byte code data;
[0146] flash_data[7:0]: code data read from the Flash memory by the SPI bus;
[0147] cache_data[7:0]: When the data address of the code data to be read exists in the preset cache space, the preset cache space Cache returns the code data to the MCU;
[0148] Spi Ctrl: registers used to configure and control the SPI bus;
[0149] clk gate: used to control the clock master_clk of the Spi Ctrl module;
[0150] master_clk: The clock of the Spi Ctrl module, used to control the clock spi_clk of the SPI bus spi_bus;
[0151] spi_bus: SPI bus.
[0152] The disclosed embodiment obtains the code running speed of the microcontroller MCU and compares the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result. When the comparison result meets a preset condition, for example, the code reading speed of the Flash memory is slightly lower than the code running speed of the MCU or the code reading speed of the Flash memory is slightly higher than the code running speed of the MCU, it is determined to directly read and run the code data from the Flash memory through the first reading strategy. At this time, after waiting for the SPI bus to complete the transmission of each byte of code data read from the Flash memory, the microcontroller MCU will run the code data.
[0153] like Figure 8As shown, when the code data is read and executed directly from the Flash memory by the first reading strategy, if the code data to be read in the next reading cycle has an address jump, in order to minimize the speed impact caused by the SPI bus resending the address information after the address jump, the MCU will first search for a matching code address in the cache space Cache according to the miss module. Among them, the cache space Cache stores the code data that the MCU has read and executed and the data address corresponding to the code data. Therefore, in the case of a successful match, the corresponding code data cache_data[7:0] is directly fed back to the MCU by the cache space Cache. At this time, the valid signal 1'b1 of the Cache transmission of 1byte code data takes effect. After the code data is transmitted, the MCU reads the response signal mempsack as a low level state, and according to the response signal, cache_data[7:0] is used as the code data memdata[7:0] obtained by the MCU in the current reading cycle.
[0154] In the case of a match failure, it is determined that the code data needs to be read from the Flash memory. It should be noted that, since the code data to be read in the next read cycle has an address jump, the code data to be read in the next read cycle can be used as the starting code data, thereby determining a new fetch cycle, and based on the new fetch cycle, reading the code data corresponding to the continuous address from the Flash memory, that is, Figure 8 The address information memaddr[15:0] of the code data to be accessed is sent to the Flash memory. The address information is the address information corresponding to the new data acquisition cycle. After receiving the address information, SpiCtrl sends the address information to the Flash memory through the SPI bus spi_bus, so that the Flash memory will feedback the code data flash_code corresponding to the address information through the SPI bus spi_bus according to the address information, and Spi Ctrl will store the feedback code data flash_code in the cache space Cache.
[0155] Among them, when the amount of code data fed back each time is 1 byte, the code data fed back by the Flash memory in the current read cycle is flash_data[7:0]. At this time, the valid signal flash_ack for the SPI bus to read the 1-byte code data of the Flash memory is effective. Therefore, after the code data of flash_data[7:0] is transmitted, the MCU reads the response signal mempsack as a high-level state, and according to the response signal, uses flash_data[7:0] as the code data memdata[7:0] obtained by the MCU in the current read cycle.
[0156] In addition, when the code reading speed of the Flash memory is slightly higher than the code running speed of the MCU, there will be a situation where the SPI bus has completed the transmission of the 1-byte code data corresponding to the next read cycle, but the MCU has not yet completed the execution of the 1-byte code data corresponding to the current read cycle. At this time, if the SPI bus continues to transmit data, it will cause an instruction fetch error, causing the MCU to execute the code abnormally. Therefore, the MCU can send information to stop the SPI bus from continuing to transmit data. For example, through the clk gate module, the read clock master_clk of Spi Ctrl is configured to the pause state, thereby turning off the read clock spi_clk of the SPI bus, until the MCU has completed the execution of the 1-byte code data corresponding to the current read cycle, and the master_clk is configured to the recovery state, thereby restoring the read clock spi_clk of the SPI bus to continue reading data.
[0157] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.
[0158] In a second aspect, an embodiment of the present disclosure provides a code execution device.
[0159] Fig. 9 A schematic diagram of a code running device provided by an embodiment of the present disclosure is shown, and the device specifically includes:
[0160] An acquisition unit 91 is used to acquire the code running speed of the microcontroller;
[0161] A comparison unit 92, used for comparing the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result;
[0162] An operating unit 93 is used to select a first reading strategy corresponding to the preset condition from the preset reading strategies when the comparison result satisfies the preset condition, and directly read and run the code data from the Flash memory through the first reading strategy; wherein the preset reading strategy also includes: a second reading strategy, used to pre-read the code data in the Flash memory to a preset storage space when the comparison result does not satisfy the preset condition, so as to read and run the code data from the preset storage space.
[0163] In an optional implementation, the comparison result satisfies a preset condition including: a difference between a code running speed of the microcontroller and a code reading speed of the Flash memory is within a preset threshold range; and directly reading and running code data from the Flash memory through the first reading strategy includes: when the code reading speed is greater than the code running speed, directly reading and running the first code data corresponding to the current read cycle from the Flash memory through the first reading strategy, and controlling the reading operation of the second code data corresponding to the next read cycle stored in the Flash memory through reading control information.
[0164] In an optional implementation, controlling the read operation of the second code data corresponding to the next read cycle stored in the Flash memory by reading the control information includes:
[0165] Before the first code data is finished running, sending a pause type of read control information to the SPI bus used to read the Flash memory, so as to control the SPI bus to pause the operation of reading the second code data corresponding to the next read cycle from the Flash memory;
[0166] After the first code data is executed, read control information of a recovery type is sent to the SPI bus to control the SPI bus to resume the operation of reading the second code data corresponding to the next read cycle from the Flash memory.
[0167] In an optional implementation, the sending of pause-type read control information to the SPI bus for reading the Flash memory includes: configuring a first read clock of the SPI control to be in an off state so that the SPI control turns off a second read clock corresponding to the SPI bus; wherein the SPI control is provided in the microcontroller and is used to control a data read operation of the SPI bus;
[0168] The sending of the recovery type read control information to the SPI bus includes: configuring a first read clock of the SPI control to be in an on state so that the SPI control can start a second read clock corresponding to the SPI bus.
[0169] In an optional implementation, directly reading and running code data from the Flash memory using the first reading strategy specifically includes:
[0170] After the first code data transmitted in the current read cycle is directly read from the Flash memory and executed by the first read strategy, if the comparison result between the data address of the first code data transmitted in the current read cycle and the data address of the target code data to be read in the next read cycle meets the preset address jump condition, the target code data to be read in the next read cycle is read and executed in combination with the preset cache space;
[0171] The preset cache space is used to store the first code data that has been read and executed and the data address of the first code data in the Flash memory.
[0172] In an optional implementation, the step of reading and executing the target code data to be read in the next read cycle in combination with the preset cache space includes:
[0173] Determine a matching result between a data address of the target code data to be read in the next read cycle and a preset cache space;
[0174] When the matching result is a successful match, reading and executing the target code data from the preset cache space;
[0175] When the matching result is a matching failure, the target code data is directly read from the Flash memory and executed.
[0176] In an optional implementation, directly reading and running code data from the Flash memory using the first reading strategy includes:
[0177] In the case where the code data is the starting code data corresponding to a data acquisition cycle, the address information corresponding to the data acquisition cycle is sent to the Flash memory through the first reading strategy, so as to sequentially read and run the code data corresponding to the address information fed back by the Flash memory according to the reading cycle within the data acquisition cycle.
[0178] The functions or modules included in the device provided in the embodiments of the present disclosure can be used to execute the method described in the first aspect of the method embodiment above. Its specific implementation and technical effects can be referred to the description of the method embodiment above. For the sake of brevity, they will not be repeated here.
[0179] It should be noted that all modules involved in this embodiment are logic modules. In practical applications, a logic unit may be a physical unit, or a part of a physical unit, or may be implemented as a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by the present disclosure, but this does not mean that there are no other units in this embodiment.
[0180] Reference Fig.10 , an embodiment of the present disclosure provides an electronic device, comprising:
[0181] One or more processors 1001;
[0182] A memory 1002, on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement any one of the above code running methods;
[0183] One or more I / O interfaces 1003 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.
[0184] Among them, the processor 1001 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 1002 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 1003 is connected between the processor 1001 and the memory 1002, and can realize information interaction between the processor 1001 and the memory 1002, including but not limited to a data bus (Bus), etc.
[0185] In some embodiments, the processor 1001 , the memory 1002 , and the I / O interface 1003 are connected to each other through a bus, and further connected to other components of the computing device.
[0186] This embodiment also provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the code running method provided in this embodiment is implemented. To avoid repeated description, the specific steps of the code running method are not repeated here.
[0187] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the invented method described above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0188] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0189] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.
[0190] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.
Claims
1. A code running method, characterized in that: Applied to a microcontroller, the method comprises: Obtaining the code running speed of the microcontroller; Comparing the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result; In the case where the comparison result meets the preset condition, selecting a first reading strategy corresponding to the preset condition from the preset reading strategies, and directly reading and running the code data from the Flash memory through the first reading strategy; The preset read strategy further includes: a second read strategy for pre-reading the code data in the Flash memory to a preset storage space when the comparison result does not meet the preset condition, so as to read and run the code data from the preset storage space.
2. The code running method according to claim 1, characterized in that: The comparison result satisfies a preset condition including: a difference between the code running speed of the microcontroller and the code reading speed of the Flash memory is within a preset threshold range; The directly reading and running code data from the Flash memory by using the first reading strategy includes: In the case where the code reading speed is greater than the code running speed, the first code data corresponding to the current read cycle is directly read from the Flash memory and run through the first reading strategy, and the reading operation of the second code data corresponding to the next read cycle stored in the Flash memory is controlled through the reading control information.
3. The code running method according to claim 2, characterized in that: The controlling the reading operation of the second code data corresponding to the next reading cycle stored in the Flash memory by reading the control information comprises: Before the first code data is executed, a pause type of read control information is sent to the SPI bus used to read the Flash memory, so as to control the SPI bus to pause the operation of reading the second code data corresponding to the next read cycle from the Flash memory; After the first code data is executed, read control information of a recovery type is sent to the SPI bus to control the SPI bus to resume the operation of reading the second code data corresponding to the next read cycle from the Flash memory.
4. The code running method according to claim 3, characterized in that: The sending of the pause type read control information to the SPI bus for reading the Flash memory comprises: configuring a first read clock of the SPI control to be in an off state so that the SPI control can turn off a second read clock corresponding to the SPI bus; wherein the SPI control is arranged in the microcontroller and is used to control the data reading operation of the SPI bus; The sending of the recovery type read control information to the SPI bus includes: configuring a first read clock of the SPI control to be in an on state so that the SPI control can start a second read clock corresponding to the SPI bus.
5. The code running method according to any one of claims 1 to 4, characterized in that: The directly reading and running code data from the Flash memory by using the first reading strategy specifically includes: After the first code data transmitted in the current read cycle is directly read from the Flash memory and executed by the first read strategy, if the comparison result between the data address of the first code data transmitted in the current read cycle and the data address of the target code data to be read in the next read cycle meets the preset address jump condition, the target code data to be read in the next read cycle is read and executed in combination with the preset cache space; The preset cache space is used to store the first code data that has been read and executed and the data address of the first code data in the Flash memory.
6. The code running method according to claim 5, characterized in that: The method of reading and running the target code data to be read in the next reading cycle in combination with the preset cache space includes: Determine a matching result between a data address of the target code data to be read in the next read cycle and a preset cache space; When the matching result is a successful match, reading and executing the target code data from the preset cache space; When the matching result is a matching failure, the target code data is directly read from the Flash memory and executed.
7. The code running method according to any one of claims 1 to 4, characterized in that: The step of directly reading and running code data from the Flash memory by using the first reading strategy includes: In the case where the code data is the starting code data corresponding to a data acquisition cycle, the address information corresponding to the data acquisition cycle is sent to the Flash memory through the first reading strategy, so as to sequentially read and run the code data corresponding to the address information fed back by the Flash memory according to the reading cycle within the data acquisition cycle.
8. A code running device, characterized in that: The code running device is arranged in a microcontroller, and the code running device comprises: An acquisition unit, used for acquiring a code running speed of the microcontroller; A comparison unit, used for comparing the code running speed of the microcontroller with the code reading speed of the Flash memory to obtain a comparison result; An operating unit is used to select a first reading strategy corresponding to the preset condition from the preset reading strategies when the comparison result satisfies the preset condition, and directly read and run the code data from the Flash memory through the first reading strategy; wherein the preset reading strategy also includes: a second reading strategy, used to pre-read the code data in the Flash memory to a preset storage space when the comparison result does not satisfy the preset condition, so as to read and run the code data from the preset storage space.
9. An electronic device, characterized in that: include: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.
10. A computer readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 7.