Application programming interface to access non-uniform memory access nodes

Abstract

The invention discloses an application programming interface for accessing non-uniform memory access nodes. Apparatuses, systems, and techniques for accessing one or more non-uniform memory access (NUMA) nodes are disclosed. In at least one embodiment, one or more circuitry is to execute an application programming interface (API) such that one or more NUMA nodes or one or more physical addresses assigned to one or more graphics processing units (GPUs) are accessed based at least in part on one or more indications within the API.

Description

Technical Field

[0001] At least one embodiment relates to a processing resource for executing one or more programs written for a parallel computing platform and an application programming interface. For example, at least one embodiment relates to a processor or computing system that executes an application programming interface (API) according to the various novel techniques described herein. Background Art

[0002] Performing memory management operations may use a significant amount of time, power, or computing resources. The amount of time, power, or computing resources may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating a computing environment according to at least one embodiment;

[0004] Figure 2 An execution API to access one or more non-uniform memory access (NUMA) nodes is shown in accordance with at least one embodiment;

[0005] Figure 3 An execution API is shown to store information in one or more NUMA stores in accordance with at least one embodiment;

[0006] Figure 4 An execution API is shown according to at least one embodiment to indicate whether one or more storages correspond to one or more NUMA storages;

[0007] Figure 5 is a flow chart of a technique for accessing one or more NUMA nodes according to at least one embodiment;

[0008] Figure 6 is a flow chart of a technique for storing information within one or more NUMA stores according to at least one embodiment;

[0009] Figure 7 is a flow chart of a technique for indicating whether one or more stores correspond to one or more NUMA stores in accordance with at least one embodiment;

[0010] Figure 8 is a block diagram illustrating an example of a processor according to at least one embodiment;

[0011] Fig. 9 is a block diagram illustrating a driver and / or runtime environment according to at least one embodiment;

[0012] Fig.10 illustrates an exemplary data center in accordance with at least one embodiment;

[0013] Fig.11 A processing system according to at least one embodiment is shown;

[0014] Fig.12 A computer system according to at least one embodiment is shown;

[0015] Fig.13 A system according to at least one embodiment is shown;

[0016] Fig.14 An exemplary integrated circuit according to at least one embodiment is shown;

[0017] Fig.15 A computing system according to at least one embodiment is shown;

[0018] Fig.16 An APU is shown according to at least one embodiment;

[0019] Fig.17 A CPU according to at least one embodiment is shown;

[0020] Fig.18 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0021] Fig.19A and Fig.19B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0022] Fig. 20A illustrates a graphics core according to at least one embodiment;

[0023] Fig. 20B A GPGPU is shown according to at least one embodiment;

[0024] Fig.21A illustrates a parallel processor according to at least one embodiment;

[0025] Fig.21B illustrates a processing cluster according to at least one embodiment;

[0026] Fig. 21C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0027] Fig. 22 A graphics processor according to at least one embodiment is shown;

[0028] Fig.23 A processor according to at least one embodiment is shown;

[0029] Fig.24 A processor according to at least one embodiment is shown;

[0030] Fig.25 illustrates a graphics processor core according to at least one embodiment;

[0031] Fig.26 illustrates a PPU according to at least one embodiment;

[0032] Fig. 27 shows a GPC according to at least one embodiment;

[0033] Fig.28 A streaming multiprocessor is shown according to at least one embodiment;

[0034] Fig.29 A software stack for a programming platform according to at least one embodiment is shown;

[0035] Fig.30 According to at least one embodiment, Fig.29 CUDA implementation of the software stack;

[0036] Fig.31 According to at least one embodiment, Fig.29 ROCm implementation of the software stack;

[0037] Fig.32 According to at least one embodiment, Fig.29 OpenCL implementation of the software stack;

[0038] Fig.33 illustrates software supported by a programming platform according to at least one embodiment;

[0039] Fig.34 According to at least one embodiment, Figure 29-32 Compiled code executed on the programming platform;

[0040] Fig.35 According to at least one embodiment, Figure 29-32 More detailed compiled code executed on the programming platform;

[0041] Fig.36 Transforming source code prior to compiling the source code according to at least one embodiment is shown;

[0042] Fig.37A A system configured to compile and execute CUDA source code using different types of processing units according to at least one embodiment is shown;

[0043] Fig.37B A method configured to compile and execute using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Fig.37A CUDA source code system;

[0044] Fig.37C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Fig.37A CUDA source code system;

[0045] Fig.38 According to at least one embodiment, Fig.37C An example kernel converted by the CUDA to HIP conversion tool;

[0046] Fig.39 In more detail, the Fig.37C A non-CUDA-enabled GPU;

[0047] Fig.40 shows how threads of an exemplary CUDA grid are mapped to Fig.39 different computing units of

[0048] Fig.41 It shows how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment.

[0049] Fig.42 Components of a system for accessing a large language model in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0050] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0051] Figure 11 is a block diagram illustrating a computing environment 100 according to at least one embodiment. In at least one embodiment, a computer system 102 includes a non-uniform memory access (NUMA) node set 104 and a parallel processing unit (PPU) set 106 (e.g., one or more accelerators such as a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or some other suitable device). In at least one embodiment, the PPU set 106 includes a graphics processing unit (GPU) set. In at least one embodiment, the NUMA node set 104 includes a NUMA node 108, which includes a processor 110 and a memory 112. In at least one embodiment, the NUMA node set 104 includes a NUMA node 114, which includes a processor 116 and a memory 118. In at least one embodiment, the NUMA node set 104 is a host NUMA node and the GPUs in the PPU set 106 are devices.

[0052] In at least one embodiment, a NUMA node includes a collection of hardware components (e.g., one or more processors, one or more storage (such as memory), one or more other types of storage devices, one or more network components, and / or other suitable components). In at least one embodiment, a NUMA node in a system that employs a NUMA node architecture and / or enables a collection of hardware to be viewed as a NUMA node can access memory in other NUMA nodes and / or GPUs, but has faster access and less latency to memory within the NUMA node. In at least one embodiment, the computer system 102 is a server platform with more than one system bus. In at least one embodiment, different processor sockets on a multi-socket motherboard are located in different NUMA nodes.

[0053] In at least one embodiment, PPU set 106 includes GPU 120 and GPU 122. In at least one embodiment, GPU set 106 includes a different number of GPUs (e.g., less than or more than two GPUs). In at least one embodiment, GPU 120 includes GPU memory 124 and GPU 122 includes GPU memory 126. In at least one embodiment, GPU memory 124 and / or GPU memory 126 include more than one level and / or type of memory (e.g., global memory accessible by the entire GPU, memory accessible by a subset of processors on the GPU, cache memory accessible by individual processors on the GPU, shared memory accessible by a specific thread group).

[0054] In at least one embodiment, GPU 120 includes one or more processors 128. In at least one embodiment, GPU 122 includes one or more processors, not shown for clarity. In at least one embodiment, different numbers of processors (e.g., more than one processor 110 and / or processor 116) and / or different numbers of memories (e.g., more than one memory 112 and / or memory 118) are included in computer system 102. In at least one embodiment, one or more of processors 110 and processor 116 are central processing units (CPUs). In at least one embodiment, processor 110 and processor 116 are both CPUs. In at least one embodiment, computer system 102 includes one or more other components (e.g., a network interface card, a permanent storage device, one or more input devices, one or more output devices, and / or one or more other suitable components) not shown for clarity. In at least one embodiment, computer system 102 includes different numbers of NUMA nodes. In at least one embodiment, NUMA node 108 and / or NUMA node 114 include one or more other components, not shown for clarity. In at least one embodiment, NUMA node 108 and / or NUMA node 114 include different numbers of processors and / or memories.

[0055] In at least one embodiment, one or more of processors 110 and processor 116 are single core processors. In at least one embodiment, one or more of processors 110 and processor 116 are multi-core processors. In at least one embodiment, one or more of processors 110 and processor 116 are elements of a processing system such as processing system 1100 described herein. In at least one embodiment, one or more of processors 110 and processor 116 are elements of a computer system such as computer system 1200 described herein. In at least one embodiment, one or more of processors 110 and processor 116 are elements of a system such as system 1300 described herein. In at least one embodiment, one or more of processors 110 and processor 116 are elements of a computing system such as computing system 1500 described herein. In at least one embodiment, one or more of processors 110 and processor 116 are elements of a computing unit such as computing unit 3940 described herein. In at least one embodiment, one or more of processors 110 and processor 116 are some other processors shown and / or described herein.

[0056] In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are graphics processor 1910 as described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are graphics processor 1940 as described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are graphics multiprocessor 2134 as described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are graphics processor 2200 as described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are graphics processor 2408 as described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are GPU 3792 as described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in PPU set 106 are some other GPUs shown and / or described herein. In at least one embodiment, computer system 102 includes one or more accelerators (eg, one or more parallel processing units (PPUs), FPGAs, ASICs, and / or other suitable accelerators) in place of or in addition to the GPUs in PPU set 106 .

[0057] In at least one embodiment, the computer system 102 includes an API set 130. In at least one embodiment, when one or more APIs are referred to as performing an action or aspect of a technique, one or more hardware components (e.g., a CPU, a GPU, and / or other hardware components) of the computer system running the API perform the action or aspect of the technique. In at least one embodiment, the API set 130 is an API set for a GPU in the PPU set 106 and / or one or more NUMA nodes in the NUMA node set 104. In at least one embodiment, one or more operations described with respect to the GPU in the PPU set 106 and / or the API in the API set 130 are performed by one or more accelerators (not shown for clarity) that are not GPUs. In at least one embodiment, the API set 130 is referred to as an API (e.g., a driver API) that includes a plurality of callable functions. In at least one embodiment, the API set 130 is implemented in a dynamic library. In at least one embodiment, the API set 130 is an imperative API based on a handle. In at least one embodiment, API set 130 is a parallel processing framework API (eg, a Compute Unified Device Architecture (CUDA) driver API, a portable heterogeneous computing interface (HIP) API, or some other API).

[0058] In at least one embodiment, one or more APIs in the API set 130 are high-level APIs (e.g., APIs accessed using a high-level programming language such as C++, Python, Java, Fortran, C, or some other suitable language). In at least one embodiment, one or more APIs in the API set 130 are low-level APIs (e.g., APIs accessed using instructions of a programming framework such as CUDA PTX instructions or some other suitable intermediate representation that can be compiled into a machine-level binary representation for a specific hardware architecture). In at least one embodiment, one or more APIs in the API set 130 can also be implemented as instructions, such as PTX, assembly, x86, GPU instruction set architecture (ISA), machine-level instructions, or some other suitable type of instructions.

[0059] In at least one embodiment, API set 130 is an API set for a programming platform. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL TMDeveloped by the Khronos Group), SYCL, or Intel's one API. In at least one embodiment, although some aspects of the API and / or techniques for combining operations are discussed with respect to CUDA (including CUDA APIs and / or CUDA kernels), it should be understood that ROCm, OpenCL, SYCL, One API, and / or any other suitable API and / or kernel may be used. In at least one embodiment, one or more APIs in the API set 130 are accessed at least in part by including a header file in one or more portions of code that define one or more functions of the one or more APIs. In at least one embodiment, one or more APIs in the API set are functions (e.g., defined in a function library).

[0060] In at least one embodiment, one or more APIs in the API set 130 perform one or more actions on a range of memories. In at least one embodiment, the range of memories is a set of virtual memories accessible by one or more NUMA nodes (e.g., processors of one or more host NUMA nodes) and one or more GPUs. In at least one embodiment, the range of memories is virtual memories managed by one or more drivers (not shown for clarity) and / or one or more memory managers (not shown for clarity). In at least one embodiment, managed memory is referred to as unified memory. In at least one embodiment, managed memory is allocated using one or more functions and / or APIs (e.g., cuMemAllocManaged) and / or declared using specific declaration statements (e.g., using __managed__variables).

[0061] In at least one embodiment, the API set 130 includes a memory location preference API 132. In at least one embodiment, the memory location preference API 132 is referred to as a managed memory preference indication API. In at least one embodiment, the memory location preference API 132 is referred to as cuMemAdvise_v2(), cudaMemAdvise-v2(), or some other suitable API name. In at least one embodiment, the memory location preference API 132 is used to set a preferred memory location of a set of managed virtual memories accessible to one or more GPUs and one or more CPUs to a NUMA node based at least in part on an identifier of the NUMA node (e.g., NUMA-id) provided as one or more inputs to the memory location preference API 132. In at least one embodiment, the memory location preference API 132 is used to cause one or more physical addresses of one or more NUMA nodes (e.g., memory 112 of NUMA node 108) or memory allocated to one or more GPUs (e.g., GPU memory 124) to be accessed based at least in part on one or more indications within the API. In at least one embodiment, Figure 2 API 200, Figure 5 Technology 500, Figure 8 The managed memory preference indication module 804 and / or Fig. 9 One or more of the indication managed memory preferred location functions 916 further describe one or more aspects of the memory location preference API 132 .

[0062] In at least one embodiment, the API set 130 includes a memory prefetch API 134. In at least one embodiment, the memory prefetch API 134 is referred to as an asynchronous managed memory prefetch API. In at least one embodiment, the memory prefetch API 134 is referred to as cuMemPrefetchAsync_v2(), cudaMemPrefetchAsync-v2(), or some other suitable API name. In at least one embodiment, the memory prefetch API 134 is used to cause data stored in a set of virtual memories accessible to one or more CPUs and one or more GPUs to be prefetched to memory in a NUMA node based at least in part on an identifier (e.g., NUMA-id) of a NUMA node provided as one or more inputs to the memory prefetch API 134. In at least one embodiment, the memory prefetch API 134 is used to cause information to be stored in one or more NMA storages (e.g., memory 112 of NUMA node 108) or one or more GPU physical storages (e.g., memory 124 of GPU 120) based at least in part on one or more indicators to be indicated by one or more users of the memory prefetch API 134. In at least one embodiment, the memory prefetch API 134 is used to cause information to be read from one or more NUMA storages (e.g., memory 112 of NUMA node 108) or one or more GPU physical storages (e.g., memory 124 of GPU 120) based at least in part on one or more indicators to be indicated by one or more users of the memory prefetch API 134. In at least one embodiment, the memory prefetch API 134 is used to cause information to be read from one or more NUMA storages (e.g., memory 112 of NUMA node 108) or one or more GPU physical storages (e.g., memory 124 of GPU 120) based at least in part on one or more indicators to be indicated by one or more users of the memory prefetch API 134. Figure 3 API 300, Figure 6 Technology 600, Figure 8 The managed memory prefetch module 806 and / or Fig. 9 One or more aspects of the memory prefetch API 134 are further described in detail with reference to one or more of the prefetch managed memory functions 918 .

[0063] In at least one embodiment, the API set 130 includes a get memory attribute API 136. In at least one embodiment, the get memory attribute API 136 is referred to as a get managed memory attribute API. In at least one embodiment, the get memory attribute API 136 is referred to as cuMemRangeGetAttribute(), or as some other suitable API name. In at least one embodiment, the get memory attribute API 136 is used to indicate, return, and / or otherwise provide an indication of a NUMA node previously set (e.g., last set by the memory location preference API 132) as a preferred storage location for a set of managed virtual memories accessible to one or more CPUs and one or more GPUs. In at least one embodiment, the get memory attribute API 136 is used to indicate, return, and / or otherwise provide an indication of a NUMA node to which a set of managed virtual memories accessible to one or more CPUs and one or more GPUs was prefetched (e.g., last prefetched using the memory prefetch API 134). In at least one embodiment, the get memory attributes API 136 is used to indicate whether one or more storages indicated by one or more users of the get memory attributes API 136 correspond to one or more NUMA storages or one or more GPU storages. In at least one embodiment, one or more aspects of the get memory attributes API 136 are further related to Figure 4 API 400, Figure 7 Technology 700, Figure 8 The module 808 for obtaining attributes of managed storage and / or Fig. 9 In at least one embodiment, the API set 130 includes one or more other APIs, not shown for clarity (e.g., one or more memory allocation APIs for allocating managed memory accessible to both the CPU and the GPU, one or more synchronization APIs, and / or some other suitable API).

[0064] In at least one embodiment, compiler 138 converts requests received via APIs in API set 130 into instructions that can be executed on GPU 120 and / or one or more NUMA nodes in NUMA node set 104 (e.g., generates instructions as part of the instruction set architecture of GPU 120). In at least one embodiment, the generated instructions are stored as code 140 that is copied to one or more GPUs (e.g., GPU 120) in PPU set 106 to be executed. In at least one embodiment, one or more threads use one or more APIs in API set 130, and one or more arguments can be passed to the APIs in the API set. In at least one embodiment, API set 130 includes one or more APIs that can be used by code implemented at a higher level (e.g., C++ type implementation) and / or can be used by code implemented at an intermediate level (e.g., as PTX type instructions). In at least one embodiment, one or more APIs in API set 130 provide at least one function that is accessible to application 142. In at least one embodiment, a user provides one or more parameters (eg, information as one or more inputs) to an API in API set 130. In at least one embodiment, a user is a program that calls and / or uses one or more API functions.

[0065] In at least one embodiment, computer system 102 includes node set 144. In at least one embodiment, node set 144 includes node 146, node 148, and node 150. In at least one embodiment, node set 144 includes different numbers of nodes. In at least one embodiment, the nodes in node set 144 include one or more GPUs and / or one or more NUMA nodes. In at least one embodiment, kernel information (e.g., based at least in part on code 140) is copied to one or more GPUs included in one or more nodes in node set 144. In at least one embodiment, one or more components and / or aspects of computer system 102 and / or node set 144 are implemented using one or more hardware components, one or more software components, one or more circuits, dedicated hardware such as fixed function circuits, and / or any other suitable type of hardware, software, or combination thereof.

[0066] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or clearly to the contrary, terms such as "module" and nominalized verbs (e.g., compiler, driver, manager, and / or other terms) refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" used in any implementation described herein may, for example, include, alone or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware storing instructions executed by programmable circuits. In at least one embodiment, modules may be collectively or individually embodied as circuits that form part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), and the like.

[0067] Figure 2 200 is shown to perform access to one or more non-uniform memory access (NUMA) nodes (e.g., Figure 1 In at least one embodiment, executing API 200 to access one or more NUMA nodes includes causing a preferred location of a set of memories (e.g., virtual memories accessible by one or more CPUs and one or more GPUs) to be set to a NUMA node. In at least one embodiment, one or more processors (e.g., Figure 1 The processor 128, the processor 110 and / or the processor 116) is used to execute the API 200. In at least one embodiment, the API 200 will use Figure 1 The memory location preference API 132 is executed.

[0068] In at least one embodiment, the API 200 includes one or more parameters. In at least one embodiment, the parameters of the API 200 include one or more parameters for indicating a memory range. In at least one embodiment, the parameters of the API 200 include a source parameter for indicating a pointer to a base memory address (e.g., a base memory address in a managed unified virtual memory accessible by one or more CPUs and one or more GPUs) and a size parameter for indicating the size of the memory range (e.g., a count in bytes). In at least one embodiment, the API 200 includes an information to be set parameter for indicating the type of information to be set (e.g., a preferred location). In at least one embodiment, the API 200 does not use a parameter to indicate that the preferred location is the type of information to be set, but sets the preferred location to a default and / or is an API specifically for setting a preferred location type that does not include an information to be set parameter. In at least one embodiment, the API 200 includes a location parameter for indicating a preferred location (e.g., using a NUMA id or an identifier of a GPU). In at least one embodiment, the API 200 includes parameters of different numbers and / or different types. In at least one embodiment, the response 202 to executing the API 200 includes an indication of whether the execution of the API 200 was successful (eg, the operation status). In at least one embodiment, there is no response 202 (eg, when the API 200 has a void return type).

[0069] In at least one embodiment, the API signature and / or function prototype (prototype) of API 200 (e.g., to be used with the driver API) can be expressed as: CUresult cuMemAdvise_v2 (CUdeviceptr dptr, size_t count, CUmem_advise advice CUmemLocation location). In at least one embodiment, CUdeviceptr dptr corresponds to the source parameter, size_t count corresponds to the size parameter, CUmem_advice advice corresponds to the information parameter to be set, and / or CUmemLocation location corresponds to the location parameter. In at least one embodiment, the API signature and / or function prototype (prototype) of API 200 (e.g., to be used with the runtime API) can be expressed as: cudaError_t cudaMemAdvise (const void*dptr, size_t count, cudaMemoryAdviseadvice, cudaMemLocation location). In at least one embodiment, const void*dptr corresponds to the source parameter, size_t count corresponds to the size parameter, cudaMemoryAdvice advice corresponds to the information parameter to be set, and / or cudaMemLocation location corresponds to the location parameter. In at least one embodiment, the API signature and / or function prototype of API 200 is represented using some other suitable API signature and / or function or interface prototype.

[0070] In at least one embodiment, the location parameter indicates a location type and a location identifier (e.g., a NUMA node ID). In at least one embodiment, the NUMA node ID is information that uniquely identifies a NUMA node. In at least one embodiment, the NUMA node ID uniquely identifies a NUMA node to an operating system (OS). In at least one embodiment, the location parameter is a data structure that includes a type field and an identifier field. In at least one embodiment, the location type can be further understood with respect to CUmemLocationType, which can be expressed as:

[0071]

[0072] In at least one embodiment, with respect to CU_MEM_LOCATION_TYPE_DEVICE, location is the device location and id (e.g., location identifier) ​​is the device ordinal. In at least one embodiment, with respect to CU_MEM_LOCATION_TYPE_HOST_NUMA, location is the host NUMA node and id is the host NUMA node id. In at least one embodiment, with respect to CU_MEM_LOCATION_TYPE_HOST, location is the host and id is ignored. In at least one embodiment, with respect to CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT, location is the host NUMA node of the calling thread and id is ignored.

[0073] In at least one embodiment, one or more APIs support host NUMA nodes. In at least one embodiment, host NUMA supports virtual memory managers (VMMs) (e.g., CUDA VMMs) and memory pool allocations, and drivers (e.g., CUDA drivers) use CU_MEM_LOCATION_TYPE_host_NUMA as an enumeration type in CumemLocation::CUmemLocation TYPE. In at least one embodiment, when CumemLocation::type is CU_MEM_LOCATION_type_HOST_NUMA, CumemLocation::id specifies the NUMA ID of the host CPU node. In at least one embodiment, when CumemLocation::type is CU_MEM_LOCATION_type_HOST, CumemLocation::id is ignored.

[0074] In at least one embodiment, in some cases, the NUMA node of the current thread is the desired CPU NUMA node. In at least one embodiment, CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT is used as an enumeration type of CUMemLocation::CUmemLocationType to specify the use of the NUMA node of the current thread. In at least one embodiment, when CUMemLocation::type is CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT, CUMemLocation::id is ignored. In at least one embodiment, the corresponding cudaMemLocationTypeHost and / or cudaMemLocationTypeHostNumaCurrent can also be used with cudaMemLocationType.

[0075] In at least one embodiment, when the information to be set (e.g., advice parameter) is to set the preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and the location type (e.g., CUmemLocation::type) is a host NUMA node (e.g., CU_MEM_LOCATION_TYPE_HOST_NUMA), then the location identifier (e.g., CUmemLocation::id) to be provided as input is a valid NUMA ID (e.g., CPU NUMA ID). In at least one embodiment, when the information to be set (e.g., advice) is to set the preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and the location type (e.g., CUmemLocation::type) is a device (e.g., CU_MEM_LOCATION_TYPE_DEVICE), then CUmemLocation::id is a valid device ordinal. In at least one embodiment, when the information to be set (e.g., advice) is to set the preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and the location type (e.g., CUmemLocation::type) is the host without specifying a NUMA node (e.g., CU_MEM_LOCATION_TYPE_HOST), then CUmemLocation::id is ignored. In at least one embodiment, when the information to be set (e.g., advice) is to set the preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and the location type (e.g., CUmemLocation::type) is the current host NUMA node (e.g., CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT), then CUmemLocation::id is ignored and the CPU NUMA node of the current thread will be set to the preferred location of the range. In at least one embodiment, when advise is one of CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION, CU_MEM_ADVISE_SET_READ_MOSTLY, or CU_MEM_ADVISE_UNSET_READ_MOSTLY, the CUMemLocation::type argument is ignored.In at least one embodiment, when advice is CU_MEM_ADVISE_SET_ACCESSED_BY or CU_MEM_ADVISE_UNSET_ACCESSED_BY, then CUMemLocation::type is CU_MEM_LOCATION_TYPE_DEVICE (eg, with a valid ordinal in CUMemLocation::id) or CU_MEM_LOCATION_TYPE_HOST (eg, where CUMemLocation::id will be ignored).

[0076] Figure 3 The execution API 300 is shown to store information in one or more NUMA memories (e.g., Figure 1 In at least one embodiment, executing API 300 to store information in one or more NUMA memories includes pre-fetching data stored using a set of memories (e.g., virtual memories accessible by one or more CPUs and one or more GPUs) to physical memories within a NUMA node. In at least one embodiment, one or more processors (e.g., Figure 1 The processor 128, the processor 110 and / or the processor 116 in the processor 128 is used to execute the API 300. In at least one embodiment, the use Figure 1 The memory prefetch API 134 in is used to execute API 300.

[0077] In at least one embodiment, the API 300 includes one or more parameters. In at least one embodiment, the parameters of the API 300 include one or more parameters for indicating a memory range. In at least one embodiment, the parameters of the API 300 include a source parameter for indicating a pointer to a base memory address (e.g., a base memory address in a managed unified virtual memory accessible by one or more CPUs and one or more GPUs) and a size parameter for indicating the size of the memory range (e.g., a count in bytes). In at least one embodiment, the API 300 includes a destination location parameter to the location where the data stored in the specified memory range will be prefetched (e.g., a host NUMA node using a NUMA id or a GPU using a GPU id). In at least one embodiment, the API 300 includes a stream identifier parameter for identifying the stream to which the prefetch applies. In at least one embodiment, the API 300 includes parameters of different numbers and / or different types. In at least one embodiment, the response 302 to the execution of the API 300 includes an indication of whether the execution of the API 300 was successful (e.g., an operation status). In at least one embodiment, there is no response 302 (eg, when API 300 has a void return type).

[0078] In at least one embodiment, the API signature and / or function prototype of API 300 (e.g., to be used with the driver API) can be expressed as: CUresult cuMemPrefetchAsync_v2 (CUdevice dptr, size_t count, CUmemLocation location, CUstream stream). In at least one embodiment, CUdevicedptr corresponds to the source parameter, size_t count corresponds to the size parameter, CUmemLocation location corresponds to the destination location parameter, and / or CUstream stream corresponds to the stream identifier parameter. In at least one embodiment, the API signature and / or function prototype of API 300 (e.g., to be used with the runtime API) can be expressed as: cudaError_tcudaMemPrefetchAsync_v2 (const void*dptr, size_t count, cudaMemLocation location, cudaStream stream=0). In at least one embodiment, const void*dptr corresponds to the source parameter, size_t count corresponds to the size parameter, cudaMemLocation location corresponds to the destination location parameter, and / or cudaStream stream corresponds to the stream identifier parameter. In at least one embodiment, the API signature and / or function prototype of API 300 is represented using some other suitable API signature and / or function or interface prototype.

[0079] In at least one embodiment, Figure 2One or more aspects of the CUmemLocationType, CUmemLocation Location, and / or cudaMemLocation Location shown and / or described in API 200 also apply to API 300. In at least one embodiment, specifying CU_MEM_LOCATION_TYPE_HOST_NUMA will prefetch memory (e.g., data stored in a set of managed virtual memories accessible to one or more CPUs and one or more GPUs) to the NUMA node specified by CUmemLocation::id. In at least one embodiment, when an address range is prefetched to a HOST NUMA node, if CU_MEM_ADVISE_SET_READ_MOSTLY is set for any page of the user passed in the address range, a read duplicate copy is created in the target CPU NUMA node. In at least one embodiment, if these pages are already in some other HOST NUMA nodes, the unified memory driver migrates them to the target NUMA node. In at least one embodiment, if CU_MEM_ADVISE_SET_READ_MOSTLY is not set, the page will be migrated to the target NUMA node. In at least one embodiment, specifying CUmemLocation::type=CU_MEM_LOCATION_TYPE_DEVICE will prefetch memory to the GPU specified by the device number CUmemLocation::id. In at least one embodiment, the user can also request to prefetch memory to the CPU NUMA node of the current thread by specifying CUmemLocation::type=CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT.

[0080] Figure 4 The execution API 400 is shown to indicate whether one or more stores correspond to one or more NUMA stores (e.g., Figure 1 In at least one embodiment, executing API 400 to indicate whether one or more storages correspond to one or more NUMA storages includes generating an indication of a NUMA node to which a group of storages were last prefetched. In at least one embodiment, executing API 400 to indicate whether one or more storages correspond to one or more NUMA storages includes generating an indication of a NUMA node that is set as a preferred location for a group of storages. In at least one embodiment, one or more processors (e.g., Figure 1The processor 128, the processor 110 and / or the processor 116) is used to execute the API 400. In at least one embodiment, the use Figure 1 The Get Memory Attributes API 136 is used to execute the API 400 .

[0081] In at least one embodiment, the API 400 includes one or more parameters. In at least one embodiment, the parameters of the API 400 include a result location parameter for indicating the memory location where the result of the attribute query of the API 400 will be compiled. In at least one embodiment, the API 400 includes a result size parameter for indicating the size of the data. In at least one embodiment, the API 400 includes an attribute parameter for indicating the attribute to be queried (e.g., the last prefetch location or preferred location set for a group of memories). In at least one embodiment, the API 400 includes a memory range start parameter for indicating the start of the range to be queried. In at least one embodiment, the API 400 includes a memory range size parameter for indicating the size of the range to be queried (e.g., a count in bytes). In at least one embodiment, the API 400 includes different numbers and / or different types of parameters. In at least one embodiment, the response 402 to the execution of the API 400 includes an indication of whether the execution of the API 400 was successful (e.g., an operation status). In at least one embodiment, there is no response 402 (e.g., when the API 400 has an invalid return type).

[0082] In at least one embodiment, the API signature and / or function prototype of API 400 can be expressed as: CUresultcuMemRangeGetAttribute(void*data, size_t dataSize, CUmem_range_attribute, CUdeviceceptr devPtr, size_t count). In at least one embodiment, void*data corresponds to the result location parameter, size_t dataSize corresponds to the result size parameter, CUmem_range_attribute corresponds to the attribute parameter, CUdeviceceptr devPtr corresponds to the memory range start parameter, and / or size_t count corresponds to the memory range size parameter. In at least one embodiment, the type of the range attribute parameter can be expressed as:

[0083]

[0084] In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY is used to specify that the attribute to be returned is whether the range is mostly read and only occasionally written. In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION is used to specify that the attribute to be returned is the preferred location of the range, but is not enabled for NUMA and a NUMA id cannot be returned. In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY is used to specify that the attribute to be returned is whether the memory range has ::CU_MEM_ADVISE_SET_ACCESSED_BY set for the specified device. In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION is used to specify that the attribute to be returned is the last prefetch location, but is not enabled for NUMA and a NUMA id cannot be returned. In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION_v2 is used to specify that the attribute to be returned is the preferred CUmemLocation of the range (e.g., which may include a preferred NUMA node). In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION_v2 is used to specify that the attribute to be returned is the last prefetched CUmemLocation of the range (e.g., which may be the NUMA node to which the range was prefetched).

[0085] In at least one embodiment, API 400 (e.g., using cuMemRangeGetAttribute()) enables a user to query the Figure 2 API 200 (e.g., using cuMemAdvise to set preferences) and / or Figure 3300 (e.g., prefetched using cuMemPrefetchAsync). In at least one embodiment, the preferred location of the CUMemLocation and / or address range is enumerated for retrieving the last prefetched location. In at least one embodiment, when the preferred location is specified as an attribute (e.g., using CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION_v2), the data argument will be interpreted as a pointer to a CUMemLocation and dataSize will be at least sizeof(CUmemLocation). In at least one embodiment, if all pages in the specified address range have the same GPU device as their preferred location, the returned location.type will be CU_MEM_LOCATION_TYPE_DEVICE and the location.id will be the device ID (e.g., the id of the GPU). In at least one embodiment, if all pages in the specified address range have the same CPUNUMA node as their preferred location, the returned location.type will be CU_MEM_LOCATION_TYPE_HOST_NUMA and location.id will be the CPU NUMA ID. In at least one embodiment, if a CPU NUMA node ID is not specified to set the preferred location to be part of the host or to have different CPUs paging as their preferred location, then location.type will be CU_MEM_LOCATION_TYPE_HOST.

[0086] In at least one embodiment, when the last prefetch location is specified as an attribute (e.g., using CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION_v2), the data argument will be interpreted as a pointer to a CUmemLocation, and dataSize will be at least sizeof(CUmemLocation). In at least one embodiment, if all pages in the specified address range are explicitly prefetched on a single GPU, the returned location.type will be CU_MEM_LOCATION_TYPE_DEVICE, and location.id will be the device ID (e.g., the device ID of the GPU). In at least one embodiment, if all pages in the specified address range are explicitly prefetched on a single CPU NUMA node, the returned location.type will be CU_MEM_LOCATION_TYPE_HOST_NUMA, and location.id will be the CPU NUMAID. In at least one embodiment, if the CPU NUMA node ID is not specified as part of the prefetch operation to the host or the page is explicitly prefetched to a different CPU, the returned location.type will be CU_MEM_LOCATION_TYPE_HOST.

[0087] In at least one embodiment, one or more aspects of API 200, API 300 and / or API 400 will be used with a NUMA-enabled system. In at least one embodiment, API 200, API 300 and API 400 are referred to as NUMA-aware and / or one or more indications of one or more NUMA nodes as one or more input parameters. In at least one embodiment, one or more aspects of API 200, API 300 and / or API 400 will be used for a system including one or more CPUs and one or more GPUs connected to each other using a high-bandwidth chip-to-chip (C2C) interconnect. In at least one embodiment, the presence of a high-bandwidth C2C link between a CPU and a GPU and the use of high-capacity memory make it possible to increase the amount of high-bandwidth memory available to the GPU. In at least one embodiment, the extended ability of a GPU to access CPU memory on a remote socket or node is referred to as extended GPU memory (EGM). In at least one embodiment, based at least in part on a C2C link, EGM allows faster access to system memory (sysmem) than PCIe. In at least one embodiment, one or more APIs enable the creation of target allocations and / or management of virtual memory in different CPU memories on different sockets (e.g., in different NUMA nodes) to better use EGM features compared to older technologies that are NUMA-agnostic and / or do not allow the specification of specific NUMA nodes. In at least one embodiment, CPU nodes are enumerated as different NUMA nodes within the system. In at least one embodiment, passing the NUMA ID of the GPU instead of the CPU to API 200, API 300, and / or API 400 causes an API failure (e.g., with CUDA_ERROR_INVALID_VALUE). In at least one embodiment, a driver (e.g., a CUDA driver) will pass the user-specified NUMA ID to a unified virtual memory (UVM) driver.

[0088] Figure 5 is a flow chart of a technique 500 for accessing one or more NUMA nodes according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 500 are described in detail. Figure 1 10, 110, 116, 120, 122, and / or memory location preference API 132) and / or with respect to one or more components, techniques, and / or other aspects shown or described in other figures herein. In at least one embodiment, technique 500 includes performing Figure 2In at least one embodiment, at block 502, technique 500 includes obtaining a managed memory set attribute request (e.g., via a method such as Figure 1 In at least one embodiment, at block 504, technique 500 includes setting managed memory attributes (e.g., executing Figure 1 The memory location preference API 132 and / or Figure 2 In at least one embodiment, at block 506, technique 500 includes performing other actions (e.g., returning an indication that setting a preferred location for a set of managed memory was successfully performed and / or returning to block 502 to obtain another managed memory set attribute request). In at least one embodiment, performing other actions at block 506 includes storing an indication of a preferred storage location (e.g., a NUMA id) in association with one or more indications of a set of virtual memories (e.g., managed virtual memories accessible by one or more CPUs and one or more GPUs).

[0089] In at least one embodiment, at least one aspect of the technique 500 includes executing an API (e.g., Figure 1 The memory location preference API 132 and / or Figure 2The API 200 of the present invention is used to cause one or more non-uniform memory access (NUMA) nodes or one or more physical addresses assigned to one or more graphics processing units (GPUs) to be accessed based at least in part on one or more instructions within the API. In at least one embodiment, the API is used to cause the memory of the NUMA node to be set as a preferred storage location based at least in part on the one or more instructions. In at least one embodiment, the one or more instructions include information indicating a set of virtual memories accessible by a central processing unit (CPU) and one or more GPUs. In at least one embodiment, the one or more instructions include information indicating a NUMA node to be used as a preferred storage location. In at least one embodiment, the API is used to cause a NUMA node among a plurality of NUMA nodes to be used as a preferred storage location for data to be stored using one or more virtual memory addresses accessible to a central processing unit (CPU) of one or more GPUs and a NUMA node. In at least one embodiment, the API is used to cause one or more instructions to be stored, the one or more instructions including information indicating a NUMA node to be used as a preferred storage location for information stored using one or more virtual memory addresses accessible to a central processing unit (CPU) of one or more GPUs and a NUMA node. In at least one embodiment, a non-transitory computer-readable medium has stored thereon a set of instructions that, if executed by one or more processors, causes the one or more processors to perform at least one or more aspects of technique 500 .

[0090] Figure 6 is a flow chart of a technique 600 for storing information in one or more NUMA storages according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 500 are described in detail. Figure 1 10, 110, 116, 120, 122, and / or memory prefetch API 134) and / or with respect to one or more components, techniques, and / or other aspects shown or described herein. In at least one embodiment, technique 600 includes performing Figure 3 In at least one embodiment, at block 602, technique 600 includes (e.g., via a method such as Figure 1 In at least one embodiment, at block 604, technique 600 includes executing a prefetch of the managed memory (e.g., executing Figure 1 The memory prefetch API 134 and / or Figure 3In at least one embodiment, performing a prefetch of the managed memory includes causing a driver and / or a memory manager to prefetch data to a NUMA node. In at least one embodiment, at block 606, technique 600 includes performing other actions (e.g., returning an indication that the memory prefetch operation was successfully performed and / or returning to block 602 to obtain another managed memory prefetch request).

[0091] In at least one embodiment, at least one aspect of technique 600 includes executing an API (e.g., Figure 1 The memory prefetch API 134 and / or Figure 4 The API 400) is provided to cause information to be stored in one or more non-uniform memory access (NUMA) storage or one or more graphics processor unit (GPU) physical storage based at least in part on one or more indicators to be indicated by one or more users of the API. In at least one embodiment, the API is used to cause information accessible to one or more central processing units (CPUs) and one or more GPUs to be stored in NUMA storage based at least in part on one or more indicators. In at least one embodiment, the API is used to prefetch information to a location specified by one or more of the one or more indicators. In at least one embodiment, the API is used to cause information to be prefetched to a NUMA node in a plurality of NUMA nodes. In at least one embodiment, the information is located in a managed virtual memory accessible to one or more central processing units (CPUs) and one or more GPUs, and the API is used to cause the information to be prefetched to a memory of a NUMA node including one or more of the one or more CPUs. In at least one embodiment, the information indicates a NUMA node to which the information is to be stored. In at least one embodiment, a non-transitory computer-readable medium has stored thereon a set of instructions that, if executed by one or more processors, causes the one or more processors to perform at least one or more aspects of technique 600 .

[0092] In at least one embodiment, at least one aspect of technique 600 includes executing an API (e.g., Figure 1 The memory prefetch API 134 and / or Figure 3The API 300 of the present invention is to cause information to be read from one or more non-uniform memory access (NUMA) storage or one or more graphics processor unit (GPU) physical storage based at least in part on one or more indicators to be indicated by one or more users of the API. In at least one embodiment, the information is stored using one or more NUMA nodes and one or more virtual memory addresses accessible to one or more GPUs, and the API is used to cause the information to be stored in a specific NUMA node of the one or more NUMA nodes. In at least one embodiment, the information is stored using one or more virtual memory addresses accessible to one or more NUMA nodes and one or more GPUs, and the one or more indicators indicate the one or more virtual memory addresses and the location to which the information is to be prefetched. In at least one embodiment, the information is stored using one or more virtual memory addresses, and the API is used to store the information in the NUMA storage of the NUMA node indicated by one or more of the one or more indicators. In at least one embodiment, the one or more indicators indicate a set of virtual memories and NUMA nodes. In at least one embodiment, virtual memory accessible by multiple NUMA nodes and one or more GPUs is used to store information, and an API is used to cause information to be read from the storage of a NUMA node in the multiple NUMA nodes. In at least one embodiment, a non-transitory computer-readable medium has stored thereon an instruction set that, if executed by one or more processors, causes the one or more processors to perform at least one or more aspects of technique 600.

[0093] Figure 7 is a flow chart of a technique 700 for indicating whether one or more storages correspond to one or more NUMA storages according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 700 are described with respect to Figure 1 10. The technique 700 may be performed with respect to one or more aspects shown or described herein (e.g., processor 110, processor 116, GPU 120, GPU 122, and / or get memory attributes API 136) and / or with respect to one or more components, techniques, and / or other aspects shown or described herein. In at least one embodiment, the technique 700 includes performing Figure 4 In at least one embodiment, at block 702, technique 700 includes (e.g., via a method such as Figure 1 In at least one embodiment, at block 704, technique 700 includes providing the requested memory attributes (e.g., executing Figure 1Get memory attribute API 136 and / or Figure 4 In at least one embodiment, at block 706, technique 700 includes performing other actions (e.g., returning an indication that the requested memory attribute operation was successfully performed and / or returning to block 702 to obtain another get managed memory attributes request).

[0094] In at least one embodiment, at least one aspect of technique 700 includes executing an API (e.g., Figure 1 Get memory attribute API 136 and / or Figure 4 The API 400 of the embodiment of the present invention is used to indicate whether the one or more storages indicated by the one or more users of the API correspond to one or more non-uniform memory access (NUMA) storages or one or more graphics processing unit (GPU) storages. In at least one embodiment, the one or more storages indicated by the one or more users of the API are one or more managed memory locations indicated by information indicating a set of managed memories received as one or more inputs to the API. In at least one embodiment, the API is used to indicate a preferred NUMA storage or GPU storage among the one or more storages indicated by the one or more users. In at least one embodiment, the API is used to indicate the NUMA storage or GPU storage to which the one or more storages were last prefetched. In at least one embodiment, the one or more NUMA storages are physical memories included in one or more NUMA nodes, each NUMA node including one or more central processing units (CPUs). In at least one embodiment, the one or more storages indicated by the one or more users are one or more virtual memory addresses accessible by the one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, a non-transitory computer-readable medium has stored thereon a set of instructions that, if executed by one or more processors, causes the one or more processors to perform at least one or more aspects of technique 700 .

[0095] Figure 8802 performs one or more processes such as those described herein to set a NUMA node as a preferred storage location for data to be stored using a set of managed memories (e.g., virtual memories accessible by one or more CPUs and one or more GPUs). In at least one embodiment, the processor 802 performs one or more processes such as those described herein to prefetch data stored using a set of managed memories to a NUMA node. In at least one embodiment, the processor 802 performs one or more processes such as those described herein to obtain one or more attributes (e.g., the last location (e.g., NUMA node) to which a set of memories was explicitly prefetched and / or an identifier of a location (e.g., NUMA node) set as a preferred storage location for a set of memories).

[0096] In at least one embodiment, processor 802 performs Figure 1 processor 110, processor 116, processor 128 and / or one or more APIs in API set 130, Figure 2 API 200, Figure 3 API 300, Figure 4 API 400, Figure 5 Technology 500, Figure 6 Technology 600, Figure 7 ART 700 and / or Fig. 9 In at least one embodiment, the processor 802 performs such as combining Figures 1 to 7 One or more processes such as those described.

[0097] In at least one embodiment, processor 802 includes, for example, a combination of Figures 25 to 40In at least one embodiment, the processor 802 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, the processor 802 includes a managed memory preference indication module 804, a managed memory prefetch module 806, and an acquisition managed memory attribute module 808. In at least one embodiment, the managed memory preference indication module 804, the managed memory prefetch module 806, and / or the acquisition managed memory attribute module 808 are part of the processor 802 and / or one or more other processors. In at least one embodiment, the managed memory preference indication module 804, the managed memory prefetch module 806, and / or the acquisition managed memory attribute module 808 are distributed among multiple processors that communicate via a bus, a network, by writing to a shared memory, and / or any appropriate communication process such as those described herein.

[0098] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or clearly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" used in any implementation described herein may, for example, include hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware storing instructions implemented and / or executed by programmable circuits, alone or in any combination. In at least one embodiment, modules may be collectively or individually embodied as circuits forming part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), and the like. In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof.

[0099] In at least one embodiment, the managed memory preference indication module 804 is a module that generates one or more wireless network metrics. In at least one embodiment, the managed memory preference indication module 804 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise usable to perform the one or more processes (e.g., by the processor 802). In at least one embodiment, the managed memory preference indication module 804 sets a NUMA node as a preferred storage location for a set of managed memories based at least in part on receiving information specifying a NUMA node and a set of memories via an API. In at least one embodiment, the managed memory preference indication module 804 performs instructions regarding Figure 1 Memory location preference API 132, Figure 2 API 200 and / or Figure 5 One or more aspects of the technology 500 shown or described.

[0100] In at least one embodiment, the managed memory prefetch module 806 is a module that prefetches information stored using a set of virtual memories to a specified location (e.g., a NUMA node). In at least one embodiment, the managed memory prefetch module 806 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause the one or more processes to be performed or are otherwise usable to perform the one or more processes (e.g., by the processor 802). In at least one embodiment, the managed memory prefetch module 806 performs information about Figure 1 Memory prefetch API 134, Figure 3 API 300 and / or Figure 6 One or more aspects of the technology 600 shown or described.

[0101] In at least one embodiment, the get managed memory attributes module 808 is a module that generates, returns, and / or otherwise provides the last location (e.g., NUMA node) to which a set of memories was explicitly prefetched and / or the location (e.g., NUMA node) that is set as the preferred storage location for a set of memories. In at least one embodiment, the get managed memory attributes module 808 performs one or more processes such as those described herein by at least including or otherwise encoding instructions that cause the one or more processes to be performed or are otherwise usable to perform the one or more processes (e.g., by the processor 802). In at least one embodiment, the get managed memory attributes module 808 performs instructions regarding Figure 1 Get managed storage attribute API 136, Figure 4API 400 and / or Figure 7 One or more aspects of the technology 700 shown or described.

[0102] In at least one embodiment, a processor (e.g., Figure 1 The processor 110, the processor 116 and / or the processor 128) includes one or more circuits for executing the API (e.g., Figure 1 The memory location preference indication API 132 and / or Figure 2 The API 200) can cause one or more non-uniform memory access (NUMA) nodes (e.g., Figure 1 NUMA node 108) or one or more physical addresses (e.g., Figure 1In at least one embodiment, the API is used to cause the storage of a NUMA node to be set as a preferred storage location for data to be stored at one or more virtual memory addresses. In at least one embodiment, the API is used to cause the memory of a NUMA node including a central processing unit (CPU) to be set as a preferred storage location. In at least one embodiment, the API is used to cause one of the multiple NUMA nodes to be used as a preferred storage location for data to be stored using one or more virtual memory addresses accessible to the central processing unit (CPU) and one or more GPUs. In at least one embodiment, the API is used to cause access to the memory in the NUMA node based at least in part on information included in one or more indications indicating the NUMA node. In at least one embodiment, one or more indications within the API include information provided as input indicating a set of managed memory and NUMA nodes. In at least one embodiment, one or more NUMA nodes include one or more central processing units (CPUs), and one or more indications within the API include information provided as input indicating a set of virtual memory addresses accessible to one or more CPUs and one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API to indicate that physical memory corresponding to a subset of a set of CPUs is to be used to store data corresponding to one or more virtual memory addresses shared by the subset of CPUs and one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API to indicate that physical memory within a NUMA node is to be used to store data stored using one or more virtual memory addresses shared by the NUMA node and one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API to cause a preferred managed memory location to be indicated based at least in part on an identifier of the NUMA node.

[0103] In at least one embodiment, the system includes one or more processors (e.g., Figure 1 110, processor 116, and / or processor 128), the one or more processors executing the API (e.g., Figure 1 The memory location preference indication API and / or Figure 2 200) to enable one or more non-uniform memory access (NUMA) nodes (e.g., Figure 1108) or one or more physical addresses (e.g., Figure 1 In at least one embodiment, the one or more indications include information indicating a set of virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, the API is used to cause the memory of the NUMA node including the central processing unit (CPU) to be used as a preferred physical storage location for data to be stored using one or more virtual memory addresses accessible by the CPU and one or more GPUs. In at least one embodiment, the one or more indications include information indicating the NUMA node to be used as the storage location for the data. In at least one embodiment, the one or more indications include information indicating the NUMA node to be used as the physical storage location for the data and information indicating a set of virtual memory addresses. In at least one embodiment, the API is used to cause an indication of a preferred physical storage location for a set of virtual memory addresses to be stored.

[0104] In at least one embodiment, a processor (e.g., Figure 1 The processor 110, the processor 116 and / or the processor 128) includes one or more circuits for executing the API (e.g., Figure 1 The memory prefetch API 134 and / or Figure 3 API 300) to enable the user to perform a task based at least in part on one or more indicators (e.g., Figure 3 One or more parameters of the API 300) and store the information in one or more non-uniform memory access (NUMA) storages (e.g., Figure 1 memory 118) or one or more graphics processor units (GPUs) physically storing (e.g., Figure 1In at least one embodiment, the API is used to cause information to be pre-fetched to the memory of the NUMA node. In at least one embodiment, the one or more indicators include information indicating a storage location type and a storage location identifier. In at least one embodiment, the API is used to cause information to be stored in the NUMA storage of a NUMA node including a central processing unit (CPU) in response to one or more indicators indicating a storage location type of the host NUMA node. In at least one embodiment, the API is used to cause information to be pre-fetched to the memory of the host NUMA node specified by one or more of the one or more indicators. In at least one embodiment, one or more virtual memory addresses accessible to one or more GPUs and one or more central processing units (CPUs) are used to store information, and the API is used to cause the information to be stored in the physical memory of the NUMA node. In at least one embodiment, the one or more indicators include an indication of a NUMA node among a plurality of NUMA nodes, and the API is used to cause the information to be stored in the indicated NUMA node. In at least one embodiment, the processor includes one or more circuits for executing an API so that physical memory corresponding to a subset of a set of CPUs is used to store data corresponding to one or more virtual memory addresses shared by the subset of CPUs and one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API so that physical memory within a NUMA node is used to store data stored using one or more virtual memory addresses shared by the NUMA node and one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API so that a set of managed memories is prefetched based at least in part on an identifier of a NUMA node.

[0105] In at least one embodiment, the system includes one or more processors (e.g., Figure 1 110, processor 116, and / or processor 128), the one or more processors executing the API (e.g., Figure 1 The memory prefetch API 134 and / or Figure 3 API 300) to determine the user's preferences based at least in part on one or more indicators (e.g., Figure 3 One or more parameters of the API 300) causes the information to be stored in one or more non-uniform memory access (NUMA) storages (e.g., Figure 1 memory 112) or one or more graphics processor units (GPUs) physically storing (e.g., Figure 1In at least one embodiment, information is stored using a virtual address accessible to one or more central processing units (CPUs) and one or more GPUs, and an API is used to cause the information to be stored in a physical memory of a NUMA node. In at least one embodiment, one or more indicators include information indicating a set of memories accessible to one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, an API is used to cause information to be pre-fetched to a NUMA node including a central processing unit. In at least one embodiment, one or more indicators indicate a set of virtual memories and NUMA nodes. In at least one embodiment, one or more indicators indicate a starting position and size of the information to be stored.

[0106] In at least one embodiment, a processor (e.g., Figure 1 The processor 110, the processor 116 and / or the processor 128) includes one or more circuits for executing the API (e.g., Figure 1 The memory prefetch API 134 and / or API 300 of the present invention may be configured to enable the prefetching of the memory prefetching API 134 and / or API 300 to be based at least in part on one or more indicators (e.g., Figure 3 One or more parameters of the API 300) from one or more non-uniform memory access (NUMA) storages (e.g., Figure 1 112 and / or memory 118) or one or more graphics processor units (GPUs) physical storage (e.g., Figure 1In at least one embodiment, the API is used to cause information to be read from NUMA storage based at least in part on causing the information to be prefetched to NUMA storage. In at least one embodiment, the information is stored using one or more virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs, and the API is used to cause the information to be read based at least in part on causing the information to be stored within the NUMA storage. In at least one embodiment, the one or more indicators include one or more indicators indicating virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, the one or more indicators include one or more indicators indicating a NUMA node to which the information is to be prefetched. In at least one embodiment, the one or more indicators include: one or more indicators indicating virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs; and one or more indicators indicating a specific NUMA node among a plurality of NUMA nodes. In at least one embodiment, an API is used to cause information to be read from NUMA storage based at least in part on causing the information to be stored at a NUMA node indicated by one or more of the one or more indicators.

[0107] In at least one embodiment, the system includes one or more processors (e.g., Figure 1 110, processor 116, and / or processor 128), the one or more processors for executing the API (e.g., Figure 1 The memory prefetch API 134 and / or Figure 3 API 300) such that based at least in part on one or more indicators (e.g., Figure 3 One or more parameters of the API 300) from one or more non-uniform memory access (NUMA) storages (e.g., Figure 1 memory 118) or one or more graphics processor units (GPUs) physically storing (e.g., Figure 1In at least one embodiment, information is stored using one or more virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs, and the API is used to cause information to be read from NUMA storage based at least in part on causing the information to be stored at NUMA storage. In at least one embodiment, information is stored using one or more virtual memory addresses, and one or more of the one or more indicators indicate the one or more virtual memory addresses. In at least one embodiment, the one or more indicators include one or more indicators indicating a specific NUMA node among a plurality of NUMA nodes. In at least one embodiment, the API is used to cause information to be read from NUMA storage within a specific NUMA node among a plurality of NUMA nodes. In at least one embodiment, information is stored using one or more virtual memory addresses accessible by a plurality of NUMA nodes and one or more GPUs.

[0108] In at least one embodiment, a processor (e.g., Figure 1 The processor 110, the processor 116 and / or the processor 128) includes one or more circuits for executing the API (e.g., Figure 1 Get memory attribute API 136 and / or Figure 4 API 400) to indicate that one or more users of the API (e.g., using Figure 4 The one or more parameters of the API 400) indicate whether the one or more storages correspond to one or more non-uniform memory access (NUMA) storages (e.g., Figure 1 memory 112 or memory 118) or one or more graphics processing units (GPUs) storage (e.g., Figure 1In at least one embodiment, the API is used to indicate the NUMA node to which data was last prefetched by another API. In at least one embodiment, the API is used to indicate the NUMA node set as the preferred location of one or more memory addresses by another API. In at least one embodiment, the API is used to indicate the location type and location identifier of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, the API is used to receive one or more inputs indicating a group of memories. In at least one embodiment, the one or more storages indicated by one or more users are a group of virtual memories accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, the API is used to return an identifier of the location type and an identifier of the location identifier based at least in part on the one or more inputs indicating a group of memories. In at least one embodiment, the processor includes one or more circuits that execute the API to provide an indication of a subset of the CPU set to the user based at least in part on one or more virtual memory addresses shared between the subset of CPUs and the one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API to provide an indication of a NUMA node to a user based at least in part on one or more virtual memory addresses shared between the NUMA node and one or more GPUs. In at least one embodiment, the processor includes one or more circuits for executing an API to obtain an indication of a NUMA node based at least in part on an input parameter indicating a set of managed memory attributes to be obtained.

[0109] In at least one embodiment, the system includes one or more processors (e.g., Figure 1 110, processor 116, and / or processor 128), the one or more processors for executing the API (e.g., Figure 1 Get memory attribute API 136 and / or Figure 4 API 400) to indicate that one or more users of the API (e.g., using Figure 4 The one or more parameters of the API 400) indicate whether the one or more storages correspond to one or more non-uniform memory access (NUMA) storages (e.g., Figure 1 112) or one or more graphics processing units (GPUs) storing (e.g., Figure 1In at least one embodiment, the API is used to indicate the NUMA node to which data stored using one or more virtual memory addresses was last explicitly prefetched. In at least one embodiment, the API is used to indicate the NUMA node that is set as the preferred storage location for a set of virtual memory addresses. In at least one embodiment, the API is used to indicate the NUMA node to which a set of virtual memories indicated by one or more users were last prefetched. In at least one embodiment, information indicating one or more virtual memory locations accessible by one or more NUMA nodes and one or more GPUs is used as input to the API to indicate one or more storages indicated by one or more users of the API. In at least one embodiment, the API is used to indicate the NUMA node to which a set of virtual memories accessible by one or more NUMA nodes and one or more GPUs was last prefetched using the API.

[0110] In at least one embodiment, an API (e.g., Figure 1 The memory location preference API 132 and / or Figure 2 The API 200 is used to indicate a preference that physical memory of a subset of the set of CPUs is to be used for virtual addresses shared by the subset of CPUs and the GPU. In at least one embodiment, this is a preference (e.g., expressed as a hint via the API), and execution of the API causes the memory manager to use the preference when it determines where to locate physical memory, but may not comply with the preference (e.g., a heuristic indicates that another location is better or if the subset of CPUs has insufficient memory). In at least one embodiment, the subset of CPUs is a NUMA node, and the API receives an identifier of the NUMA node.

[0111] In at least one embodiment, an API (e.g., Figure 1 The memory prefetch API 134 and / or Figure 3 The API 300 is used to cause data stored at a virtual address shared by a subset of CPUs and a GPU to be pre-fetched to a physical memory of a subset of the set of CPUs. In at least one embodiment, the input to the API specifies a virtual address and an identifier of the subset of CPUs. In at least one embodiment, the identifier is a NUMA node identifier. In at least one embodiment, executing the API causes the data stored at the virtual address to be stored in the physical memory of the identified subset of CPUs.

[0112] In at least one embodiment, an API (e.g., Figure 1 Get memory attribute API 136 and / or Figure 4 API 400) is used to indicate preferences to the user (using such as Figure 2In at least one embodiment, the API allows a user to input a virtual memory address into the API and obtain an indication of what preference has been set for the location of physical memory for that virtual memory. In at least one embodiment, the input to the API includes a virtual memory address shared between the set of CPUs and the GPU. In at least one embodiment, execution of the API causes an identifier of a subset of the set of CPUs to be provided to the user (e.g., to enable the user to change the preference).

[0113] Fig. 9 900 is a block diagram illustrating a driver and / or runtime environment 900 including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, the software program 902 is a software module. In at least one embodiment, the software program 902 includes one or more software modules, including but not limited to at least one of the software modules described herein. Figure 8 In at least one embodiment, the software modules are as follows Figure 8 In at least one embodiment, one or more APIs 910 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, executing the software instructions includes running the software instructions. In at least one embodiment, in conjunction with Figure 8 One or more aspects of one or more software modules shown or described are included in part in a software program 902 (e.g., instructions and / or code for calling a function when executed by a processor) and in part in one or more APIs 910 and / or functions 912 (e.g., instructions and / or code that implement the called function when executed by a processor).

[0114] In at least one embodiment, one or more APIs 910 are allocated or otherwise provided as part of one or more libraries 906, drivers and / or runtimes 904, and / or any other software grouping, non-transitory computer-readable instructions, and / or executable code further described herein. In at least one embodiment, one or more APIs 910 perform one or more computing operations in response to a call by a software program 902. In at least one embodiment, a software program 902 is a collection of software codes, commands, instructions, or other text sequences that instruct a computing device to perform one or more computing operations and / or call one or more other instruction sets (such as APIs 910 or API functions 912) to be executed. In at least one embodiment, the functionality provided by one or more APIs 910 includes software functions 912, such as those functions that can be used to accelerate one or more portions of a software program 902 using one or more parallel processing units (PPUs), such as a graphics processing unit (GPU). In at least one embodiment, the APIs 910 and / or API functions 912 include functions for performing operations related to a computing device. Figure 1 One or more APIs in the API set 130, Figure 2 API 200, Figure 3 API 300, Figure 4 API400, Figure 5 Technology 500, Figure 6 TECH 600 and / or Figure 7 The technology 700 illustrates or describes one or more aspects of the API and / or functionality.

[0115] In at least one embodiment, the API 910 is a hardware interface to one or more circuits that are used to perform one or more computing operations. In at least one embodiment, one or more software APIs 910 described herein are implemented as one or more circuits that are used to perform the operations described herein in conjunction with Figures 1 to 8 In at least one embodiment, one or more software programs 902 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the techniques described herein. Figures 1 to 8In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to manage virtual memory and / or allocate or otherwise reserve one or more blocks of memory 914 of one or more NUMA nodes and / or one or more PPUs (such as GPUs). In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to manage virtual memory and / or allocate or otherwise reserve blocks of memory.

[0116] In at least one embodiment, a user-implemented software program (e.g., Figure 1 A software program 902, such as an application 142 (such as an application 142 of FIG. 1 ), utilizes one or more application programming interfaces (APIs) 910 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations as further described herein performed by a parallel processing unit (PPU) such as a graphics processing unit (GPU). In at least one embodiment, the one or more APIs 910 provide a callable function set 912, referred to herein as an API, an API function, and / or a function, which respectively perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, the processor uses an API including an indication of a preferred location of managed memory function 916. In at least one embodiment, the indication of a preferred location of managed memory function 916 performs Figure 1 Memory location preference API 132, Figure 2 API 200, Figure 5 TECH 500 and / or Figure 8 In at least one embodiment, the processor uses an API including a prefetch managed memory function 918. In at least one embodiment, the prefetch managed memory function 918 performs Figure 1 Memory prefetch API 134, Figure 3 API 300, Figure 6 TECH 600 and / or Figure 8 In at least one embodiment, the processor uses an API including a get managed memory attribute function 920. In at least one embodiment, the get managed memory attribute function 920 performs Figure 1 Get memory attribute API 136, Figure 4 API 400, Figure 7 ART 700 and / or Figure 8One or more aspects of the managed memory attribute acquisition module 808.

[0117] In at least one embodiment, one or more software programs 902 interact with or otherwise communicate with one or more APIs 910 to perform one or more computing operations using one or more NUMA nodes and one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations that are accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 902 interact with one or more APIs 910 to facilitate parallel computing using remote or local interfaces.

[0118] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 912 provided by the one or more APIs 910. In at least one embodiment, the software programs 902 use a native interface when a software developer compiles the one or more software programs 902 in conjunction with one or more libraries 906 that include or otherwise provide access to the one or more APIs 910. In at least one embodiment, the one or more software programs 902 are statically compiled in conjunction with precompiled libraries 906 or uncompiled source code that includes instructions for executing the one or more APIs 910. In at least one embodiment, the one or more software programs 902 are dynamically compiled and the one or more software programs are linked to the one or more precompiled libraries 906 that include the one or more APIs 910 using a linker.

[0119] In at least one embodiment, the software program 902 uses a remote interface when the software program utilizes or otherwise communicates with a library 906 including one or more APIs 910 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 906 including one or more APIs 910 are to be executed by a remote computing service such as a computing resource service provider. In another embodiment, the one or more libraries 906 including one or more APIs 910 are to be executed by any other computing host that provides the one or more APIs 910 to the one or more software programs 902.

[0120] In at least one embodiment, a processor executing or using one or more software programs 902 calls, uses, executes, or otherwise implements one or more APIs 910 to allocate and otherwise manage memory to be used by the software programs 902. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 to allocate and otherwise manage memory to be used by one or more portions of the software programs 902 to accelerate the software programs 902 using one or more PPUs such as a GPU or any other accelerator or processor further described herein.

[0121] In at least one embodiment, the API in one or more APIs 910 is an API for facilitating parallel computing. In at least one embodiment, the one or more APIs 910 include any other APIs further described herein. In at least one embodiment, the one or more APIs 910 are provided by a driver and / or runtime 904. In at least one embodiment, the API in one or more APIs 910 is provided by a CUDA user mode driver. In at least one embodiment, the API in one or more APIs 910 is provided by a CUDA runtime. In at least one embodiment, the driver 904 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 912 of the API 910 during the loading and execution of one or more parts of the software program 902. In at least one embodiment, the driver and / or runtime 904 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 912 of the API 910 during the execution of the software program 902. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 implemented or otherwise provided by a driver and / or runtime 904 to perform combined arithmetic operations by the one or more software programs 902 during execution by one or more PPUs (e.g., GPUs).

[0122] Data Center

[0123] The following figure illustrates, but is not limited to, an exemplary data center system that can be used to implement at least one embodiment. In at least one embodiment, one or more of the data center components in the following figure can implement Figures 1 to 9 In at least one embodiment, one or more data center components include: Figure 1In at least one embodiment, one or more components of computer system 102 (e.g., NUMA node 108, NUMA node 110, processor 110, processor 116, compiler 138, memory 112, memory 118, API set 130, code 140, GPU 120, and / or one or more components of node set 144). In at least one embodiment, one or more data center components execute Figure 2 API 200, Figure 3 API 300 and / or Figure 4 In at least one embodiment, one or more data center components perform Figure 5 Technology 500, Figure 6 TECH 600 and / or Figure 7 In at least one embodiment, one or more data center components include: Figure 8 The processor 800 and / or Figure 8 In at least one embodiment, one or more data center components include and / or perform Fig. 9 One or more aspects of the environment 900 (e.g., a driver and / or runtime 904, one or more APIs 910, and / or one or more functions in function 912).

[0124] Fig.10 An example data center 1000 is shown in accordance with at least one embodiment. In at least one embodiment, data center 1000 includes, but is not limited to, a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0125] In at least one embodiment, Fig.10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node CRs") 1016 (1)-1016 (N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 1016 (1)-1016 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), data processing units ("DPUs") in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1016 (1)-1016 (N) may be a server having one or more of the above computing resources.

[0126] In at least one embodiment, the grouped computing resources 1014 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 1014 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0127] In at least one embodiment, resource coordinator 1012 may configure or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may include a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource coordinator 1012 may include hardware, software, or some combination thereof.

[0128] In at least one embodiment, Fig.10As shown, the framework layer 1020 includes, but is not limited to, a job scheduler 1032, a configuration manager 1034, a resource manager 1036, and a distributed file system 1038. In at least one embodiment, the framework layer 1020 may include a framework that supports software 1052 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1052 or the application 1042 may include a web-based service software or application, such as a service or application provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a free and open source software network application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 1038 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 1032 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 1000. In at least one embodiment, the configuration manager 1034 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and a distributed file system 1038 for supporting large-scale data processing. In at least one embodiment, the resource manager 1036 may be capable of managing clustered or grouped computing resources mapped to or allocated to support the distributed file system 1038 and the job scheduler 1032. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1014 on the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1036 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0129] In at least one embodiment, software 1052 included in software layer 1030 may include software used by at least a portion of node CRs 1016(1)-1016(N), grouped computing resources 1014, and / or distributed file system 1038 of framework layer 1020. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0130] In at least one embodiment, one or more applications 1042 included in application layer 1040 may include one or more types of applications used by at least a portion of node CRs 1016(1)-1016(N), grouped computing resources 1014, and / or distributed file system 1038 of framework layer 1020. The one or more types of applications may include, but are not limited to, CUDA applications.

[0131] In at least one embodiment, any of the configuration manager 1034, resource manager 1036, and resource coordinator 1012 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 1000 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0132] Computer-based systems

[0133] The following figures set forth, but are not limited to, exemplary computer-based systems that can be used to implement at least one embodiment. In at least one embodiment, one or more of the computer-based systems in the following figures implement Figures 1 to 9 In at least one embodiment, one or more computer-based systems include: Figure 1 In at least one embodiment, one or more computer-based systems execute one or more components of computer system 102 (e.g., NUMA node 108, NUMA node 110, processor 110, processor 116, compiler 138, memory 112, memory 118, API set 130, code 140, GPU 120, and / or one or more components of node set 144). Figure 2 API 200, Figure 3 API 300 and / or Figure 4 In at least one embodiment, one or more computer-based systems perform Figure 5 Technology 500, Figure 6 TECH 600 and / or Figure 7 In at least one embodiment, one or more computer-based systems include: Figure 8 The processor 800 and / or Figure 8 In at least one embodiment, one or more computer-based systems include and / or execute Fig. 9One or more aspects of the environment 900 (e.g., a driver and / or runtime 904, one or more APIs 910, and / or one or more functions of function 912).

[0134] Fig.11 A processing system 1100 is shown according to at least one embodiment. In at least one embodiment, the system 1100 includes one or more processors 1102 and one or more graphics processors 1108, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1102 or processor cores 1107. In at least one embodiment, the processing system 1100 is a processing platform incorporated into a system on a chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device. In at least one embodiment, the processor core 1107 is referred to as a computing unit or an operation unit.

[0135] In at least one embodiment, the processing system 1100 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the processing system 1100 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 1100 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1100 is a television or set-top box device having one or more processors 1102 and a graphical interface generated by one or more graphics processors 1108.

[0136] In at least one embodiment, one or more processors 1102 each include one or more processor cores 1107 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1107 is configured to process a specific instruction set 1109. In at least one embodiment, the instruction set 1109 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing through very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1107 can each process a different instruction set 1109, which can include instructions that help emulate other instruction sets. In at least one embodiment, the processor core 1107 can also include other processing devices, such as a digital signal processor (DSP).

[0137] In at least one embodiment, the processor 1102 includes a cache memory (cache) 1104. In at least one embodiment, the processor 1102 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor 1102. In at least one embodiment, the processor 1102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share the logic between the processor cores 1107 using known cache coherence techniques. In at least one embodiment, the processor 1102 additionally includes a register file 1106, and the processor 1102 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1106 may include general registers or other registers.

[0138] In at least one embodiment, one or more processors 1102 are coupled to one or more interface buses 1110 to transmit communication signals, such as address, data, or control signals, between the processor 1102 and other components in the system 1100. In at least one embodiment, the interface bus 1110 can be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus 1110 is not limited to a DMI bus, and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1102 includes an integrated memory controller 1116 and a platform controller hub 1130. In at least one embodiment, the memory controller 1116 facilitates communication between storage devices and other components of the processing system 1100, while the platform controller hub (PCH) 1130 provides connections to input / output (I / O) devices through a local I / O bus. In at least one embodiment, the one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface for the processor.

[0139] In at least one embodiment, the storage device 1120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a processor memory. In at least one embodiment, the storage device 1120 may be used as a system memory of the processing system 1100 to store data 1122 and instructions 1121 for use when one or more processors 1102 execute applications or processes. In at least one embodiment, the memory controller 1116 is also coupled to an optional external graphics processor 1112, which may communicate with one or more graphics processors 1108 in the processor 1102 to perform graphics and media operations. In at least one embodiment, a display device 1111 may be connected to the processor 1102. In at least one embodiment, the display device 1111 may include one or more internal display devices, such as in a mobile electronic device or portable computer device or an external display device connected via a display interface (e.g., a display port (DisplayPort) or the like). In at least one embodiment, the display device 1111 may include a head mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0140] In at least one embodiment, the platform controller hub 1130 enables peripheral devices to be connected to the storage device 1120 and the processor 1102 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1146, a network controller 1134, a firmware interface 1128, a wireless transceiver 1126, a touch sensor 1125, a data storage device 1124 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1124 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1128 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 1134 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1110. In at least one embodiment, the audio controller 1146 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1100 includes an optional legacy I / O controller 1140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 1100. In at least one embodiment, the platform controller hub 1130 can also be connected to one or more universal serial bus (USB) controllers 1142, which connect input devices such as a keyboard and mouse 1143 combination, a camera 1144, or other USB input devices.

[0141] In at least one embodiment, instances of the memory controller 1116 and the platform controller hub 1130 may be integrated into a discrete external graphics processor, such as the external graphics processor 1112. In at least one embodiment, the platform controller hub 1130 and / or the memory controller 1116 may be external to one or more processors 1102. For example, in at least one embodiment, the processing system 1100 may include the external memory controller 1116 and the platform controller hub 1130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 1102.

[0142] Fig.12A computer system 1200 is shown according to at least one embodiment. In at least one embodiment, the computer system 1200 may be a system with interconnected devices and components, a SOC, or some combination. In at least one embodiment, the computer system 1200 is formed by a processor 1202, which may include an execution unit for executing instructions. In at least one embodiment, the computer system 1200 may include, but is not limited to, components, such as the processor 1202, which employs an execution unit including logic to execute algorithms for process data. In at least one embodiment, the computer system 1200 may include a processor, such as a PENTIUM 1200 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0143] In at least one embodiment, computer system 1200 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0144] In at least one embodiment, computer system 1200 may include, but is not limited to, processor 1202, which may include, but is not limited to, one or more execution units 1208, which may be configured to execute Compute Unified Device Architecture ("CUDA") Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, the computer system 1200 is a single processor desktop or server system. In at least one embodiment, the computer system 1200 may be a multi-processor system. In at least one embodiment, the processor 1202 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0145] In at least one embodiment, processor 1202 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. In at least one embodiment, processor 1202 may include a combination of internal and external caches. In at least one embodiment, register file 1206 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

[0146] In at least one embodiment, an execution unit 1208, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1202. The processor 1202 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1208 may include logic for processing a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of the general purpose processor 1202, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general purpose processor 1202. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations on one data element at a time.

[0147] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1220 may store instructions 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0148] In at least one embodiment, the system logic chip may be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 1216, and the processor 1202 may communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 may provide a high bandwidth memory path 1218 to the memory 1220 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 may initiate data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, the memory 1220, and the system I / O 1222. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via a high bandwidth memory path 1218 , and the graphics / video card 1212 may be coupled to the MCH 1216 via an Accelerated Graphics Port (“AGP”) interconnect 1214 .

[0149] In at least one embodiment, the computer system 1200 can use the system I / O 1222 as a proprietary hub interface bus to couple the MCH 1216 to an I / O controller hub ("ICH") 1230. In at least one embodiment, the ICH 1230 can provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples can include, but are not limited to, an audio controller 1229, a firmware hub ("Flash BIOS") 1228, a wireless transceiver 1226, a data store 1224, a traditional I / O controller 1223 including a user input 1225 and a keyboard interface, a serial expansion port 1227 (e.g., USB), and a network controller 1234. The data store 1224 can include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0150] In at least one embodiment, Fig.12 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Fig.12 An exemplary SoC may be shown. In at least one embodiment, Fig.12 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1200 are interconnected using a compute express link (CXL) interconnect.

[0151] Fig.13 A system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1300 is an electronic device utilizing a processor 1310. In at least one embodiment, the system 1300 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more local or cloud service providers, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0152] In at least one embodiment, system 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (version 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig.13 A system is shown, which includes interconnected hardware devices or "chips". In at least one embodiment, Fig.13 An exemplary SoC may be shown. In at least one embodiment, Fig.13 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.13 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0153] In at least one embodiment, Fig.13 The display 1324, touch screen 1325, touch pad 1330, near field communication unit ("NFC") 1345, sensor hub 1340, thermal sensor 1346, fast chipset ("EC") 1335, trusted platform module ("TPM") 1338, BIOS / firmware / flash ("BIOS, FW Flash") 1322, DSP 1360, solid state disk ("SSD") or hard disk drive ("HDD") 1320, wireless local area network unit ("WLAN") 1350, Bluetooth unit 1352, wireless wide area network unit ("WWAN") 1356, global positioning system (GPS) 1355, camera ("USB 3.0 camera") 1354 (e.g., USB 3.0 camera) or low power double data rate ("LPDDR") memory unit ("LPDDR3") 1315 implemented in, for example, the LPDDR3 standard may be included. Each of these components may be implemented in any suitable manner.

[0154] In at least one embodiment, other components may be communicatively coupled to the processor 1310 through the components discussed above. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to the sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to the EC 1335. In at least one embodiment, a speaker 1363, an earphone 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1362, which in turn may be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1362 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352 and the WWAN unit 1356 may be implemented as a next generation form factor (NGFF).

[0155] Fig.14 An exemplary integrated circuit 1400 according to at least one embodiment is shown. In at least one embodiment, the exemplary integrated circuit 1400 is a SoC, which can be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1400 includes one or more application processors 1405 (e.g., CPU), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1400 includes peripheral or bus logic, which includes a USB controller 1425, a UART controller 1430, a SPI / SDIO controller 1435, and an I2S / I2C controller 1440. In at least one embodiment, the integrated circuit 1400 may include a display device 1445 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1450 and a mobile industrial processor interface (mipI) display interface 1455. In at least one embodiment, storage may be provided by a flash subsystem 1460, including flash memory and a flash controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1470 .

[0156] Fig.15A computing system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 1500 includes a processing subsystem 1501 having one or more processors 1502 and a system memory 1504 communicating via an interconnect path that may include a memory hub 1505. In at least one embodiment, the memory hub 1505 may be a separate component within a chipset component or may be integrated within one or more processors 1502. In at least one embodiment, the memory hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. In at least one embodiment, the I / O subsystem 1511 includes an I / O hub 1507 that may enable the computing system 1500 to receive input from one or more input devices 1508. In at least one embodiment, the I / O hub 1507 may enable a display controller, included in one or more processors 1502, to provide output to one or more display devices 1510A. In at least one embodiment, the one or more display devices 1510A coupled to the I / O hub 1507 may include local, internal, or embedded display devices.

[0157] In at least one embodiment, the processing subsystem 1501 includes one or more parallel processors 1512 coupled to the memory hub 1505 via a bus or other communication link 1513. In at least one embodiment, the communication link 1513 can be one of many standard-based communication link technologies or protocols, such as but not limited to PCIe, or can be a communication interface or communication structure for a vendor. In at least one embodiment, the one or more parallel processors 1512 form a parallel or vector processing system in a computing concentration, which can include a large number of processing cores and / or processing clusters, such as many integrated core processors or computing units. In at least one embodiment, the one or more parallel processors 1512 form a graphics processing subsystem that can output pixels to one of the one or more display devices 1510A coupled via the I / O hub 1507. In at least one embodiment, the one or more parallel processors 1512 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 1510B.

[0158] In at least one embodiment, system storage unit 1514 can be connected to I / O hub 1507 to provide a storage mechanism for computing system 1500. In at least one embodiment, I / O switch 1516 can be used to provide an interface mechanism to enable connection between I / O hub 1507 and other components, such as network adapter 1518 and / or wireless network adapter 1519 that can be integrated into the platform, as well as various other devices that can be added through one or more additional devices 1520. In at least one embodiment, network adapter 1518 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1519 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0159] In at least one embodiment, computing system 1500 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1507. Fig.15 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0160] In at least one embodiment, one or more parallel processors 1512 include circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1512 include circuits optimized for general processing. In at least one embodiment, the components of the computing system 1500 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1512, memory hub 1505, processor 1502, and I / O hub 1507 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 1500 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1500 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, the I / O subsystem 1511 and the display device 1510B are omitted from the computing system 1500. In at least one embodiment, one or more parallel processors 1512 include one or more tensor memory accelerator (TMA) units that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, for example, from global memory to shared memory and vice versa.

[0161] Processing system

[0162] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment. In at least one embodiment, one or more processing systems of the following figures implement Figure 1-9 In at least one embodiment, one or more processing systems include: Figure 1 In at least one embodiment, one or more processing systems execute one or more components of computer system 102 (e.g., NUMA node 108, NUMA node 110, processor 110, processor 116, compiler 138, memory 112, memory 118, API set 130, code 140, GPU 120, and / or one or more components of node set 144). Figure 2 API 200, Figure 3 API 300 and / or Figure 4 In at least one embodiment, one or more processing systems execute Figure 5 Technology 500, Figure 6 TECH 600 and / or Figure 7 In at least one embodiment, one or more processing systems include Figure 8 The processor 800 and / or Figure 8 In at least one embodiment, one or more processing systems include and / or execute Fig. 9 One or more aspects of the environment 900 (e.g., a driver and / or runtime 904, one or more APIs 910, and / or one or more functions of function 912).

[0163] Fig.16 An accelerated processing unit ("APU") 1600 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1600 was developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, the APU 1600 may be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1600 includes, but is not limited to, a core complex 1610, a graphics complex 1640, a fabric 1660, an I / O interface 1670, a memory controller 1680, a display controller 1692, and a multimedia engine 1694. In at least one embodiment, the APU 1600 may include, but is not limited to, any combination of any number of core complexes 1610, any number of graphics complexes 1640, any number of display controllers 1692, and any number of multimedia engines 1694. For purposes of illustration, multiple instances of similar objects are represented herein by reference numerals, where the reference numeral identifies the object and the number in parentheses identifies the desired instance.

[0164] In at least one embodiment, core complex 1610 is a CPU, graphics complex 1640 is a GPU, and APU 1600 is a processing unit that is not limited to 1610 and 1640 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1610, while other tasks may be assigned to graphics complex 1640. In at least one embodiment, core complex 1610 is configured to execute main control software associated with APU 1600, such as an operating system. In at least one embodiment, core complex 1610 is the main processor of APU 1600, which controls and coordinates the operations of other processors. In at least one embodiment, core complex 1610 issues commands that control the operations of graphics complex 1640. In at least one embodiment, core complex 1610 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1640 may be configured to execute device executable code derived from CUDA source code.

[0165] In at least one embodiment, core complex 1610 includes, but is not limited to, cores 1620(1)-1620(4) and L3 cache 1630. In at least one embodiment, core complex 1610 may include, but is not limited to, any number of cores 1620 and any combination of any number and type of caches. In at least one embodiment, cores 1620 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1620 is a CPU core. In at least one embodiment, cores 1620 are referred to as computational units or operational units.

[0166] In at least one embodiment, each core 1620 includes, but is not limited to, a fetch / decode unit 1622, an integer execution engine 1624, a floating point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes these instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1624 and the floating point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 can dispatch one micro-instruction to the integer execution engine 1624 and another micro-instruction to the floating point execution engine 1626 at the same time. In at least one embodiment, the integer execution engine 1624 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating point engine 1626 performs, but is not limited to, floating point and vector operations. In at least one embodiment, the fetch-decode unit 1622 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1624 and the floating point execution engine 1626.

[0167] In at least one embodiment, each core 1620(i) may access an L2 cache 1628(i) included in the core 1620(i), where i is an integer representing a specific instance of the core 1620. In at least one embodiment, each core 1620 included in a core complex 1610(j) is connected to other cores 1620 included in the core complex 1610(j) via an L3 cache 1630(j) included in the core complex 1610(j), where j is an integer representing a specific instance of the core complex 1610. In at least one embodiment, a core 1620 included in a core complex 1610(j) may access all L3 caches 1630(j) included in the core complex 1610(j), where j is an integer representing a specific instance of the core complex 1610. In at least one embodiment, the L3 cache 1630 may include, but is not limited to, any number of slices.

[0168] In at least one embodiment, graphics complex 1640 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1640 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1640 is configured to perform operations that are not related to graphics. In at least one embodiment, graphics complex 1640 is configured to perform both graphics-related operations and graphics-independent operations.

[0169] In at least one embodiment, graphics complex 1640 includes, but is not limited to, any number of compute units 1650 and L2 cache 1642. In at least one embodiment, compute units 1650 share L2 cache 1642. In at least one embodiment, L2 cache 1642 is partitioned. In at least one embodiment, graphics complex 1640 includes, but is not limited to, any number of compute units 1650 and any number (including zero) and type of caches. In at least one embodiment, graphics complex 1640 includes, but is not limited to, any number of dedicated graphics hardware.

[0170] In at least one embodiment, each computing unit 1650 includes, but is not limited to, any number of SIMD units 1652 and shared memory 1654. In at least one embodiment, each SIMD unit 1652 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each computing unit 1650 can execute any number of thread blocks, but each thread block is executed on a single computing unit 1650. In at least one embodiment, thread blocks include, but are not limited to, any number of execution threads. In at least one embodiment, a work group is a thread block. In at least one embodiment, each SIMD unit 1652 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, a prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicated via a shared memory 1654. In at least one embodiment, each compute unit 1650 includes one or more thread block clusters, where the thread block clusters enable programmatic control of locality at a granularity greater than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently on a streaming multiprocessor to synchronize data and cooperatively acquire, exchange, or otherwise use data.

[0171] In at least one embodiment, fabric 1660 is a system interconnect that facilitates data and control transfers across core complex 1610, graphics complex 1640, I / O interface 1670, memory controller 1680, display controller 1692, and multimedia engine 1694. In at least one embodiment, APU 1600 may include, but is not limited to, any number and type of system interconnects in addition to or in lieu of fabric 1660 that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 1670. In at least one embodiment, peripheral devices coupled to I / O interface 1670 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0172] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 1694 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, memory controller 1680 facilitates data transfer between APU 1600 and unified system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share unified system memory 1690.

[0173] In at least one embodiment, APU 1600 implements a memory subsystem including, but not limited to, any number and type of memory controllers 1680 and memory devices (e.g., shared memory 1654) that may be dedicated to one component or shared among multiple components. Components. In at least one embodiment, APU 1600 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1628, L3 cache 1630, and L2 cache 1642), each of which may be private to a component or shared among any number of components (e.g., core 1620, core complex 1610, SIMD unit 1652, compute unit 1650, and graphics complex 1640).

[0174] Fig.17A CPU 1700 according to at least one embodiment is shown. In at least one embodiment, the CPU 1700 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1700 may be configured to execute an application program. In at least one embodiment, the CPU 1700 is configured to execute a main control software, such as an operating system. In at least one embodiment, the CPU 1700 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1700 may be configured to execute a host executable code derived from a CUDA source code, and the external GPU may be configured to execute a device executable code derived from such a CUDA source code. In at least one embodiment, the CPU 1700 includes, but is not limited to, any number of core complexes 1710, structures 1760, I / O interfaces 1770, and memory controllers 1780.

[0175] In at least one embodiment, core complex 1710 includes, but is not limited to, cores 1720(1)-1720(4) and L3 cache 1730. In at least one embodiment, core complex 1710 may include, but is not limited to, any number of cores 1720 and any combination of any number and type of caches. In at least one embodiment, cores 1720 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1720 is a CPU core.

[0176] In at least one embodiment, each core 1720 includes, but is not limited to, a fetch / decode unit 1722, an integer execution engine 1724, a floating point execution engine 1726, and an L2 cache 1728. In at least one embodiment, the fetch / decode unit 1722 fetches instructions, decodes these instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1724 and the floating point execution engine 1726. In at least one embodiment, the fetch / decode unit 1722 can dispatch one micro-instruction to the integer execution engine 1724 and another micro-instruction to the floating point execution engine 1726 at the same time. In at least one embodiment, the integer execution engine 1724 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating point engine 1726 performs, but is not limited to, floating point and vector operations. In at least one embodiment, the fetch-decode unit 1722 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1724 and the floating point execution engine 1726.

[0177] In at least one embodiment, each core 1720(i) may access an L2 cache 1728(i) included in the core 1720(i), where i is an integer representing a specific instance of the core 1720. In at least one embodiment, each core 1720 included in a core complex 1710(j) is connected to other cores 1720 in the core complex 1710(j) via an L3 cache 1730(j) included in the core complex 1710(j), where j is an integer representing a specific instance of the core complex 1710. In at least one embodiment, a core 1720 included in a core complex 1710(j) may access all L3 caches 1730(j) included in the core complex 1710(j), where j is an integer representing a specific instance of the core complex 1710. In at least one embodiment, the L3 cache 1730 may include, but is not limited to, any number of slices.

[0178] In at least one embodiment, fabric 1760 is a system interconnect that facilitates data and control transfers across core complexes 1710(1)-1710(N) (where N is an integer greater than zero), I / O interface 1770, and memory controller 1780. In at least one embodiment, CPU 1700 may include, in addition to or in lieu of fabric 1760, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1700. In at least one embodiment, I / O interface 1770 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 1770. In at least one embodiment, peripherals coupled to I / O interface 1770 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0179] In at least one embodiment, memory controller 1780 facilitates data transfers between CPU 1700 and system memory 1790. In at least one embodiment, core complex 1710 and graphics complex 1740 share system memory 1790. In at least one embodiment, CPU 1700 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1780 and memory devices that may be dedicated to one component or shared between multiple components. In at least one embodiment, CPU 1700 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1728 and L3 cache 1730), each of which may be private to a component or shared between any number of components (e.g., core 1720 and core complex 1710).

[0180] Fig.18 An exemplary accelerator integrated slice 1890 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general package, line card, or chip.

[0181] The application effective address space 1882 within the system memory 1814 stores process elements 1883. In one embodiment, the process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on the processor 1807. The process element 1883 contains the processing state of the corresponding application 1880. The work descriptor (WD) 1884 contained in the process element 1883 can be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 1884 is a pointer to a job request queue in the application effective address space 1882.

[0182] Graphics acceleration module 1846 and / or each graphics processing engine can be shared by all or part of the processes in the system. In at least one embodiment, an infrastructure for establishing a processing state and sending WD 1884 to graphics acceleration module 1846 to start a job in a virtualized environment can be included.

[0183] In at least one embodiment, a dedicated process programming model is implemented for. In this model, a single process owns a graphics acceleration module 1846 or an individual graphics processing engine. Since the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1846 is allocated.

[0184] In operation, the WD acquisition unit 1891 in the accelerator integrated slice 1890 acquires the next WD 1884, which includes an indication of the work to be completed by one or more graphics processing engines of the graphics acceleration module 1846. Data from the WD 1884 can be stored in registers 1845 for use by a memory management unit (MMU) 1839, an interrupt management circuit 1847, and / or an environment management circuit 1848, as shown. For example, one embodiment of the MMU 1839 includes a segment / page roaming circuit for accessing a segment / page table 1886 within an OS virtual address space 1885. The interrupt management circuit 1847 can process an interrupt event (INT) 1892 received from the graphics acceleration module 1846. When performing a graph operation, an effective address 1893 generated by the graphics processing engine is converted to an actual address by the MMU 1839.

[0185] In one embodiment, the same register set 1845 is replicated for each graphics processing engine and / or graphics acceleration module 1846 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 1890. An exemplary register that can be initialized by a hypervisor is shown in Table 1.

[0186] Table 1 – Registers initialized by the hypervisor

[0187] 1 Slice Control Register

[0188] 2 Real address (RA) plan processing area pointer

[0189] 3. Permission shield overwrite register

[0190] 4 Interrupt vector table input offset

[0191] 5 Interrupt vector table entry restrictions

[0192] 6 Status Register

[0193] 7 Logical Partition ID

[0194] 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer

[0195] 9 Storage Description Register

[0196] Example registers that may be initialized by the operating system are shown in Table 2.

[0197] Table 2 – Operating System Initialization Registers

[0198] 1. Process and Thread Identification

[0199] 2 Effective Address (EA) environment save / restore pointer

[0200] 3 Virtual Address (VA) Accelerator Utilization Record Pointer

[0201] 4 Virtual Address (VA) storage segment table pointer

[0202] 5. Permission blocking

[0203] 6 Job Descriptors

[0204] In one embodiment, each WD 1884 is specific to a specific graphics acceleration module 1846 and / or a specific graphics processing engine. It contains all the information needed by the graphics processing engine to do its work or work, or it can be a pointer to a memory location where the application has established a command queue for the work to be done.

[0205] Figures 19A-19B An exemplary graphics processor according to at least one embodiment of the present invention is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits can be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used in a SoC.

[0206] Fig.19A An exemplary graphics processor 1910 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig.19B An additional exemplary graphics processor 1940 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, Fig.19A The graphics processor 1910 is a low power graphics processor core. In at least one embodiment, Fig.19B The graphics processor 1940 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 may be Fig.14 A variant of graphics processor 1410.

[0207] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, so that the vertex processor 1905 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1915A-1915N use the primitives and vertex data generated by the vertex processor 1905 to generate a frame buffer displayed on a display device. In at least one embodiment, fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0208] In at least one embodiment, graphics processor 1910 additionally includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide a mapping of virtual to physical addresses for graphics processor 1910, including for vertex processors 1905 and / or fragment processors 1915A-1915N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B may synchronize with other MMUs within the system, including with Fig.14 One or more MMUs associated with one or more application processors 1405, image processor 1415, and / or video processor 1420 enable each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable graphics processor 1910 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0209] In at least one embodiment, graphics processor 1940 includes Fig.19AOne or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B of a graphics processor 1910. In at least one embodiment, a graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F, to 1955N-1 and 1955N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tile operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0210] Fig. 20A 2000 according to at least one embodiment. In at least one embodiment, the graphics core 2000 may include Fig.14 In at least one embodiment, the graphics core 2000 may be Fig.19BIn at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020, which are common to the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A-2001N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2000. The slices 2001A-2001N may include support logic including a local instruction cache 2004A-2004N, a thread scheduler 2006A-2006N, a thread dispatcher 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, the slices 2001A-2001N may include a set of additional function units (AFUs) 2012A-2012N, floating point units (FPUs) 2014A-2014N, integer arithmetic logic units (ALUs) 2016A-2016N, address calculation units (ACUs) 2013A-2013N, double precision floating point units (DPFPUs) 2015A-2015N, and matrix processing units (MPUs) 2017A-2017N. In at least one embodiment, the graphics core 2000 is referred to as a compute unit or an operation unit.

[0211] In one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017A-2017N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2012A-2012N can perform additional logical operations that are not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.). In at least one embodiment, graphics core 2000 is referred to as a computing unit or a computer unit.

[0212] Fig. 20BA general purpose graphics processing unit (GPGPU) 2030 in at least one embodiment is shown. In at least one embodiment, GPGPU 2030 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 2030 can be configured to enable highly parallel computing operations to be performed by a GPU array. In at least one embodiment, GPGPU 2030 can be directly linked to other instances of GPGPU 2030 to create a multi-GPU cluster to improve the execution time for CUDA programs. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to achieve connection with a host processor. In at least one embodiment, host interface 2032 is a PCIe interface. In at least one embodiment, host interface 2032 can be a manufacturer-specific communication interface or communication structure. In at least one embodiment, GPGPU 2030 receives commands from a host processor and uses a global scheduler 2034 to dispatch execution threads associated with those commands to a group of computing clusters 2036A-2036H. In at least one embodiment, the computing clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 can be used as a high-level cache for cache memories within the computing clusters 2036A-2036H.

[0213] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled to compute cluster 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memory 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0214] In at least one embodiment, computing clusters 2036A-2036H each include a set of graphics cores, such as Fig. 20A The graphics core 2000, which may include multiple types of integer and floating point logic units, may perform computational operations with various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 2036A-2036H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0215] In at least one embodiment, multiple instances of GPGPU 2030 may be configured to operate as a computing cluster. Computing clusters 2036A-2036H may implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2030 communicate through host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 with GPU link 2040, enabling direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via network devices accessible via host interface 2032. In at least one embodiment, GPU link 2040 may be configured to be connected to a host processor, in addition to or in lieu of host interface 2032. In at least one embodiment, GPGPU 2030 may be configured to execute CUDA programs.

[0216] Fig.21A A parallel processor 2100 is shown in accordance with at least one embodiment. In at least one embodiment, various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0217] In at least one embodiment, parallel processor 2100 includes parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes I / O unit 2104, which enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 is connected to other devices by using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2104 forms a communication link. In at least one embodiment, I / O unit 2104 is connected to host interface 2106 and memory cross switch 2116, wherein host interface 2106 receives commands for performing processing operations and memory cross switch 2116 receives commands for performing memory operations.

[0218] In at least one embodiment, when the host interface 2106 receives the command buffer via the I / O unit 2104, the host interface 2106 can direct work operations to execute those commands to the front end 2108. In at least one embodiment, the front end 2108 is coupled with a scheduler 2110, which is configured to distribute commands or other work items to the processing array 2112. In at least one embodiment, the scheduler 2110 ensures that the processing array 2112 is properly configured and in a valid state before assigning tasks to the processing array 2112 in the processing array 2112. In at least one embodiment, the scheduler 2110 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 2112. In at least one embodiment, the host software can prove the workload for scheduling on the processing array 2112 through one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2112 by scheduler 2110 logic within a microcontroller that includes scheduler 2110 .

[0219] In at least one embodiment, the processing array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N). In at least one embodiment, each cluster 2114A-2114N of the processing array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may allocate work to the clusters 2114A-2114N of the processing array 2112 using various scheduling and / or work allocation algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2110, or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by the processing array 2112. In at least one embodiment, different clusters 2114A-2114N of the processing array 2112 may be allocated to process different types of programs or to perform different types of computations.

[0220] In at least one embodiment, the processing array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2112 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0221] In at least one embodiment, the processing array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2112 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2112 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from the system memory via the I / O unit 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in an on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0222] In at least one embodiment, when the parallel processing unit 2102 is used to perform graph processing, the scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better distribute the graphics processing operations to multiple clusters 2114A-2114N of the processing array 2112. In at least one embodiment, portions of the processing array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2114A-2114N can be stored in a buffer to allow the intermediate data to be transferred between the clusters 2114A-2114N for further processing.

[0223] In at least one embodiment, the processing array 2112 can receive processing tasks to be performed via the scheduler 2110, which receives commands defining the processing tasks from the front end 2108. In at least one embodiment, the processing tasks can include an index of data to be processed, which can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain an index corresponding to a task, or can receive an index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing array 2112 is configured to a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0224] In at least one embodiment, each of the one or more instances of parallel processing unit 2102 can be coupled to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar switch 2116, which can receive memory requests from processing array 2112 and I / O unit 2104. In at least one embodiment, memory crossbar switch 2116 can access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B to partition unit 2120N), which can each be coupled to a portion of parallel processor memory 2122 (e.g., memory units). In at least one embodiment, the plurality of partition units 2120A-2120N are configured to be equal to the number of memory cells, such that the first partition unit 2120A has a corresponding first memory cell 2124A, the second partition unit 2120B has a corresponding memory cell 2124B, and the Nth partition unit 2120N has a corresponding Nth memory cell 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not be equal to the number of memory devices.

[0225] In at least one embodiment, the memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across the memory units 2124A-2124N, allowing the partition units 2120A-2120N to write to portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 2122. In at least one embodiment, local instances of the parallel processor memory 2122 can be eliminated to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

[0226] In at least one embodiment, any of the clusters 2114A-2114N of the processing array 2112 can process data to be written to any memory unit 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or another cluster 2114A-2114N, and the cluster 2114A-2114N can perform other processing operations on the output. In at least one embodiment, each cluster 2114A-2114N can communicate with the memory interface 2118 through the memory crossbar 2116 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2116 has connections to memory interface 2118 to communicate with I / O unit 2104, and connections to local instances of parallel processor memory 2122, thereby enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar switch 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0227] In at least one embodiment, multiple instances of parallel processing unit 2102 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 may include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2102 or parallel processor 2100 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0228] Fig.21BA processing cluster 2194 according to at least one embodiment is shown. In at least one embodiment, the processing cluster 2194 is included in a parallel processing unit. In at least one embodiment, the processing cluster 2194 is an instance of one of the processing clusters 2114A-2114N of Figure 21. In at least one embodiment, the processing cluster 2194 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit, which is configured to issue instructions to a group of processing engines in each processing cluster 2194.

[0229] In at least one embodiment, the operation of the processing cluster 2194 can be controlled by the pipeline manager 2132 that allocates processing tasks to the SIMT parallel processor. In at least one embodiment, the pipeline manager 2132 receives instructions from the scheduler 2110 of Figure 21 and manages the execution of these instructions through the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures can be included in the processing cluster 2194. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 can be included in the processing cluster 2194. In at least one embodiment, the graphics multiprocessor 2134 can process data, and the data crossbar switch 2140 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar switch 2140.

[0230] In at least one embodiment, each graphics multiprocessor 2134 within a processing cluster 2194 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0231] In at least one embodiment, the instructions transmitted to the processing cluster 2194 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes the program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, a thread group may include fewer threads than a plurality of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group may also include more threads than a plurality of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing may be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups may be executed simultaneously on the graphics multiprocessor 2134.

[0232] In at least one embodiment, the graphics multiprocessor 2134 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can abandon the internal cache and use the cache memory within the processing cluster 2194 (e.g., L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 can also access the partition unit (e.g., Fig.21A 2120N) that are shared between all processing clusters 2194 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2194 includes multiple instances of graphics multiprocessor 2134, which can share common instructions and data that can be stored in L1 cache 2148.

[0233] In at least one embodiment, each processing cluster 2194 may include an MMU 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside within the memory interface 2118 of FIG. 21 . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (talk more about tiles) and optionally to cache line indexes. In at least one embodiment, the MMU 2145 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or L1 cache 2148 or processing cluster 2194. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0234] In at least one embodiment, the processing clusters 2194 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data, for example. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2194 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2116. In at least one embodiment, a pre-raster operations unit (preROP) 2142 is configured to receive data from the graphics multiprocessor 2134, direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 2120A-2120N of FIG. 21). In at least one embodiment, the PreROP 2142 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0235] Fig. 21C A graphics multiprocessor 2196 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2196 is Fig.21B2166. In at least one embodiment, the graphics multiprocessor 2196 is coupled to the pipeline manager 2132 of the processing cluster 2194. In at least one embodiment, the graphics multiprocessor 2196 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more GPGPU cores 2162, and one or more LSUs 2166. The GPGPU cores 2162 and the LSUs 2166 are coupled to the cache memory 2172 and the shared memory 2170 via a memory and cache interconnect 2168.

[0236] In at least one embodiment, the instruction cache 2152 receives the instruction stream to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In one embodiment, the instruction unit 2154 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2162. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 2166.

[0237] In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2196. In at least one embodiment, register file 2158 provides temporary storage for operands for data paths of functional units (e.g., GPGPU core 2162, LSU 2166) connected to graphics multiprocessor 2196. In at least one embodiment, register file 2158 is divided between each functional unit so that a dedicated portion of register file 2158 is allocated to each functional unit. In at least one embodiment, register file 2158 is divided between different thread groups being executed by graphics multiprocessor 2196.

[0238] In at least one embodiment, the GPGPU cores 2162 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 2196. The GPGPU cores 2162 may be similar in architecture or the architecture may be different. In at least one embodiment, the first portion of the GPGPU core 2162 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2196 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed or special-function logic.

[0239] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction to multiple sets of data. In at least one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8 and SIMD9 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0240] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2196 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the LSU 2166 to implement load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, so that the latency of data transfer between the GPGPU core 2162 and the register file 2158 is very low. In at least one embodiment, the shared memory 2170 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2196. In at least one embodiment, the cache memory 2172 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2172, threads executing on GPGPU core 2162 may programmatically store data in shared memory.

[0241] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0242] Fig. 22A graphics processor 2200 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated within a multi-core processing system.

[0243] In at least one embodiment, the graphics processor 2200 receives batches of commands via a ring interconnect 2202. In at least one embodiment, the input commands are interpreted by a command streamer 2203 in a pipeline front end 2204. In at least one embodiment, the graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2203 provides the commands to a geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, the command streamer 2203 provides the commands to a video front end 2234, which is coupled to a media engine 2237. In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2233 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280A.

[0244] In at least one embodiment, the graphics processor 2200 includes scalable thread execution resources featuring modular graphics cores 2280A-2280N (sometimes referred to as core slices), each of which has multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2200 can have any number of graphics cores 2280A to 2280N. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, the graphics processor 2200 is a low-power processor having a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A-2280N, each of which includes a group of first sub-cores 2250A-2250N and a group of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first set of execution units (EUs) 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each of the sub-cores 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0245] Fig.23 A processor 2300 is shown for use according to at least one embodiment. In at least one embodiment, the processor 2300 may include, but is not limited to, logic circuits for executing instructions. In at least one embodiment, the processor 2300 may execute instructions, including x86 instructions, ARM instructions, special instructions for ASICs, and the like. In at least one embodiment, the processor 2310 may include registers for storing packed data, such as 64-bit wide MMXTM registers in microprocessors enabled by MMX technology as Intel Corporation, Santa Clara, California. In at least one embodiment, MMX registers available in integer and floating point form may operate with packed data elements, which are accompanied by SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX or higher versions (generally referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, the processor 2310 may execute instructions to accelerate CUAD programs.

[0246] In at least one embodiment, the processor 2300 includes an in-order front end ("front end") 2301 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, the front end 2301 may include several units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and provides the instructions to an instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2328 decodes the received instructions into one or more operations of so-called "microinstructions" or "micro-operations" (also referred to as "micro-operations" or "microinstructions") for execution. In at least one embodiment, the instruction decoder 2328 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, the trace cache 2330 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2334 for execution. In at least one embodiment, when the trace cache 2330 encounters a complex instruction, the microcode ROM 2332 provides the microinstructions required to complete the operation.

[0247] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2332. In at least one embodiment, the trace cache 2330 references the entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 2332 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 completes the micro-operation sequencing of the instruction, the front end 2301 of the machine may resume fetching micro-operations from the trace cache 2330.

[0248] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2303 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance when the instructions go down the pipeline and are scheduled for execution. The out-of-order execution engine 2303 includes, but is not limited to, a distributor / register renamer 2340, a memory microinstruction queue 2342, an integer / floating point microinstruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general floating point scheduler ("slow / general FP scheduler") 2304, and a simple floating point scheduler ("simple FP scheduler") 2306. In at least one embodiment, the fast scheduler 2302, the slow / general floating point scheduler 2304, and the simple floating point scheduler 2306 are also collectively referred to as "microinstruction schedulers 2302, 2304, 2306". The distributor / register renamer 2340 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2340 renames the logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2340 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2342 for memory operations and an integer / floating point microinstruction queue 2344 for non-memory operations, in front of the memory scheduler 2346 and the microinstruction schedulers 2302, 2304, 2306. In at least one embodiment, the microinstruction schedulers 2302, 2304, 2306 determine when the microinstructions are ready to execute based on the readiness of their slave input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2302 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2304 and the simple floating point scheduler 2306 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2302, 2304, 2306 arbitrate dispatch ports to schedule microinstructions for execution.

[0249] In at least one embodiment, execution block 2311 includes, but is not limited to, integer register file / branch network 2308, floating point register file / branch network ("FP register file / branch network") 2310, address generation units ("AGU") 2312 and 2314, fast arithmetic logic units ("fast ALU") 2316 and 2318, slow ALU 2320, floating point ALU ("FP") 2322, and floating point move unit ("FP move") 2324. In at least one embodiment, integer register file / branch network 2308 and floating point register file / bypass network 2310 are also referred to herein as "register files 2308, 2310". In at least one embodiment, ALUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating point ALU 2322, and floating point move unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0250] In at least one embodiment, register files 2308, 2310 can be arranged between microinstruction schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322 and 2324. In at least one embodiment, integer register file / branch network 2308 performs integer operations. In at least one embodiment, floating point register file / branch network 2310 performs floating point operations. In at least one embodiment, each of register files 2308, 2310 can include but is not limited to a branch network that can bypass or forward the just completed results that have not yet been written to the register file to a new slave object. In at least one embodiment, register files 2308, 2310 can communicate data with each other. In at least one embodiment, integer register file / branch network 2308 can include but is not limited to two separate register files, one register file for low-order 32-bit data, and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2310 may include, but is not limited to, 128-bit wide entries, since floating point instructions typically have operands that are 64 to 128 bits wide.

[0251] In at least one embodiment, the execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 can execute instructions. In at least one embodiment, the register files 2308, 2310 store integer and floating point data operand values ​​that the microinstructions need to execute. In at least one embodiment, the processor 2300 may include, but is not limited to, any number of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 and combinations thereof. In at least one embodiment, the floating point ALU 2322 and the floating point move unit 2324 can perform floating point, MMX, SIMD, AVX and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2322 may include, but is not limited to, a 64-bit by 64-bit floating point divider to perform division, square root and remainder micro-operations. In at least one embodiment, floating point hardware may be used to process instructions involving floating point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2316, 2318. In at least one embodiment, fast ALUs 2316, 2318 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 2320 because slow ALU 2320 can include, but is not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2312, 2314. In at least one embodiment, fast ALUs 2316, fast ALUs 2318, and slow ALUs 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALUs 2316, fast ALUs 2318, and slow ALUs 2320 can be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, the floating point ALU 2322 and floating point move unit 2324 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2322 and floating point move unit 2324 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0252] In at least one embodiment, microinstruction schedulers 2302, 2304, 2306 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in processor 2300, processor 2300 can also include logic for handling memory misses. In at least one embodiment, if the data load in the data cache misses, there may be dependent operations running in the pipeline, which temporarily prevents the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0253] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. On the contrary, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packaging data.

[0254] Fig.24 A processor 2400 is shown according to at least one embodiment. In at least one embodiment, the processor 2400 includes, but is not limited to, one or more processor cores (cores) 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. In at least one embodiment, the processor 2400 may include additional cores up to and including the additional processor core 2402N represented by the dashed box. In at least one embodiment, each processor core 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also access one or more shared cache units 2406. In at least one embodiment, the one or more processor cores 2402A-2402N are referred to as one or more computational units or operation units.

[0255] In at least one embodiment, the internal cache units 2404A-2404N and the shared cache unit 2406 represent a cache memory hierarchy within the processor 2400. In at least one embodiment, the cache memory units 2404A-2404N may include at least one level of instructions and data within each processor core and one or more levels of cache in a shared mid-level cache, such as L2, L3, Level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2406 and 2404A-2404N. In at least one embodiment, one or more processor cores 2402A-2402N are referred to as one or more computing units or computing units.

[0256] In at least one embodiment, the processor 2400 may also include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2410 provides management functions for various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external memory devices (not shown).

[0257] In at least one embodiment, one or more processor cores 2402A-2402N include support for multiple threads simultaneously. In at least one embodiment, system agent core 2410 includes components for coordinating and operating processor cores 2402A-2402N during multithreaded processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit (PCU) that includes logic and components to adjust one or more power states of processor cores 2402A-2402N and graphics processor 2408.

[0258] In at least one embodiment, the processor 2400 additionally includes a graphics processor 2408 to perform graphics processing operations. In at least one embodiment, the graphics processor 2408 is coupled to a shared cache unit 2406 and a system agent core 2410 including one or more integrated memory controllers 2414. In at least one embodiment, the system agent core 2410 also includes a display controller 2411 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2411 may also be a separate module coupled to the graphics processor 2408 via at least one interconnect, or may be integrated within the graphics processor 2408.

[0259] In at least one embodiment, a ring-based interconnect unit 2412 is used to couple the internal components of the processor 2400. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0260] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2418 (e.g., eDRAM modules). In at least one embodiment, each of processor cores 2402A-2402N and graphics processor 2408 uses embedded memory module 2418 as a shared LLC.

[0261] In at least one embodiment, the processor cores 2402A-2402N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of ISA, wherein one or more processor cores 2402A-2402N execute a common instruction set, while one or more other processor cores 2402A-2402N execute a subset of a common instruction set or a different instruction set. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2400 can be implemented on one or more chips or as a SoC integrated circuit.

[0262] Fig.25A graphics processor core 2500 is shown in accordance with at least one described embodiment. In at least one embodiment, the graphics processor core 2500 is included within a graphics core array. In at least one embodiment, the graphics processor core 2500 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2500 is an example of a graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2500 may include a fixed function block 2530 coupled to a plurality of sub-cores 2501A-2501F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0263] In at least one embodiment, fixed function block 2530 includes a geometry / fixed function pipeline 2536, which may be shared by all sub-cores in graphics processor 2500, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2536 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0264] In at least one embodiment, the fixed function block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. The graphics SoC interface 2537 provides an interface between the graphics core 2500 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 2538 is a programmable subprocessor that can be configured to manage various functions of the graphics processor 2500, including thread dispatching, scheduling, and preemption. In at least one embodiment, the media pipeline 2539 includes logic that helps decode, encode, pre-process, and / or post-process multimedia data including image and video data. In at least one embodiment, the media pipeline 2539 implements media operations via requests to calculation or sampling logic within the sub-cores 2501-2501F.

[0265] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2537 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline), and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 may also implement power management controls for the graphics core 2500 and enable interfaces between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables command buffers to be received from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to media pipeline 2539 when media operations are to be performed, or may be assigned to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2536, geometry and fixed function pipeline 2514) when graph processing operations are to be performed.

[0266] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform various scheduling and management tasks for the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graph and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2502A-2502F, 2504A-2504F in the sub-cores 2501A-2501F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2500 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, graphics microcontroller 2538 may also facilitate low power or idle states for graphics core 2500, thereby providing graphics core 2500 with the ability to save and restore registers across low power state transitions within graphics core 2500 independent of an operating system and / or graphics driver software on the system.

[0267] In at least one embodiment, the graphics core 2500 may have more or fewer sub-cores than the sub-cores 2501A-2501F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, the graphics core 2500 may also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipelines 2514, and additional fixed function logic 2516 to accelerate various graphics and compute processing operations. In at least one embodiment, the shared function logic 2510 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that may be shared by each of the N sub-cores within the graphics core 2500. The shared and / or cache memory 2512 may be the LLC for the N sub-cores 2501A-2501F within the graphics core 2500, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2514 may be included in place of geometry / fixed function pipeline 2536 within fixed function block 2530 and may include the same or similar logic units.

[0268] In at least one embodiment, the graphics core 2500 includes additional fixed function logic 2516, which may include various fixed function acceleration logic for use by the graphics core 2500. In at least one embodiment, the additional fixed function logic 2516 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and the culling pipeline within the geometry / fixed function pipeline 2516, 2536, it is an additional geometry pipeline that may be included in the additional fixed function logic 2516. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, so that shading can be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2516 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0269] In at least one embodiment, the additional fixed function logic 2516 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing a slowed down CUAD program.

[0270] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2501A-2501F, which can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-core 2501A-2501F includes multiple EU arrays 2502A-2502F, 2504A-2504F, thread dispatch and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. Each of the EU arrays 2502A-2502F, 2504A-2504F includes multiple execution units, which are GUGPUs capable of servicing graphics, media, or computing operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computing shader programs. In at least one embodiment, the TD / IC logic 2503A-2503F performs local thread dispatching and thread control operations for the execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2505A-2505F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2501A-2501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2501A-2501F may utilize shared local memory 2508A-2508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0271] Fig.26A parallel processing unit ("PPU") 2600 is shown according to at least one embodiment. In at least one embodiment, the PPU 2600 is configured with machine-readable code that, if executed by the PPU 2600, causes the PPU 2600 to perform some or all of the processes and techniques described throughout this document. In at least one embodiment, the PPU 2600 is a multithreaded processor implemented on one or more integrated circuit devices, and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by the PPU 2600. In at least one embodiment, the PPU 2600 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device (such as an LCD device). In at least one embodiment, the PPU 2600 is used to perform calculations, such as linear algebra operations and machine learning operations. Fig.26 The example parallel processor is shown for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0272] In at least one embodiment, one or more PPUs 2600 are configured to accelerate high performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2600 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2600 includes, but is not limited to, I / O unit 2606, front end unit 2610, scheduler unit 2612, work distribution unit 2614, hub 2616, crossbar switch (“Xbar”) 2620, one or more general processing clusters (“GPC”) 2618, and one or more partition units (“memory partition units”) 2622. In at least one embodiment, PPU 2600 is connected to a host processor or other PPU 2600 via one or more high-speed GPU interconnects (“GPU interconnects”) 2608. In at least one embodiment, PPU 2600 is connected to a host processor or other peripheral devices via a system bus or interconnect 2602. In one embodiment, PPU 2600 is connected to a local memory including one or more memory devices ("memory") 2604. In at least one embodiment, memory device 2604 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0273] In at least one embodiment, the high-speed GPU interconnect 2608 may refer to a wire-based multi-channel communication link that the system uses to scale and includes one or more PPUs 2600 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2600 and the CPU and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2608 transmits data and / or commands to other units of the PPU 2600, such as one or more copy engines, video encoders, video decoders, power management units, and / or other units in the PPU 2600 through the hub 2616. Fig.26 Other components that may not be explicitly shown.

[0274] In at least one embodiment, I / O unit 2606 is configured to receive data from a host processor ( Fig.26In at least one embodiment, the I / O unit 2606 communicates with the host processor directly through the system bus 2602 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2606 can communicate with one or more other processors (e.g., one or more PPUs 2600) via the system bus 2602. In at least one embodiment, the I / O unit 2606 implements a PCIe interface for communicating over a PCIe bus. In at least one embodiment, the I / O unit 2606 implements an interface for communicating with external devices.

[0275] In at least one embodiment, I / O unit 2606 decodes packets received via system bus 2602. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 2600 to perform various operations. In at least one embodiment, I / O unit 2606 sends the decoded commands to various other units of PPU 2600 as specified by the commands. In at least one embodiment, the commands are sent to front end unit 2610 and / or to hub 2616 or other units of PPU 2600, such as one or more replication engines, video encoders, video decoders, power management units, etc. ( Fig.26 In at least one embodiment, I / O unit 2606 is configured to route communications between various logical units of PPU 2600.

[0276] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2600 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2600—the host interface unit can be configured to access the buffer in the system memory connected to the system bus 2602 via the memory request transmitted via the I / O unit 2606 through the system bus 2602. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2600, so that the front end unit 2610 receives one or more command stream pointers and manages one or more command streams, reads commands from the command stream and forwards the commands to the various units of the PPU 2600.

[0277] In at least one embodiment, the front end unit 2610 is coupled to a scheduler unit 2612 that configures the various GPCs 2618 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2612 is configured to track state information related to the various tasks managed by the scheduler unit 2612, where the state information may indicate which GPC 2618 the task is assigned to, whether the task is active or inactive, a priority associated with the task, etc. In at least one embodiment, the scheduler unit 2612 manages multiple tasks that are executed on one or more GPCs 2618.

[0278] In at least one embodiment, the scheduler unit 2612 is coupled to a work distribution unit 2614, which is configured to dispatch tasks for execution on the GPCs 2618. In at least one embodiment, the work distribution unit 2614 tracks a plurality of scheduled tasks received from the scheduler unit 2612 and the work distribution unit 2614 manages a pending task pool and an active task pool for each GPC 2618. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2618; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively processed by the GPC 2618, such that as one of the tasks in the GPC 2618 completes execution, the task is evicted from the active task pool of the GPC 2618 and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2618. In at least one embodiment, if the active task is idle on GPC 2618, such as while waiting for data dependencies to be resolved, the active task is evicted from GPC 2618 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 2618.

[0279] In at least one embodiment, work distribution unit 2614 communicates with one or more GPCs 2618 via XBar 2620. In at least one embodiment, XBar 2620 is an interconnect network that couples many units of PPU 2600 to other units of PPU 2600 and can be configured to couple work distribution unit 2614 to a specific GPC 2618. In at least one embodiment, other units of one or more PPU 2600 can also be connected to XBar 2620 through hub 2616.

[0280] In at least one embodiment, the tasks are managed by the scheduler unit 2612 and assigned to one of the GPCs 2618 by the work distribution unit 2614. The GPC 2618 is configured to process the tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2618, routed to different GPCs 2618 via the XBar 2620, or stored in the memory 2604. In at least one embodiment, the results can be written to the memory 2604 via the partition unit 2622, which implements a memory interface for writing data to or reading data from the memory 2604. In at least one embodiment, the results can be transmitted to another PPU 2600 or CPU via the high-speed GPU interconnect 2608. In at least one embodiment, the PPU 2600 includes, but is not limited to, U partition units 2622, which is equal to the number of separate and different memory devices 2604 coupled to the PPU 2600.

[0281] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2600. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2600, and the PPU 2600 provides isolation, quality of service (“QoS”), and independent address spaces for multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2600, and the driver core outputs the tasks to one or more streams processed by the PPU 2600. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads, including instructions for executing tasks and exchanging data through a shared memory.

[0282] Fig. 27 FIG. 2 shows a GPC 2700 according to at least one embodiment. In at least one embodiment, the GPC 2700 is Fig.262618. In at least one embodiment, each GPC 2700 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2700 includes, but is not limited to, a pipeline manager 2702, a pre-raster operations unit ("PROP") 2704, a raster engine 2708, a work distribution crossbar ("WDX") 2716, a memory management unit ("MMU") 2718, one or more data processing clusters ("DPCs") 2706, and any suitable combination of components.

[0283] In at least one embodiment, the operation of the GPC 2700 is controlled by a pipeline manager 2702. In at least one embodiment, the pipeline manager 2702 manages the configuration of one or more DPCs 2706 to process tasks assigned to the GPC 2700. In at least one embodiment, the pipeline manager 2702 configures at least one of the one or more DPCs 2706 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2706 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2714. In at least one embodiment, the pipeline manager 2702 is configured to route packets received from the work distribution unit to appropriate logic units within the GPC 2700, and in at least one embodiment, some packets may be routed to fixed function hardware units in the PROP 2704 and / or the raster engine 2708, while other packets may be routed to the DPC 2706 for processing by the primitive engine 2712 or the SM 2714. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to execute at least a portion of a CUDA program.

[0284] In at least one embodiment, PROP unit 2704 is configured to route data generated by raster engine 2708 and DPC 2706 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Fig.252522, etc., described in more detail. In at least one embodiment, the PROP unit 2704 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2708 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2708 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information for the basic primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is transmitted to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2708 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2706).

[0285] In at least one embodiment, each DPC 2706 included in GPC 2700 includes, but is not limited to, an M-pipeline controller ("MPC") 2710; a primitive engine 2712; one or more SMs 2714; and any suitable combination thereof. In at least one embodiment, MPC 2710 controls the operation of DPC 2706, routing packets received from pipeline manager 2702 to appropriate units in DPC 2706. In at least one embodiment, packets associated with vertices are routed to primitive engine 2712, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to SM 2714.

[0286] In at least one embodiment, SM 2714 includes, but is not limited to, a programmable stream processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2714 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group simultaneously, and implements a single instruction, multiple data ("SIMD") architecture, wherein each thread in a group of threads (e.g., a warp) is configured to process different data sets based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, SM 2714 implements a single instruction, multiple thread ("SIMT") architecture, wherein each thread in a group of threads is configured to process different data sets based on the same instruction set, but wherein individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby achieving concurrency between warps and serial execution within the warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Fig.28 At least one embodiment of SM 2714 is described in further detail.

[0287] In at least one embodiment, MMU 2718 is used between GPC 2700 and memory partitioning unit (e.g., Fig.25 The MMU 2718 provides an interface between the partition unit 2522 of the memory, and provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2718 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0288] Fig.28 Streaming multiprocessor ("SM") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2800 is Fig. 27SM 2714. In at least one embodiment, SM 2800 includes, but is not limited to, instruction cache 2802; one or more scheduler units 2804; register file 2808; one or more processing cores ("cores") 2810; one or more special function units ("SFUs") 2812; one or more load / store units ("LSUs") 2814; interconnect network 2816; shared memory / level 1 ("L1") cache 2818; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), and each task is assigned to a specific data processing cluster ("DPC") within a GPC, and if the task is associated with a shader program, the task is assigned to one of SM 2800. In at least one embodiment, scheduler unit 2804 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2800. In at least one embodiment, the scheduler unit 2804 schedules thread blocks to execute as warps of parallel threads, wherein each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2804 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperative groups to various functional units (e.g., processing core 2810, SFU 2812, and LSU 2814) in each clock cycle. In at least one embodiment, the SM 2800 includes one or more thread block clusters, wherein the thread block clusters enable programmatic control of locality at a granularity greater than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, the thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently on a streaming multiprocessor to synchronize data and cooperatively acquire, exchange, or otherwise use data.

[0289] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, thereby enabling the expression of richer and more efficient parallel decompositions. In at least one embodiment, the cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of the conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads in a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, so that libraries and utility functions can be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperation group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization over an entire grid of thread blocks.

[0290] In at least one embodiment, the dispatch unit 2806 is configured to send instructions to one or more of the functional units, and the scheduler unit 2804 includes but is not limited to two dispatch units 2806 that enable two different instructions from the same thread warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2804 includes a single dispatch unit 2806 or additional dispatch units 2806.

[0291] In at least one embodiment, each SM 2800 includes, in at least one embodiment, but is not limited to, a register file 2808 that provides a set of registers for the functional units of the SM 2800. In at least one embodiment, the register file 2808 is divided between each functional unit, so that a dedicated portion of the register file 2808 is allocated to each functional unit. In at least one embodiment, the register file 2808 is divided between different thread warps executed by the SM 2800, and the register file 2808 provides temporary storage for operands of the data paths connected to the functional units. In at least one embodiment, each SM 2800 includes, but is not limited to, a plurality of L processing cores 2810. In at least one embodiment, the SM 2800 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2810. In at least one embodiment, each processing core 2810 includes, in at least one embodiment, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2810 includes, but is not limited to, 64 single precision (32-bit) floating point cores, 64 integer cores, 32 double precision (64-bit) floating point cores, and 8 tensor cores.

[0292] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2810. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0293] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating point accumulation operation on the 16-bit floating point input data. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as a CUDA-C++ API) exposes specialized matrix loads, matrix multiplications and accumulations, and matrix storage operations to efficiently use tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp level interface assumes a 16×16 size matrix across all 32 warp threads.

[0294] In at least one embodiment, each SM 2800 includes, but is not limited to, M SFUs 2812 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 2812 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 2812 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by shader programs executed by the SM 2800. In at least one embodiment, the texture maps are stored in a shared memory / L1 cache 2818. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 2800 includes, but is not limited to, two texture units.

[0295] In at least one embodiment, each SM 2800 includes, but is not limited to, N LSUs 2814 that implement load and store operations between a shared memory / L1 cache 2818 and a register file 2808. In at least one embodiment, each SM 2800 includes, but is not limited to, an interconnect network 2816 that connects each functional unit to a register file 2808, and the LSUs 2814 connect to the register file 2808 and the shared memory / L1 cache 2818. In at least one embodiment, the interconnect network 2816 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2808, and to connect the LSUs 2814 to memory locations in the register file 2808 and the shared memory / L1 cache 2818.

[0296] In at least one embodiment, the shared memory / L1 cache 2818 is an array of on-chip memory that allows data storage and communication between the SM 2800 and the primitive engines and between threads in the SM 2800 in at least one embodiment. In at least one embodiment, the shared memory / L1 cache 2818 includes, but is not limited to, a storage capacity of 128KB and is located in the path from the SM 2800 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2818 is used in at least one embodiment for caching reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2818, the L2 cache, and the memory is a backing store.

[0297] In at least one embodiment, data cache and shared memory functions are combined into a single memory block, providing improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use the shared memory or as a cache, for example, if the shared memory is configured to use half of the capacity, the texture and load / store operations can use the remaining capacity. According to at least one embodiment, the integration within the shared memory / L1 cache 2818 enables the shared memory / L1 cache 2818 to be used as a high throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, thereby creating a simpler programming model. In at least one embodiment, in a general parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 2800 to execute programs and perform computations, use shared memory / L1 cache 2818 to communicate between threads, and use LSU 2814 to read and write global memory through shared memory / L1 cache 2818 and memory partitioning units. In at least one embodiment, when configured for general parallel computing, SM 2800 writes commands to scheduler unit 2804 that can be used to start new work on a DPC. In at least one embodiment, SM 2800 includes one or more distributed shared memories (or distributed shared memories) that enable direct SM to SM operations such as load, store, and execute atomic operations on multiple SM shared memory blocks.

[0298] In at least one embodiment, SM 2800 includes one or more asynchronous execution functions, including a tensor memory accelerator (TMA) unit, which can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, for example, from global memory to shared memory and vice versa. In at least one embodiment, SM 2800 includes one or more TMAs for asynchronous copying between thread blocks in a cluster. In at least one embodiment, SM 2800 includes one or more asynchronous transaction barriers for performing atomic data movement and synchronization. In at least one embodiment, SM 2800 includes a tensor core transformer engine, which includes software and one or more cores for accelerating transformer model training and reasoning. In at least one embodiment, by re-projecting and scaling between FP8 and 16 bits in each layer of one or more neural networks, one or more processor cores of the transformer that executes one or more tensor core transformer engines manage FP8 and 16bit calculations and dynamically select between FP8 and 16bit calculations.

[0299] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a PDA, a digital camera, a vehicle, a head mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on a chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0300] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in a chipset of the motherboard.

[0301] Software Construction for General Computing

[0302] The following figures illustrate, but are not limited to, exemplary software configurations for implementing at least one embodiment.

[0303] Fig.29A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler instructions, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronosgroup), TM ), SYCL, or Intel One API.

[0304] In at least one embodiment, the software stack 2900 of the programming platform provides an execution environment for the application 2901. In at least one embodiment, the application 2901 may include any computer software that can be launched on the software stack 2900. In at least one embodiment, the application 2901 may include, but is not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0305] In at least one embodiment, the application 2901 and the software stack 2900 run on the hardware 2907. In at least one embodiment, the hardware 2907 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support programming platforms. In at least one embodiment, for example, using CUDA, the software stack 2900 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, in using OpenCL, the software stack 2900 can be used with devices from different vendors. In at least one embodiment, the hardware 2907 includes a host connected to one or more devices, which can be accessed via an application programming interface (API) call to perform computing tasks. In at least one embodiment, compared to the host in the hardware 2907, it may include but is not limited to a CPU (but may also include a computing device) and its memory, and the devices in the hardware 2907 may include but are not limited to a GPU, FPGA, AI engine or other computing device (but may also include a CPU) and its memory.

[0306] In at least one embodiment, the software stack 2900 of the programming platform includes, but is not limited to, multiple libraries 2903, runtimes 2905, and device kernel drivers 2906. In at least one embodiment, each of the libraries 2903 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the library 2903 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the library 2903 includes functions optimized for execution on one or more types of devices. In at least one embodiment, the library 2903 may include, but is not limited to, functions for performing math, deep learning, and / or other types of operations on the device. In at least one embodiment, the library 2903 is associated with a corresponding API 2902, which may include one or more APIs that expose functions implemented in the library 2903. In at least one embodiment, a processor (e.g., a CPU, a GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can launch a second kernel (e.g., a child kernel), and the second kernel can be used by the processor to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. In at least one embodiment, the processor executes an API or calls an API to be executed from a memory to support dynamic stream priorities (e.g., updating priorities when a stream is used to perform an operation). For example, when the processor executes the API, it allows a programmer to copy stream priorities from one stream to one or more other streams.

[0307] In at least one embodiment, the software stack 2900 includes an API for supporting dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows the programmer to set the priority of a stream at any time after creation. In at least one embodiment, the software stack 2900 includes an API for supporting dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows the programmer to obtain the current priority of a stream, where the priority is one of multiple attributes of a stream. In at least one embodiment, the software stack 2900 includes an API for supporting dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows the programmer to obtain the current priority of a stream as a single attribute. In at least one embodiment, the software stack 2900 includes an API for supporting dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows the programmer to launch the kernel to perform operations on the stream at a set priority (which may be different from the stream priority). In at least one embodiment, the software stack 2900 includes an API for indicating whether an object (e.g., a thread synchronization object such as a barrier) that tracks whether all data movement operations for a set of threads operating on a GPU are completed and have a specified state after a specified time period, wherein the specified state can be a state indicating that the data has been moved and is ready for use, and is specified using an expected parity value as an input to the API.

[0308] In at least one embodiment, the software stack 2900 includes one or more APIs for updating the kernel. In at least one embodiment, the processor executes an API or calls an API to be executed from a memory to update to an existing API to support context-free kernels, which allows programmers to add kernel nodes to a graph without a graphics context so that the graphics context can be dynamically associated with the kernel at runtime. In at least one embodiment, the software stack 2900 includes one or more APIs for allowing programmers to obtain a kernel identifier and a graphics context as separate parameters from a kernel node, thereby obtaining parameters from a kernel and a context-free kernel. In at least one embodiment, the software stack 2900 includes one or more APIs for starting a task graph (e.g., a task graph) and executing one or more task graphs (e.g., including one or more programs) using a parallel processor (such as, one or more graphics processing units).

[0309] In at least one embodiment, the software stack 2900 includes one or more APIs for associating one or more instructions with one or more memory ordering operations (e.g., fence or memory bar operations). In at least one embodiment, instructions are associated with one or more domains so that memory ordering operations are performed in association with one or more specific domains without interfering with instructions in other domains. The API is used to indicate that a thread has reached (e.g., at a thread synchronization barrier) or has completed a work phase associated with an asynchronous data movement operation on the GPU. In at least one embodiment, the software stack 2900 includes one or more APIs for allowing a programmer to manually indicate an expected transaction count when a thread has completed a work phase, which transaction count is used to update an object that tracks whether all data movement operations for a group of threads are completed.

[0310] In at least one embodiment, the application 2901 is written as source code that is compiled into executable code as follows: Figure 34-36 2901. In at least one embodiment, the executable code of the application 2901 can be run at least in part on an execution environment provided by the software stack 2900. In at least one embodiment, during the execution of the application 2901, code that needs to be run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, the runtime 2905 can be called to load and start the necessary code on the device. In at least one embodiment, the runtime 2905 can include any technically feasible runtime system capable of supporting the execution of the application 2901.

[0311] In at least one embodiment, runtime 2905 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 2904). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on a device (sometimes referred to as "kernels" when the function is a global function callable from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0312] In at least one embodiment, the runtime library and corresponding API 2904 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API may be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on top of a language-independent runtime API.

[0313] In at least one embodiment, one or more processors disclosed in the "processing system" may execute, access, or otherwise use the software stack 2900. For example, the APU 1600, the CPU 1700, the 19A-19B exemplary graphics processor, the general purpose graphics processing unit ("GPGPU") 2030, the parallel processor 2100, the processing cluster 2194, the graphics multiprocessor 2134, the graphics multiprocessor 2196, the graphics processor 2200, the processor 2300, the processor 2400, the parallel processing unit ("PPU") 2600, the GPC 2700, and / or the streaming multiprocessor ("SM") 2800 may execute, use, call, or otherwise implement (e.g., by accessing memory) one or more APIs included in the software stack 2900.

[0314] In at least one embodiment, the device kernel driver 2906 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2906 can provide APIs such as API 2904 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 2906 can be configured to compile the intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2906 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code (cache compiled binary code) for a specific target device at runtime, which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device, which may not exist when the source code is initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the need for the device kernel driver 2906 to compile the IR code at runtime.

[0315] Fig.30 According to at least one embodiment, Fig.293001. In at least one embodiment, the CUDA software stack 3000 on which the application 3001 can be launched includes a CUDA library 3003, a CUDA runtime 3005, a CUDA driver 3007, and a device kernel driver 3008. In at least one embodiment, the CUDA software stack 3000 is executed on hardware 3009, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0316] In at least one embodiment, the application 3001, the CUDA runtime 3005, and the device kernel driver 3008 can respectively perform functions similar to the application 2801, the runtime 2805, and the device kernel driver 2906, and the above combination Fig.29 It is described. In at least one embodiment, the CUDA driver 3007 includes a library (libcuda.so) that implements the CUDA driver API 3006. In at least one embodiment, similar to the CUDA runtime API 3004 implemented by the CUDA runtime library (cudart), the CUDA driver API 3006 can disclose but is not limited to functions for memory management, execution control, device management, error handling, synchronization and / or graphics interoperability, etc. In at least one embodiment, the CUDA driver API 3006 is different from the CUDA runtime API 3004 in that the CUDA runtime API 3004 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded library) management. In contrast to the high-level CUDA runtime API 3004, in at least one embodiment, the CUDA driver API 3006 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3006 can disclose functions for context management that are not disclosed by the CUDA runtime API 3004. In at least one embodiment, the CUDA driver API 3006 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 3004. Furthermore, in at least one embodiment, the development libraries including the CUDA runtime 3005 can be considered separate from the driver components, including the user-mode CUDA driver 3007 and the kernel-mode device driver 3008 (sometimes also referred to as a "display" driver).

[0317] In at least one embodiment, the CUDA library 3003 may include, but is not limited to, a math library, a deep learning library, a parallel algorithm library, and / or a signal / image / video processing library, which may be utilized by a parallel computing application (e.g., application 3001). In at least one embodiment, the CUDA library 3003 may include a math library, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, etc. In at least one embodiment, the CUDA library 3003 may include a deep learning library, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0318] Fig.31 According to at least one embodiment, Fig.29 In at least one embodiment, the ROCm software stack 3100 on which the application 3101 can be launched includes a language runtime 3103, a system runtime 3105, a thunk 3107, and a ROCm kernel driver 3108. In at least one embodiment, the ROCm software stack 3100 is executed on hardware 3109, which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0319] In at least one embodiment, application 3101 may execute in conjunction with the above Fig.29 In addition, in at least one embodiment, the language runtime 3103 and the system runtime 3105 can perform functions similar to those of the application 2901 discussed above. Fig.29The language runtime 3103 and the system runtime 3105 have similar functions. In at least one embodiment, the difference between the language runtime 3103 and the system runtime 3105 is that the system runtime 3105 is a language-independent runtime that implements the ROCr system runtime API 3104 and utilizes the heterogeneous system architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user mode API that exposes interfaces for accessing and interacting with AMDGPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3105, the language runtime 3103 is an implementation of a language-specific runtime API 3102 layered on top of the ROCr system runtime API 3104. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous computing interface ("HIP") language runtime API, a heterogeneous computing compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a combination of the above Fig.30 Functions similar to the CUDA runtime API 3004 discussed above, such as functions for memory management, execution control, device management, error handling, synchronization, etc.

[0320] In at least one embodiment, thunk (ROCt) 3107 is an interface 3106 that can be used to interact with the underlying ROCm driver 3108. In at least one embodiment, the ROCm driver 3108 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Fig.29 The HSA kernel driver 2906 is a device kernel driver that allows different types of processors to more efficiently share system resources via hardware features.

[0321] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3100 above the language runtime 3103 and provide for integration with the above. Fig.30 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFT, and the like.

[0322] Fig.32 According to at least one embodiment, Fig.29 3201. In at least one embodiment, the OpenCL software stack 3200 on which the application 3201 can be launched includes an OpenCL framework 3210, an OpenCL runtime 3206, and a driver 3207. In at least one embodiment, the OpenCL software stack 3200 is executed on hardware 3009 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0323] In at least one embodiment, the application 3201, the OpenCL runtime 3206, the device kernel driver 3207 and the hardware 3208 can each execute in conjunction with the above Fig.29 The discussed application 2901, runtime 2905, device kernel driver 2906, and hardware 2907 have similar functionality. In at least one embodiment, the application 3201 also includes an OpenCL kernel 3202 having code to be executed on the device.

[0324] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3203 and runtime API 3205. In at least one embodiment, the runtime API 3205 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, and the runtime API 3205 can use the context to manage the command queue, program objects and kernel objects, shared memory objects, etc. of the device. In at least one embodiment, the platform API 3203 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfers from and to devices, etc. In addition, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, etc.

[0325] In at least one embodiment, compiler 3204 is also included in OpenCL framework 3210. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3204, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0326] Fig.33 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform 3304 is configured to support various programming models 3303, middleware and / or libraries 3302, and frameworks 3301 that an application 3300 may rely on. In at least one embodiment, an application 3300 may be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0327] In at least one embodiment, programming platform 3304 can be a combination of the above Fig.30 , Fig.31 and Fig.32 One of the CUDA, ROCm, or OpenCL platforms described. In at least one embodiment, the programming platform 3304 supports multiple programming models 3303, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3303 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3303 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0328] In at least one embodiment, the library and / or middleware 3302 provides an abstract implementation of the programming model 3304. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3304, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3302 may include, but is not limited to, cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3302 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0329] In at least one embodiment, application framework 3301 relies on library and / or middleware 3302. In at least one embodiment, each application framework 3301 is a software framework for implementing a standard structure of application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0330] Fig.34 Compiled code according to at least one embodiment is shown to Figure 29-32 3401 is executed on one of the programming platforms of . In at least one embodiment, the compiler 3401 receives source code 3400, which includes both host code and device code. In at least one embodiment, the compiler 3401 is configured to convert the source code 3400 into a host executable code 3402 for execution on the host and a device executable code 3403 for execution on the device. In at least one embodiment, the source code 3400 can be compiled offline before executing the application, or compiled online during the execution of the application. In at least one embodiment, the compiler 3401 includes or accesses one or more libraries to identify API call sequences to execute a single fused API, where the single fused API is a combined API for two or more APIs.

[0331] In at least one embodiment, source code 3400 may include code in any programming language supported by compiler 3401, such as C++, C, Fortran, etc. In at least one embodiment, source code 3400 may be included in a single-source file having a mixture of host code and device code, and indicating the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3400 may include multiple source code files, rather than a single source file, in which host code and device code are separated.

[0332] In at least one embodiment, compiler 3401 is configured to compile source code 3400 into host executable code 3402 for execution on a host and device executable code 3403 for execution on a device. In at least one embodiment, compiler 3401 performs operations including parsing source code 3400 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3400 includes a single source file, compiler 3401 can separate device code from host code in such a single source file, compile the device code and host code into device executable code 3403 and host executable code 3402, respectively, and link device executable code 3403 and host executable code 3402 together in a single file, as described below with respect to Fig.35 discussed in more detail.

[0333] In at least one embodiment, host executable code 3402 and device executable code 3403 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3402 may include native object code, and device executable code 3403 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3402 and device executable code 3403 may include target binary code.

[0334] Fig.35 is a compiled code according to at least one embodiment to Figure 29-323501 is a more detailed illustration of the execution on one of the programming platforms of . In at least one embodiment, the compiler 3501 is configured to receive the source code 3500, compile the source code 3500, and output an executable file 3510. In at least one embodiment, the source code 3500 is a single source file, such as a .cu file, a .hip.cpp file, or a file in other formats, which includes both host code and device code. In at least one embodiment, the compiler 3501 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in a .cu file, or the HCC compiler for compiling HIP code in a .hip.cpp file.

[0335] In at least one embodiment, compiler 3501 includes compiler front end 3502, host compiler 3505, device compiler 3506, and linker 3509. In at least one embodiment, compiler front end 3502 is configured to separate device code 3504 from host code 3503 in source code 3500. In at least one embodiment, device code 3504 is compiled by device compiler 3506 into device executable code 3508, which may include binary code or IR code as described. In at least one embodiment, host code 3503 is separately compiled by host compiler 3505 into host executable code 3507. In at least one embodiment, for NVCC, host compiler 3505 may be, but is not limited to, a general C / C++ compiler that outputs native object code, and device compiler 3506 may be, but is not limited to, a low-level virtual machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3505 and the device compiler 3506 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0336] In at least one embodiment, after source code 3500 is compiled into host executable code 3507 and device executable code 3508, linker 3509 links host and device executable code 3507 and 3508 together in executable file 3510. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0337] Fig.363601, which converts the source code into a converted source code 3602. In at least one embodiment, a compiler 3603 is used to compile the converted source code 3602 into a host executable code 3604 and a device executable code 3605, similar to the process of compiler 3401 compiling source code 3400 into host executable code 3402 and device executable code 3403, as described above in conjunction with Fig.34 discussed.

[0338] In at least one embodiment, the conversion performed by conversion tool 3601 is used to port source code 3600 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, conversion tool 3601 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, conversion of source code 3600 may include parsing source code 3600 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figures 37A-38 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3601 may sometimes be incomplete, requiring additional manual work to fully port the source code 3600.

[0339] Configuring GPUs for general computing

[0340] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code according to at least one embodiment.

[0341] Fig.37AA system 3700 is shown configured to compile and execute CUDA source code 3710 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3700 includes, but is not limited to, CUDA source code 3710, a CUDA compiler 3750, a host executable 3770(1), a host executable 3770(2), a CUDA device executable 3784, a CPU 3790, a CUDA-enabled GPU 3794, a GPU 3792, a CUDA to HIP conversion tool 3720, a HIP source code 3730, a HIP compiler driver 3740, an HCC 3760, and an HCC device executable 3782.

[0342] In at least one embodiment, CUDA source code 3710 is a collection of human-readable code of the CUDA programming language. In at least one embodiment, CUDA code is human-readable code of the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, which includes but is not limited to defining device code and distinguishing between device code and host code. In at least one embodiment, device code is a source code that can be executed in parallel on a device after compilation. In at least one embodiment, a device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3790, GPU 37192, or another GPGPU. In at least one embodiment, host code is a source code that can be executed on a host after compilation. In at least one embodiment, a host is a processor optimized for sequential instruction processing, such as a CPU 3790.

[0343] In at least one embodiment, the CUDA source code 3710 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, global functions 3712, device functions 3714, host functions 3716, and host / device functions 3718 can be mixed in the CUDA source code 3710. In at least one embodiment, each global function 3712 is executable on a device and can be called from a host. Therefore, in at least one embodiment, one or more of the global functions 3712 can serve as an entry point for a device. In at least one embodiment, each global function 3712 is a kernel. In at least one embodiment and in a technique called dynamic parallelism, one or more global functions 3712 define a kernel that can be executed on a device and can be called from such a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on a device during execution.

[0344] In at least one embodiment, each device function 3714 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3716 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3716 defines both a host version of a function that is executable on a host and can only be called from such a host, and a device version of a function that is executable on a device and can only be called from such a device.

[0345] In at least one embodiment, the CUDA source code 3710 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3702. In at least one embodiment, the CUDA runtime API 3702 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host memory and device memory, managing systems with multiple devices, and the like. In at least one embodiment, the CUDA source code 3710 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, the CUDA API may be any API designed to be used by CUDA code. In at least one embodiment, the CUDA API includes, but is not limited to, the CUDA runtime API 3702, the CUDA driver API, an API for any number of CUDA libraries, and the like. In at least one embodiment and relative to the CUDA runtime API 3702, the CUDA driver API is a lower-level API, but may provide finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0346] In at least one embodiment, the CUDA compiler 3750 compiles input CUDA code (e.g., CUDA source code 3710) to generate host executable code 3770 (1) and CUDA device executable code 3784. In at least one embodiment, the CUDA compiler 3750 is NVCC. In at least one embodiment, the host executable code 3770 (1) is a compiled version of the host code included in the input source code executable on the CPU 3790. In at least one embodiment, the CPU 3790 can be any processor optimized for sequential instruction processing.

[0347] In at least one embodiment, the CUDA device executable code 3784 is a compiled version of the device code included in the input source code executable on the CUDA-enabled GPU 3794. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, IR code, such as PTX code, which is further compiled by the device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3794). In at least one embodiment, the CUDA-enabled GPU 3794 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 3794 is developed by NVIDIA Corporation of Santa Clara, California.

[0348] In at least one embodiment, the CUDA to HIP conversion tool 3720 is configured to convert the CUDA source code 3710 into a functionally similar HIP source code 3730. In at least one embodiment, the HIP source code 3730 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is a human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language, which includes but is not limited to a functionally similar version of the CUDA mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes but is not limited to a mechanism for defining global functions 3712, but such a HIP programming language may lack support for dynamic parallelism, and therefore, the global functions 3712 defined in the HIP code can only be called from the host.

[0349] In at least one embodiment, the HIP source code 3730 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, the HIP source code 3730 may also include any number of calls to any number of functions specified in the HIP runtime API 3732. In one embodiment, the HIP runtime API 3732 includes, but is not limited to, functionally similar versions of a subset of functions included in the CUDA runtime API 3702. In at least one embodiment, the HIP source code 3730 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP API includes, but is not limited to, the HIP runtime API 3732, the HIP driver API, an API for any number of HIP libraries, an API for any number of ROCm libraries, and the like.

[0350] In at least one embodiment, the CUDA to HIP conversion tool 3720 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts any number of calls to functions specified in the CUDA runtime API 3702 to any number of calls to functions specified in the HIP runtime API 3732.

[0351] In at least one embodiment, the CUDA to HIP conversion tool 3720 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3720 is a tool called hipify-clang, which performs a more complex and robust conversion process relative to hipify-perl, which involves parsing the CUDA code using clang (compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3720, correctly converting the CUDA code to HIP code may also require modifications (e.g., manual editing).

[0352] In at least one embodiment, the HIP compiler driver 3740 is a front end that determines the target device 3746 and then configures a compiler compatible with the target device 3746 to compile the HIP source code 3730. In at least one embodiment, the target device 3746 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3740 can determine the target device 3746 in any technically feasible manner.

[0353] In at least one embodiment, if the target device 3746 is CUDA compatible (e.g., a CUDA-enabled GPU 3794), the HIP compiler driver 3740 generates HIP / NVCC compile commands 3742. In at least one embodiment and in conjunction with Fig.37B As described in more detail, HIP / NVCC compile command 3742 configures CUDA compiler 3750 to compile HIP source code 3730 using, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries. In at least one embodiment and in response to HIP / NVCC compile command 3742, CUDA compiler 3750 generates host executable code 3770(1) and CUDA device executable code 3784.

[0354] In at least one embodiment, if the target device 3746 is not compatible with CUDA, the HIP compiler driver 3740 generates HIP / HCC compilation commands 3744. In at least one embodiment and in conjunction with Fig.37C Described in more detail, HIP / HCC compile command 3744 configures HCC 3760 to compile HIP source code 3730 using HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compile command 3744, HCC 3760 generates host executable code 3770 (2) and HCC device executable code 3782. In at least one embodiment, HCC device executable code 3782 is a compiled version of the device code included in HIP source code 3730 that can be executed on GPU 3792. In at least one embodiment, GPU 3792 can be any processor optimized for parallel instruction processing, incompatible with CUDA and compatible with HCC. In at least one embodiment, GPU 3792 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, GPU 3792 is a GPU 3792 that does not enable CUDA.

[0355] For illustrative purposes only, Fig.37A3710 for execution on the CPU 3790 and different devices. In at least one embodiment, the direct CUDA process compiles the CUDA source code 3710 for execution on the CPU 3790 and the CUDA-enabled GPU 3794 without converting the CUDA source code 3710 to the HIP source code 3730. In at least one embodiment, the indirect CUDA process converts the CUDA source code 3710 to the HIP source code 3730 and then compiles the HIP source code 3730 for execution on the CPU 3790 and the CUDA-enabled GPU 3794. In at least one embodiment, the CUDA / HCC process converts the CUDA source code 3710 to the HIP source code 3730 and then compiles the HIP source code 3730 for execution on the CPU 3790 and the GPU 3792.

[0356] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3750 receives a CUDA source code 3710 and a CUDA compile command 3748 that configures the CUDA compiler 3750 to compile the CUDA source code 3710. In at least one embodiment, the CUDA source code 3710 used in the direct CUDA flow is written in the CUDA programming language, which is based on other programming languages ​​other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3748, the CUDA compiler 3750 generates a host executable code 3770 (1) and a CUDA device executable code 3784 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3770 (1) and the CUDA device executable code 3784 can be executed on a CPU 3790 and a CUDA-enabled GPU 3794, respectively. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, PTX code, and is further compiled into binary code for a specific target device at runtime.

[0357] The indirect CUDA flow that can be implemented in at least one embodiment can be described by a dashed line and a series of bubble notes B1-B6. In at least one embodiment and as shown in bubble note B1, the CUDA to HIP conversion tool 3720 receives the CUDA source code 3710. In at least one embodiment and as shown in bubble note B2, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 to HIP source code 3730. In at least one embodiment and as shown in bubble note B3, the HIP compiler driver 3740 receives the HIP source code 3730 and determines whether the target device 3746 is CUDA enabled.

[0358] In at least one embodiment and as indicated by bubble note B4, HIP compiler driver 3740 generates HIP / NVCC compile commands 3742 and sends both HIP / NVCC compile commands 3742 and HIP source code 3730 to CUDA compiler 3750. Fig.37B As described in more detail, the HIP / NVCC compile command 3742 configures the CUDA compiler 3750 to compile the HIP source code 3730 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3742, the CUDA compiler 3750 generates a host executable code 3770 (1) and a CUDA device executable code 3784 (indicated by bubble comment B5). In at least one embodiment and as indicated by bubble comment B6, the host executable code 3770 (1) and the CUDA device executable code 3784 can be executed on a CPU 3790 and a CUDA-enabled GPU 3794, respectively. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0359] The CUDA / HCC flow that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as shown in bubble comment C1, the CUDA to HIP conversion tool 3720 receives the CUDA source code 3710. In at least one embodiment and as shown in bubble comment C2, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 to the HIP source code 3730. In at least one embodiment and as shown in bubble comment C3, the HIP compiler driver 3740 receives the HIP source code 3730 and determines that the target device 3746 is not CUDA-enabled.

[0360] In at least one embodiment, the HIP compiler driver 3740 generates a HIP / HCC compile command 3744 and sends both the HIP / HCC compile command 3764 and the HIP source code 3730 to the HCC 3760 (indicated by bubble comment C4). Fig.37C As described in more detail, HIP / HCC compile command 3764 configures HCC 3760 to compile HIP source code 3730 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3744, HCC 3760 generates host executable code 3770(2) and HCC device executable code 3782 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3770(2) and HCC device executable code 3782 can be executed on CPU 3790 and GPU 3792, respectively.

[0361] In at least one embodiment, after converting the CUDA source code 3710 to the HIP source code 3730, the HIP compiler driver 3740 can then be used to generate executable code for the CUDA-enabled GPU 3794 or GPU 3792 without re-implementing the CUDA to HIP conversion tool 3720. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 to the HIP source code 3730, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3740 then configures the HCC 3760 to generate a host executable code 3770 (2) and an HCC device executable code 3782 based on the HIP source code 3730. In at least one embodiment, the HIP compiler driver 3740 then configures the CUDA compiler 3750 to generate a host executable code 3770 (1) and a CUDA device executable code 3784 based on the stored HIP source code 3730.

[0362] Fig.37B 3790 and a CUDA-enabled GPU 3794 are configured to compile and execute Fig.37A In at least one embodiment, the system 3704 includes, but is not limited to, the CUDA source code 3710, a CUDA to HIP conversion tool 3720, a HIP source code 3730, a HIP compiler driver 3740, a CUDA compiler 3750, a host executable code 3770(1), a CUDA device executable code 3784, a CPU 3790, and a CUDA-enabled GPU 3794.

[0363] In at least one embodiment and as previously incorporated herein Fig.37A As described, CUDA source code 3710 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, CUDA source code 3710 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0364] In at least one embodiment, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 into HIP source code 3730. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts each kernel call in the CUDA source code 3710 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3710 into any number of other functionally similar HIP calls.

[0365] In at least one embodiment, the HIP compiler driver 3740 determines that the target device 3746 is CUDA-enabled and generates HIP / NVCC compile commands 3742. In at least one embodiment, the HIP compiler driver 3740 then configures the CUDA compiler 3750 via the HIP / NVCC compile commands 3742 to compile the HIP source code 3730. In at least one embodiment, as part of configuring the CUDA compiler 3750, the HIP compiler driver 3740 provides access to a HIP to CUDA translation header 3752. In at least one embodiment, the HIP to CUDA translation header 3752 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3750 uses the HIP to CUDA translation header 3752 in conjunction with a CUDA runtime library 3754 corresponding to the CUDA runtime API 3702 to generate host executable code 3770(1) and CUDA device executable code 3784. In at least one embodiment, the host executable code 3770(1) and the CUDA device executable code 3784 can then be executed on the CPU 3790 and the CUDA-enabled GPU 3794, respectively. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0366] Fig.37C A system 3706 is shown that is configured to compile and execute using a CPU 3790 and a non-CUDA enabled GPU 3792 according to at least one embodiment. Fig.37A CUDA source code 3710. In at least one embodiment, system 3706 includes, but is not limited to, CUDA source code 3710, CUDA to HIP conversion tool 3720, HIP source code 3730, HIP compiler driver 3740, HCC 3760, host executable code 3770(2), HCC device executable code 3782, CPU 3790, and GPU 3792.

[0367] In at least one embodiment, and as previously described herein in conjunction with Fig.37AAs described, CUDA source code 3710 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, CUDA source code 3710 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0368] In at least one embodiment, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 into HIP source code 3730. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts each kernel call in the CUDA source code 3710 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3710 into any number of other functionally similar HIP calls.

[0369] In at least one embodiment, the HIP compiler driver 3740 then determines that the target device 3746 is not CUDA-enabled and generates HIP / HCC compile commands 3744. In at least one embodiment, the HIP compiler driver 3740 then configures the HCC 3760 to execute the HIP / HCC compile commands 3744 to compile the HIP source code 3730. In at least one embodiment, the HIP / HCC compile commands 3744 configure the HCC 3760 to generate host executable code 3770 (2) and HCC device executable code 3782 using, but not limited to, a HIP / HCC runtime library 3758 and an HCC header 3756. In at least one embodiment, the HIP / HCC runtime library 3758 corresponds to the HIP runtime API 3732. In at least one embodiment, the HCC header 3756 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, the host executable code 3770 ( 2 ) and the HCC device executable code 3782 may be executed on the CPU 3790 and the GPU 3792 , respectively.

[0370] Fig.38 According to at least one embodiment, Fig.37C37. An exemplary kernel converted by the CUDA to HIP conversion tool 3720 of FIG. 37. In at least one embodiment, the CUDA source code 3710 divides the overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in cooperation. In at least one embodiment, threads within a thread block can collaborate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0371] In at least one embodiment, CUDA source code 3710 organizes thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0372] In at least one embodiment, a kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3810 is used to specify the size of the grid on which the kernel is executed ...

Claims

1. A processor, comprising: One or more circuits for executing an application programming interface (API) so that one or more non-uniform memory access NUMA nodes or one or more physical addresses assigned to one or more graphics processing units (GPUs) are accessed based at least in part on one or more indications within the API.

2. The processor of claim 1, wherein the API is used to cause storage of a NUMA node to be set as a preferred storage location for data to be stored at one or more virtual memory addresses. 3 . The processor according to claim 1 , wherein the API is used to cause a memory of a NUMA node including a central processing unit (CPU) to be set as a preferred storage location.

4. The processor of claim 1 , wherein the API is used to cause one of a plurality of NUMA nodes to be used as a preferred storage location for data to be stored using one or more virtual memory addresses accessible by a central processing unit (CPU) and the one or more GPUs.

5. The processor of claim 1, wherein the API is to cause memory of a NUMA node to be accessed based at least in part on information included in the one or more indications indicating the NUMA node.

6. The processor of claim 1, wherein the one or more indications within the API include information provided as input indicating a set of managed memory and NUMA nodes.

7. The processor of claim 1 , wherein the one or more NUMA nodes include one or more central processing units (CPUs), and the one or more indications within the API include information provided as input indicating a set of virtual memory addresses accessible to the one or more CPUs and the one or more GPUs.

8. A system comprising: One or more processors, the one or more processors being configured to execute an application programming interface (API) so that one or more non-uniform memory access (NUMA) nodes or one or more physical addresses assigned to one or more graphics processing units (GPUs) are accessed based at least in part on one or more indications within the API. 9 . The system of claim 8 , wherein the one or more indications include information indicating a set of virtual memory addresses accessible by one or more central processing units (CPUs) and the one or more GPUs.

10. The system of claim 8, wherein the API is used to cause a memory of a NUMA node including a central processing unit (CPU) to be used as a preferred physical storage location for data to be stored using one or more virtual memory addresses accessible by the CPU and the one or more GPUs.

11. The system of claim 8, wherein the one or more indications include information indicating a NUMA node to be used as a storage location for data.

12. The system of claim 8, wherein the one or more indications include information indicating a NUMA node to be used as a physical storage location for data and information indicating a set of virtual memory addresses.

13. The system of claim 8, wherein the API is to cause an indication of preferred physical storage locations for a set of virtual memory addresses to be stored.

14. A method comprising: An application programming interface (API) is executed such that one or more non-uniform memory access (NUMA) nodes or one or more physical addresses assigned to one or more graphics processing units (GPUs) are accessed based at least in part on one or more indications within the API.

15. The method of claim 14, wherein the API is used to cause a memory of a NUMA node to be set as a preferred storage location based at least in part on the one or more indications. 16 . The method of claim 14 , wherein the one or more indications include information indicating a set of virtual memories accessible by a central processing unit (CPU) and the one or more GPUs.

17. The method of claim 14, wherein the one or more indications include information indicating a NUMA node to be used as a preferred storage location.

18. The method of claim 14, wherein the API is used to cause one NUMA node of a plurality of NUMA nodes to be used as a preferred storage location for data to be stored using one or more virtual memory addresses accessible by a central processing unit (CPU) of the one NUMA node and the one or more GPUs.

19. The method of claim 14, wherein the API is used to cause one or more indications to be stored, the one or more indications comprising information indicating the NUMA node to be used as a preferred storage location for information stored using one or more virtual memory addresses accessible by the one or more GPUs and a central processing unit (CPU) of the NUMA node.

20. A non-transitory computer readable medium having stored thereon a set of instructions, which when executed by one or more processors, cause the one or more processors to perform at least the method of claim 14.

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