Method for processing write command by DRAM-free storage device

Abstract

The invention provides a method for processing a write command by a DRAM (Dynamic Random Access Memory)-free storage device, which comprises the following steps of: responding to a received write command, analyzing the write command to obtain an LBA (Local Block Address), distributing a physical address for the LBA address, selecting a first storage unit from a cache, and recording the LBA address and the physical address in the first storage unit; updating a first table and a second table stored in a memory based on the LBA address and the first storage unit; wherein the first table comprises a plurality of entries, each entry in the first table is used for recording a physical address of a storage block in the NVM chip, and the storage block is located in the NVM chip and used for storing a specified number of L2P table entries.

Description

Technical Field

[0001] The present application relates to storage technology, and in particular, to a storage medium management method for a DRAM-free storage device and a storage device thereof. Background Art

[0002] Figure 1A The block diagram of the storage device is shown. The storage device 102 is coupled to the host to provide storage capacity for the host. The host and the storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] Figure 1B A detailed block diagram showing the control components of a storage device.

[0008] The host accesses the storage device with IO commands that comply with the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, and erase commands) that comply with the interface protocol of the NVM chip based on the media interface commands. The control component also tracks that all media interface commands generated from an IO command have been executed and indicates the processing results of the IO commands to the host. Figure 1BThe control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a medium interface controller, and a storage medium management unit. The host interface obtains the IO command provided by the host, and generates a storage command to provide to the storage command processing unit. The storage command, for example, accesses storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. The physical page records one or more data frames. For example, the size of the physical page is 17664 bytes, and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0009] The storage medium management unit maintains the conversion of the logical address to the physical address for each storage command. For example, the storage medium management unit includes an FTL table (Flash Translation Layer). The storage medium management unit uses FTL to maintain the mapping information from the logical address to the physical address. The logical address constitutes the storage space of the storage device perceived by the upper-layer software such as the operating system. The physical address is the address of the physical storage unit used to access the solid-state storage device. In the prior art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address. Optionally, the host accessing the storage device provides an FTL table. The FTL table is also called an L2P table. Usually, the data items of the FTL table record the address mapping relationship in the storage device in units of a specified size (for example, 512 bytes, 2KB, 4KB, etc.). For a read command, the storage medium management unit outputs the physical address corresponding to the logical address accessed by the storage command. For a write command, the storage medium management unit allocates an available physical address to it and records the mapping relationship between the logical address accessed and the allocated physical address. The storage media management unit also maintains functions required to manage the NVM chip, such as garbage collection and wear leveling.

[0010] The storage command processing unit operates the media interface controller to issue a storage media access command to the NVM chip according to the physical address provided by the storage media management unit. For the purpose of clarity, the command sent by the host to the storage device is called an IO command, the command sent by the host command processing unit to the storage command processing unit is called a storage command, the command sent by the storage command processing unit to the media interface controller is called a media interface command, and the command sent by the media interface controller to the NVM chip is called a storage media access command. The storage media access command follows the interface protocol of the NVM chip. Summary of the invention

[0011] As the capacity of storage devices increases, in order to record more storage units, the size of the L2P table increases accordingly, and a larger memory (DRAM) is required to accommodate the L2P table. In order to address updated storage units, the size of each entry in the L2P table also needs to increase. For example, a 32-bit L2P table entry can address 2^32 (4G) data units. If the size of each data unit is 4KB, 2^32 data units correspond to 16TB of storage capacity, and accordingly the size of the L2P table itself is 16GB (4Bx4G=16GB, one entry is 4 bytes, 4G entries total 16GB), which requires at least 16GB of memory space.

[0012] In order to reduce cost / power consumption, some storage devices place a small amount of or no memory such as DRAM on the storage device to store the L2P table. In addition, in addition to storing the L2P table, the memory also stores some other data, such as pre-read data, firmware or other data, so that the storage resources are insufficient and cannot accommodate the complete L2P table, that is, the storage medium management unit directly manages part of the L2P table content, and the complete L2P table is stored in the NVM chip. For example, the control component receives a read command, and the L2P table entry corresponding to the logical address LBA indicated by the read command is not currently stored in the memory. The storage medium management unit cannot find the physical address of the NVM chip corresponding to the logical address by directly querying the L2P table stored in the memory (the mapping relationship between the logical address and the physical address is not stored in the memory). Accessing the NVM chip requires knowing the physical address (the storage medium access command sent by the media interface controller to the NVM chip needs to indicate the physical address. In the case where the memory of the storage device does not accommodate the entire L2P table, the present application still hopes that the storage device can effectively perform read / write operations and reduce the negative impact on the performance of the storage device.

[0013] According to a first aspect of the present application, a read command processing method for a first storage device according to the first aspect of the present application is provided, in response to receiving a read command, determining a first storage unit index in a cache based on an LBA address indicated by the read command, determining a first storage unit based on the first storage unit index, and obtaining a physical address corresponding to the LBA address based on the first storage unit; in response to failure to determine the first storage unit index based on the LBA address indicated by the read command, calculating a first entry index in a first table based on the LBA address indicated by the read command, determining a first entry based on the first entry index, and obtaining a physical address corresponding to the LBA address based on the first entry; wherein the first table includes a plurality of first-category entries, each of the first-category entries being used to record a physical address of a storage block in an NVM chip, the storage block being located in the NVM chip and being used to store a specified number of L2P table entries; accessing the NVM chip to read data based on the physical address.

[0014] According to the read command processing method of the first storage device according to the first aspect of the present application, there is provided a read command processing method of the second storage device according to the first aspect of the present application, wherein a hash value is calculated according to the LBA address, and the first storage unit index is determined according to the hash value; and when the first storage unit index is not determined according to the hash value, the first entry index is calculated according to the LBA address.

[0015] According to the read command processing method of the second storage device of the first aspect of the present application, there is provided a read command processing method of the third storage device according to the first aspect of the present application, determining the first storage unit index according to the hash value, comprising: indexing a second entry from the second table according to the hash value, and obtaining the first storage unit index from the entry in response to the second entry recording the storage unit index, wherein the second table includes multiple second-category entries, and each second-category entry is used to record a corresponding storage unit index.

[0016] According to one of the read command processing methods of the first to third storage devices of the first aspect of the present application, a read command processing method of the fourth storage device according to the first aspect of the present application is provided, wherein, in response to determining the first storage unit index, the physical address corresponding to the LBA is obtained from the corresponding first storage unit in the cache according to the first storage unit index.

[0017] According to the read command processing method of the fourth storage device of the first aspect of the present application, there is provided a read command processing method of the fifth storage device according to the first aspect of the present application, obtaining the physical address corresponding to the LBA from the corresponding first storage unit in the cache according to the first storage unit index, including: obtaining the information recorded by the first storage unit from the cache based on the first storage unit index; obtaining the physical address corresponding to the LBA address based on the information recorded by the first storage unit.

[0018] According to one of the read command processing methods of the first to fifth storage devices of the first aspect of the present application, a read command processing method of the sixth storage device according to the first aspect of the present application is provided, and the physical address corresponding to the LBA is obtained according to the first storage unit index, including: determining whether the LBA address recorded in the first storage unit matches the LBA indicated by the read command; if they match, using the physical address recorded in the first storage unit as the physical address corresponding to the LBA address indicated by the read command.

[0019] According to the read command processing method of the sixth storage device of the first aspect of the present application, there is provided a read command processing method of the seventh storage device according to the first aspect of the present application, wherein, if the LBA address recorded by the first storage unit does not match the LBA indicated by the read command, the LBA range is determined according to the LBA address recorded by the first storage unit and the length recorded by the first storage unit; wherein the length represents the number of consecutive LBA addresses; it is determined whether the LBA indicated by the read command is within the LBA range; if the LBA indicated by the read command is within the LBA range, the physical address recorded by the first storage unit is used as the physical address corresponding to the LBA address indicated by the read command.

[0020] According to the read command processing method of the seventh storage device of the first aspect of the present application, there is provided a read command processing method of the eighth storage device according to the first aspect of the present application, wherein, when the LBA indicated by the read command is not within the LBA range, at least one storage unit is determined in sequence; wherein each recorded LBA address of the at least one storage unit and the hash value corresponding to the LBA address recorded by the first storage unit are indexed into the same entry in the second table; it is determined in sequence whether there is a storage unit in the at least one storage unit whose recorded LBA matches the LBA indicated by the read command or the LBA indicated by the read command is within the corresponding LBA range; if so, the physical address recorded by the storage unit is used as the physical address of the LBA indicated by the read command.

[0021] According to the read command processing method of the eighth storage device of the first aspect of the present application, there is provided a read command processing method of the ninth storage device according to the first aspect of the present application, wherein, if there is no storage unit whose recorded LBA matches the LBA indicated by the read command or the LBA indicated by the read command is within the corresponding LBA range, then the first entry index is calculated according to the LBA address indicated by the read command.

[0022] According to the read command processing method of the eighth or ninth storage device of the first aspect of the present application, there is provided a read command processing method of the tenth storage device according to the first aspect of the present application, wherein the physical address corresponding to the LBA address is obtained according to the second storage unit index recorded in the first designated field in the first storage unit, and the first designated field records the index of the second storage unit, wherein the hash value corresponding to the LBA address recorded by the second storage unit and the first storage unit is indexed into the same entry in the second table.

[0023] According to one of the read command processing methods of the first to tenth storage devices of the first aspect of the present application, there is provided an eleventh read command processing method of the storage device according to the first aspect of the present application, wherein a first entry is indexed from a first table according to the first entry index, a physical address of a storage block recorded by the first entry in an NVM chip is obtained, and the storage block is read from the NVM chip according to the physical address; an L2P table entry corresponding to the LBA address indicated by the read command is determined among a specified number of L2P table entries recorded by the storage block, and the physical address recorded by the L2P table entry is used as the physical address corresponding to the LBA indicated by the read command.

[0024] According to one of the read command processing methods of the first to eleventh storage devices of the first aspect of the present application, a read command processing method of the twelfth storage device according to the first aspect of the present application is provided, which also includes: in response to the first storage unit index in the cache not being determined according to the LBA address indicated by the read command, determining the storage block information corresponding to the LBA; judging whether the storage block is stored in the host memory HMB based on the storage block information; if it is stored in the HMB, reading the storage block from the HMB, determining an L2P table entry corresponding to the LBA address indicated by the read command among the specified number of L2P table entries recorded by the storage block, and using the physical address recorded by the L2P table entry as the physical address corresponding to the LBA indicated by the read command.

[0025] According to the read command processing method of the twelfth storage device of the first aspect of the present application, there is provided a read command processing method of the thirteenth storage device according to the first aspect of the present application, wherein, if the storage block is not stored in the HMB, the first entry index is calculated according to the LBA; the first entry is indexed from the first table according to the first entry index, and the physical address of the storage block recorded by the first entry in the NVM chip is obtained, and the storage block is read from the NVM chip according to the physical address; an L2P entry corresponding to the LBA address among the specified number of L2P entries recorded by the storage block is determined, and the physical address recorded by the L2P entry is used as the physical address corresponding to the LBA.

[0026] According to the second aspect of the present application, a write command processing method for a first storage device according to the second aspect of the present application is provided. In response to receiving a write command, the write command is parsed to obtain an LBA address, a physical address is assigned to the LBA address, and a first storage unit is selected from a cache, and the LBA address and the physical address are recorded in the first storage unit; a first table and a second table stored in a memory are updated based on the LBA address and the first storage unit; wherein the first table includes multiple entries, each entry in the first table is used to record the physical address of a storage block in an NVM chip, and the storage block is located in the NVM chip and is used to store a specified number of L2P table entries; the second table includes multiple entries, each entry in the second table is used to record the address of a storage unit in the cache corresponding to the LBA address.

[0027] According to the second aspect of the present application, a write command processing method for a first storage device is provided, and a write command processing method for a second storage device is provided, wherein a first storage unit is selected from a cache, including: determining at least one free storage unit in the cache, and selecting the first storage unit from the at least one free storage unit, wherein the cache includes multiple storage units.

[0028] According to the write command processing method of the first or second storage device of the second aspect of the present application, a write command processing method of the third storage device according to the second aspect of the present application is provided, wherein, in response to parsing the LBA address and length from the write command, a physical address is assigned to the LBA address, and the LBA address, the assigned physical address corresponding to the LBA address, and the length are recorded in the first storage unit; wherein the length represents the number of consecutive LBA addresses.

[0029] According to one of the write command processing methods for the first to third storage devices of the second aspect of the present application, a write command processing method for the fourth storage device of the second aspect of the present application is provided, wherein each entry in the first table is indexed by the storage block index recorded therein; and each entry in the second table is indexed by the hash value corresponding to the LBA address.

[0030] According to the write command processing method of the fourth storage device of the second aspect of the present application, there is provided a write command processing method of the fifth storage device according to the second aspect of the present application, wherein the corresponding storage block index is calculated based on the LBA address, and the first entry is indexed from the first table based on the storage block index; the physical address of the storage block recorded in the first entry in the NVM chip is updated to the index of the selected first storage unit in the cache.

[0031] According to one of the write command processing methods of the first to fifth storage devices of the second aspect of the present application, a write command processing method of the sixth storage device according to the second aspect of the present application is provided, and the number of entries in the second table is less than the number of LBA address values.

[0032] According to one of the write command processing methods of the first to sixth storage devices of the second aspect of the present application, a write command processing method of the seventh storage device according to the second aspect of the present application is provided, which also includes: reading the data of the storage block corresponding to the first entry from the NVM chip to the memory.

[0033] According to one of the write command processing methods of the fifth to seventh storage devices of the second aspect of the present application, there is provided a write command processing method of the eighth storage device according to the second aspect of the present application, wherein the LBA address is hashed to obtain a hash value, and the second entry is indexed from the second table based on the hash value; the second table is updated based on the status of the second entry, wherein the status of the second entry includes whether the second entry is empty or not empty.

[0034] According to the write command processing method of the eighth storage device of the second aspect of the present application, there is provided a write command processing method of the ninth storage device of the second aspect of the present application, wherein, in response to the second entry being empty, the index of the first storage unit is recorded to the second entry; in response to the second entry being non-empty, the second storage unit index recorded in the second entry is obtained, the second storage unit in the cache is determined based on the second storage unit index, and a first specified field is added to the data structure recorded by the second storage unit, the first specified field records the index of the first storage unit, and is used to represent that the hash value corresponding to the LBA address recorded by the second storage unit and the first storage unit indexes the same entry in the second table.

[0035] According to the write command processing method of the ninth storage device of the second aspect of the present application, there is provided a write command processing method of the tenth storage device of the second aspect of the present application, wherein, in response to receiving a first write command, the first write command is parsed to obtain a first LBA address, a physical address is assigned to the first LBA address, a third storage unit is selected from a cache, and the first LBA address and the physical address are recorded in the third storage unit; in response to receiving a second write command, the second write command is parsed to obtain a second LBA address, a physical address is assigned to the second LBA address, and a fourth storage unit is selected from the cache, and the second LBA address and the physical address are recorded in the fourth storage unit; in response to the storage block indexes calculated based on the first LBA address and the second LBA address being the same, a second designated field is added to the fourth storage unit, and the second designated field records the index of the third storage unit, which is used to characterize that the LBA addresses recorded by the fourth storage unit and the third storage unit correspond to the same storage block.

[0036] According to the write command processing method of the sixth to tenth storage devices of the second aspect of the present application, a write command processing method of the eleventh storage device according to the second aspect of the present application is provided, which also includes: in response to indexing a first entry from the first table, obtaining the physical address of the storage block recorded in the first entry in the NVM chip, and recording the physical address of the storage block recorded in the first entry in the NVM chip into the first storage unit.

[0037] According to the write command processing method of the eleventh storage device of the second aspect of the present application, there is provided a write command processing method of the twelfth storage device according to the second aspect of the present application. If the first entry records the index of the cached storage unit, the index of the cached storage unit recorded in the first entry is recorded in the second designated field of the first storage unit.

[0038] According to one of the write command processing methods for the first to twelfth storage devices of the second aspect of the present application, a write command processing method for the thirteenth storage device according to the second aspect of the present application is provided, wherein the number of entries in the first table is the same as the number of storage units in the cache, and the entries in the first table correspond one-to-one to the storage units in the cache.

[0039] According to one of the write command processing methods of the first to thirteenth storage devices of the second aspect of the present application, a write command processing method of the fourteenth storage device according to the second aspect of the present application is provided, the number of entries in the second table is the same as the number of storage blocks in the NVM chip, and the entries in the first table correspond one-to-one to the storage blocks in the NVM chip.

[0040] According to a third aspect of the present application, a flash processing method for a first storage device according to the third aspect of the present application is provided, in response to triggering a flash operation, selecting a first entry from a first table, wherein the first table includes a plurality of entries, each entry corresponding one-to-one to a storage block, and the storage block is located in an NVM chip and is used to store a specified number of L2P table entries; reading an L2P table entry of a first storage block corresponding to the first entry from the NVM chip, and determining at least one first storage unit from a cache, wherein each first storage unit records an LBA address recorded by the L2P table entry in the first storage block and a physical address of the NVM chip corresponding thereto; updating the L2P table entry corresponding to the first storage block according to the data recorded by the at least one first storage unit, and writing the updated L2P table entry to the NVM chip.

[0041] According to the flash processing method of the first storage device according to the third aspect of the present application, a flash processing method of the second storage device according to the third aspect of the present application is provided, which also includes: in response to writing the updated L2P table entry to the NVM chip, deleting the data recorded in the at least one first storage unit in the cache.

[0042] According to the flash processing method of the second storage device of the third aspect of the present application, a flash processing method of the third storage device according to the third aspect of the present application is provided, wherein a second storage block in the NVM chip is allocated to the updated 2P table entry, and the updated 2P table entry is written to the second storage block of the NVM chip; wherein the second storage block is different from the first storage block.

[0043] According to one of the flash processing methods of the first to third storage devices of the third aspect of the present application, a fourth storage device according to the third aspect of the present application is provided.

[0044] In response to the free capacity in the cache being less than a first threshold or the used capacity in the cache being greater than a second threshold, a flush operation is triggered; or in response to a preset condition being met, a flush operation is triggered.

[0045] According to one of the flush processing methods of the first to fourth storage devices of the third aspect of the present application, a flush processing method of the fifth storage device according to the third aspect of the present application is provided, and a first entry is selected from a first table, including: selecting an entry that records the storage unit index from the first table, and using the selected entry as the first entry; or selecting from the first table an entry corresponding to a specified number of L2P table entries corresponding to storage blocks that are recorded in the cache and corresponding to the largest number of storage blocks as the first entry.

[0046] According to the flush processing method of the fifth storage device of the third aspect of the present application, there is provided a flush processing method of the sixth storage device according to the third aspect of the present application, wherein the storage unit index recorded in the entry of the first table is the index of the cache unit allocated when recording the LBA address and physical address of the write command in the storage unit allocated from the cache for processing the write command, wherein the LBA address range of a specified number of L2P table entries stored in the storage block corresponding to the entry of the first table includes the LBA address of the write command.

[0047] According to one of the flash processing methods for the third to sixth storage devices of the third aspect of the present application, a flash processing method for the seventh storage device according to the third aspect of the present application is provided, which also includes: in response to writing the updated L2P table entry to the NVM chip, updating the first table and the second table; wherein the second table includes multiple entries, each entry in the second table is used to record the address of a storage unit in the cache corresponding to the LBA address.

[0048] According to the flash processing method of the seventh storage device of the third aspect of the present application, there is provided a flash processing method of the eighth storage device according to the third aspect of the present application, updating the first table and the second table, including: updating the storage unit index recorded in the first entry in the first table to the physical address of the second storage block in the NVM chip; deleting the address of the at least one first storage unit recorded from the entry of the second table.

[0049] According to the flash processing method of the seventh or eighth storage device of the third aspect of the present application, a flash processing method of the ninth storage device according to the third aspect of the present application is provided, wherein:

[0050] Determine a second storage unit in the cache that has a hash value corresponding to the LBA address recorded in each first storage unit and indexes the same entry in the second table;

[0051] Modifying the storage unit index recorded in the specified field in the data recorded in the second storage unit based on the storage unit index recorded in the specified field in the data recorded in the first storage unit;

[0052] In response to the completion of modifying the storage unit index recorded in the designated field in the data recorded in the second storage unit, the data recorded in the at least one storage unit is deleted.

[0053] According to the flash processing method of the ninth storage device of the third aspect of the present application, there is provided a flash processing method of the tenth storage device according to the third aspect of the present application, wherein, in response to the index of the third storage unit recorded in the specified field in the data recorded by the first storage unit, the index of the second storage unit recorded in the specified field in the data recorded by the second storage unit is recorded, and the index of the second storage unit recorded in the specified field in the data recorded by the second storage unit is modified to the index of the third storage unit.

[0054] According to the flash processing method of the seventh or eighth storage device of the third aspect of the present application, there is provided a flash processing method of the eleventh storage device according to the third aspect of the present application, wherein an index is obtained from the second table according to the hash value corresponding to the LBA address recorded by each first storage unit, and at least one second storage unit corresponding to the index obtained from the second table is obtained, and if the number of the at least one second storage unit is one, the index is deleted from the second table; if the number of the at least one second storage unit is greater than one, the index obtained from the second table or one of the at least one second storage units is modified so that the at least one second storage unit no longer includes one of each first storage unit.

[0055] According to one of the flash processing methods of the first to eleventh storage devices according to the third aspect of the present application, a flash processing method of the twelfth storage device according to the third aspect of the present application is provided, wherein, in response to reading the L2P table entry corresponding to the first storage block, the L2P table entry is stored in a designated storage space in the cache.

[0056] According to the flash processing method of the twelfth storage device of the third aspect of the present application, there is provided a flash processing method of the thirteenth storage device according to the third aspect of the present application, wherein the physical address corresponding to the LBA address stored in the designated storage space is updated according to the data recorded by the at least one first storage unit; and the data stored in the updated designated space is written to the second storage block in the NVM chip.

[0057] According to the first to thirteenth storage device flushing processing methods of the third aspect of the present application, a fourteenth storage device flushing processing method according to the third aspect of the present application is provided, which also includes: writing the updated L2P table entry into the host memory cache HMB.

[0058] According to a fourth aspect of the present application, a read and write processing method of a first storage device according to the fourth aspect of the present application is provided. In response to receiving a write command, a physical address is allocated to a first LBA address indicated by the write command and a first storage unit is allocated to the write command from a cache, and the first LBA address and the physical address are recorded in the allocated first storage unit; a first table stored in a memory is updated based on the first LBA address and the first storage unit; wherein the first table includes multiple entries, each entry is used to record the physical address of a storage block in an NVM chip or the index of a storage unit in the cache, and the storage block is located in the NVM chip and is used to store a specified number of L2P entries; and the data to be written indicated by the write command is written into the NVM chip according to the allocation of a physical address to the first LBA address.

[0059] According to the read and write processing method of the first storage device according to the fourth aspect of the present application, a read and write processing method of the second storage device according to the fourth aspect of the present application is provided, at least one storage unit is selected from the cache, and the at least one storage unit is assigned to the write command.

[0060] According to the read and write processing method of the first or second storage device according to the fourth aspect of the present application, a read and write processing method of the third storage device according to the fourth aspect of the present application is provided, wherein, in response to parsing the length from the write command, the number of first storage units allocated to the write command is the same as the number of consecutive LBA addresses indicated by the length.

[0061] According to one of the read command processing methods of the first to third storage devices according to the fourth aspect of the present application, a read command processing method of the fourth storage device according to the fourth aspect of the present application is provided, wherein each entry in the first table is indexed by the storage block index recorded therein.

[0062] According to the read and write processing method of the fourth storage device of the fourth aspect of the present application, there is provided a read and write processing method of the fifth storage device according to the fourth aspect of the present application, wherein the corresponding storage block index is calculated based on the first LBA address, and the first entry is indexed from the first table based on the storage block index; the first entry is updated according to the index of the first storage unit.

[0063] According to one of the read and write processing methods of the first to fifth storage devices of the fourth aspect of the present application, a read and write processing method of the sixth storage device according to the fourth aspect of the present application is provided, wherein, in response to receiving a first write command, a second storage unit is allocated to the first write command, and the second LBA address corresponding to the first write command and its corresponding physical address are recorded in the second storage unit; in response to receiving a second write command, a third storage unit is allocated to the second write command, and the third LBA address corresponding to the second write command and its corresponding physical address are recorded in the third storage unit; in response to the storage block indexes calculated based on the second LBA address and the third LBA address being the same, a specified field is added to the third storage unit, and the index of the second storage unit is recorded in the specified field to indicate that the LBA addresses recorded in the third storage unit and the second storage unit correspond to the same storage block.

[0064] According to the read and write processing method of the sixth storage device of the fourth aspect of the present application, a read and write processing method of the seventh storage device according to the fourth aspect of the present application is provided, wherein, if the first entry records the index of the storage unit, the index of the cached storage unit recorded in the first entry is recorded in the designated field of the first storage unit.

[0065] According to one of the read and write processing methods of the fifth to seventh storage devices of the fourth aspect of the present application, a read and write processing method of the eighth storage device according to the fourth aspect of the present application is provided, which also includes: in response to indexing a first entry from the first table, obtaining the physical address of the storage block recorded in the first entry in the NVM chip, and recording the physical address of the storage block recorded in the first entry in the NVM chip into the first storage unit.

[0066] According to one of the read and write processing methods of the first to eighth storage devices of the fourth aspect of the present application, a read and write processing method of the ninth storage device according to the fourth aspect of the present application is provided, wherein the number of entries in the first table is the same as the number of storage blocks in the NVM chip, and the entries in the first table correspond one-to-one to the storage blocks in the NVM chip.

[0067] According to one of the read and write processing methods of the first to ninth storage devices of the fourth aspect of the present application, a read and write processing method of the tenth storage device according to the fourth aspect of the present application is provided, which also includes: reading the data of the storage block corresponding to the first entry from the NVM chip to the memory.

[0068] According to one of the read and write processing methods of the first to tenth storage devices of the fourth aspect of the present application, there is provided a read and write processing method of the eleventh storage device according to the fourth aspect of the present application, which also includes: in response to receiving a read command, determining a second entry index according to a fourth LBA address indicated by the read command; determining a second entry in the first table according to the second entry index, obtaining a physical address corresponding to the fourth LBA address according to the second entry, and accessing the NVM chip to read data according to the physical address.

[0069] According to the read and write processing method of the eleventh storage device of the fourth aspect of the present application, a read and write processing method of the twelfth storage device according to the fourth aspect of the present application is provided, wherein the storage block index of the L2P table entry corresponding to the LBA address is calculated; and the storage block index is used as the second entry index.

[0070] According to the eleventh or twelfth storage device read and write processing method of the fourth aspect of the present application, a thirteenth storage device read and write processing method according to the fourth aspect of the present application is provided, wherein, in response to the second entry recording the physical address of the storage block in the NVM chip, the storage block is read from the NVM chip according to the physical address, and the position of the L2P entry corresponding to the fourth LBA address in the storage block is determined, and the physical address corresponding to the fourth LBA is obtained from the L2P entry according to the position; or in response to the second entry recording the storage unit index, the physical address corresponding to the fourth LBA is obtained from the cache according to the storage unit index.

[0071] According to the read and write processing method of the thirteenth storage device of the fourth aspect of the present application, there is provided a read and write processing method of the fourteenth storage device of the fourth aspect of the present application, and the physical address corresponding to the LBA is obtained from the cache according to the storage unit index, including: determining the fourth storage unit according to the index of the storage unit recorded in the second entry, and obtaining the LBA address recorded in the fourth storage unit; if the LBA address recorded in the fourth storage unit matches the fourth LBA address, using the physical address recorded in the fourth storage unit as the physical address corresponding to the fourth LBA address.

[0072] According to the read and write processing method of the fourteenth storage device of the fourth aspect of the present application, there is provided a read and write processing method of the fifteenth storage device according to the fourth aspect of the present application, wherein, if the LBA address recorded by the fourth storage unit does not match the fourth LBA address, it is determined that the recorded LBA address and the LBA address recorded by the fourth storage unit correspond to a fifth storage unit of the same storage block; wherein the LBA address recorded by the fifth storage unit matches the fourth LBA address; and the physical address recorded by the fifth storage unit is used as the physical address corresponding to the fourth LBA address.

[0073] According to the read and write processing method of the fifteenth storage device of the fourth aspect of the present application, there is provided a read and write processing method of the sixteenth storage device according to the fourth aspect of the present application, wherein, according to the storage unit index recorded in the designated field of the storage unit, at least one sixth storage unit corresponding to the same storage block as the LBA address recorded by the fourth storage unit is determined in sequence; the LBA addresses recorded by the at least one sixth storage unit are obtained in sequence from the at least one sixth storage unit, and the fifth storage unit is determined according to the LBA address obtained each time.

[0074] According to one of the read and write processing methods of the eleventh to sixteenth storage devices of the fourth aspect of the present application, a read and write processing method of the seventeenth storage device according to the fourth aspect of the present application is provided, which also includes: determining the storage block information corresponding to the fourth LBA, and judging whether the storage block is stored in the host memory HMB based on the storage block information; if it is stored in the HMB, reading the storage block from the HMB, determining the L2P entry corresponding to the fourth LBA address among the specified number of L2P entries recorded in the storage block, and using the physical address recorded by the L2P entry as the physical address corresponding to the fourth LBA address.

[0075] According to one of the read and write processing methods of the seventeenth storage device of the fourth aspect of the present application, there is provided a read and write processing method of the eighteenth storage device of the fourth aspect of the present application, wherein, if the storage block is not stored in the HMB, the second entry index is calculated according to the LBA; the second entry is indexed from the first table according to the second entry index, and the physical address of the storage block recorded by the second entry in the NVM chip is obtained, and the storage block is read from the NVM chip according to the physical address; an L2P entry corresponding to the fourth LBA address among the specified number of L2P entries recorded by the storage block is determined, and the physical address recorded by the L2P entry is used as the physical address corresponding to the fourth LBA address.

[0076] According to one of the read and write processing methods of the eleventh to seventeenth storage devices of the fourth aspect of the present application, a read and write processing method of the eighteenth storage device according to the fourth aspect of the present application is provided, wherein the physical address of the corresponding storage block recorded in the NVM chip by each entry in the first table includes first data and second data, wherein the first data is data of high bits of a specified number of bits in the physical address, and the second data is a portion of the physical address that is different from the first data; updating the first table stored in the memory based on the first LBA address and the first storage unit includes: keeping the second data in the entry to be updated of the first table unchanged, and updating the first data of the entry with the index of the first storage unit in the cache.

[0077] According to one of the read and write processing methods of the seventeenth storage device of the fourth aspect of the present application, a read and write processing method of the nineteenth storage device according to the fourth aspect of the present application is provided, wherein the fifth storage unit records the first data in the physical address of the storage block corresponding to the second LBA address in the NVM chip, and the entry in the first table corresponding to the second LBA address records the second data in the physical address of the storage block corresponding to the second LBA address in the NVM chip; wherein the first data and the second data are partial data of the physical address of the storage block in the NVM chip; respectively obtain the first data recorded in the fifth storage unit and the second data recorded in the entry in the first table corresponding to the second LBA address, and splice the first data and the second data to obtain the physical address of the storage block corresponding to the second LBA address in the NVM chip.

[0078] According to one of the read and write processing methods of the eleventh to nineteenth storage devices of the fourth aspect of the present application, a read and write processing method of the twentieth storage device according to the fourth aspect of the present application is provided, wherein, in response to updating the first entry in the first table, the number of L2P table entries recorded in the cache in the storage block corresponding to the first entry is determined according to the number of updates, and the number is recorded in the first entry.

[0079] According to the fifth aspect of the present application, a read and write processing method of a first storage device according to the fifth aspect of the present application is provided, in response to a received write command indicating a first LBA address and a length, a plurality of consecutive physical addresses are allocated to the first LBA address and a first storage unit in a cache is allocated to the write command, the first LBA address, the starting physical address in the plurality of consecutive physical addresses, and the length are recorded in the first storage unit, wherein the length represents the number of the plurality of consecutive LBA addresses indicated by the write command, and also represents the number of the plurality of consecutive physical addresses; a first table stored in a memory is updated based on the first LBA address and the first storage unit; wherein the first table includes a plurality of entries, each entry in the first table is used to record the physical address of a storage block in an NVM chip, the storage block is located in the NVM chip, and is used to store a specified number of L2P table entries.

[0080] According to the read and write processing method of the first storage device according to the fifth aspect of the present application, a read and write processing method of the second storage device according to the fifth aspect of the present application is provided, and a first storage unit in the cache is allocated to the write command, including: determining at least one free storage unit in the cache, and selecting the first storage unit from the at least one free storage unit, wherein the cache includes multiple storage units.

[0081] According to the read and write processing method of the first or second storage device of the fifth aspect of the present application, a read and write processing method of the third storage device according to the fifth aspect of the present application is provided, wherein the cache includes at least one storage unit, each storage unit includes an address field and a length information field; the first LBA address, the first physical address of the multiple consecutive physical addresses, and the length are recorded to the first storage unit, including: recording the first LBA address and the first physical address to the address field in the first storage unit, and recording the length indicated by the write command to the length information field in the first storage unit.

[0082] According to one of the read and write processing methods of the first to third storage devices of the fifth aspect of the present application, a read and write processing method of the fourth storage device according to the fifth aspect of the present application is provided, which also includes: updating a second table stored in the memory based on the first LBA address and the first storage unit, wherein the second table includes multiple entries, and each entry in the second table is used to record the index of the storage unit allocated from the cache to the corresponding LBA address.

[0083] According to the read and write processing method of the fourth storage device of the fifth aspect of the present application, a read and write processing method of the fifth storage device according to the fifth aspect of the present application is provided, wherein each entry in the first table is indexed by the storage block index recorded therein; and each entry in the second table is indexed by the hash value corresponding to the LBA address.

[0084] According to the read and write processing method of the fifth storage device of the fifth aspect of the present application, there is provided a read and write processing method of the sixth storage device of the fifth aspect of the present application, wherein the corresponding storage block index is calculated based on the first LBA address, and the first entry is indexed from the first table based on the storage block index; the physical address of the storage block recorded in the first entry in the NVM chip is updated to the index of the selected first storage unit in the cache.

[0085] According to the read and write processing method of the sixth storage device of the fifth aspect of the present application, a read and write processing method of the seventh storage device according to the fifth aspect of the present application is provided, which also includes: reading the data of the storage block corresponding to the first entry from the NVM chip to the memory.

[0086] According to one of the read and write processing methods of the fifth to seventh storage devices of the fifth aspect of the present application, a read and write processing method of the eighth storage device according to the fifth aspect of the present application is provided, wherein the first LBA address is hashed to obtain a hash value, and the second entry is indexed from the second table based on the hash value; the second table is updated based on the status of the second entry, wherein the status of the second entry includes whether the second entry is empty or not empty.

[0087] According to the read and write processing method of the eighth storage device of the fifth aspect of the present application, a read and write processing method of the ninth storage device of the fifth aspect of the present application is provided, wherein, in response to the second entry being empty, the index of the first storage unit is recorded to the second entry; in response to the second entry being non-empty, the index of the second storage unit recorded in the second entry is obtained, and the second storage unit in the cache is determined based on the index of the second storage unit, and the index of the first storage unit is recorded in the first designated field of the second storage unit, which is used to represent that the hash value corresponding to the LBA address recorded by the second storage unit and the first storage unit indexes the same entry in the second table.

[0088] According to one of the read and write processing methods of the fourth to ninth storage devices according to the fifth aspect of the present application, a tenth read and write processing method of the storage device according to the fifth aspect of the present application is provided, wherein each entry in the second table corresponds to multiple LBA addresses.

[0089] According to the read and write processing method of the tenth storage device of the fifth aspect of the present application, a read and write processing method of the eleventh storage device according to the fifth aspect of the present application is provided, wherein multiple LBA addresses corresponding to the same entry in the second table are recorded into at least one storage unit in the cache.

[0090] According to the read and write processing method of the eleventh storage device of the fifth aspect of the present application, a read and write processing method of the twelfth storage device according to the fifth aspect of the present application is provided, wherein, in response to multiple LBA addresses corresponding to the same entry in the second table being recorded in multiple storage units in the cache; each of the storage units also includes a first designated field, and the indexes of other storage units of the same entry in the second table corresponding to the LBA address recorded therein are recorded through the first designated field in each storage unit.

[0091] According to the read and write processing method of the twelfth storage device of the fifth aspect of the present application, a read and write processing method of the thirteenth storage device of the fifth aspect of the present application is provided, wherein each storage unit also includes a first designated field, wherein, in response to the LBA addresses indicated by the received multiple write commands corresponding to the same entry in the second table, the first designated field in the storage unit assigned to the write command is updated.

[0092] According to the read and write processing method of the first to thirteenth storage devices of the fifth aspect of the present application, a read and write processing method of the fourteenth storage device according to the fifth aspect of the present application is provided, wherein each storage unit also includes a second designated field, wherein, in response to the LBA addresses indicated by the received multiple write commands corresponding to the same storage block, the second designated field in the storage unit assigned to the write command is updated.

[0093] According to the read and write processing method of the fourteenth storage device of the fifth aspect of the present application, there is provided a read and write processing method of the fifteenth storage device of the fifth aspect of the present application, wherein updating the second designated field in the storage unit allocated for the write command comprises: recording the index of the storage unit allocated for the next write command among the multiple write commands in the second designated field of the storage unit allocated for the previous write command among the multiple write commands.

[0094] According to the read and write processing method of the fourteenth or fifteenth storage device of the fifth aspect of the present application, there is provided a read and write processing method of the sixteenth storage device according to the fifth aspect of the present application, wherein, in response to receiving a first write command, the first write command is parsed to obtain a second LBA address, a physical address is assigned to the second LBA address, and a third storage unit is selected from the cache, and the second LBA address and the physical address are recorded in the third storage unit; in response to receiving a second write command, the second write command is parsed to obtain a third LBA address, a physical address is assigned to the third LBA address, and a fourth storage unit is selected from the cache, and the third LBA address and the physical address are recorded in the fourth storage unit; in response to the storage block index calculated based on the second LBA address and the third LBA address being the same, the index of the third storage unit is recorded in the second designated field of the fourth storage unit, for characterizing that the LBA addresses recorded in the fourth storage unit and the third storage unit correspond to the same storage block.

[0095] According to one of the read and write processing methods of the sixth to sixteenth storage devices of the fifth aspect of the present application, a read and write processing method of the seventeenth storage device according to the fifth aspect of the present application is provided, which also includes: in response to indexing a first entry from the first table, obtaining the physical address of the storage block recorded in the first entry in the NVM chip, and recording the physical address of the storage block recorded in the first entry in the NVM chip into the first storage unit.

[0096] According to one of the read and write processing methods of the sixth to seventeenth storage devices of the fifth aspect of the present application, a read and write processing method of the eighteenth storage device according to the fifth aspect of the present application is provided, wherein the physical address of the corresponding storage block recorded in the NVM chip by each entry in the first table includes first data and second data, wherein the first data is data of high bits of a specified number of bits in the physical address, and the second data is a portion of the physical address that is different from the first data; updating the first table stored in the memory based on the first LBA address and the first storage unit includes: keeping the second data in the entry to be updated of the first table unchanged, and updating the first data of the entry with the index of the first storage unit in the cache.

[0097] According to the read and write processing method of the eighteenth storage device of the fifth aspect of the present application, a read and write processing method of the nineteenth storage device according to the fifth aspect of the present application is provided, which also includes: recording the first data in the physical address into the first storage unit.

[0098] According to one of the read and write processing methods of the first to eighteenth storage devices of the fifth aspect of the present application, a read and write processing method of the nineteenth storage device according to the fifth aspect of the present application is provided, wherein, in response to updating the first entry in the first table, the number of L2P table entries recorded in the cache in the storage block corresponding to the first entry is determined according to the number of updates, and the number is recorded in the first entry.

[0099] According to one of the read and write processing methods of the first to nineteenth storage devices of the fifth aspect of the present application, a read and write processing method of the twentieth storage device according to the fifth aspect of the present application is provided, and also includes: in response to performing a flush operation, selecting a storage block with the most L2P table entries in the recorded cache according to the number recorded by each entry in the first table, and updating the storage block according to the first table and the storage unit in the cache.

[0100] (Use of the number: when updating the UT according to the first table and the cache unit, the UT corresponding to the first table entry with large data is preferentially selected for updating)

[0101] According to one of the read and write processing methods of the seventeenth to twentieth storage devices of the fifth aspect of the present application, a read and write processing method of the twenty-first storage device of the fifth aspect of the present application is provided, wherein, if the first entry records the index of the cached storage unit, the index of the cached storage unit recorded in the first entry is recorded in the second designated field of the first storage unit.

[0102] According to one of the read and write processing methods of the first to twenty-first storage devices of the fifth aspect of the present application, a read and write processing method of the twenty-second storage device according to the fifth aspect of the present application is provided, wherein the number of entries in the first table is the same as the number of storage blocks in the NVM chip, and the entries in the first table correspond one-to-one to the storage blocks in the NVM chip.

[0103] According to one of the read and write processing methods of the first to twenty-second storage devices of the fifth aspect of the present application, a read and write processing method of the twenty-third storage device according to the fifth aspect of the present application is provided, including: in response to receiving a read command, and determining the index of the fifth storage unit in the cache based on the fourth LBA address indicated by the read command, and obtaining the physical address corresponding to the fourth LBA address according to the index of the fifth storage unit; in response to the index of the fifth storage unit not being determined based on the fourth LBA address, calculating the third entry index in the first table according to the fourth LBA address, and obtaining the physical address corresponding to the fourth LBA address according to the third entry index; accessing the NVM chip to read data according to the physical address.

[0104] According to the read and write processing method of the twenty-third storage device of the fifth aspect of the present application, there is provided a read and write processing method of the twenty-fourth storage device of the fifth aspect of the present application, wherein a hash value is calculated according to the fourth LBA address, and the fourth entry is indexed from the second table according to the hash value, and the index of the sixth storage unit is obtained from the fourth entry in response to the fourth entry recording the index of the sixth storage unit; the sixth storage unit is indexed from the cache according to the index of the sixth storage unit, and the starting LBA address, physical address and first length recorded in the sixth storage unit are obtained from the sixth storage unit; it is determined whether the starting LBA address recorded in the sixth storage unit matches the fourth LBA address; if they match, the index of the fifth storage unit is the same as the index of the sixth storage unit.

[0105] According to one of the read and write processing methods of the first to twenty-first storage devices of the fifth aspect of the present application, a read and write processing method of the twenty-fifth storage device according to the fifth aspect of the present application is provided, wherein, if there is no match, the first LBA range is determined according to the starting LBA address and the first length recorded in the sixth storage unit; it is determined whether the fourth LBA address is within the first LBA range; if the fourth LBA address is within the first LBA range, the index of the fifth storage unit is the same as the index of the sixth storage unit.

[0106] According to the read and write processing method of the twenty-fifth storage device of the fifth aspect of the present application, there is provided a read and write processing method of the twenty-sixth storage device of the fifth aspect of the present application, wherein, when the fourth LBA address is not within the first LBA range, at least one storage unit in the cache is determined in turn; wherein each LBA address recorded in the at least one storage unit and the hash value corresponding to the LBA address recorded in the sixth storage unit are indexed into the same entry in the second table; and it is determined in turn whether there is a storage unit in the at least one storage unit whose recorded starting LBA matches the fourth LBA address or the fourth LBA address is within the first LBA range corresponding thereto; if so, the index of the storage unit is used as the index of the fifth storage unit.

[0107] According to the read and write processing method of the twenty-sixth storage device of the fifth aspect of the present application, there is provided a read and write processing method of the twenty-seventh storage device of the fifth aspect of the present application, wherein, if there is no storage unit whose recorded starting LBA matches the fourth LBA address or the fourth LBA address is within the corresponding first LBA range when traversing the at least one storage unit, the third entry index is calculated according to the fourth LBA address.

[0108] According to one of the read and write processing methods of the twenty-fifth to twenty-eighth storage devices of the fifth aspect of the present application, a read and write processing method of the twenty-ninth storage device according to the fifth aspect of the present application is provided, wherein, in response to the starting LBA address recorded by the fifth storage unit in the cache matching the fourth LBA address, the recorded physical address is obtained from the fifth storage unit, and the physical address is the physical address corresponding to the fourth LBA address.

[0109] According to one of the read and write processing methods of the twenty-fifth to twenty-eighth storage devices of the fifth aspect of the present application, a read and write processing method of the thirtieth storage device according to the fifth aspect of the present application is provided, wherein, in response to the LBA address range recorded by the fifth storage unit in the cache covering the fourth LBA address; the difference between the LBA matching the fourth LBA address and the starting LBA address recorded by the fifth storage unit is determined, and the physical address corresponding to the fourth LBA address is obtained based on the difference and the physical address corresponding to the starting LBA address.

[0110] According to one of the read and write processing methods of the twenty-fifth to thirtieth storage devices of the fifth aspect of the present application, a read and write processing method of the thirty-first storage device of the fifth aspect of the present application is provided, which also includes: obtaining the physical address of the storage block corresponding to the fourth LBA address in the NVM chip; reading the storage block corresponding to the four LBA addresses from the NVM chip to the memory according to the physical address.

[0111] According to the read and write processing method of the thirty-first storage device of the fifth aspect of the present application, there is provided a read and write processing method of the thirty-second storage device of the fifth aspect of the present application, wherein, in response to determining the index of the fifth storage unit in the cache based on the fourth LBA address indicated by the read command, the fifth storage unit records the first data in the physical address of the storage block corresponding to the fourth LBA address in the NVM chip, and the entry in the first table corresponding to the fourth LBA address records the second data in the physical address of the storage block corresponding to the fourth LBA address in the NVM chip; wherein the first data and the second data are partial data of the physical address of the storage block in the NVM chip; respectively obtain the first data recorded in the fifth storage unit and the second data recorded in the entry in the first table corresponding to the fourth LBA address, and splice the first data and the second data to obtain the physical address of the storage block corresponding to the fourth LBA address in the NVM chip.

[0112] According to the read and write processing method of the thirty-second storage device of the fifth aspect of the present application, a read and write processing method of the thirty-third storage device according to the fifth aspect of the present application is provided, wherein, in response to the storage unit including a first specified field, the index of the seventh storage unit recorded by the first specified field in the fifth storage unit is obtained, and at least one storage unit is determined based on the index of the seventh storage unit; in response to the storage unit not including the first specified field, at least one storage unit having the same hash value as that corresponding to the LBA address recorded by the fifth storage unit is calculated according to the LBA address recorded by each storage unit, or the third entry index is calculated according to the fourth LBA address.

[0113] According to one of the read and write processing methods of the twenty-fifth to thirty-third storage devices of the fifth aspect of the present application, a read and write processing method of the thirty-fourth storage device of the fifth aspect of the present application is provided, wherein a third entry is indexed from the first table according to the third entry index, the physical address of the storage block recorded by the third entry in the NVM chip is obtained, and the storage block is read from the NVM chip according to the physical address; an L2P table entry corresponding to the fourth LBA address is determined among the specified number of L2P table entries recorded by the storage block, and the physical address recorded by the L2P table entry is used as the physical address corresponding to the fourth LBA address.

[0114] According to one of the read and write processing methods of the twenty-fourth to thirty-fourth storage devices of the fifth aspect of the present application, there is provided a read and write processing method of the thirty-fifth storage device according to the fifth aspect of the present application, which also includes: in response to the fifth storage unit index in the cache not being determined according to the fourth LBA address, determining the storage block information corresponding to the fourth LBA address; judging whether the storage block is stored in the host memory HMB based on the storage block information; if it is stored in the HMB, reading the storage block from the HMB, determining an L2P table entry corresponding to the fourth LBA address among the specified number of L2P table entries recorded by the storage block, and using the physical address recorded by the L2P table entry as the physical address corresponding to the fourth LBA address.

[0115] According to the read and write processing method of the thirty-fifth storage device of the fifth aspect of the present application, there is provided a read and write processing method of the thirty-sixth storage device of the fifth aspect of the present application, wherein, if the storage block is not stored in the HMB, the third entry index is calculated according to the fourth LBA address; the third entry is indexed from the first table according to the third entry index, and the physical address of the storage block recorded by the third entry in the NVM chip is obtained, and the storage block is read from the NVM chip according to the physical address; an L2P table entry corresponding to the fourth LBA address among the specified number of L2P table entries recorded by the storage block is determined, and the physical address recorded by the L2P table entry is used as the physical address corresponding to the fourth LBA address.

[0116] According to a sixth aspect of the present application, a control component according to the sixth aspect of the present application is provided, including: the control component is used to implement one of the methods described in the first aspect to the fifth aspect.

[0117] According to a seventh aspect of the present application, a storage device according to the seventh aspect of the present application is provided, comprising: a storage medium and a control component as described in the seventh aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] Figure 1A shows a block diagram of a storage device;

[0119] Figure 1B A detailed block diagram showing the control components of a storage device;

[0120] Figure 2A A schematic diagram of an NVM chip storing an L2P table provided in an embodiment of the present application is shown;

[0121] Figure 2B The structural diagram of Table A provided in the embodiments of the present application is shown;

[0122] Figure 2C A schematic diagram of a cache provided in an embodiment of the present application is shown;

[0123] Figure 2D A schematic diagram of a cache provided by another embodiment of the present application is shown;

[0124] Figure 2E The structural diagram of Table B provided in the embodiment of the present application is shown;

[0125] Figure 2F A schematic diagram of another cache provided in an embodiment of the present application is shown;

[0126] Figure 3 A schematic diagram showing a control component processing a write command provided in an embodiment of the present application is shown;

[0127] Figure 4A A schematic diagram of updating table A provided in an embodiment of the present application is shown;

[0128] Figure 4B A schematic diagram of an update table A provided in another embodiment of the present application is shown;

[0129] Figure 4C A schematic diagram showing the allocation of storage units from a cache during the process of a control component processing a write command provided by an embodiment of the present application is shown;

[0130] Figure 4D A schematic diagram showing allocation of storage units from a cache during processing of a write command by a control component provided by another embodiment of the present application is shown;

[0131] Figure 4E A schematic diagram showing a control component processing a write command according to an embodiment of the present application is shown;

[0132] Figure 5 A schematic diagram showing a control component performing a flash operation provided by an embodiment of the present application is shown;

[0133] Fig. 6A A schematic diagram showing a control component performing a flash operation provided by another embodiment of the present application is shown;

[0134] Figure 6B A schematic diagram showing updating A during a flash operation performed by a control component provided in an embodiment of the present application is shown;

[0135] Figure 7 A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown;

[0136] Figure 8 A schematic diagram showing a control component processing a write command provided by another embodiment of the present application is shown;

[0137] Fig. 9 A schematic diagram showing a storage medium management unit management and maintenance table B provided in an embodiment of the present application is shown;

[0138] Fig. 10A A schematic diagram showing a control component performing a flash operation provided by another embodiment of the present application is shown;

[0139] Fig. 10B A schematic diagram of updating the cache during the flashing process of the control component provided in an embodiment of the present application is shown;

[0140] Fig.11 A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown;

[0141] Fig. 12A A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown;

[0142] Fig. 12B A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown;

[0143] Fig.13 A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown. DETAILED DESCRIPTION

[0144] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0145] Figure 2A A schematic diagram of an NVM chip storing an L2P table provided in an embodiment of the present application is shown.

[0146] As an example, Figure 2AAs shown, in the NVM chip, the L2P table is stored in multiple storage blocks of the NVM chip (UT0, UT1, UT2, UT3...UTk, k is a positive integer). Each storage block has a storage space of a specified size, for example, the size of each storage block is 4KB. The physical addresses between the storage blocks may be continuous or discontinuous, and the physical addresses of the storage spaces in the same storage block are continuous. Each storage block includes multiple storage units (entries), for example, each storage block includes m storage units, where m is a positive integer. The size of each storage unit may be equal to an L2P table entry, and an L2P table entry is recorded in each storage unit, that is, a mapping relationship between a logical address and a physical address is recorded in each storage unit, so as to realize that a specified number of L2P table entries are stored in each storage block. In addition, the logical addresses indicated by all L2P table entries stored in the same storage block are continuous, and the entries of the L2P table are stored in the order of the storage blocks. For example, the L2P table is stored in four storage blocks, namely UT0, UT1, UT2 and UT3, each storage block includes 1000 storage units, and the entries of the L2P table are stored in the order of UT0, UT1, UT2 and UT3. The logical address range of the L2P table entries stored in UT0 is 0 to 999, the logical address range of the L2P table entries stored in UT1 is 1000 to 1999, the logical address range of the L2P table entries stored in UT2 is 2000 to 2999, and the logical address range of the L2P table entries stored in UT3 is 3000 to 3999. It can be understood that in order to record the mapping relationship between the logical address and the physical address, the L2P table entry can only store its physical address, and the corresponding logical address is calculated by the storage block to which the L2P table entry belongs and the position in the storage block.

[0147] When the required L2P table entries are stored in the NVM chip, since the NVM chip cannot be accessed at a random address but can only be read by page, the storage medium management unit cannot directly manage, maintain and query the entire L2P table. In this case, the storage medium management unit needs to have the ability to manage, maintain and query the L2P table in the NVM chip. In order to enable the storage medium management unit to manage, maintain and query the L2P table in the NVM chip, the storage medium management unit manages and maintains Table A in the embodiment of the present application; wherein Table A records the physical addresses of each storage block in the NVM chip that stores the L2P table entries.

[0148] Figure 2B A schematic diagram of the structure of Table A provided in the embodiments of the present application is shown.

[0149] As an example, Figure 2BAs shown, Table A includes multiple entries, the number of entries included in Table A is the same as the number of storage blocks storing the L2P table in the NVM chip, and each entry in Table A corresponds to a storage block storing the L2P table in the NVM chip. Each entry in Table A records the physical address of the corresponding storage block in the NVM chip. Each entry in Table A is indexed by an entry index. For example, the entry index can be a storage block index (such as a storage block number), and the storage block index can be calculated from the logical address indicated by the received read command or write command, so that the entry index does not need to be recorded in Table A. Since the number of L2P table entries that can be stored in the storage block used to store some entries of the L2P table in the NVM chip is specified, and the logical addresses of the L2P table entries stored in the same storage block are also continuous, the storage medium management unit can determine the storage block number of the storage block corresponding to the logical address indicated by the received read command or write command according to the number of L2P table entries stored in each storage block, index an entry in table A according to the storage block number, read the physical address of the storage block corresponding to the storage block number from the entry, obtain the storage block from the NVM chip according to the physical address, and then obtain the L2P table entry recorded in the storage block. The storage medium management unit can update, query, etc. the L2P table entry recorded in the obtained storage block, thereby realizing the management, maintenance and query of the L2P table in the NVM chip.

[0150] For example, if the logical address indicated by the current read command or write command is LBA3, the storage block number of the corresponding storage block is determined to be UT0 according to LBA3, and entry 0 in table A is indexed according to UT0, and the physical address recorded in entry 0 is read, and according to the physical address, the storage block UT0 storing the L2P table entry corresponding to LBA3 can be obtained from the NVM chip, and the L2P table entry corresponding to LBA3 can be obtained from the storage block UT0.

[0151] As another example, the control component may need to process hundreds or thousands of write commands in a period of time. After the control component receives a write command, the storage medium management unit needs to allocate a physical address to the logical address indicated by the write command and record the mapping relationship between the logical address and the physical address.<LBA,PPA> However, the NVM chip needs to write data page by page, and the time required to write data is relatively long (e.g., about 100us), while the mapping relationship between the logical address and the physical address is recorded.<LBA,PPA> The size of the L2P table entry is, for example, 4 bytes, so it is extremely inefficient to write to the NVM chip for each L2P table update caused by a write command. Therefore, in order not to affect the performance of the storage device, the storage medium management unit also manages and maintains the cache, and uses the cache to record the physical address corresponding to the logical address indicated by one or more write commands. In the embodiments according to the present application, unless otherwise stated, "cache" refers to a storage space of a specified size for recording the physical address corresponding to the logical address indicated by one or more write commands provided in the embodiments of the present application. The "cache" according to the embodiments of the present application is provided by a high-performance memory such as SRAM, DRAM, TCM, etc.

[0152] Figure 2C A schematic diagram of the cache provided in an embodiment of the present application is shown.

[0153] As an example, Figure 2C As shown, the cache includes multiple storage units (storage unit 0, storage unit 1, storage unit 2, ..., storage unit N, N is a positive integer). Each storage unit has a designated storage space for recording a logical address indicated by a write command and a corresponding physical address. It should be understood that the storage units in the cache are different from Figure 2B The storage unit in the storage block described. The storage block is located in the NVM chip, so the storage unit in the storage block is a storage space of a specified size in the NVM chip. The cache is an external memory coupled to the control component, or is located in the internal memory of the control component. The memory mentioned here is different from the NVM chip. The memory is, for example, a high-performance memory such as DRAM, SRAM or TCM. Therefore, the storage unit in the cache is a storage space of a specified size in the memory.

[0154] Continue to see Figure 2C Each storage unit includes a logical address field and a physical address field, wherein the logical address field records the logical address (LBA) indicated by the corresponding write command, and the physical address field records the physical address (PPA) allocated to the logical address. Figure 2C Only the fields included in storage unit 0 are shown. It should be understood that the fields included in other storage units in the cache are the same as the fields included in storage unit 0.

[0155] The memory capacity of the storage device accommodating the cache is limited, so the capacity of the cache or the number of storage units according to the embodiment of the present application is also limited. For example, the cache includes 1000, 2000, 8000 or other number of storage units.

[0156] Optionally, in addition to recording a mapping relationship between a logical address and a physical address indicated by a write command, each storage unit of the cache may also record other information, such as a physical address of a storage block in the NVM chip corresponding to an L2P table entry. Each storage unit also includes a storage block physical address field, through which the physical address of the storage block in the NVM chip is recorded.

[0157] Optionally, in addition to indicating the logical address, the write command also indicates the length, wherein the length represents the number of consecutive logical addresses (denoted as Seq). Each storage unit also includes a length information field, which records the number of consecutive logical addresses indicated by the write command.

[0158] Optionally, since each storage block can store more than one L2P table entry, there may be a mapping relationship between the logical address and the physical address recorded by multiple storage units in the cache.<LAB,PPA> Corresponding to the same storage block. In order to record the data recorded by multiple storage units in the cache<LAB,PPA> Corresponding to this relationship of the same storage block, each storage unit may also include field 1 (referred to as Link next field). Field 1 records a storage unit index in the cache. The storage unit index recorded in field 1 indicates the storage unit record of the index.<LAB,PPA> The storage unit where the current field 1 is located records<LAB,PPA> Corresponding to the same storage block. A linked list of several storage units corresponding to the same storage block in the cache is constructed through the storage unit index recorded in field 1 of each storage unit. The specific role of this linked list will be described in the flash operation process below, and will not be repeated here.

[0159] Optionally, the LBA addresses of multiple storage units in the cache may have the same hash value. In order to record the relationship that the LBA addresses recorded by multiple storage units in the cache have the same hash value, see Figure 2C , each storage unit may also include field 2 (recording the search list field). Field 2 records a storage unit index in the cache. The storage unit index recorded in field 2 indicates that the LAB address recorded in the storage unit indexed by it has the same hash value as the LAB address recorded in the storage unit where the current field 2 is located. A linked list of several storage units in the cache whose recorded LBA addresses have the same hash value is constructed through the storage unit index recorded in field 2 in each storage unit. The specific role of this linked list will be described in the read operation below, and will not be repeated here.

[0160] Figure 2D A schematic diagram of a cache provided in another embodiment of the present application is shown.

[0161] As an example, Figure 2D As shown, the cache includes storage unit 0, storage unit 1, storage unit 2, storage unit 3, storage unit 4, storage unit 5, and storage unit 6. The storage unit index recorded in field 1 of storage unit 6 is storage unit 2, and the storage unit index recorded in field 1 of storage unit 2 is storage unit 0. The recorded<LAB,PPA> A linked list of several storage units corresponding to the same storage block: storage unit 6->storage unit 2->storage unit 0. Based on this linked list, we can know the data recorded in storage unit 6, storage unit 2, and storage unit 0.<LAB,PPA> Corresponding to the same storage block, several or all storage units corresponding to the same storage block in the cache may be obtained.

[0162] In order for the storage medium management unit to directly manage and query one or more<LAB,PPA> As another example, the storage medium management unit also maintains and manages table B; wherein table B records the cache records<LAB,PPA> The storage unit index of .

[0163] Figure 2E A schematic diagram showing the structure of Table B provided in the examples of the present application is shown.

[0164] As an example, Figure 2E As shown, table B includes multiple entries (entry 0, entry 1, entry 2, ..., entry M, where M is a positive integer), and the number of entries included in table B is not greater than the number of storage units in the cache. Table B records the index of the storage unit in the cache that has stored the logical address and the physical address. The storage unit in the cache can be accessed through the storage unit index recorded in table B.

[0165] Each entry in table B is also indexed by an entry index. The entry index of an entry in table B is different from Figure 2BThe entry index of the entry in Table A, and the entry index of the entry in Table B are the hash values ​​obtained by hashing the logical address (recorded as Hash(LBA)). When the control component receives a read command, the storage medium management unit calculates the corresponding hash value based on the LBA address indicated by the read command, and indexes the entry in Table B based on the hash value. If an entry is indexed from Table B, and the entry records the storage unit index (or the entry is non-empty), it means that the LBA address indicated by the read command and its physical address are currently recorded in the cache. The storage medium management unit determines the corresponding storage unit based on the storage unit index recorded by the indexed entry in Table B, obtains the physical address corresponding to the LBA address indicated by the read command from the storage unit, and reads data from the NVM chip based on the physical address.

[0166] As another example, the entry in index table B is indexed according to the hash value corresponding to the LBA address. If the indexed entry does not record the storage unit index (or the entry is empty), the LBA address and its corresponding physical address are not recorded in the cache. At this time, it is necessary to read the L2P table entry corresponding to the LBA address from the NVM chip to obtain the physical address corresponding to the LBA address. The storage medium management unit reads the L2P table entry corresponding to the LBA address from the NVM chip. For the specific process, see Figure 2B , I will not go into details here.

[0167] As another example, the hash values ​​obtained by hash calculation of multiple LBA addresses may be the same, that is, multiple LBA addresses correspond to the same hash value; and the entries in Table B are indexed according to the hash values ​​corresponding to the LBA addresses, so that multiple LBA addresses with the same hash value correspond to entries in Table B, that is, the relationship between the LBA address and the entries in Table B is many-to-one, so the number of entries in Table B is much smaller than the number of optional LBA values.

[0168] Figure 2F A schematic diagram of another cache provided in an embodiment of the present application is shown.

[0169] As an example, Figure 2F As shown, the cache includes storage unit 0, storage unit 1, storage unit 2, storage unit 3 and storage unit 4. The storage unit index recorded in field 2 of storage unit 0 is storage unit 3, and the storage unit index recorded in field 2 of storage unit 3 is storage unit 1. According to the storage unit indexes recorded in field 2 of storage unit 0 and storage unit 3, a linked list of storage units with the same hash value corresponding to the recorded LAB addresses is constructed: storage unit 0->storage unit 3->storage unit 1.

[0170] In the embodiment of the present application, the storage medium management unit manages, maintains and queries the L2P table in the NVM chip through part or all of Table A, cache, and Table B. Table A, cache, and Table B can be located in a memory coupled to the outside of the control component, or in a memory inside the control component, such as DRAM, SRAM, or TCM. For ease of understanding, the following describes the process of the storage medium management unit managing, maintaining, and querying the L2P table in the NVM chip through part or all of Table A, cache, and Table B in the embodiment of the present application from three aspects: read command processing, write command processing, and flush processing.

[0171] Figure 3 A schematic diagram showing the control component processing a write command provided in an embodiment of the present application is shown.

[0172] As an example, Figure 3 As shown, the control component is coupled to the memory, the memory includes a cache and a table A, and the storage medium management unit can manage and maintain the table A and the cache in the memory. The following describes in detail the process of the control component processing a write command.

[0173] like Figure 3 As shown, the host transmits a write command to the storage device through the host interface, and the host interface transmits the write command to the host command processing unit, which is represented as process (1). The host command processing unit processes the write command to generate one or more storage commands, and sends the storage command to the storage command processing unit, which is represented as process (2). In response to receiving the storage command, the storage command processing unit parses the storage command to obtain the LBA address indicated by it, and sends the LBA address to the storage medium management unit, which is represented as process (3). In response to receiving the LBA address, the storage medium management unit selects a storage unit from the cache and assigns it to the LBA address, for example, selects a free storage unit from the cache and assigns it to the LBA address. And assigns a physical address to the LBA address, and records the LBA address and the physical address to the selected storage unit, which is represented as process (4). The storage command processing unit generates a media interface command according to the physical address assigned to the LBA address by the storage medium management unit, and sends the media interface command to the media interface controller, which is represented as process (5). In response to receiving the media interface command, the storage medium generates one or more storage medium access commands based on the media interface command, and writes the data indicated by the write command to the NVM chip based on the one or more storage medium access commands. This process is represented as process (6).

[0174] When a physical address is assigned to an LBA address, the mapping relationship between the LBA address and the physical address is different from the mapping relationship between the LBA address and the physical address recorded in the L2P table in the NVM chip. This difference needs to be recorded, and the new mapping relationship between the LBA address and the physical address should be used to replace the old mapping relationship recorded in the NVM chip at an appropriate time. Figure 3 In order to write one or more LBA addresses recorded in the storage unit in the cache and the physical address corresponding to each LBA address to the NVM chip, the storage medium management unit records the LBA address indicated by the write command and the physical address assigned to it in the storage unit of the cache and then updates Table A. This process is represented as process (7). For example, the storage medium management unit calculates the storage block index according to the LBA address indicated by the write command, and obtains an entry in Table A according to the storage block index. Figure 2B As shown, the entry in Table A initially stores the physical address of the corresponding storage block in the NVM chip. After obtaining an entry in Table A according to the storage block index, the physical address of the storage block in the NVM chip recorded in the entry is changed to the index of the storage unit in the cache that records the LBA address indicated by the write command and its corresponding physical address.

[0175] It should be noted that, in the embodiment of the present application, when the storage medium management unit uses the LBA address indicated by the write command recorded in the cache and the storage unit index of the corresponding physical address to update the physical address of the storage block in the NVM chip recorded in the corresponding entry in Table A, the storage unit index can be used to replace part or all of the physical address of the storage block in the NVM chip recorded in the corresponding entry in Table A. In addition, when the storage unit index in the cache is used to update the corresponding entry in Table A, the physical address of part or all of the storage block in the NVM chip replaced by the storage unit index is also recorded in the storage unit corresponding to the storage unit index.

[0176] Thus, when the content of an entry in Table B is a cache unit index rather than a physical address of a storage block, it means that at least one L2P table entry of the storage block has been updated, and the updated mapping relationship between the LBA address and the physical address is recorded in the cached storage unit. Furthermore, since the storage block includes multiple L2P tables, when multiple L2P table entries of the storage block are updated, only one storage unit index is recorded in the entry of Table B corresponding to the storage block. And the linked list formed by field 1 in the storage unit is used to associate multiple updated L2P table entries in the same storage block.

[0177] Figure 4A A schematic diagram of the update table A provided in an embodiment of the present application is shown.

[0178] For example, the control component receives a write command 1, the logical address indicated by the write command 1 is LBA0, the storage medium management unit in the control component allocates storage unit 2 in the cache for the write command 1, and the physical address allocated to LBA0 is PPA0.<LBA0,PPA0> Recorded in storage unit 2. The storage medium management unit calculates the corresponding storage block UT0 according to LBA0, and indexes to entry 0 in table A according to UT0, wherein entry 0 records the physical address UT0_PPA of storage block UT0 in the NVM chip. Figure 4A As shown, the storage media management unit will<LBA0,PPA0> After recording storage unit 2, the storage unit 2 index replaces the entire content of entry 0 in table A, that is, UT0_PPA in entry 0 is updated to the storage unit 2 index. And the storage block physical address field is also recorded in storage unit 2, and its value is UT0_PPA.

[0179] Figure 4B A schematic diagram of an update table A provided in yet another embodiment of the present application is shown.

[0180] For example, the physical address of the storage block recorded by each entry in Table A in the NVM chip has a specified size (or a specified number of bits), and the physical address of the storage block recorded by each entry in the NVM chip is divided into two parts, UT_PPA_1 and UT_PPA_2, according to the high and low bits. For example, UT_PPA_1 includes a specified number of high bits in the physical address, and UT_PPA_2 includes other bits in the physical address except UT_PPA_1. Figure 4B As shown, the size of the physical address of the storage block recorded by each entry in Table A in the NVM chip is, for example, 3 bytes, UT_PPA_1 is the upper 2-byte part of the physical address, and UT_PPA_2 is the lower 1-byte part of the physical address. When the storage medium management unit updates an entry in Table A using the storage unit index in the cache, it uses the storage unit index in the cache to update part of the data of UT_PPA_1 in the entry, while UT_PPA_2 remains unchanged. In this case, the data recorded in the storage block physical address field of the cached storage unit is the data of UT_PPA_1.

[0181] Continue to see Figure 4B, when the storage medium management unit updates entry 0 in table A with the index of storage unit 2 in the cache, it replaces part of the data of UT_PPA_1 in entry 0 with the index of storage unit 2, while keeping UT_PPA_2 in entry 0 unchanged. In this case, entry 0 of table A contains both part of the data of the physical address of the storage block in the NVM chip (UT_PPA_2) and the index of the storage unit of the cache storing the L2P table entry in UT0. In addition, in this case, storage unit 2 records UT0_PPA1 in the storage block physical address field.

[0182] Optionally, when multiple L2P table entries in the same storage block are stored in the cache, each time an L2P table entry in the storage block is stored in a storage unit in the cache, the entry corresponding to the storage block in Table A is optionally updated, that is, the same entry in Table A can be updated multiple times. Figure 4B When the same entry in table A is updated multiple times using the storage unit index in the cache, the number of updates (Count) is also recorded in the UT_PPA_1 part of the entry, and the number is used to represent the number of L2P table entries in the storage block corresponding to the entry cached in the current cache.

[0183] pass Figure 4B The organization of the entries in table A saves the storage space occupied by table A and the cache as a whole. In some cases, the size of the entry in table A is different from the size of the cache unit index. For example, in Figure 4B In the example, the size of the table A entry is 3 bytes (used to accommodate the physical address of the storage block), while the cache unit index only needs 14 bits. When the cache unit index completely replaces the storage block physical address in the table A entry, some storage space will be wasted, and 3 bytes will be required in the cache unit to accommodate the table A entry, resulting in a larger cache storage space requirement. Figure 4B In an embodiment, the entries of table A are divided into two parts, and only the 2-byte data of UT_PPA_1 is recorded in the cache unit, and the 2-byte space occupied by UT_PPA_1 is used to record the cache unit index, and a number (for example, 2) bits are left to record the number of times (Count).

[0184] Figure 4C A schematic diagram of allocating storage units from a cache during the process of processing a write command by a control component provided in an embodiment of the present application is shown.

[0185] As an example, in the cache, the storage unit records the LBA address and the corresponding physical address PPA, such as Figure 4CAs shown. The control component responds to receiving write command 2, and the write command indicates the logical address and length; wherein, the logical address indicated by write command 2 is LBA2, and the length is 100. In other words, write command 2 indicates an LBA address range, and its LBA address range is LBA2 to LBA101. The storage medium management unit selects 100 storage units from the cache according to the LBA address range indicated by write command 2, and each storage unit is used to record an LBA address in the LBA address range indicated by write command 2 and its corresponding physical address. For example, storage unit 0 to storage unit 99 are selected from the storage units and assigned to write command 2. It should be understood that the multiple storage units allocated by the storage medium management unit for the write command may be continuous or discontinuous in the cache, and this is not limited here.

[0186] Figure 4D A schematic diagram showing allocation of storage units from a cache during processing of a write command by a control component provided in yet another embodiment of the present application is shown.

[0187] As an example, each storage unit in the cache also includes a length information field, such as Figure 4D As shown. The control component responds to receiving write command 2, which indicates the logical address and length; wherein the logical address indicated by write command 2 is LBA2, and the length is 100, that is, write command 2 indicates an LBA address range, and its LBA address range is LBA2 to LBA101. The storage medium management unit selects a storage unit from the cache, such as selecting storage unit 0, records LBA2 in the logical address field of the storage unit 0, records the physical address corresponding to LBA2 in the physical address field, and records the number of consecutive LBAs indicated by write command 2 as 100 in the length information field.

[0188] In an embodiment of the present application, when a write command indicates multiple consecutive LBA addresses, a length information field is set in a storage unit of the cache to record the length indicated by the write command. There is no need to allocate multiple storage units in the cache for the write command. Information of multiple consecutive LBA addresses can be stored by allocating one storage unit from the cache, thereby reducing the storage space occupied by the cache.

[0189] Figure 4E A schematic diagram showing a control component processing a write command provided by an embodiment of the present application is shown.

[0190] Figure 4EIn the example, each storage unit in the cache also includes field 1. As an example, the control component receives a write command A1, wherein the logical address indicated by the write command A1 is LBA_B1; when the control component processes the write command A1, the storage medium management unit allocates storage unit 2 in the cache for the write command A1, allocates the physical address PPA1, and determines that it corresponds to the storage block UT1 according to LBA_B1. The storage medium management unit<LBA_B1,PPA1> Recorded in storage unit 2, and updated entry 1 corresponding to UT1 in table A according to the index of storage unit 2.

[0191] Next, the control unit receives a write command A2, in which the logical address indicated by the write command A2 is LBA_B2. When the control unit processes the write command A2, the storage medium management unit allocates storage unit 0 in the cache for the write command A2 and allocates the physical address PPA2. The storage medium management unit determines that LBA_B2 also corresponds to storage block UT1. In addition to updating the entry 1 corresponding to UT1 in table A according to the index of storage unit 0, the storage medium management unit also updates the entry 1 corresponding to UT1 in table A according to the index of storage unit 0.<LBA_B2,PPA2> In addition to recording to storage unit 0, the storage unit 2 index is also recorded in field 1 of storage unit 0. The storage unit 2 index in field 1 indicates that the LBA recorded in storage unit 2 and the LBA recorded in storage unit 0 correspond to the same storage block.

[0192] Figure 5 A schematic diagram showing a control component performing a flash operation provided in an embodiment of the present application is shown.

[0193] When processing a write command, the mapping relationship between the LBA address and the corresponding physical address PPA is updated, so that the L2P table recorded in the storage block of the NVM chip cannot represent the latest mapping relationship between the LBA address and the physical address. Therefore, it is necessary to use the mapping relationship between the LBA address and the physical address PPA recorded in the cache to update the L2P table in the storage block and release the cache unit. This process is called flushing. In the flushing operation, even if some L2P table entries in the storage block still represent the latest mapping relationship between the LBA address and the physical address, the storage block is updated as a whole.

[0194] As an example, Figure 5As shown, the control component is coupled to the memory, the memory includes a cache and a table A, and the storage medium management unit can manage and maintain the table A and the cache in the memory. Due to the limited storage resources of the cache, for the data recorded by one or more storage units in the cache<LBA,PPA> The flash is written to the NVM chip through periodic or conditional triggering. For example, when the storage resources in the cache are occupied and the free storage resources are less than the preset threshold, the flash operation is triggered to write part or all of the data recorded in the cache.<LBA,PPA> Flash to the NVM chip; or preset the flash mechanism to flash part or all of the data in the cache<LBA,PPA> Flashing to the NVM chip. The following is a detailed description of the control component flashing process.

[0195] like Figure 5 As shown, as an example, the storage block UT0 needs to be rewritten. The storage medium management unit selects entry 0 from table A, and obtains the physical address of the storage block UT0 in the NVM chip from the entry 0. This process is represented as process (5-1). According to the physical address of the storage block UT0 in the NVM chip, the storage block UT0 is read from the NVM chip and stored in the memory. This process is represented as processes (5-2) and (5-3). It is determined that the storage units in the cache that record the L2P table entry in the storage block UT0 are storage unit 0 and storage unit 1, where storage unit 0 records<LBA0,PPA0'> , storage unit 1 records<LBA1,PPA1'> , which correspond to L2P table entries entry0 and entry1 in storage block UT0 respectively.

[0196] The memory location 0 records<LBA0,PPA0'> To update the L2P table entry entry 0 of the storage block UT0 in the memory,<LBA0,PPA0> Change to<LBA0,PPA0'> , which is represented as process (5-4).<LBA1,PPA1'> To update the L2P table entry 1 of the storage block UT0,<LBA1,PPA1> Change to<LBA1,PPA1'> , which is represented by process (5-5). In response to the completion of the update of the storage block in the memory, the updated storage block UT0 in the memory is flashed to the NVM chip, which is represented by processes (5-6) and (5-7).

[0197] It can be understood that the NVM chip does not support in-situ rewrite operations, so the physical address of UT0 in the NVM chip after the update is different from the physical address of UT0 in the NVM chip before the update. In response to UT0 being rewritten into the NVM chip, the updated physical address of UT0 in the NVM chip is also recorded in entry 0 of table A.

[0198] As another example, in response to the completion of the flashing of the updated storage block, the information recorded in one or more storage units in the cache corresponding to the storage block UT0 is deleted, and these storage units in the cache are released.

[0199] As another example, during a flash process, the storage medium management unit selects an entry from Table A that corresponds to the storage block with the largest number of L2P table entries recorded in the cache. Figure 4B As shown, the entry corresponding to the storage block with the largest number of L2P table entries recorded in the cache is determined according to the number of updates (Count) recorded in each entry in Table A. For another example, Figure 4E The storage medium management unit also adds field 1 to the cached storage unit, and uses the storage unit index recorded in field 1 to represent its difference from the storage unit recorded in the current storage unit.<LBA,PPA> The storage medium management unit constructs the cache according to the storage unit index recorded in field 1 of each storage unit in the cache.<LBA,PPA> The linked list of corresponding storage blocks. Determine the entry corresponding to the storage block with the largest number of L2P table entries recorded in the cache according to the linked list of each storage block. For another example, Figure 4A , the storage unit records the recorded<LBA,PPA> The physical address of the corresponding storage block in the NVM chip is recorded in the cache.<LBA,PPA> The physical address of the storage block recorded in each storage block in the NVM chip determines the entry corresponding to the storage block with the largest number of L2P table entries recorded in the cache.

[0200] Fig. 6A A schematic diagram showing a control component performing a flash operation provided by another embodiment of the present application is shown.

[0201] As an example, Fig. 6AAs shown, the cache includes storage unit 0, storage unit 1, storage unit 2, storage unit 3, storage unit 4, storage unit 5, storage unit 6 and storage unit 7, wherein storage unit 0, storage unit 1, storage unit 3, storage unit 5 and storage unit 7 are recorded with data, which are recorded in storage unit 0.<LBA8,PPA8'> , storage unit 1 records<LBA13,PPA13> , storage unit 3 records<LBA9,PPA9'> , storage unit 5 records<LBA10,PPA10'> , storage unit 7 records<LBA12,PPA12> . The data recorded in storage unit 0, storage unit 3 and storage unit 5<LBA,PPA> Located in the same storage block UT1, the storage medium management unit selects to store the data recorded in storage unit 0, storage unit 3 and storage unit 5 in the cache.<LBA,PPA> The storage medium management unit determines the physical address of the storage block UT1 in the NVM chip, and reads the storage block UT1 from the NVM chip based on the physical address. The read storage block UT1 includes<LBA6,PPA6> ,<LBA7,PPA7> ,<LBA8,PPA8> ,<LBA9,PPA9> ,<LBA10,PPA10> as well as<LBA11,PPA11> The physical addresses corresponding to LBA8 and LBA10 in the cache are different from those recorded in the storage block UT1. Therefore, when writing, the physical addresses in the storage block UT1 need to be<LBA8,PPA8> Updated to<LBA8,PPA8'> ,Will<LBA10,PPA10> Updated to<LBA10,PPA10'> , and then get UT1' (updated UT1), and write UT1' into the NVM chip, wherein the physical address of UT1' in the NVM chip is different from the physical address of UT1 in the NVM chip before the update, and the physical address of UT1' in the NVM chip is recorded in the entry corresponding to UT1 in Table A, and the physical address of UT1' in the NVM chip is recorded in the entry of UT1. See the following process for Figure 6B .

[0202] As another example, in response to the process of processing a write command, the storage medium management unit updates the physical address of the storage block recorded in the entry in the corresponding table A according to the storage unit index assigned to the write command. In the flashing process, the storage block corresponding to the selected entry in table A is flashed. In order to obtain the L2P table entry for reading the storage block from the NVM chip and to flash the updated storage block to the NVM chip after updating the storage block, it is necessary to determine the physical address of the storage block in the NVM chip and to flash one or more of the storage blocks recorded in the cache.<LBA,PPA> Before or after flashing to the NVM chip,<LBA,PPA> The entry content of the corresponding storage block in table A is modified to the physical address of the storage block in the NVM chip.

[0203] Figure 6B A schematic diagram showing updating table A during a flash operation performed by a control component provided in an embodiment of the present application is shown.

[0204] As an example, Figure 6B As shown, in Table A, entry 1 corresponding to UT1 records the index of storage unit 3.<LBA8,PPA8'> , the storage unit 3 records<LBA9,PPA9'> , the storage unit 5 records<LBA10,PPA10'> Flashing to UT1 to obtain UT1', before or after flashing UT1' to the NVM chip, the storage medium management unit updates the entry corresponding to UT1 in table A to the physical address UT1'-PPA of UT1' in the NVM chip to obtain the updated table A.

[0205] Figure 7 A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown.

[0206] As an example, Figure 7 As shown, the control component is coupled to the memory, the memory includes a cache and a table A, and the storage medium management unit can manage and maintain the table A and the cache in the memory. The following describes in detail the process of the control component processing a read command.

[0207] like Figure 7As shown, the host transmits a read command to the storage device through the host interface, and the host interface transmits the read command to the host command processing unit, which is represented as process (7-1). The host command processing unit processes the read command to generate one or more storage commands, and sends the storage command to the storage command processing unit, which is represented as process (7-2). In response to receiving the storage command, the storage command processing unit parses the storage command to obtain the LBA address indicated by it, and sends the LBA address to the storage medium management unit, which is represented as process (7-3). In response to receiving the LBA address indicated by the read command, the storage medium management unit calculates the storage block corresponding to the LBA address and the position in the storage block according to the LBA address indicated by the read command, determines the storage block index corresponding to the LBA address, and determines the corresponding entry in the query table A according to the determined storage block index, which is represented as process (7-4).

[0208] As an example, in response to the entry determined from Table A recording the physical address of the storage block in the NVM chip, the storage block including the L2P table entry corresponding to the LBA address is read from the NVM chip into the memory, and the physical address corresponding to the LBA address is obtained from the read storage block according to the position of the LBA address in the storage block. This process is represented as processes (7-5) and (7-6). As another example, if the storage unit index in the cache is recorded according to the entry determined from Table A, the corresponding storage unit in the cache is obtained according to the storage unit index. The physical address corresponding to the LBA address is obtained from the storage unit. This process is represented as process (7-7).

[0209] Continue to see Figure 7 The storage command processing unit generates a media interface command according to the physical address corresponding to the LBA address obtained by the storage medium management unit, and sends the media interface command to the media interface controller. This process is represented as process (7-8). In response to receiving the media interface command, the storage medium generates one or more storage medium access commands based on the media interface command, and reads the data indicated by the read command to be read from the NVM chip based on the one or more storage medium access commands. This process is represented as process (7-9).

[0210] In addition, Figure 7 In the embodiment, the media interface controller stores the response data in the memory in response to receiving the response data of the read command fed back by the NVM chip, and the host command processing unit sends the response data to the host through the host interface.

[0211] In accordance with Figure 7In the embodiment of the present application, in order to process the read command, it is necessary to read the storage block UT from the NVM chip, or traverse the linked list formed by the field 1 of the cached storage unit unit to find the L2P table entry corresponding to the LBA address of the read command. Whether reading the storage block from the NVM chip or traversing the storage unit linked list, additional processing delays are introduced, resulting in an extension of the read command processing time. According to the embodiment of the present application, the read command processing time is reduced by introducing Table B.

[0212] Figure 8 A schematic diagram showing a control component processing a write command provided in yet another embodiment of the present application is shown.

[0213] As an example, Figure 8 As shown, the control component is coupled to the memory, the memory includes a cache, table A and table B, and the storage medium management unit can manage, maintain and query the L2P table in the NVM chip by managing and maintaining the cache, table A and table B in the memory. The following describes in detail the process of the control component processing a write command.

[0214] like Figure 8 As shown, the host transmits a write command to the storage device through the host interface, and the host interface transmits the write command to the host command processing unit, which is represented as process (8-1). The host command processing unit processes the write command to generate one or more storage commands, and sends the storage command to the storage command processing unit, which is represented as process (8-2). In response to receiving the storage command, the storage command processing unit parses the storage command to obtain the LBA address indicated by it, and sends the LBA address to the storage medium management unit, which is represented as process (8-3). In response to receiving the LBA address, the storage medium management unit selects a storage unit from the cache and assigns it to the LBA address. For example, a free storage unit is selected from the cache and assigned to the LBA address; and a physical address is assigned to the LBA address, and the LBA address and the assigned physical address are recorded in the selected storage unit, which is represented as process (8-4). The storage command processing unit generates a media interface command according to the physical address assigned to the LBA address by the storage medium management unit, and sends the media interface command to the media interface controller, which is represented as process (8-5). In response to receiving the media interface command, the storage medium generates one or more storage medium access commands based on the media interface command, and writes the data indicated by the write command to the NVM chip based on the one or more storage medium access commands. This process is represented as process (8-6).

[0215] Optionally, continue to see Figure 8In order to facilitate writing one or more LBA addresses recorded in the storage unit in the cache and the physical address corresponding to each LBA address to the NVM chip, the storage medium management unit also updates Table A before or after recording the LBA address indicated by the write command and the physical address allocated to it in the storage unit of the cache. This process is represented as process (8-7). It should be noted that Figure 8 The storage media management unit manages and maintains the cache and table A. Figure 3 Similar, I will not go into details here.

[0216] Optionally, continue to see Figure 8 In addition to managing and maintaining the cache and table A, the storage medium management unit also needs to manage and maintain table B. This process is represented as process (8-8).

[0217] Fig. 9 A schematic diagram of the storage medium management unit management and maintenance table B provided in an embodiment of the present application is shown.

[0218] As an example, in response to receiving a write command C1, the write command C1 indicates a logical address LBAm. In the process of processing the write command C1, the storage medium management unit allocates a storage unit 5 in the cache and a physical address PPA2 for the write command C1.<LBAm,PPA2> Stored in storage unit 5. Perform a hash operation on LBAm to obtain its corresponding hash value (recorded as Hash(LBAm)). Use Hash(LBAm) as the index (for example, index 0 in table B = Hash(LBAm)) to obtain entry 0 in table B, and update entry 0 in table B according to the status of entry 0 in table B. Among them, the status of entry 0 in table B includes non-empty or empty. If entry 0 in table B is empty, the index of storage unit 5 is recorded in entry 0 in table B. If entry 0 in table B is not empty, the index of storage unit 1 recorded in entry 0 in table B is obtained, and the corresponding storage unit 1 in the cache is determined according to the index of storage unit 1, and field 2 of storage unit 1 is set, and the index of storage unit 5 is recorded in field 2 of storage unit 1.

[0219] Further, the control component receives a write command C2, which indicates a logical address LBAn. When the control component processes the write command C2, the storage medium management unit allocates a storage unit 3 in the cache and a physical address PPA3 for the write command C2.<LBAn,PPA3> Stored in storage unit 3. Perform hash operation on LBAn to obtain its corresponding hash value Hash(LBAn). As an example, entry 0 in table B is also obtained by using Hash(LBAn) as the index. Storage unit 1 is obtained according to the storage unit 1 index recorded in entry 0 of table B, storage unit 5 is obtained according to the storage unit 5 index recorded in field 2 of storage unit 1, and storage unit 3 index is recorded in field 2 of storage unit 5. Based on this, according to the information recorded in field 2 of storage unit 1 and storage unit 5, it can be determined that the hash values ​​corresponding to the LBAs recorded in storage unit 1, storage unit 5 and storage unit 3 are indexed to the same entry (entry 0) in table B.

[0220] It should be noted that in the embodiment of the present application, when the storage medium management unit manages, maintains and queries the L2P table in the NVM chip by managing and maintaining the cache, table A and table B in the memory, the control component processes the write command including all the operations of controlling the processing of the write command when managing, maintaining and querying the L2P table in the NVM chip through the cache and table A, which will not be repeated here.

[0221] As an example, when the storage medium management unit manages, maintains and queries the L2P table in the NVM chip by managing and maintaining the cache, table A and table B in the memory, the control component processes a flash write, including all operations of the control component during the flash write process when the storage medium management unit manages, maintains and queries the L2P table in the NVM chip through the cache and table A, which will not be repeated here.

[0222] Further, when the storage medium management unit manages, maintains and queries the L2P table in the NVM chip by managing and maintaining the cache, table A and table B in the memory, the control component also includes updating the table B entry during the flash process. The storage medium management unit responds to the one or more storage units in the cache recording<LBA,PPA> After or before writing to the corresponding storage block, the hash value corresponding to the LBA recorded in each storage unit in one or more storage units to be written is also calculated, and the entries in table B are indexed according to the hash value of each LBA. According to the indexed table B entry, the content of the indexed table B entry is deleted, and the table B resources are released, so that the entry status in index table B is updated from non-empty to empty.

[0223] A hash operation may result in a hash conflict, and may cause the hash values ​​Hash(LBA) of multiple different LBA values ​​to be the same. According to an embodiment of the present application, the occurrence of a hash conflict is recorded by a linked list formed by field 2 in the storage unit, and the resolution of the hash conflict is facilitated. Usually, the probability of a hash conflict is low, which makes the length of the linked list formed by field 2 in the storage unit usually shorter (for example, shorter than the linked list formed by field 1 in the storage unit). Therefore, even if a hash conflict occurs, and it is necessary to traverse the linked list formed by field 2 to find the physical address corresponding to the logical address LBA, the additional overhead introduced in this way is usually significantly lower than the overhead introduced by traversing the linked list formed by field 1.

[0224] Fig. 10A A schematic diagram showing a control component performing a flash operation provided by another embodiment of the present application is shown.

[0225] As an example, as shown in FIG10 , during a flash process, the storage medium management unit needs to store the data recorded in storage unit 1, storage unit 3, and storage unit 5.<LBA,PPA> Flash to the corresponding storage block in the NVM chip. The storage medium management unit indexes to entry 0 in table B according to the hash value corresponding to the LBA recorded by storage unit 1, indexes to entry 2 in table B according to the hash value corresponding to the LBA recorded by storage unit 3, and indexes to entry 1 in table B according to the hash value corresponding to the LBA recorded by storage unit 5; wherein entry 0 of table B records the index of storage unit 1, entry 1 records the index of storage unit 5, and entry 2 records the index of storage unit 3. In response to the storage unit 1, storage unit 3, and storage unit 5 recording the<LBA,PPA> After or before writing to the corresponding storage block in the NVM chip, the storage unit 1 index, storage unit 5 and storage unit 3 index recorded in entry 0, entry 1 and entry 2 are deleted, so that entry 0, entry 1 and entry 2 change from non-empty to empty.

[0226] Fig. 10B A schematic diagram of updating the cache during the flashing process of the control component provided in an embodiment of the present application is shown.

[0227] As an example, the storage medium management unit stores the data recorded in storage unit 0 in the cache.<LBA8,PPA8'> , the storage unit 3 records<LBA9,PPA9'> , the storage unit 5 records<LBA10,PPA10'> After writing to UT1 to obtain the updated UT1, it is necessary to release the cache resources and clear storage unit 0, storage unit 3, and storage unit 5. For example,<LBA8,PPA8'> , the storage unit 3 records<LBA9,PPA9'> , the storage unit 5 records<LBA10,PPA10'> Delete; in addition, other information recorded in storage unit 0, storage unit 3 and storage unit 5 (such as the physical address, length, field 1, field 2 of the storage block in the NVM chip) are deleted.

[0228] like Fig. 10B As shown, field 2 of storage unit 0 records <storage unit 5 index>, field 2 of storage unit 1 records <storage unit 7 index>, field 2 of storage unit 3 is empty, field 2 of storage unit 5 records <storage unit 3 index>, and field 2 of storage unit 7 records <storage unit 0 index>. Based on the contents recorded in field 2 of storage unit 0, storage unit 1, storage unit 3, storage unit 5, and storage unit 7, a linked list indicating the same entry in table B is constructed as: storage unit 1→storage unit 7→storage unit 0→storage unit 5→storage unit 3. That is, the hash values ​​corresponding to the LBAs recorded by storage unit 1, storage unit 7, storage unit 0, storage unit 5, and storage unit 3 are the same. When storage unit 0, storage unit 3 and storage unit 5 are cleared, field 2 in storage unit 0, storage unit 3 and storage unit 5 will also be deleted; and deleting field 2 in storage unit 0, storage unit 3 and storage unit 5 will change the linked list of the same entry in the above-mentioned indication table B, so it is necessary to adjust the linked list constructed by field 2 of each storage unit, and update field 2 of each storage unit in the cache according to the adjusted linked list. For example, Fig. 10B As shown, after deleting field 2 in storage unit 0, storage unit 3 and storage unit 5, the adjusted linked list is storage unit 1→storage unit 7, and the storage unit 0 index recorded in field 2 in storage unit 7 is deleted according to the adjusted linked list.

[0229] Optionally, the entry of table B records the index of storage unit 3. When storage unit 0, storage unit 3, and storage unit 5 are cleared, the entry of table B is also updated to record the index of storage unit 7.

[0230] Fig.11 A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown.

[0231] As an example, the control component is coupled to a memory, the memory includes a cache and a table A, and the storage medium management unit can manage and maintain the table A and the cache in the memory. The following describes in detail the process of the control component processing a read command.

[0232] When the control component receives a read command and processes the read command, the storage medium management unit performs a hash operation according to the LBA address indicated by the read command to obtain its corresponding hash value Hash(LBA), and indexes to the corresponding entry in Table B according to the Hash(LBA) value.

[0233] like Fig.11 As shown, as an example, the entry 0 in table B is indexed according to the Hash (LBA) value. If the entry 0 in table B indexed according to the Hash (LBA) value is not empty, but records the storage unit 0 index, it may be necessary to obtain the physical address corresponding to the LBA from the cache, rather than from the L2P table recorded in the storage block of the NVM chip, because the cache may record a new physical address corresponding to the LBA, and the physical address in the L2P table is outdated. The storage medium management unit obtains the storage unit 0 in the cache according to the storage unit 0 index, and obtains the physical address recorded in the storage unit 0.<LBAm,PPA2> , and confirm the data recorded in storage unit 0<LBAm,PPA2> Whether it matches the LBA indicated by the read command, for example, whether the LBAm recorded in storage unit 0 is the same as the LBA indicated by the read command.

[0234] If the value recorded in memory cell 0 is<LBAm,PPA2> Different from the LBA indicated by the read command. As an example, if the storage unit 0 also includes a length information field, and the number of consecutive LBAs recorded in the length information field is greater than 1, the storage medium management unit calculates the LBA range (LBAm, LBAm+Seq) recorded in the storage unit 0 according to the number of consecutive LBAs Seq recorded in the length information field in the storage unit 0, and queries whether the LBA indicated by the read command falls within the LBA range recorded in the storage unit 0. If the LBA indicated by the read command falls within the LBA range recorded in the storage unit 0, and the LBA that matches the LBA indicated by the read command is LBAm+a, then the physical address corresponding to the LBA indicated by the read command is PPA2+a.

[0235] If the value recorded in memory cell 0 is<LBAm,PPA2> The physical address PPA2 is the same as the LBA indicated by the read command, and is used as the physical address of the LBA indicated by the read command.

[0236] As another example, if the LBA indicated by the read command does not fall within the LBA range recorded in storage unit 0, in response to the fact that storage unit 0 also includes field 2, field 2 of storage unit 0 records the index of storage unit 5, storage unit 5 in the cache is queried according to the index of storage unit 5, and the LBA recorded in storage unit 5 is obtained.<LBA,PPA> , and query the data recorded in storage unit 5<LBA,PPA> Or whether the LBA range matches the LBA indicated by the read command.<LBA,PPA> Or the LBA range does not match the LBA indicated by the read command. Query the storage unit index recorded in field 2 of storage unit 5, and continue to match the LBA indicated by the read command in the same way as storage unit 5. And so on, until field 2 in the found storage unit is empty, stop searching, and report that the LBA indicated by the read command is not recorded in the cache. If so on, an LBA matching the LBA indicated by the read command is found in the storage unit in the cache, and the physical address recorded in the storage unit is used as the physical address of the LBA indicated by the read command.

[0237] As another example, in response to the LBA indicated by the read command not being stored in the cache (for example, entry 0 in table B is empty, or when the entry in table B is not empty, the storage unit recording the logical address LBA to be accessed by the read command is not found from the storage units in the cache), the storage medium management unit will execute the following Figure 7 The processes (7-5), (7-6), (7-7) and (7-8) shown in the figure obtain the physical address corresponding to the LBA indicated by the read command. As another example, in response to the LBA indicated by the read command being stored in the cache, the physical address corresponding to the LBA indicated by the read command is obtained from the corresponding storage unit. The control component reads data from the NVM chip according to the physical address corresponding to the LBA indicated by the read command.

[0238] When the physical address corresponding to the logical address LBA is recorded in the cache, according to the embodiment of the present application, the entry of table B obtained by using the hash value of the LBA as an index must be non-empty, so that the storage unit in the cache that records the physical address corresponding to the LBA can be quickly obtained through the entry of table B, thereby speeding up the processing of the read command. When the physical address corresponding to the logical address LBA is not recorded in the cache, the entry of table B obtained by using the hash value of the LBA as an index is likely to be empty, so that it can be immediately known that the L2P table corresponding to the LBA needs to be obtained from the NVM chip, thereby introducing fewer additional operations for the read operation. Only in the case of extremely rare probability, the entry of table B obtained by using the hash value of the LBA as an index is non-empty, but the physical address corresponding to the LBA is not recorded in the cache. At this time, not only is it necessary to obtain the L2P table corresponding to the LBA from the NVM chip, but also the overhead of traversing the linked list formed by field 2 of the storage unit in the cache is introduced.

[0239] As an example, the host includes a host memory buffer (HMB). A storage device based on the NVMe protocol can use the HMB in a manner of accessing a memory (rather than an NVM chip). Thus, the time required to access the HMB is significantly lower than the time required to access the NVM chip. In addition to being written to the NVM chip, the L2P table can also be written to the host memory buffer (HMB) on the host side. Thus, according to an embodiment of the present application, the HMB is used as a temporary storage space for the L2P table.

[0240] Fig. 12A A schematic diagram showing a control component processing a flash operation provided by another embodiment of the present application is shown.

[0241] For example, see Fig. 12A When the storage medium processing unit is flashing a storage block, in addition to writing the updated storage block to the NVM chip, it also writes the updated storage block to the HMB of the host.

[0242] Optionally, during the flashing process, the updated storage block is written to the HMB, and the writing to the NVM chip is postponed. After the HMB space occupied by the storage block is greater than a threshold, or the time the storage block is in the HMB exceeds a threshold, the storage block in the HMB is written to the NVM chip. And the address for the HMB is recorded in the entry of Table A to identify that the corresponding storage block is located in the HMB (rather than in the NVM chip).

[0243] Fig. 12B A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown.

[0244] As an example, Fig. 12B As shown, the control component responds to receiving the read command and processes the read command. The storage medium management unit learns from Table B that the LBA address indicated by the read command is not stored in the cache. The storage medium management unit determines the storage block corresponding to the LBA address and the position in the storage block according to the LBA address indicated by the read command, and inquires whether the storage block is stored in the HMB (for example, through Table A). If the storage block corresponding to the LBA address indicated by the read command is stored in the HMB, the control component obtains the storage block from the HMB, and obtains the PPA corresponding to the LBA address from the storage block according to the position of the LBA address indicated by the read command in the storage block.

[0245] Further, in response to the storage block corresponding to the LBA address indicated by the read command not being stored in the HMB, the storage medium management unit will execute the following Figure 7The processes (7-5), (7-6), (7-7) and (7-8) shown in the figure obtain the physical address corresponding to the LBA indicated by the read command. The control component reads data from the NVM chip according to the physical address corresponding to the LBA indicated by the read command.

[0246] Fig.13 A schematic diagram showing a control component processing a read command provided by another embodiment of the present application is shown.

[0247] As another example, Fig.13 As shown, a storage block cache is also provided in the memory, and the storage block cache includes a plurality of cache units with a specified size, for example, the size of each cache unit is 1KB. When the control component processes the read command CMD1, if the L2P table entry corresponding to the LBA indicated by the read command CMD1<LBA8,PPA8> To obtain from the storage block UT1 stored in the NVM chip, obtain the LBA corresponding to the read command<LBA8,PPA8> When a command is executed, the specified size of continuous data is read from the corresponding storage block, for example, 1KB of continuous data is read from the storage block; wherein, the specified size of continuous data read from the corresponding storage block includes the L2P table entry corresponding to the LBA indicated by the read command, such as the specified large continuous data read includes<LBA6,PPA6> ,<LBA7,PPA7> ,<LBA8,PPA8> as well as<LBA9,PPA9> . Will read from the corresponding storage block<LBA6,PPA6> ,<LBA7,PPA7> ,<LBA8,PPA8> as well as<LBA9,PPA9> Stored in cache unit 1 of the storage block cache.

[0248] In response to receiving the read command CMD2, the control component queries whether the LBA address indicated by the read command CMD2 is stored in the storage block cache when processing the read command CMD2. If it is stored in the storage block cache, the physical address corresponding to the LBA address is directly read from the storage block cache without querying Table A and / or Table B. If the LBA address indicated by the read command CMD2 is not in the storage block cache, the control component will Figure 7 or Fig.11 Processing process to process the read command CMD2, see Figure 7 and Fig.11 , which will not be described in detail here. Optionally, the storage block cache is provided by HMB.

[0249] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for processing a write command of a storage device, characterized in that: include: In response to receiving a write command, the write command is parsed to obtain an LBA address, a physical address is assigned to the LBA address, a first storage unit is selected from a cache, and the LBA address and the physical address are recorded in the first storage unit; A first table and a second table stored in a memory are updated based on the LBA address and the first storage unit; wherein the first table includes a plurality of entries, each entry in the first table is used to record a physical address of a storage block in an NVM chip, the storage block is located in the NVM chip, and is used to store a specified number of L2P table entries; the second table includes a plurality of entries, each entry in the second table is used to record an address of a storage unit in a cache corresponding to an LBA address.

2. The method according to claim 1, characterized in that in, In response to parsing the LBA address and length from the write command, a physical address is allocated to the LBA address, and the LBA address, the allocated physical address corresponding to the LBA address, and the length are recorded in the first storage unit; wherein the length represents the number of consecutive LBA addresses.

3. The method according to claim 1 or 2, characterized in that in, Each entry in the first table is indexed by the storage block index recorded therein; each entry in the second table is indexed by the hash value corresponding to the LBA address.

4. The method according to claim 3, characterized in that in, Calculate a corresponding storage block index based on the LBA address, and index a first entry from the first table based on the storage block index; The physical address of the storage block recorded in the first entry in the NVM chip is updated to the index of the selected first storage unit in the cache.

5. The method according to claim 4, characterized in that Also includes: In response to indexing a first entry from the first table, a physical address of the storage block recorded in the first entry in the NVM chip is obtained, and the physical address of the storage block recorded in the first entry in the NVM chip is recorded in the first storage unit.

6. The method according to any one of claims 3 to 5, characterized in that: in, Performing a hash operation on the LBA address to obtain a hash value, and indexing a second entry from the second table based on the hash value; The second table is updated based on a status of the second entry, wherein the status of the second entry includes whether the second entry is empty or not empty.

7. The method according to claim 6, characterized in that in, In response to the second entry being empty, recording the index of the first storage unit into the second entry; In response to the second entry being non-empty, obtain the second storage unit index recorded in the second entry, determine the second storage unit in the cache based on the second storage unit index, and add a first specified field to the data structure recorded by the second storage unit, wherein the first specified field records the index of the first storage unit, and is used to represent that the hash value corresponding to the LBA address recorded by the second storage unit and the first storage unit indexes the same entry in the second table.

8. The method according to any one of claims 1 to 7, characterized in that: in, In response to receiving a first write command, the first write command is parsed to obtain a first LBA address, a physical address is assigned to the first LBA address, a third storage unit is selected from a cache, and the first LBA address and the physical address are recorded in the third storage unit; In response to receiving a second write command, the second write command is parsed to obtain a second LBA address, a physical address is assigned to the second LBA address, a fourth storage unit is selected from the cache, and the second LBA address and the physical address are recorded in the fourth storage unit; In response to the storage block indexes calculated based on the first LBA address and the second LBA address being the same, a second designated field is added to the fourth storage unit, and the second designated field records the index of the third storage unit, which is used to indicate that the LBA addresses recorded by the fourth storage unit and the third storage unit correspond to the same storage block.

9. The method according to any one of claims 1 to 8, characterized in that: The number of entries in the second table is the same as the number of storage blocks in the NVM chip, and the entries in the first table correspond one-to-one to the storage blocks in the NVM chip.

10. A control component, characterized in that: include: The control component is used to implement one of the methods according to claims 1-9.

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