Information reading method, information reading device, electronic equipment and storage medium

Abstract

The invention discloses an information reading method, an information reading device, electronic equipment and a storage medium, and the method comprises the steps: receiving input data transmitted by a serial port transceiving unit through a CPLD (Complex Programmable Logic Device), and switching on a first path between a transmitting end of the CPLD and a receiving end of the serial port transceiving unit when the input data comprises first indication information; if the first path is conducted, the main processor state information stored in the CPLD register is read through the CPLD, and the read main processor state information is sent through the serial port transceiving unit. A first path between a CPLD (Complex Programmable Logic Device) and a serial port transceiving unit is conducted through first indication information in input data, so that the CPLD sends read state information of a main processor through the serial port transceiving unit, the state information of the main processor can be read under the condition that the main processor or a communication bus goes wrong, and the reading efficiency of the main processor is improved. And debugging the main processor by a user according to the read state information of the main processor.

Description

Technical Field

[0001] The present application relates to the technical field of hardware devices, and in particular to an information reading method, an information reading device, an electronic device and a storage medium. Background Art

[0002] In some electronic devices, since the CPU (Central Processing Unit) needs to be debugged, the CPU is usually connected to a CPLD (Complex Programmable Logic Device). During the debugging process, the CPLD obtains the main processor status information, such as the CPU power-on / power-off information, the CPU usage information, etc., and stores the obtained main processor status information in its own register. The CPU reads the main processor status information stored in the CPLD register through the communication bus, and transmits it to the serial port display through the serial port transceiver for display, so that the staff can intuitively monitor the current status of the CPU.

[0003] When the CPU is not started or is hung, the serial port transceiver cannot obtain the main processor status information stored in the CPLD register, so the CPU debugging cannot be performed. Therefore, in the known technology, the CPU and BMC (English: Baseboard Management Controller, Chinese: Baseboard Management Controller) are usually used to read the CPLD register together, that is, when the CPU is not started or is hung, the BMC is used to read the CPLD register.

[0004] However, in the above information reading method, when the CPU is not started or is hung, and the BMC is not started or is hung, or when the communication bus is inaccessible, the CPLD register still cannot be read, thereby making it impossible to debug the CPU. Summary of the invention

[0005] The present application provides an information reading method, an information reading device, an electronic device and a storage medium, which are used to solve the problem in the prior art that the information stored in the CPLD register cannot be read due to problems with the main processor or the communication bus.

[0006] In a first aspect, an embodiment of the present application provides an information reading method, which is applied to a hardware device, wherein the hardware device includes a main processor, a complex programmable logic device CPLD and a serial port transceiver unit, wherein the CPLD includes a CPLD register, and the method includes:

[0007] receiving input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data includes first indication information, conducting a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit;

[0008] If the first path is connected, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit.

[0009] The information reading method disclosed in the embodiment of the present application includes receiving input data transmitted by a serial port transceiver unit through a CPLD, and when the input data includes first indication information, conducting a first path between a transmitting end of the CPLD and a receiving end of the serial port transceiver unit; if the first path is conducted, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit. Through the first indication information in the input data, the first path between the CPLD and the serial port transceiver unit is conducted, so that the CPLD sends the read main processor status information through the serial port transceiver unit, and then in the case of a problem with the main processor or the communication bus, the main processor status information can also be read, so that the user can debug the main processor according to the read main processor status information.

[0010] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected to a transmitting end of the CPLD, and an output end of the gating unit is electrically connected to a receiving end of the serial port transceiver unit;

[0011] When the input data includes the first indication information, conducting a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit includes:

[0012] When the input data includes the first indication information, the CPLD controls the conduction of a path between the first input terminal of the gating unit and the output terminal of the gating unit.

[0013] In the above embodiment, the hardware device also includes a gating unit, a first input end of the gating unit is electrically connected to the transmitting end of the CPLD, and an output end of the gating unit is electrically connected to the receiving end of the serial port transceiver unit; when the input data includes first indication information, the CPLD controls the path between the first input end of the gating unit and the output end of the gating unit to be connected, thereby making the path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit connected, so that the CPLD can send the read main processor status information through the serial port transceiver unit.

[0014] In a possible implementation, the CPLD further includes an additional CPLD register, and the reading of the main processor status information stored in the plurality of CPLD registers through the CPLD includes:

[0015] Traversing the address information of each CPLD register through the CPLD;

[0016] The main processor status information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information.

[0017] In the above embodiment, the address information of each CPLD register is traversed by the CPLD; then, the main processor status information stored in the CPLD register corresponding to the address information is read by the CPLD according to the traversed address information. Through the above method, the main processor status information stored in each CPLD register is read.

[0018] In a possible implementation manner, after receiving, by the CPLD, the input data transmitted by the serial port transceiver unit, the method further includes:

[0019] Within a preset time period, determine whether new input data is received;

[0020] If the new input data is not received, then when the input data includes the first indication information, the first path is turned on;

[0021] If the new input data is received, the input data and the new input data are used as contents of file transmission through the CPLD.

[0022] In the above embodiment, after receiving the input data transmitted by the serial port transceiver unit through the CPLD, the CPLD determines whether new input data is received within a preset time length; if no new input data is received, the first path is turned on if the input data includes the first indication information; if no new input content is received, the CPLD uses the input data and the new input data as the content of the file transmission. By determining whether new input data is input within the preset time length, the possibility that the received input data is the content of the file transmission is screened out, thereby improving the reliability of the device.

[0023] In a possible implementation, after receiving, by the CPLD, input data transmitted by the serial port transceiver unit, and before determining, by the CPLD within a preset time period, whether new input data is received, the method further includes:

[0024] Determining, by the CPLD, that preset data transmitted by the serial port transceiver unit is received;

[0025] The CPLD uses the time when the preset data is received as the starting time of the preset duration.

[0026] In the above embodiment, first, the CPLD determines that the preset data transmitted by the serial port transceiver unit is received, and then the moment when the preset data is received is used as the starting moment of the preset duration. Through the above method, it is avoided that the input data is misjudged as the content of the file transmission due to the existence of the preset data, for example, the preset data is a null character, thereby improving the reliability of the system.

[0027] In a possible implementation, the method further includes:

[0028] When the input data includes second indication information, a second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD;

[0029] If the second path is connected, the main processor status information stored in the CPLD memory is read by the main processor, and the read main processor status information is sent through the serial port transceiver unit.

[0030] In the above embodiment, when the input data includes the second indication information, the second path between the sending end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD; when the second path is connected, the main processor state information stored in the CPLD memory is read by the main processor, and the read main processor state information is sent through the serial port transceiver unit. By controlling the connection of the second path, the main processor state information stored in the CPLD memory can also be read by the main processor, thereby improving the reliability of the system.

[0031] In a possible implementation, the second input terminal of the gating unit is electrically connected to the transmitting terminal of the main processor;

[0032] When the input data includes the second indication information, conducting the second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit through the CPLD includes:

[0033] When the input data includes the second indication information, the CPLD controls the conduction of a path between the second input terminal of the gating unit and the output terminal of the gating unit.

[0034] In the above embodiment, the second input end of the gating unit is electrically connected to the transmitting end of the main processor; when the input data includes the second indication information, the CPLD controls the conduction of the path between the second input end of the gating unit and the output end of the gating unit, thereby conducting the path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit, thereby achieving conduction of the second path.

[0035] In a possible implementation manner, the input data is triggered by a user, or is generated according to a device state of the main processor.

[0036] In a second aspect, an embodiment of the present application provides an information reading device, which is applied to a hardware device, wherein the hardware device includes a main processor, a complex programmable logic device CPLD and a serial port transceiver unit, wherein the CPLD includes a CPLD register, and the device includes:

[0037] A data processing module, configured to receive input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data includes first indication information, a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit is connected;

[0038] The information transmission module is used for reading the main processor status information stored in the CPLD register through the CPLD if the first path is connected, and sending the read main processor status information through the serial port transceiver unit.

[0039] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected to a transmitting end of the CPLD, and an output end of the gating unit is electrically connected to a receiving end of the serial port transceiver unit;

[0040] The data processing module is specifically used for:

[0041] When the input data includes the first indication information, the CPLD controls the conduction of a path between the first input terminal of the gating unit and the output terminal of the gating unit.

[0042] In a possible implementation, the CPLD further includes an additional CPLD register, and the data processing module is specifically used for:

[0043] Traversing the address information of each CPLD register through the CPLD;

[0044] The main processor status information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information.

[0045] In a possible implementation, the information reading device further includes a first data identification module;

[0046] The first data identification module is used to determine whether new input data is received within a preset time period;

[0047] If the new input data is not received, then when the input data includes the first indication information, the first path is turned on;

[0048] If the new input data is received, the input data and the new input data are used as contents of file transmission through the CPLD.

[0049] In a possible implementation, the information reading device further includes a second data identification module;

[0050] The second data identification module is used to determine, through the CPLD, that preset data transmitted through the serial port transceiver unit is received;

[0051] The CPLD uses the time when the preset data is received as the starting time of the preset duration.

[0052] In a possible implementation, the data processing module is further used to:

[0053] When the input data includes second indication information, a second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD;

[0054] If the second path is connected, the main processor status information stored in the CPLD memory is read by the main processor, and the read main processor status information is sent through the serial port transceiver unit.

[0055] In a possible implementation, the second input terminal of the gating unit is electrically connected to the transmitting terminal of the main processor; then the data processing module is specifically used for:

[0056] When the input data includes the second indication information, the CPLD controls the conduction of a path between the second input terminal of the gating unit and the output terminal of the gating unit.

[0057] In a possible implementation manner, the input data is triggered by a user, or is generated according to a device state of the main processor.

[0058] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the information reading method as described in any one of the embodiments of the first aspect above is implemented.

[0059] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the information reading method as described in any one of the embodiments of the first aspect above are implemented.

[0060] For the technical effects that may be achieved by the information reading device disclosed in the second aspect, the electronic device disclosed in the third aspect, and the computer-readable storage medium disclosed in the fourth aspect, please refer to the technical effects that can be achieved by the first aspect or various possible schemes in the first aspect, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0062] Figure 1 A schematic diagram of the structure of a hardware device provided by the known technology;

[0063] Figure 2 A schematic diagram of the structure of a hardware device provided in an embodiment of the present application;

[0064] Figure 3 A flowchart of an information reading method provided in an embodiment of the present application;

[0065] Figure 4 A schematic diagram of the structure of another hardware device provided in an embodiment of the present application;

[0066] Figure 5 A schematic diagram of the structure of another hardware device provided in an embodiment of the present application;

[0067] Figure 6 A flowchart of another information reading method provided in an embodiment of the present application;

[0068] Figure 7 A flowchart of another information reading method provided in an embodiment of the present application;

[0069] Figure 8 A schematic diagram of the module structure of an information reading device provided in an embodiment of the present application;

[0070] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0071] Fig.10 A schematic diagram of a program product of an information reading method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0073] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0074] In order to facilitate the user to debug the CPU, the CPU status information needs to be displayed on a display. In the known technology, the CPU status information stored in the CPLD register is usually read by the CPU, such as Figure 1 As shown, it is a structural schematic diagram of a system for reading CPLD registers, including CPU 11, CPLD 12, serial port transceiver 13 and display 14, wherein CPU 11 is communicatively connected with CPLD 12 via a communication bus, the output end of CPU 11 is also communicatively connected with the receiving end of CPLD 12, the TX (English: Transmit, Chinese: Send) end of CPU 11 is communicatively connected with the RX (English: Receive, Chinese: Receive) end of serial port transceiver 13, the receiving end (RX) of CPU 11 is communicatively connected with the transmitting end (TX) of serial port transceiver 13, and the output end of serial port transceiver 13 is communicatively connected with the receiving end of display 14.

[0075] In a specific implementation, after the system is powered on, the CPLD 12 obtains the status information of the CPU 11 and stores the obtained CPU status information in the CPLD register. In order to enable the user to intuitively understand the CPU status information, the CPU 11 reads the CPU status information stored in the CPLD register through the communication bus according to the preset communication protocol, and transmits the read CPU status information to the receiving end (RX) of the serial port transceiver 13 through the transmitting end (TX); after the serial port transceiver 13 receives the CPU status information, it transmits it to the display 14 for display, so that the user can intuitively understand the current status of the CPU through the display and debug the CPU according to the current status.

[0076] However, if the CPU fails, for example, the CPU does not start, or the CPU hangs, the CPU cannot read the CPU status information stored in the CPLD register, and the display cannot display the CPU status information. The user cannot know the current status of the CPU in time, and cannot debug the CPU.

[0077] In order to solve the above problems, the embodiments of the present application provide an information reading method, an information reading device, an electronic device and a storage medium, so that the CPLD register can still be read when the CPU fails.

[0078] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0079] An information reading method provided in an embodiment of the present application will be described and illustrated in detail below in conjunction with the accompanying drawings.

[0080] The present application embodiment provides an information reading method, which is applied to a hardware device, such as Figure 2 As shown, it is a structural diagram of a hardware device 20, and the hardware device 20 includes a main processor 21, a CPLD 22 and a serial port transceiver unit 23, wherein the transmitting end (TX) of the serial port transceiver unit 23 is respectively connected to the receiving end (RX) of the main processor 21 and the receiving end (RX) of the CPLD 22, the receiving end (RX) of the serial port transceiver unit 23 is respectively connected to the transmitting end (TX) of the main processor 21 and the transmitting end (TX) of the CPLD 22, and the main processor 21 is also connected to the CPLD 22 through a communication bus. Specifically, the CPLD 22 includes a CPLD register, and the CPLD 22 obtains the status information of the main processor 21, and stores the obtained main processor status information in the CPLD register.

[0081] It should be noted that the main processor in the embodiment of the present application can be a CPU, and other control electronic devices, such as BMC, etc., can be used according to the actual application scenario, and the embodiment of the present application does not impose any restrictions on this; the CPLD in the embodiment of the present application can be replaced by other logic devices according to the actual application scenario, such as FPGA (English: Field Programmable Gate Array, Chinese: Field Programmable Logic Gate Array), etc., and the embodiment of the present application does not impose any restrictions on this; the CPLD in the embodiment of the present application can include one CPLD register or multiple CPLD registers, and the embodiment of the present application does not impose any restrictions on this; in addition, the serial port transceiver unit in the embodiment of the present application may include a serial port transceiver, and the embodiment of the present application does not impose any restrictions on this.

[0082] like Figure 3 FIG. 1 is a flowchart of an information reading method provided in an embodiment of the present application, the method comprising:

[0083] Step S301, receiving input data transmitted by a serial port transceiver unit through a CPLD, wherein when the input data includes first indication information, a first path between a transmitting end of the CPLD and a receiving end of the serial port transceiver unit is opened.

[0084] It should be noted that the input data in the embodiment of the present application can be characters or bytes, and the embodiment of the present application does not impose any restrictions on this.

[0085] Optionally, input data can be user triggered.

[0086] In a specific implementation, the serial port transceiver unit can also be connected to other external devices, such as a keyboard, a mouse, etc. The user can send input data to the serial port transceiver unit through the keyboard. After receiving the input data, the serial port transceiver unit transmits it to the CPLD so that the CPLD determines whether to open the first path based on the input data.

[0087] Alternatively, input data may be generated based on the device state of the host processor.

[0088] In a specific implementation, when the main processor is in a normal startup / abnormal startup state, the main processor will generate status information for characterizing normal operation / abnormal operation, generate input data based on the aforementioned status information, and transmit the input data to the CPLD through the serial port transceiver unit based on the status information generated by the main processor, so that the CPLD determines whether to turn on the first path based on the input data.

[0089] In one possible implementation, Figure 4 As shown, it is another structural schematic diagram of the hardware device 20, and the hardware device 20 also includes a gating unit 24, a first input end of the gating unit 24 is electrically connected to the transmitting end (TX) of the CPLD 22, an output end of the gating unit 24 is electrically connected to the receiving end (RX) of the serial port transceiver unit 23, and a control end of the gating unit 24 is electrically connected to a control end (English: ConTroL, abbreviated: CTL) of the CPLD 22; when the input data includes the first indication information, the path between the first input end of the gating unit 24 and the output end of the gating unit 24 is controlled by the CPLD 22, thereby conducting the path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial port transceiver unit 23, that is, conducting the first path.

[0090] For example, in Figure 4In the structure of the hardware device 20 shown, the first indication information may be "CTRL+G", and the input data received by the CPLD 22 includes the first indication information, then the CPLD 22 outputs a control signal to the control end of the selection unit 24 through the CTL end, for example, the control signal may be a high-level signal; the selection unit 24, under the control of the control signal, turns on the path between its own first input end and output end, thereby turning on the path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial port transceiver unit 23, that is, turning on the first path.

[0091] Optional, such as Figure 5 As shown, the gating unit 24 includes a gate 241, a first resistor R1 and a second resistor R2, the first input end of the gate 241 serves as the first input end of the gating unit 24, the output end of the gate 241 serves as the output end of the gating unit 24, the control end of the gate 241 is respectively connected to one end of the first resistor R1 and one end of the second resistor R2, the other end of the first resistor R1 serves as the control end of the gating unit 24, and the other end of the second resistor R2 is grounded.

[0092] In such Figure 5 In the gating unit 24 shown, the gating function of the first path is realized by the gating device 241, and the first resistor R1 and the second resistor R2 are connected to the control end of the gating device 241 to prevent the gating device 241 from being triggered by mistake, thereby improving the reliability of the system.

[0093] In the above method, the hardware device also includes a gating unit, the first input end of the gating unit is electrically connected to the transmitting end of the CPLD, and the output end of the gating unit is electrically connected to the receiving end of the serial port transceiver unit; when the input data includes the first indication information, the CPLD controls the path between the first input end of the gating unit and the output end of the gating unit to be connected, thereby making the path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit connected, so that the CPLD can send the read main processor status information through the serial port transceiver unit.

[0094] Step S302: if the first path is turned on, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit.

[0095] In a specific implementation, when the first path is turned on, all main processor status information stored in the CPLD register is read through the CPLD, and all the read main processor status information is sent to the serial port transceiver unit, so that the serial port transceiver unit sends the received main processor status information to an external device connected to the hardware device, for example, it can be sent to a display unit, so that the display unit displays the received main processor status information.

[0096] For example, Figure 4 As shown, the hardware device 20 is communicatively connected with the display unit 25. Specifically, the output end of the serial port transceiver unit 23 is communicatively connected with the input end of the display unit 25. The serial port transceiver unit 23 sends the main processor status information read by the CPLD 22 to the display unit 25 through the serial port transceiver unit 23. The display unit 25 displays the main processor status information received, so that the staff can intuitively see the main processor status information through the display unit 25, which is convenient for the staff to adjust the main processor according to the main processor status information.

[0097] Optionally, the display unit 34 may be a display or other device with a display function, and the embodiment of the present application does not impose any limitation on this.

[0098] The information reading method disclosed in the embodiment of the present application includes receiving input data transmitted by a serial port transceiver unit through a CPLD, and when the input data includes first indication information, conducting a first path between a transmitting end of the CPLD and a receiving end of the serial port transceiver unit; if the first path is conducted, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit. Through the first indication information in the input data, the first path between the CPLD and the serial port transceiver unit is conducted, so that the CPLD sends the read main processor status information through the serial port transceiver unit, and then in the case of a problem with the main processor or the communication bus, the main processor status information can also be read, so that the user can debug the main processor according to the read main processor status information.

[0099] In one possible implementation, Figure 6 As shown, the above method also includes:

[0100] Step S601, when the input data includes the second indication information, a second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD;

[0101] In one possible implementation, Figure 4 As shown, the second input terminal of the gating unit 24 is electrically connected to the transmitting terminal (TX) of the main processor 21; when the input data includes the second indication information, the CPLD 22 controls the conduction of the path between the second input terminal of the gating unit 24 and the output terminal of the gating unit 24, thereby conducting the path between the transmitting terminal (TX) of the main processor 21 and the receiving terminal (RX) of the serial port transceiver unit 23, thereby realizing the conduction of the second path.

[0102] For example, in Figure 4In the structure of the hardware device 20 shown, the second indication information may be "CTRL+U", and the input data received by the CPLD 22 includes the first indication information, then the CPLD 22 outputs a control signal to the control end of the selection unit 24 through the CTL end, for example, the control signal may be a low-level signal; the selection unit 24, under the control of the control signal, turns on the path between its own second input end and output end, thereby turning on the path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial port transceiver unit, that is, turning on the second path.

[0103] Optional, such as Figure 5 As shown, the second input end of the gate 241 serves as the second input end of the gate unit 24, and the gate function of the second path is realized through the gate 241. The first resistor R1 and the second resistor R2 are connected to the control end of the gate 241 to prevent the gate 241 from being triggered by mistake, thereby improving the reliability of the system.

[0104] In the above method, when the input data includes the first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit is turned on through the CPLD control; when the input data includes the second indication information, the second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is turned on through the CPLD control, thereby realizing the reading of the CPLD register in different ways.

[0105] Step S602: if the second path is connected, the main processor state information stored in the CPLD memory is read by the main processor, and the read main processor state information is sent through the serial port transceiver unit.

[0106] In the above method, when the input data includes the second indication information, the second path between the sending end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD; when the second path is connected, the main processor status information stored in the CPLD memory is read through the main processor, and the read main processor status information is sent through the serial port transceiver unit. By controlling the connection of the second path, the main processor status information stored in the CPLD memory can also be read through the main processor, thereby improving the reliability of the system.

[0107] In a possible implementation, if the CPLD further includes an additional CPLD register, reading the main processor status information stored in the CPLD register through the CPLD may be implemented in the following manner:

[0108] Traverse the address information of each CPLD register through CPLD;

[0109] The main processor state information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information.

[0110] In the specific implementation, Figure 4 As shown, when the first path is turned on by the gating unit 24, that is, the path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial port transceiver unit 23 is turned on, the path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial port transceiver unit 23 is disconnected. At this time, the CPLD 22 directly reads the main processor status information stored in each CPLD memory. Specifically, the CPLD 22 traverses the address information of each CPLD register, and reads the main processor status information stored in the CPLD register corresponding to the address information one by one according to each address information, until the main processor status information stored in each CPLD register in the CPLD 22 is read, and the read main processor status information is sent through the serial port transceiver unit 24.

[0111] Exemplarily, the CPLD starts from address information 0X00, reads the main processor status information stored in the CPLD register corresponding to address information 0X00, and then the CPLD adds 1 to the address information, that is, reads the main processor status information stored in the CPLD register corresponding to address information 0X01, and then the CPLD adds 1 to the address information again until the main processor status information stored in the CPLD register corresponding to the last address information is read, that is, the reading operation of the main processor status information stored in the CPLD register is completed, and then all the read main processor status information is transmitted to the display unit through the serial port transceiver unit, so that the display unit displays the main processor status information.

[0112] The above method traverses the address information of each CPLD register through the CPLD; then, the main processor status information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information. Through the above method, the main processor status information stored in each CPLD register is read.

[0113] In the specific implementation, Figure 4 As shown, when the second path is turned on by the selection unit 24, that is, the path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial port transceiver unit 23 is turned on, the path between the transmitting end (TX) of the PLD 22 and the receiving end (RX) of the serial port transceiver unit 23 is disconnected. At this time, the main processor 21 selectively reads the main processor status information stored in the memory of the CPLD 22 through the communication bus, and then the main processor 21 sends the read main processor status information to the serial port transceiver unit.

[0114] Exemplarily, the main processor can read the main processor status information stored in the CPLD register according to a preset communication protocol. For example, the main processor can read the main processor status information stored in all CPLD registers in the CPLD, the main processor can also read the main processor status information stored in any one or more CPLD registers in the CPLD, and the main processor can also read the main processor status information stored in the CPLD register corresponding to the preset address. The embodiment of the present application does not impose any restrictions on this. The main processor transmits the read main processor status information to the display unit through the serial port transceiver unit, so that the display unit displays the main processor status information.

[0115] In the specific implementation, Figure 4 As shown, when the control end (CTL) of the CPLD 22 outputs a high-level signal, the control turns on the path between the first input end and the output end of the gate 241, thereby turning on the first path between the transmitting end (TX) of the CPLD 22 and the receiving end (RX) of the serial port transceiver 231; when the control end (CTL) of the CPLD 22 outputs a low-level signal, the control turns on the path between the second input end and the output end of the gate 241, thereby turning on the second path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial port transceiver 231. If CPLD 22 fails, the control end (CTL) of CPLD 22 outputs a high impedance state to the control end of gate 241. When the control end of gate 241 receives the high impedance state, the path between the second input end and the output end of gate 241 is turned on, and then the second path between the transmitting end (TX) of main processor 21 and the receiving end (RX) of serial port transceiver 231 is turned on, so that serial port transceiver 231 is still available. The first resistor R1 is used to prevent gate 241 from being triggered by mistake.

[0116] It should be noted that, in the implementation of the present application, in the initial state, the path between the transmitting end (TX) of the main processor 21 and the receiving end (RX) of the serial port transceiver 23 can be turned on by default.

[0117] In a possible implementation, after receiving the input data transmitted by the serial port transceiver unit through the CPLD, the following processing is also performed: within a preset time length, it is determined whether new input data is received; if no new input data is received, when the input data includes the first indication information, the first path is turned on; if new input data is received, the input data and the new input data are used as the content of the file transmission through the CPLD.

[0118] In a specific implementation, when a file is transferred, there may be a situation where the content of the file transfer includes the same information as the first indication information or the second indication information. For example, the content of the file transfer is: "ALT+CTRL+G+HALLO", wherein the content of the file transfer includes the same information as the first indication information "CTRL+G", and it is easy to misjudge the content of the file transfer as input data containing the first indication information, thereby erroneously generating a corresponding control signal. Therefore, in order to avoid the occurrence of the above problem, after receiving the input data, the CPLD will determine whether there is new input data input within a preset time length. If the CPLD receives new input data within the preset time length, it means that the input data currently received by the CPLD is the content of the file transfer; if the CPLD does not receive new input data within the preset time length, and the currently received input data includes the first indication information, then the first path between the sending end of the CPLD and the receiving end of the serial port transceiver unit is turned on; if the CPLD does not receive new input data within the preset time length, and the currently received input data includes the second indication information, then the second path between the sending end of the main processor and the receiving end of the serial port transceiver unit is turned on.

[0119] Exemplarily, the preset duration may be 100ms, i.e., after receiving the input data "CTRL+G", the CPLD detects whether new input data is received within a duration of 100ms. If the CPLD receives the input data "ATE" 10ms after receiving the input data "CTRL+G", it means that the currently received input data "CTRL+G" and the newly received input data "ATE" are the contents of the file transfer, i.e., the user is currently transferring a file, and the content of the transfer is "CTRL+GATE". If the CPLD does not receive new input data 100ms after receiving the input data "CTRL+G", the first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit is turned on. Similarly, if the CPLD does not receive new input data 100ms after receiving the input data "CTRL+U", the second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is turned on.

[0120] The above method, after receiving the input data transmitted by the serial port transceiver unit through the CPLD, determines whether new input data is received within a preset time length through the CPLD; if no new input data is received, the first path is turned on when the input data includes the first indication information; if new input data is received, the input data and the new input data are used as the content of the file transmission through the CPLD. By determining whether new input data is input within the preset time length, the possibility that the received input data is the content of the file transmission is screened out, thereby improving the reliability of the device.

[0121] In one possible implementation, after receiving the input data transmitted by the serial port transceiver unit through the CPLD, the CPLD determines that the preset data transmitted by the serial port transceiver unit is received; then, the CPLD uses the time when the preset data is received as the starting time of the preset time length, and within the preset time length, the CPLD determines whether new input data is received.

[0122] It should be noted that the preset data in the embodiment of the present application may be a blank character (BLANK), and the embodiment of the present application does not impose any limitation on this.

[0123] In a specific implementation, it can be determined that the preset data is received by:

[0124] Determine whether there is preset data at the preset position through CPLD, wherein the preset position is a position after the position occupied by the input data and adjacent to the last position among the positions occupied by the input data. Exemplarily, the input data "CTRL+G" can occupy the 6th character position, and the preset position is the 7th character position; the input data "CTRL+U" can occupy the 12th character position, and the preset position is the 13th character position.

[0125] In a specific implementation, due to the external device connected to the serial port transceiver unit, the input data usually contains a null character. For example, the octopus device will cause the above phenomenon. If the null character is not processed, the CPLD will judge it as new input data, and then identify the received input data as the content of the file transfer, resulting in a misjudgment. Therefore, in order to avoid the occurrence of the above phenomenon, after receiving the input data transmitted by the serial port transceiver unit, the CPLD first determines whether the preset data transmitted by the serial port transceiver unit is received; if the preset data is received, the moment when the preset data is received is used as the starting moment of the preset time length, and within the preset time length, the CPLD determines whether new input data is received; if the preset data is not received, the moment when the input data is received is used as the starting moment of the preset time length, and within the preset time length, the CPLD determines whether new input data is received.

[0126] The above method first determines, through the CPLD, that the preset data transmitted through the serial port transceiver unit is received, and then uses the moment when the preset data is received as the starting moment of the preset duration. Through the above method, it is avoided that the input data is misjudged as the content of the file transmission due to the existence of the preset data, for example, the preset data is a null character, thereby improving the reliability of the system.

[0127] In order to further understand the solution proposed by the present invention, the following is introduced in conjunction with specific embodiments. Figure 7, is a workflow diagram of an information reading method provided in an embodiment of the present application, and the method flow specifically includes:

[0128] Step S701, receiving input data transmitted by the serial port transceiver unit through the CPLD;

[0129] Step S702, determining whether preset data transmitted by the serial port transceiver unit is received by the CPLD, if so, executing step S703, otherwise executing step S704;

[0130] Step S703, taking the time when the preset data is received as the starting time of the preset duration;

[0131] Step S704, determining whether new input data is received within a preset time period, if so, executing step S705, otherwise, executing step S706 or step S708;

[0132] Step S705, using the CPLD to transmit the input data and new input data as the contents of the file;

[0133] Step S706, when the input data includes the first indication information, controlling the path between the first input terminal of the gating unit and the output terminal of the gating unit through the CPLD;

[0134] Step S707, conducting a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit through the gating unit;

[0135] Step S708, when the input data includes the second indication information, controlling the path between the second input terminal of the gating unit and the output terminal of the gating unit through the CPLD;

[0136] Step S709, conducting a second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit through the gating unit;

[0137] Step S7010, reading the main processor status information stored in the CPLD register according to the conducted path, and sending the read main processor status information through the serial port transceiver unit.

[0138] Based on the same concept, an embodiment of the present application also provides an information reading device, which is applied to a hardware device, wherein the hardware device includes a central processing unit CPU, a complex programmable logic device CPLD and a serial port transceiver unit, wherein the CPLD includes a CPLD register. Since the device is the device in the method in the embodiment of the present application, and the principle of solving the problem by the device is similar to that of the method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0139] like Figure 8As shown, the above device includes the following modules:

[0140] The data processing module 801 is used to receive input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data includes the first indication information, the first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit is connected;

[0141] The information transmission module 802 is used to read the main processor status information stored in the CPLD register through the CPLD if the first path is connected, and send the read main processor status information through the serial port transceiver unit.

[0142] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected to a transmitting end of the CPLD, and an output end of the gating unit is electrically connected to a receiving end of the serial port transceiver unit;

[0143] The data processing module 801 is specifically used for:

[0144] When the input data includes the first indication information, the CPLD controls the conduction of a path between the first input terminal of the gating unit and the output terminal of the gating unit.

[0145] In a possible implementation, the CPLD further includes an additional CPLD register, and the data processing module 801 is specifically used for:

[0146] Traverse the address information of each CPLD register through CPLD;

[0147] The main processor state information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information.

[0148] In a possible implementation, the information reading device further includes a first data identification module;

[0149] A first data identification module, used to determine whether new input data is received within a preset time period;

[0150] If no new input data is received, when the input data includes the first indication information, the first path is turned on;

[0151] If new input data is received, the input data and the new input data are used as the contents of the file transmission through the CPLD.

[0152] In a possible implementation, the information reading device further includes a second data identification module;

[0153] A second data identification module, used for determining, through the CPLD, received preset data transmitted through the serial port transceiver unit;

[0154] The time when the preset data is received is used as the starting time of the preset time length by the CPLD.

[0155] In a possible implementation, the data processing module 801 is further configured to:

[0156] When the input data includes the second indication information, the second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD;

[0157] If the second path is connected, the main processor status information stored in the CPLD memory is read by the main processor, and the read main processor status information is sent through the serial port transceiver unit.

[0158] In a possible implementation, the second input terminal of the gating unit is electrically connected to the transmitting terminal of the main processor; then the data processing module 801 is specifically used for:

[0159] When the input data includes the second indication information, the CPLD controls the conduction of a path between the second input terminal of the gating unit and the output terminal of the gating unit.

[0160] In one possible implementation, the input data is triggered by a user or generated according to a device state of a main processor.

[0161] Based on the same concept, an embodiment of the present application also provides an electronic device. Since the electronic device is the electronic device in the method in the embodiment of the present application, and the principle of solving the problem by the electronic device is similar to that of the method, the implementation of the electronic device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0162] Refer to the following Fig. 9 An electronic device 90 according to this embodiment of the present application will be described. Fig. 9 The electronic device 90 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0163] like Fig. 9 As shown, the electronic device 90 may be in the form of a general computing device, for example, it may be a terminal device. The components of the electronic device 90 may include, but are not limited to: the at least one processor 91, the at least one memory 92 storing executable instructions of the processor 91, and a bus 93 connecting different system components (including the memory 92 and the processor 91), and the processor 91 is a processor of a smart device.

[0164] The processor 91 executes the executable instructions to implement the following steps:

[0165] Receiving input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data includes the first indication information, conducting a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit;

[0166] If the first path is turned on, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit.

[0167] In a possible implementation, the hardware device further includes a gating unit, a first input end of the gating unit is electrically connected to a transmitting end of the CPLD, and an output end of the gating unit is electrically connected to a receiving end of the serial port transceiver unit;

[0168] The processor 91 is specifically used for:

[0169] When the input data includes the first indication information, the CPLD controls the conduction of a path between the first input terminal of the gating unit and the output terminal of the gating unit.

[0170] In a possible implementation, the CPLD further includes an additional CPLD register, and the processor 91 is specifically configured to:

[0171] Traverse the address information of each CPLD register through CPLD;

[0172] The main processor state information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information.

[0173] In a possible implementation manner, the processor 91 is further configured to:

[0174] Within a preset time period, determine whether new input data is received;

[0175] If no new input data is received, when the input data includes the first indication information, the first path is turned on;

[0176] If new input data is received, the input data and the new input data are used as the contents of the file transmission through the CPLD.

[0177] In a possible implementation manner, the processor 91 is further configured to:

[0178] Determine, through the CPLD, that preset data transmitted through the serial port transceiver unit is received;

[0179] The time when the preset data is received is used as the starting time of the preset time length by the CPLD.

[0180] In a possible implementation manner, the processor 91 is further configured to:

[0181] When the input data includes the second indication information, the second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD;

[0182] If the second path is connected, the main processor status information stored in the CPLD memory is read by the main processor, and the read main processor status information is sent through the serial port transceiver unit.

[0183] In a possible implementation, the second input terminal of the gating unit is electrically connected to the transmitting terminal of the main processor;

[0184] The processor 91 is specifically used for:

[0185] When the input data includes the second indication information, the CPLD controls the conduction of a path between the second input terminal of the gating unit and the output terminal of the gating unit.

[0186] In one possible implementation, the input data is triggered by a user or generated according to a device state of a main processor.

[0187] Bus 93 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.

[0188] The memory 92 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read-only memory (ROM) 923 .

[0189] The memory 92 may also include a program / utility 925 having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include an implementation of a network environment.

[0190] The electronic device 90 may also communicate with one or more external devices 94 (e.g., keyboards, pointing devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 90, and / or may communicate with any device that enables the electronic device 90 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 95. Furthermore, the electronic device 90 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 96. As shown, the network adapter 96 communicates with other modules of the electronic device 90 via a bus 93. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 90, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0191] In some possible implementations, various aspects of the present application may also be implemented in the form of a program product, which includes a program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of each module in the information reading device according to various exemplary implementations of the present disclosure described in the above "Exemplary Method" section of this specification, for example, receiving input data transmitted by a serial port transceiver unit through a CPLD, wherein when the input data includes first indication information, a first path between a transmitting end of the CPLD and a receiving end of the serial port transceiver unit is turned on; if the first path is turned on, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit.

[0192] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0193] like Fig.10As shown, a program product 100 for an information reading method according to an embodiment of the present application is described, which can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0194] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, wherein readable program code is carried. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium other than a readable storage medium, which may transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0195] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0196] Program code for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0197] It should be noted that, although several modules or submodules of the system are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided into multiple modules to be embodied.

[0198] In addition, although the operations of the modules of the system of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in the specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some operations may be omitted, multiple operations may be combined into one operation, and / or one operation may be decomposed into multiple operations.

[0199] The present application is described above with reference to the block diagrams and / or flow charts showing the methods, devices (systems) and / or computer program products according to the embodiments of the present application. It should be understood that a block of the block diagram and / or flow chart diagram and a combination of blocks of the block diagram and / or flow chart diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer and / or other programmable data processing device to produce a machine, so that the instructions executed by the computer processor and / or other programmable data processing device create a method for implementing the functions / actions specified in the block diagram and / or flow chart block.

[0200] Accordingly, the present application may also be implemented with hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium, which has a computer-usable or computer-readable program code implemented in the medium, for use by an instruction execution system or in conjunction with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium may be any medium that may contain, store, communicate, transmit, or convey a program for use by an instruction execution system, device, or apparatus, or in conjunction with an instruction execution system, device, or apparatus.

[0201] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for reading information, characterized in that: Applied to a hardware device, the hardware device includes a main processor, a complex programmable logic device CPLD and a serial port transceiver unit, wherein the CPLD includes a CPLD register, and the method includes: receiving input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data includes first indication information, conducting a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit; If the first path is connected, the main processor status information stored in the CPLD register is read through the CPLD, and the read main processor status information is sent through the serial port transceiver unit.

2. The method according to claim 1, characterized in that The hardware device further comprises a gating unit, wherein a first input end of the gating unit is electrically connected to a transmitting end of the CPLD, and an output end of the gating unit is electrically connected to a receiving end of the serial port transceiver unit; When the input data includes the first indication information, conducting a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit includes: When the input data includes the first indication information, the CPLD controls the conduction of a path between the first input terminal of the gating unit and the output terminal of the gating unit.

3. The method according to claim 1, characterized in that The CPLD further includes an additional CPLD register, and the reading of the main processor status information stored in the CPLD register through the CPLD includes: Traversing the address information of each CPLD register through the CPLD; The main processor status information stored in the CPLD register corresponding to the address information is read through the CPLD according to the traversed address information.

4. The method according to claim 1, characterized in that After receiving the input data transmitted by the serial port transceiver unit through the CPLD, the method further includes: Within a preset time period, determine whether new input data is received; If the new input data is not received, then when the input data includes the first indication information, the first path is turned on; If the new input data is received, the input data and the new input data are used as contents of file transmission through the CPLD.

5. The method according to claim 4, characterized in that After receiving the input data transmitted by the serial port transceiver unit through the CPLD, and before determining whether new input data is received through the CPLD within a preset time period, the method further includes: Determining, by the CPLD, that preset data transmitted by the serial port transceiver unit is received; The CPLD uses the time when the preset data is received as the starting time of the preset duration.

6. The method according to claim 2, characterized in that Also includes: When the input data includes second indication information, a second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit is connected through the CPLD; If the second path is connected, the main processor status information stored in the CPLD memory is read by the main processor, and the read main processor status information is sent through the serial port transceiver unit.

7. The method according to claim 6, characterized in that The second input terminal of the gating unit is electrically connected to the transmitting terminal of the main processor; When the input data includes the second indication information, conducting the second path between the transmitting end of the main processor and the receiving end of the serial port transceiver unit through the CPLD includes: When the input data includes the second indication information, the CPLD controls the conduction of a path between the second input terminal of the gating unit and the output terminal of the gating unit.

8. The method according to any one of claims 1 to 7, characterized in that: The input data is user triggered or generated according to the device state of the main processor.

9. An information reading device, characterized in that: Applied to a hardware device, the hardware device includes a main processor, a complex programmable logic device CPLD and a serial port transceiver unit, wherein the CPLD includes a CPLD register, and the device includes: A data receiving module, configured to receive input data transmitted by the serial port transceiver unit through the CPLD, wherein when the input data includes first indication information, a first path between the transmitting end of the CPLD and the receiving end of the serial port transceiver unit is connected; The information reading module is used for reading the main processor status information stored in the CPLD register through the CPLD if the first path is connected, and sending the read main processor status information through the serial port transceiver unit.

10. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 8 is implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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