Processor, electronic device, and data communication method

Abstract

The application relates to a processor, an electronic device and a data communication method. According to the application, the communication interconnection between the processor and other processors through a network exchange device can realize data communication by using multiple groups of QP transceiving channels borne on the same port cascade transmission link. The multiple groups of QP transceiving channels have a corresponding relationship with multiple types of interactive data involved in the data communication, and the multiple types of interactive data can respectively realize independent stream transmission through the multiple groups of QP transceiving channels concurrently. Therefore, compared with the serial mode of time-division multiplexing of the port cascade transmission link for the stream transmission of the multiple types of interactive data, the transmission deadlock risk of the data communication between the processors can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data communication, and in particular to a processor, an electronic device, and a data communication method. BACKGROUND

[0002] Multiple processors can cooperatively complete a processing task with high computing power requirement such as large model training through data communication between each other. Among them, multiple processors can be connected to different physical ports of a network switching device, so that any two processors can be interconnected through a port cascade transmission link with the network switching device as a forwarding node.

[0003] The data communication between multiple processors can involve multiple types of interactive data, and the multiple types of interactive data involved in the data communication between any two processors can be time-division multiplexed on the port cascade transmission link between the two processors.

[0004] However, time-division multiplexing of multiple types of interactive data on the same port cascade transmission link can cause a flow transmission deadlock, and how to reduce the risk of transmission deadlock of data communication between processors becomes a technical problem to be solved. SUMMARY

[0005] Embodiments of the present application provide a processor, an electronic device, and a data communication method, which can reduce the risk of transmission deadlock of data communication between processors by using a QP (Queue Pair, cache queue pair) connection based on RDMA (Remote Direct Memory Access).

[0006] In an embodiment of the present application, a processor is provided, comprising:

[0007] A chip communication port, configured to implement communication interconnection of the processor with other processors through a network switching device, the communication interconnection being used for data communication between the processor and the other processors, the communication interconnection comprising a port cascade transmission link between the processor and the other processors based on port switching and forwarding of the network switching device, and the data communication comprising flow transmission of multiple types of interactive data through the port cascade transmission link;

[0008] A port driver circuit is used to create multiple sets of QP transceiver channels based on RDMA. The multiple sets of QP transceiver channels are carried in the same port cascaded transmission link between the processor and the other processors. Furthermore, the multiple types of interactive data are transmitted independently through the multiple sets of QP transceiver channels based on the correspondence between the multiple types and the multiple sets of QP transceiver channels.

[0009] In some examples, optionally, the processor further includes: a chip processing core, which is connected to the port driver circuit via the processor's on-chip bus, the on-chip bus carrying multiple bus logic channels, and the multiple bus logic channels being used to respectively implement the on-chip transmission of the multiple types of interactive data in the processor; wherein the correspondence between the multiple sets of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logic channels and the multiple types, so that the transmission connection between the streaming transmission and the on-chip transmission of the multiple types of interactive data is independent of each other.

[0010] In some examples, optionally, the multiple types include: write requests, atomic requests, read requests, and read responses; the multiple bus logical channels include: a first bus logical channel corresponding to the write request and the atomic request, a second bus logical channel corresponding to the read request, and a third bus logical channel corresponding to the read response; the multiple sets of QP transceiver channels include a set of write request QP transceiver channels corresponding to the write request and the atomic request, a set of read request QP transceiver channels corresponding to the read request, and a set of read response QP transceiver channels corresponding to the read response.

[0011] In some examples, optionally, the transmission priority of the read response QP transceiver channel is higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel.

[0012] In some examples, optionally, the multiple bus logic channels further include a fourth bus logic channel for transmitting write responses, and the port driver circuit is also configured to respond to the write request received from the chip processing core by returning the corresponding write response to the chip processing core through the fourth bus logic channel; the write response corresponding to the write request received through the write request QP receiving channel is generated internally by the other processor that initiated the write request.

[0013] In some examples, optionally, the on-chip bus is an AXI bus, and: the first bus logical channel includes at least one of the AW channel and W channel of the AXI bus; the second bus logical channel includes the AR channel of the AXI bus; the third bus logical channel includes the R channel of the AXI bus; and the fourth bus logical channel includes the B channel of the AXI bus.

[0014] In some examples, optionally, the write request QP transceiver channel includes a write request QP send channel, the read request QP transceiver channel includes a read request QP send channel, and the read response QP transceiver channel includes a read response QP send channel, wherein: the transmission order of the write request and the atomic request in the stream transmission implemented in the write request QP send channel is the same as the transmission order in the on-chip transmission implemented in the first bus logic channel; the transmission order of the read request in the stream transmission implemented in the read request QP send channel is the same as the transmission order in the on-chip transmission implemented in the second bus logic channel; and the transmission order of the read response in the stream transmission implemented in the read response QP send channel is the same as the transmission order in the on-chip transmission implemented in the third bus logic channel.

[0015] In some examples, optionally, the write request QP transceiver channel includes a write request QP receive channel, the read request QP transceiver channel includes a read request QP receive channel, and the read response QP transceiver channel includes a read response QP receive channel, wherein: the transmission order of write requests using the same other processor as a data source in the intra-chip transmission implemented on the first bus logical channel is the same as the transmission order in the streaming transmission implemented on the write request QP receive channel; the transmission order of atomic requests using the same other processor as a data source in the intra-chip transmission implemented on the first bus logical channel is decoupled from the transmission order in the streaming transmission implemented on the write request QP receive channel; the transmission order of read requests using the same other processor as a data source in the intra-chip transmission implemented on the second bus logical channel is decoupled from the transmission order in the streaming transmission implemented on the read request QP receive channel; and the transmission order of read responses using the same other processor as a data source in the intra-chip transmission implemented on the third bus logical channel is the same as the transmission order in the streaming transmission implemented on the read response QP receive channel.

[0016] In some examples, optionally, the on-chip bus is configured to perform on-chip transmission in a pre-order manner for interactive data with the same bus identifier, and: the bus identifier includes a first bus identifier applied to the first bus logical channel, and the port driver circuit is further configured to: allocate the same first bus identifier corresponding to the data source for all write requests using the same other processor as the data source; the bus identifier includes a first exclusive identifier applied to the first bus logical channel, and the port driver circuit is further configured to: allocate different first exclusive identifiers for different atomic requests, and the first exclusive identifier allocated to each atomic request is reclaimed in response to the successful operation of the atomic request; the bus identifier includes a first exclusive identifier applied to the other processor as the data source. The second exclusive identifier of the second bus logical channel, the port driver circuit is further configured to: allocate different second exclusive identifiers for different read requests, and the second exclusive identifier allocated to each read request is reclaimed in response to the successful operation of the read request; the bus identifier includes a second bus identifier applied to the third bus logical channel, and the port driver circuit is further configured to: query the second bus identifier associated with the read operation tag of the read response; wherein the read response and the corresponding read request carry the same read operation tag, and the second bus identifier is pre-allocated for the corresponding read response and associated with the corresponding read operation tag when the read request is sent to the same other processor.

[0017] Optionally, in some examples, the chip communication port is connected to a first network switching port of the network switching device, and the network switching device further includes a second network switching port connected to other chip communication ports of the other processors. The port cascading transmission link includes a first port serial link between the chip communication port and the first network switching port, a second port serial link between the second network switching port and the other chip communication ports, and a port switching link between the first network switching port and the second network switching port to implement the port switching forwarding. The multiple sets of QP transceiver channels are created between the chip communication port and the other chip communication ports, and the multiple sets of QP transceiver channels are respectively carried on two segments of the first port serial link and the second port serial link, and are bridged through corresponding multiple sets of switching channels between the first network switching port and the second network switching port.

[0018] In some examples, optionally, the processor further includes: a chip processing core, which is connected to the port driver circuit via the processor's on-chip bus, the on-chip bus carrying multiple bus logic channels, and the multiple bus logic channels being used to respectively implement the on-chip transmission of the multiple types of interactive data in the processor; the correspondence between the multiple sets of QP transceiver channels and the multiple types is matched with the correspondence between the multiple bus logic channels and the multiple types, so that the transmission connection between the streaming transmission and the on-chip transmission of the multiple types of interactive data is independent of each other; the port driver circuit is used to maintain multiple sets of first on-chip transceiver buffer queues, the multiple sets of first on-chip transceiver buffer queues being used to implement the association and connection between the multiple sets of QP transceiver channels and the multiple bus logic channels, and the association and connection being used for the transmission connection between the on-chip transmission and the streaming transmission.

[0019] In some examples, optionally, the multiple sets of first intra-chip transceiver buffer queues include multiple receive buffer queues, each of the multiple receive buffer queues being used to buffer interactive data of the same corresponding type from different data sources. The different data sources include multiple different other processors. Any one of the multiple receive buffer queues is connected to the corresponding bus logical channel among the multiple bus logical channels through a parallel FIFO queue group. The parallel FIFO queue group includes multiple FIFO queues that correspond one-to-one with different data sources. The interactive data from different data sources buffered in any one of the multiple receive buffer queues is distributed in order to the FIFO queues of the same data source in the parallel FIFO queue group by polling the lookup tables of different data sources.

[0020] In some examples, optionally, the multiple types include: write requests, atomic requests, read requests, and read responses; the multiple bus logical channels include: a first bus logical channel corresponding to the write request and the atomic request, a second bus logical channel corresponding to the read request, and a third bus logical channel corresponding to the read response; the multiple sets of QP transceiver channels include: a write request QP sending channel and a write request QP receiving channel corresponding to the write request and the atomic request, a read request QP sending channel and a read request QP receiving channel corresponding to the read request, and a read response QP sending channel and a read response QP receiving channel corresponding to the read response. The P receive channel; the multiple sets of first on-chip transceiver buffer queues include: multiple receive buffer queues corresponding to the write request QP receive channel, the read request QP receive channel, and the read response QP receive channel respectively; the receive buffer queue corresponding to the write request QP receive channel is connected to the first bus logical channel, and the receive buffer queue corresponding to the read request QP receive channel is connected to the second bus logical channel through different parallel FIFO queue groups, and the receive buffer queue corresponding to the read response QP receive channel is connected to the third bus logical channel through a FIFO queue.

[0021] In some examples, the port driver circuit may optionally also have a receive status register group corresponding to the plurality of receive buffer queues, and each register bit of the receive status register group is used to characterize whether the corresponding receive buffer queue in the plurality of receive buffer queues currently caches the polling result of the interaction data of the corresponding data source.

[0022] In some examples, the port driver circuit may optionally also have a stock status register group corresponding to the parallel FIFO queue group, each register bit of the stock status register group being used to characterize whether the corresponding FIFO queue in the parallel FIFO queue group is currently filled with interactive data from the corresponding data source, and the execution range of the lookup table excludes the data source corresponding to the FIFO queue indicated by the stock status register group as currently filled.

[0023] In some examples, optionally, any type of interactive data carries a network-global identifier to uniquely represent the data source.

[0024] Another embodiment of this application provides a multiprocessor system, the multiprocessor system including a first processor, a second processor and a network switching device, wherein the first processor is configured as the processor described in the foregoing embodiments, and the second processor includes other processors that communicate with the processor described in the foregoing embodiments.

[0025] Another embodiment of this application provides an electronic device, which includes a network switching device and at least two computing devices. One of the at least two computing devices includes a processor as described in the foregoing embodiments, and the other computing devices include other processors that communicate with the processor described in the foregoing embodiments via a communication interconnection.

[0026] Another embodiment of this application provides a data communication method applied to a processor; the processor has a chip communication port, which is used to realize communication interconnection between the processor and other processors through a network switching device. The communication interconnection is used for data communication between the processor and the other processors. The communication interconnection includes a port-cascaded transmission link between the processor and the other processors based on port switching forwarding of the network switching device. The data communication includes the streaming transmission of multiple types of interactive data through the port-cascaded transmission link. Furthermore, the data communication method includes:

[0027] Create multiple sets of QP transceiver channels based on RDMA, wherein the multiple sets of QP transceiver channels are carried in the same port cascaded transmission link between the processor and the other processors;

[0028] Based on the correspondence between the multiple types and the multiple sets of QP transceiver channels, the streaming transmission of the multiple types of interactive data is achieved independently using the multiple sets of QP transceiver channels.

[0029] In some examples, optionally, the on-chip bus of the processor carries multiple bus logical channels; the data communication method further includes: using the multiple bus logical channels to respectively realize the on-chip transmission of the multiple types of interactive data in the processor; wherein, the correspondence between the multiple sets of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the transmission connection between the streaming transmission and the on-chip transmission of the multiple types of interactive data is independent of each other.

[0030] In some examples, optionally, the multiple types include: write requests, atomic requests, read requests, and read responses; the multiple bus logical channels include: a first bus logical channel corresponding to the write request and the atomic request, a second bus logical channel corresponding to the read request, and a third bus logical channel corresponding to the read response; the multiple sets of QP transceiver channels include a set of write request QP transceiver channels corresponding to the write request and the atomic request, a set of read request QP transceiver channels corresponding to the read request, and a set of read response QP transceiver channels corresponding to the read response.

[0031] In some examples, optionally, the transmission priority of the read response QP transceiver channel is higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel.

[0032] In some examples, optionally, the plurality of bus logical channels further includes a fourth bus logical channel for transmitting write responses, and the data communication method further includes: in response to a write request generated from within the processor on the fourth bus logical channel, returning a corresponding write response through the fourth bus logical channel; the write response corresponding to the write request received through the write request QP receiving channel is generated within the other processor that initiated the write request.

[0033] In some examples, optionally, the write request QP transceiver channel includes a write request QP send channel, the read request QP transceiver channel includes a read request QP send channel, and the read response QP transceiver channel includes a read response QP send channel; the implementation of the intra-chip transmission of the multiple types of interactive data in the processor using the multiple bus logical channels includes: maintaining the transmission order of the write request and the atomic request in the stream transmission implemented on the write request QP send channel as the same as the transmission order in the intra-chip transmission implemented on the first bus logical channel; maintaining the transmission order of the read request in the stream transmission implemented on the read request QP send channel as the same as the transmission order in the intra-chip transmission implemented on the second bus logical channel; and maintaining the transmission order of the read response in the stream transmission implemented on the read response QP send channel as the same as the transmission order in the intra-chip transmission implemented on the third bus logical channel.

[0034] In some examples, optionally, the write request QP transceiver channel includes a write request QP receive channel, the read request QP transceiver channel includes a read request QP receive channel, and the read response QP transceiver channel includes a read response QP receive channel; the step of independently implementing the streaming transmission of the multiple types of interactive data based on the correspondence between the multiple types and the multiple sets of QP transceiver channels, using the corresponding QP send and QP receive channels in the multiple sets of QP transceiver channels, includes: maintaining the transmission order of the write requests using the same other processor as the data source in the on-chip transmission implemented on the first bus logic channel as the same as the transmission order in the streaming transmission implemented on the write request QP receive channel. The transmission order of atomic requests using the same other processor as a data source in the on-chip transfer implemented on the first bus logic channel is decoupled from the transmission order in the streaming transfer implemented on the write request QP receive channel; the transmission order of read requests using the same other processor as a data source in the on-chip transfer implemented on the second bus logic channel is decoupled from the transmission order in the streaming transfer implemented on the read request QP receive channel; and the transmission order of read responses using the same other processor as a data source in the on-chip transfer implemented on the third bus logic channel is kept the same as the transmission order in the streaming transfer implemented on the read response QP receive channel.

[0035] In some examples, optionally, the on-chip bus is configured to perform the on-chip transfer in a pre-order manner for interactive data with the same bus identifier, and: the bus identifier includes a first bus identifier applied to the first bus logical channel; maintaining the transmission order of write requests using the same other processor as the data source in the on-chip transfer implemented on the first bus logical channel as the same as the transmission order in the streaming transfer implemented on the write request QP receiving channel includes: assigning the same first bus identifier corresponding to the data source to all write requests using the same other processor as the data source; the bus identifier includes a first exclusive identifier applied to the first bus logical channel; deassociating the transmission order of atomic requests using the same other processor as the data source in the on-chip transfer implemented on the first bus logical channel with the transmission order in the streaming transfer implemented on the write request QP receiving channel includes: assigning different first exclusive identifiers to different atomic requests, and assigning each atomic... The first exclusive identifier requested is reclaimed in response to the successful operation of the atomic request; the bus identifier includes a second exclusive identifier applied to the second bus logical channel, and the deassociation of the transmission order of the read requests using the same other processor as the data source in the on-chip transmission implemented on the second bus logical channel with the transmission order in the streaming transmission implemented on the read request QP receiving channel includes: assigning different second exclusive identifiers to different read requests, and the second exclusive identifier assigned to each read request is reclaimed in response to the successful operation of the read request; the bus identifier includes a second bus identifier applied to the third bus logical channel, and the maintenance of the transmission order of the read responses using the same other processor as the data source in the on-chip transmission implemented on the third bus logical channel to be the same as the transmission order in the streaming transmission implemented on the read response QP receiving channel includes: assigning the same second bus identifier corresponding to the data source to all read responses using the same other processor as the data source.

[0036] In some examples, optionally, the chip communication port is connected to a first network switching port of the network switching device, and the network switching device further includes a second network switching port connected to other chip communication ports of the other processors. The port cascading transmission link includes a first port serial link between the chip communication port and the first network switching port, a second port serial link between the second network switching port and the other chip communication ports, and a port switching link between the first network switching port and the second network switching port to implement the port switching forwarding. The multiple sets of QP transceiver channels are segmented and created between the chip communication port and the other chip communication ports. Furthermore, the multiple sets of QP transceiver channels are respectively carried on two segments of the first port serial link and the second port serial link, and are bridged through corresponding multiple sets of switching channels between the first network switching port and the second network switching port.

[0037] In some examples, optionally, the processor's on-chip bus carries multiple bus logical channels, and the multiple bus logical channels are used to respectively implement the on-chip transmission of the multiple types of interactive data in the processor; the correspondence between the multiple sets of QP transceiver channels and the multiple types matches the correspondence between the multiple bus logical channels and the multiple types, so that the transmission continuity between the streaming transmission and the on-chip transmission of the multiple types of interactive data is independent of each other; the processor maintains multiple sets of first on-chip transceiver buffer queues, the multiple sets of first on-chip transceiver buffer queues are used to implement the association and connection between the multiple sets of QP transceiver channels and the multiple bus logical channels, and the association and connection are used for the transmission continuity between the on-chip transmission and the streaming transmission; the multiple sets of first on-chip transceiver buffer queues include multiple receive buffer queues, the... Each of the multiple receive buffer queues is used to buffer interactive data of the same corresponding type from different data sources. The different data sources include multiple different other processors. Any one of the multiple receive buffer queues is connected to the corresponding bus logic channel of the multiple bus logic channels through a parallel FIFO queue group. The parallel FIFO queue group includes multiple FIFO queues that correspond one-to-one with different data sources. The on-chip transmission of the multiple types of interactive data in the processor using the multiple bus logic channels includes: distributing the interactive data of different data sources buffered in any one of the multiple receive buffer queues to the corresponding FIFO queues of the same data source in the parallel FIFO queue group in order by polling a lookup table of different data sources.

[0038] In some examples, optionally, any type of interactive data carries a network-global identifier to uniquely represent the data source.

[0039] Another embodiment of this application provides an electronic device, which includes a network switching device, a processor for performing the data communication method as described in the foregoing embodiments, and other processors that communicate with the processor described in the foregoing embodiments via the network switching device based on a communication interconnection.

[0040] Based on the above embodiments of this application, the communication interconnection between processors and other processors via a network switching device can utilize multiple sets of QP transceiver channels carried on the same port cascaded transmission link to achieve data communication. These multiple sets of QP transceiver channels correspond to multiple types of interactive data involved in the data communication, and the multiple types of interactive data can be concurrently and independently streamed through the multiple sets of QP transceiver channels. Therefore, compared to the serial method of time-division multiplexing port cascaded transmission links for streaming multiple types of interactive data, the risk of transmission deadlock in data communication between processors can be reduced. Attached Figure Description

[0041] The following figures are for illustrative purposes only and do not limit the scope of this application:

[0042] Figure 1 This is a schematic diagram of the multiprocessor network structure in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of the communication interconnection structure between multiple processors in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of an extended structure for communication interconnection between multiple processors in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram illustrating the principle of data communication between multiple processors in an embodiment of this application;

[0046] Figure 5 This is a schematic diagram of a transport deadlock in a comparative example;

[0047] Figure 6 This is a schematic diagram illustrating the effect of avoiding transmission deadlock in data communication between multiple processors in this application embodiment;

[0048] Figure 7 This is a schematic diagram of an exemplary internal structure of the processor in an embodiment of this application;

[0049] Figure 8 This is a schematic diagram illustrating the extended principle of data communication between multiple processors in an embodiment of this application;

[0050] Figure 9 This is a schematic diagram of multi-source interference in a comparative example;

[0051] Figure 10 This is a schematic diagram of the optimized structure of the chip communication port of the processor in the embodiments of this application;

[0052] Figure 11 This is an exemplary flowchart illustrating the data communication method in the embodiments of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0054] Figure 1 This is a schematic diagram of the multiprocessor network structure in an embodiment of this application. Please refer to [link / reference]. Figure 1 In the embodiments of this application, the network switching device SW may include multiple network switching ports Ps_1 to Ps_N. These multiple network switching ports Ps_1 to Ps_N can be physically connected to the chip communication ports Pu_1 to Pu_N of multiple processors U_1 to U_N, respectively. Furthermore, the multiple processors U_1 to U_N can communicate and interconnect with each other through the network switching device SW. Here, N is a positive integer greater than 1. For example, the embodiments of this application use N=32 as an example for illustrative purposes. In addition, in the embodiments of this application, the network switching device SW may have the physical form of a board, or the network switching device SW may have the physical form of a complete device.

[0055] For example, in the embodiments of this application, any one of the multiple processors U_1 to U_N, processor U_i, can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit). That is, the above description of processor types in the embodiments of this application is intended to express that the communication interconnection between each processor U_i and other processors U_j through the network switching device SW is not limited by the processor type.

[0056] For example, in the embodiments of this application, multiple processors U_1 to U_N can be distributed across multiple computing devices Dev_1 to Dev_M. Furthermore, each processor U_i can be connected to any other processor U_j via a network switch SW, which can be located on the same computing device Dev_k within the multiple computing devices Dev_1 to Dev_M, or they can be located on different computing devices within the multiple computing devices Dev_1 to Dev_M. Here, M is a positive integer greater than or equal to 1, and M and N can be the same, or N can be greater than M. For example, the embodiments of this application use N=32 and M=4 as an example for illustrative illustration. In this case, the 32 processors U_1 to U_32 can be divided into 4 groups of 8 and deployed in 4 computing devices Dev_1 to Dev_4, with each group serving as a unit. It is understood that the embodiments of this application describe the distribution of multiple processors U_1 to U_N across multiple computing devices Dev_1 to Dev_M, with the aim of expressing that the communication interconnection between each processor U_i and other processors U_j through the network switching device SW is not limited by the device affiliation of the processor.

[0057] For example, in embodiments of this application, data communication between multiple processors can be implemented based on the Ethernet protocol. In this case, the network switching device may include an Ethernet switch.

[0058] Figure 2 This is a schematic diagram of the communication interconnection structure between multiple processors in an embodiment of this application. Please refer to... Figure 2 In the embodiments of this application, the communication interconnection between any one processor U_i among multiple processors U_1~U_N and other processors U_j may include a port cascaded transmission link based on port switching and forwarding of a network switching device SW. In this embodiment, an exemplary illustration is provided using i = 25 and j = 8 as an example to illustrate the communication interconnection between one processor U_i and another processor U_j.

[0059] For example, in the embodiments of this application, each network switching port Ps_i among the multiple network switching ports Ps_1 to Ps_N of the network switching device SW can be physically connected to the chip communication port Pu_i of a corresponding processor U_i. Furthermore, the physical connection between each network switching port Ps_i of the network switching device SW and the chip communication port Pu_i of the corresponding processor U_i can be referred to as the port serial link of the processor U_i in the network switching device SW. Here, i is a positive integer greater than or equal to 1 and less than or equal to N.

[0060] For example, in the embodiments of this application, data can be forwarded between any two network switching ports Ps_i and Ps_j of the network switching device SW. Furthermore, the internal forwarding link between any two network switching ports Ps_i and Ps_j of the network switching device SW can be referred to as the port switching link within the network switching device SW. Here, j is a positive integer greater than or equal to 1 and less than or equal to N, and j is different from i.

[0061] For example, to facilitate the distinction between the network switching ports Ps_i and Ps_j of different network switching devices SW that are connected to different processors U_i and U_j respectively, the embodiments of this application will refer to the network switching ports Ps_i and Ps_j as the first network switching port and the second network switching port, respectively, in the following text. The first network switching port can be considered as the network switching port in the network switching device SW that is connected to the processor U_i, as determined from the perspective of the processor U_i; and the second network switching port can be considered as the network switching port in the network switching device SW that is connected to any other processor U_j, as determined from the perspective of each processor U_i. In this case, for any processor U_i among the multiple processors U_1 to U_N, its chip communication port Pu_i can be connected to one of the corresponding network switching ports Ps_i among the multiple network switching ports Ps_1 to Ps_N of the network switching device SW; and for any other processor U_j among the multiple processors U_1 to U_N besides the processor U_i, its chip communication port Pu_i can be connected to another corresponding network switching port Ps_j among the multiple network switching ports Ps_1 to Ps_N of the network switching device SW.

[0062] For example, in order to distinguish the port serial links corresponding to different processors U_i and U_j in the network switching device SW, the embodiments of this application may refer to the port serial link between the chip communication port Pu_i of any processor U_i and the first network switching port Ps_i as the first port serial link, and refer to the port serial link between the chip communication port Pu_j of any other processor U_j and the second network switching port Ps_j as the second port serial link.

[0063] For example, in the embodiments of this application, the first port serial link and the second port serial link corresponding to any one processor U_i and any other processor U_j among the plurality of processors U_1 to U_N, and the port switching link between the first network switching port Ps_i and the second network switching port Ps_j within the network switching device SW, can be cascaded between two processors U_i and U_j into a port cascaded transmission link; and any one processor U_i and any other processor U_j among the plurality of processors U_1 to U_N can achieve communication interconnection with each other based on the port cascaded transmission link between them. Thus, each processor U_i among the plurality of processors U_1 to U_N has a port cascaded transmission link with any other processor U_j through the network switching device SW, and each processor U_i among the plurality of processors U_1 to U_N can communicate and interconnect with any other processor U_j among the plurality of processors U_1 to U_N through the network switching device SW. That is, the port cascade transmission link between any one processor U_i among multiple processors U_1~U_N and other processors U_j based on port switching and forwarding of network switching device SW may include: a first port serial link between the chip communication port Pu_i of processor U_i and the first network switching port Ps_i of network switching device SW; a second port serial link between the second network switching port Ps_j of network switching device SW and other chip communication ports Pu_j of other processors U_j; and a port switching link between the first network switching port Ps_i and the second network switching port Ps_j that implements port switching and forwarding within network switching device SW.

[0064] Figure 3 This is a schematic diagram of an extended structure for communication interconnection between multiple processors in an embodiment of this application. Please refer to... Figure 3 In the embodiments of this application, for any one of the multiple processors U_i (U_1~U_N), the network switching device SW may have multiple second network switching ports Ps_j respectively connected to multiple different other processors U_j. Furthermore, the chip communication port Pu_i of the processor U_i can achieve communication interconnection between the processor U_i and multiple different other processors U_j through the network switching device SW. For example, this application embodiment uses i = 25 and j including 8 and 16 as an example to provide an exemplary illustrated representation of the communication interconnection between one processor U_i and multiple different other processors U_j.

[0065] For example, in the embodiments of this application, the port cascade transmission link between the processor U_i and each other processor U_j interconnected via the network switching device SW can physically reuse the first port serial link between the chip communication port Pu_i of the processor U_i and the first network switching port Ps_i of the network switching device SW. That is, the port cascade transmission link between the processor U_i and each other processor U_j interconnected via the network switching device SW all include the first port serial link between the chip communication port Pu_i of the processor U_i and the first network switching port Ps_i of the network switching device SW. Furthermore, the port switching link and the second port serial link in the port cascade transmission link between the processor U_i and multiple different other processors U_j interconnected via the network switching device SW are different from each other. That is, the port switching link and the second port serial link in the port cascade transmission link between the processor U_i and multiple different other processors U_j interconnected via the network switching device SW are respectively located between the first network switching port Ps_i and different second network switching ports Ps_j, and between different second network switching ports Ps_j. Between j and other chip communication ports of different processors U_j and Pu_j.

[0066] It is understood that, in the embodiments of this application, Figure 3 The above explanation is intended to express:

[0067] Any one of the multiple processors U_1 to U_N, U_i, can achieve communication interconnection with at least one other processor U_j through the network switching device SW; and,

[0068] The port cascade transmission link that enables communication interconnection between any processor U_i among multiple processors U_1~U_N and any other processor U_j includes the first port serial link between the chip communication port Pu_i of processor U_i and the first network switching port Ps_i of network switching device SW.

[0069] Figure 4 This is a schematic diagram illustrating the principle of data communication between multiple processors in an embodiment of this application. Please refer to... Figure 4In the embodiments of this application, the chip communication port Pu_i of processor U_i can enable the processor U_i to communicate with other processors U_j through the network switching device SW. The communication interconnection between the processor U_i and any other processor U_j can be used for data communication between the processor U_i and the other processor U_j. The communication interconnection between the processor U_i and any other processor U_j can include a port cascaded transmission link between the processor U_i and the other processor U_j based on port switching forwarding of the network switching device SW. Furthermore, the data communication between the processor U_i and the other processor U_j can include multiple types of interactive data streaming transmission (e.g., Ethernet streaming transmission) through the port cascaded transmission link.

[0070] For example, in the embodiments of this application, the data communication between any one processor U_i among multiple processors U_1 to U_N and any other processor U_j can be used to realize the multi-processor computing power fusion of the processor U_i and at least one other processor U_j. For example, multi-processor computing power fusion can be applied to application scenarios with high computing power requirements, such as large model training.

[0071] For example, in the embodiments of this application, processor U_i among the multiple processors U_1 to U_N and other processors U_j can each include a chip processing core. Furthermore, data communication between processor U_i and other processors U_j, through streaming of multiple types of interactive data, can be generated by the chip processing core of processor U_i and processed by the chip processing cores of other processors U_j, or vice versa. For instance, the chip processing core may include a DMA (Direct Memory Access) module, and the initiation and processing of interactive data by the chip processing core can be performed by the DMA module.

[0072] For example, in embodiments of this application, the multiple types of interactive data may include: a write request for writing data to a specified address, an atomic request for performing an atomic operation on a specified address, a read request for reading data from a specified address, and a read response for returning read data successfully obtained from a specified address.

[0073] Exemplarily, in embodiments of this application, multiple processors U_1~U_N may each include their own port driver circuits MP_1~MP_N. The port driver circuit MP_i of any one of the processors U_i among the multiple processors U_1~U_N can be used to: create multiple sets of QP transceiver channels based on RDMA (e.g., Figure 4 As shown by the dashed arrow in the diagram, multiple sets of QP transceiver channels can be carried in the same port cascaded transmission link between the processor U_i and any other processor U_j. There is a pre-defined correspondence between the multiple sets of QP transceiver channels and the multiple types of interactive data. Furthermore, the multiple types of interactive data can be transmitted independently through the multiple sets of QP transceiver channels based on the correspondence between the multiple types and the multiple sets of QP transceiver channels. Such streaming transmission can be referred to as classified streaming transmission in the embodiments of this application.

[0074] For example, in the embodiments of this application, multiple sets of QP transceiver channels, which correspond to multiple types of interactive data and are negotiated and created by the port driver circuit MP_i of processor U_i and the other port driver circuit MP_j of processor U_j, can be located between the chip communication port Pu_i of processor U_i and the other chip communication ports Pu_j of processor U_j. Furthermore, the multiple sets of QP transceiver channels may include: a first channel segment of a first port serial link carried between the chip communication port Pu_i of processor U_i and the other chip communication ports Pu_j of processor U_j; and a second channel segment of a second port serial link carried between the chip communication port Pu_j of the other processor U_j and the second network switching port Ps_j of the network switching device SW. In this case, multiple sets of QP transceiver channels are respectively carried on two segments of the first port serial link and the second port serial link (i.e., the first channel segment and the second channel end). Multiple sets of switching channels between two network switching ports (i.e., the first network switching port Ps_i and the second network switching port Ps_j) can be bridged by the network switching device SW. Thus, multiple types of interactive data can be streamed between the processor U_i and the other processor U_j through multiple sets of QP transceiver channels.

[0075] For example, in the embodiments of this application, the different sets of QP transceiver channels carried in the same port cascaded transmission link between processor U_i and any other processor U_j can occupy different link bandwidth resources in each segment of the port serial link (first port serial link, port switching link, or second port serial link). Therefore, it is possible to support the independent concurrent streaming transmission of multiple types of interactive data in each segment of the port serial link and the port switching link.

[0076] For example, in the embodiments of this application, the chip processing core of processor U_i and the port driver circuit MP_i, as well as the chip processing core of other processor U_j and the port driver circuit MP_j, can be connected through an on-chip bus. Furthermore, the on-chip bus can be distributed in the NOC (Network on Chip) of the chip processing core, so that each core module in the chip processing core, such as the DMA module, can access the on-chip bus.

[0077] For example, in embodiments of this application, the on-chip bus bearer may include multiple bus logical channels, and the multiple bus logical channels may be used to respectively implement the on-chip transmission of multiple types of interactive data in processor U_i or other processor U_j. The on-chip transmission utilizing multiple bus logical channels respectively can be referred to as classified on-chip transmission in embodiments of this application.

[0078] For example, in an embodiment of this application, if the multiple types of interactive data include write requests, atomic requests, read requests, and read responses, then the multiple bus logic channels of the on-chip bus may include: a first bus logic channel corresponding to write requests and atomic requests, a second bus logic channel corresponding to read requests, and a third bus logic channel corresponding to read responses.

[0079] Exemplarily, in embodiments of this application, the on-chip bus of processor U_i or other processor U_j may include any AMBA (Advanced Microcontroller Bus Architecture) bus, such as APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), or AXI (Advanced eXtensible Interface). Preferably, in embodiments of this application, the on-chip bus may include an AXI bus. In this case, the first bus logical channel may include at least one of the AW channel and W channel of the AXI bus for on-chip transfer of write requests and atomic requests; the second bus logical channel includes an AR channel for on-chip transfer of read requests on the AXI bus; and the third bus logical channel may include an R channel of the AXI bus for on-chip transfer of read responses.

[0080] For example, in the embodiments of this application, the correspondence between multiple sets of QP transceiver channels (i.e., the two segments respectively carried on the first port serial link and the second port serial link) between processor U_i and any other processor U_j and multiple types of interactive data, as well as the correspondence between multiple sets of switching channels in the network switching device SW and multiple types of interactive data, can be matched with the correspondence between multiple bus logical channels and multiple types. Thus, the transmission connection between the streaming transmission of multiple types of interactive data and the on-chip transmission can be independent of each other.

[0081] For example, in the embodiments of this application, in the QP transceiver channels (including two segments respectively carried on the first port serial link or the second port serial link) carried in the same port cascaded transmission link between processor U_i and any other processor U_j, each group of QP transceiver channels corresponding to each type can include one QP transmit channel and one QP receive channel. Specifically, the QP transmit channel of processor U_i can be regarded as a QP receive channel for other processors U_j on the other end; similarly, the QP receive channel of processor U_i can be regarded as a QP transmit channel for other processors U_j on the other end.

[0082] Furthermore, in the network switching device SW, among the multiple sets of switching channels carrying the port switching link between any two network switching ports (e.g., the first network switching port Ps_i and the second network switching port Ps_j), each set of switching channels corresponding to each type may include a first switching channel and a second switching channel that are mutually reversed. Therefore, the multiple sets of QP transceiver channels between processor U_i and any other processor U_j may include multiple QP transmit channels and multiple QP receive channels that correspond to multiple types of interactive data; and the multiple sets of switching channels in the network switching device SW carrying the port switching link between any two network switching ports (e.g., the first network switching port Ps_i and the second network switching port Ps_j) may include multiple first switching channels and multiple second switching channels that correspond to multiple types of interactive data. Thus, bidirectional streaming transmission of multiple types of interactive data can be realized.

[0083] For example, in the embodiments of this application, if the multiple types of interactive data include write requests, atomic request read requests, and read responses, then the multiple QP transmission channels in the multiple sets of QP transceiver channels between processor U_i and any other processor U_j can include: a write request QP transmission channel corresponding to write requests and atomic requests and connected to the first bus logic channel, a read request QP transmission channel corresponding to read requests and connected to the second bus logic channel, and a read response QP transmission channel corresponding to read responses and connected to the third bus logic channel.

[0084] For example, in the embodiments of this application, if the multiple types of interactive data include write requests, atomic request read requests, and read responses, then the multiple QP receiving channels in the multiple sets of QP transceiver channels between processor U_i and any other processor U_j can include: a write request QP receiving channel corresponding to write requests and atomic requests and connected to the first bus logic channel, a read request QP receiving channel corresponding to read requests and connected to the second bus logic channel, and a read response QP receiving channel corresponding to read responses and connected to the third bus logic channel.

[0085] For example, in an embodiment of this application, if the multiple types of interactive data include write requests, atomic read requests, and read responses, then the multiple first switching channels in the multiple sets of switching channels between the first network switching port Ps_i and the second network switching port Ps_j inside the network switching device SW may include:

[0086] The first write request exchange channel corresponds to the write request and the atomic request. This first write request exchange channel is used to cascade two channel segments of the write request QP transmission channel that sends write requests and atomic requests from processor U_i to other processors U_j. As mentioned above, the write request QP transmission channel that sends write requests and atomic requests from processor U_i to other processors U_j is, for the other processors U_j on the other end, a write request QP reception channel that receives write requests and atomic requests from processor U_i.

[0087] A first read request exchange channel corresponds to the read request, and this first read request exchange channel is used to cascade two channel segments of the read request QP transmission channel that sends read requests from processor U_i to other processors U_j. Furthermore, as mentioned above, the read request QP transmission channel that sends read requests from processor U_i to other processors U_j is, for the other processors U_j on the other end, a read request QP reception channel that receives read requests from processor U_i; and...

[0088] The first read response exchange channel corresponds to the read response, and the first read response exchange channel is used to cascade two channel segments of the read response QP transmission channel that sends read responses from processor U_i to other processors U_j. As mentioned above, the read response QP transmission channel that sends read responses from processor U_i to other processors U_j is, for the other processors U_j on the other end, a read response QP reception channel that receives read responses from processor U_i.

[0089] For example, in an embodiment of this application, if the multiple types of interactive data include write requests, atomic request read requests, and read responses, then the multiple second switching channels in the multiple sets of switching channels between the first network switching port Ps_i and the second network switching port Ps_j inside the network switching device SW may include: a second write request switching channel that is the opposite of the first write request switching channel, a second read request switching channel that is the opposite of the first read request switching channel, and a second read response switching channel that is the opposite of the first read response switching channel.

[0090] For example, in the embodiments of this application, the processor U_i (e.g., the port driver circuit MP_i of the processor U_i) can be used to maintain multiple sets of first on-chip transceiver buffer queues connected to the on-chip bus of the processor U_i, and other processors U_j (e.g., the port driver circuit MP_j of other processors U_j) can be used to maintain multiple sets of second transceiver buffer queues connected to the on-chip bus of other processors U_j. The network switching device SW can maintain multiple sets of first switching transceiver buffer queues for the first network switching port Ps_i, and the network switching device SW can maintain multiple sets of second switching transceiver buffer queues for the second network switching port Ps_j.

[0091] For example, in the embodiments of this application, the multiple sets of first intra-chip transceiver buffer queues of processor U_i, the multiple sets of second transceiver buffer queues of other processors U_j, and the multiple sets of first switching transceiver buffer queues and multiple sets of second switching transceiver buffer queues of network switching device SW can all correspond to multiple types of interactive data, that is, the multiple sets of first intra-chip transceiver buffer queues and the multiple sets of first switching transceiver buffer queues correspond one-to-one.

[0092] For example, in the embodiments of this application, multiple sets of QP transceiver channels between processor U_i and any other processor U_j (i.e., multiple sets of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j) can be created between multiple sets of first on-chip transceiver buffer queues of processor U_i and multiple sets of second transceiver buffer queues of other processor U_j. Thus, the multiple sets of QP transceiver channels can be connected to the on-chip bus of processor U_i and other processor U_j respectively through multiple sets of first on-chip transceiver buffer queues of processor U_i and multiple sets of second transceiver buffer queues of other processor U_j.

[0093] For example, in the embodiments of this application, the multiple sets of switching channels between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device SW can be used to realize data exchange between multiple sets of first switching transceiver buffer queues maintained by the network switching device SW for the first network switching port Ps_i and multiple sets of second switching transceiver buffer queues maintained by the network switching device SW for the second network switching port Ps_j. Therefore, the multiple sets of QP transceiver channels between processor U_i and any other processor U_j (i.e., the multiple sets of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j) can use the multiple sets of first switching transceiver buffer queues maintained by the network switching device SW for the first network switching port Ps_i and the multiple sets of second switching transceiver buffer queues maintained by the network switching device SW for the first network switching port Ps_j as relay buffer nodes.

[0094] For example, in the embodiments of this application, if the multiple sets of QP transceiver channels between processor U_i and any other processor U_j include multiple QP transmit channels and multiple QP receive channels, and the multiple sets of switching channels in the network switching device SW carrying the port switching link between the first network switching port Ps_i and the second network switching port Ps_j include multiple first switching channels and multiple second switching channels, then each of the multiple sets of first intra-chip transceiver buffer queues, each of the multiple sets of first switching transceiver buffer queues, each of the multiple sets of second switching transceiver buffer queues, and each of the multiple sets of second intra-chip buffer queues can include a transmit buffer queue and a receive buffer queue. That is, the multiple sets of first intra-chip transceiver buffer queues, the multiple sets of first switching transceiver buffer queues, the multiple sets of second switching transceiver buffer queues, and the multiple sets of second intra-chip buffer queues can all include multiple transmit buffer queues and multiple receive buffer queues.

[0095] For example, in the embodiments of this application, among the multiple sets of QP transceiver channels (i.e., multiple sets of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j) between processor U_i and any other processor U_j: multiple QP transmit channels (i.e., multiple QP receive channels for any other processor U_j to receive interactive data from processor U_i) used by processor U_i to send interactive data to any other processor U_j can be created between multiple transmit buffer queues in multiple sets of first intra-chip transceiver buffer queues and multiple receive buffer queues in multiple sets of second intra-chip transceiver buffer queues. Furthermore, multiple receive buffer queues in multiple sets of first exchange transceiver buffer queues and multiple transmit buffer queues in multiple sets of second exchange transceiver buffer queues serve as relay buffer nodes. That is, interactive data is transmitted from multiple receive buffer queues in the first exchange transceiver buffer queues to multiple transmit buffer queues in the second exchange transceiver buffer queues.

[0096] For example, in the embodiments of this application, among the multiple sets of QP transceiver channels of processor U_i (i.e., multiple sets of QP transceiver channels between chip communication port Pu_i and other chip communication ports Pu_j): multiple QP receive channels for processor U_i to receive interactive data from any other processor U_j (multiple QP send channels for any other processor U_j to send interactive data to processor U_i) can be created between multiple receive buffer queues in multiple sets of first intra-chip transceiver buffer queues and multiple send buffer queues in multiple sets of second intra-chip transceiver buffer queues. Furthermore, multiple send buffer queues in multiple sets of first exchange transceiver buffer queues and multiple receive buffer queues in multiple sets of second exchange transceiver buffer queues serve as relay buffer nodes. That is, interactive data is transmitted from multiple receive buffer queues in the second exchange transceiver buffer queues to multiple send buffer queues in the first exchange transceiver buffer queues.

[0097] For example, in the embodiments of this application, among the multiple sets of switching channels between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device SW, the multiple first switching channels can be located between multiple receive buffer queues in the multiple sets of first switching transmit / receive buffer queues and multiple transmit buffer queues in the multiple sets of second switching transmit / receive buffer queues. The multiple second switching channels can be located between multiple transmit buffer queues in the multiple sets of first switching transmit / receive buffer queues and multiple receive buffer queues in the multiple sets of second switching transmit / receive buffer queues. Furthermore, the direction of data exchange between the multiple first switching channels and the multiple second switching channels between the first network switching port Ps_i and the second network switching port Ps_j of the network switching device SW is set according to the following principle: between the multiple sets of first switching transmit / receive buffer queues and the multiple sets of second switching transmit / receive buffer queues, the switching forwarding is adopted from the receive buffer queue to the transmit buffer queue.

[0098] For example, in an embodiment of this application, if the multiple sets of QP transceiver channels between processor U_i and any other processor U_j include a write request QP sending channel and a write request QP receiving channel (i.e., a set of write request QP transceiver channels), a read request QP sending channel and a read request QP receiving channel (i.e., a set of read request QP transceiver channels), and a read response QP sending channel and a read response QP receiving channel (i.e., a set of read response QP transceiver channels), and the multiple sets of switching channels carried between the first network switching port Ps_i and the second network switching port Ps_j include a first write request switching channel and a second write request switching channel (i.e., a set of write request switching channels), a first read request switching channel and a second read request switching channel (i.e., a set of read request switching channels), and a first read response switching channel and a second read response switching channel (i.e., a set of read request switching channels), then the multiple sets of first on-chip transceiver buffer queues of processor U_i, the multiple sets of first switching transceiver buffer queues maintained by network switching device SW for the first network switching port Ps_i, and the multiple sets of first switching transceiver buffer queues maintained by network switching device SW for the second network switching port Ps_j The multiple sets of second-level exchange transmit / receive buffer queues maintained by j, and the multiple sets of second-level on-chip transmit / receive buffer queues of other processors U_j, can all include a set of transmit buffer queues Wt and receive buffer queues Wr corresponding to write requests and atomic requests, a set of transmit queues Rt and receive queues Rr corresponding to read requests, and a set of transmit buffer queues Ct and receive buffer queues Cr corresponding to read responses.

[0099] For example, in an embodiment of this application, among the multiple sets of QP transceiver channels between processor U_i and other processors U_j, the write request QP transmission channel (i.e., the write request QP reception channel for other processors U_j to receive interactive data from processor U_i) used by processor U_i to send write requests and atomic requests to any other processor U_j can be connected to the first bus logic channel (e.g., the AW or W channel of AXI) in processor U_i and other processors U_j respectively at both ends. Furthermore, it can be created between the corresponding write request and atomic request transmission buffer queue Wt in the first intra-chip transceiver buffer queue group of processor U_i and the corresponding write request and atomic request reception buffer queue Wr in the second intra-chip transceiver buffer queue group of other processors U_j. Therefore, from the perspective of processor U_i, the streaming transmission process of write requests and atomic requests in the write request QP transmission channel of processor U_i (i.e., the write request QP reception channel of other processors U_j) can be exemplarily represented as "Wt → Wr".

[0100] For example, in the embodiments of this application, the write request QP sending channel of processor U_i (i.e., the write request QP receiving channel of other processors U_j at the other end) can also be a relay cache node, with the receiving cache queue Wr corresponding to the write request and atomic request in the first switching and receiving cache queue group of the network switching device SW mentioned above, and the sending cache queue Wt corresponding to the write request and atomic request in the second switching and receiving cache queue group. Furthermore, the streaming transmission process of write requests and atomic requests in the write request QP sending channel of processor U_i (i.e., the write request QP receiving channel of other processors U_j at the other end) can also include data exchange from the corresponding receiving cache queue Wr to the sending cache queue Wt in the network switching device SW. That is, from the perspective of processor U_i, the streaming transmission process of write requests and atomic requests in the write request QP sending channel of processor U_i (i.e., the write request QP receiving channel of other processors U_j at the other end) can be further represented as "Wt → Wr - exchange - Wt → Wr".

[0101] For example, in an embodiment of this application, among the multiple sets of QP transceiver channels between processor U_i and other processors U_j, the write request QP transmission channel for processor U_i to receive write requests and atomic requests from any other processor U_j (i.e., the write request QP transmission channel for other processors U_j to receive interactive data from processor U_i) can be connected to the first bus logic channel (e.g., the AW or W channel of AXI) in processor U_i and other processors U_j respectively at both ends. Furthermore, it can be created between the receive buffer queue Wr corresponding to write requests and atomic requests in the first intra-chip transceiver buffer queue group of processor U_i and the transmit buffer queue Wt corresponding to write requests and atomic requests in the second intra-chip transceiver buffer queue group of other processors U_j. Therefore, from the perspective of processor U_i, the streaming transmission process of write requests and atomic requests in the write request QP receive channel of processor U_i (i.e., the write request QP transmission channel of other processors U_j) can be exemplarily represented as "Wr <—Wt".

[0102] For example, in the embodiments of this application, the write request QP receiving channel of processor U_i (i.e., the write request QP sending channel of other processor U_j at the other end) in the network switching device SW can use the receive buffer queue Wr corresponding to the write request and atomic request in the second switching transmit and receive buffer queue group, and the send buffer queue Wt corresponding to the write request and atomic request in the second switching transmit and receive buffer queue group to realize data exchange. That is, from the perspective of processor U_i, the streaming process in the write request QP receiving channel of processor U_i (i.e., the write request QP sending channel of other processor U_j at the other end) can be further represented as "Wr<—Wt - exchange- Wr<—Wt".

[0103] For example, in an embodiment of this application, among the multiple sets of QP transceiver channels between processor U_i and other processors U_j, the read request QP transmission channel used by processor U_i to send a read request to any other processor U_j (i.e., the read request QP reception channel used by the other processor U_j to receive a read request from processor U_i) can be connected to the second bus logic channel (e.g., the AR channel of AXI) in processor U_i and the other processor U_j respectively at both ends. Furthermore, it can be created between the transmit buffer queue Rt corresponding to the read request in the first intra-chip transceiver buffer queue group of processor U_i and the receive buffer queue Rr corresponding to the read request in the second intra-chip transceiver buffer queue group of other processor U_j. Therefore, from the perspective of processor U_i, the streaming process of the read request in the read request QP transmission channel of processor U_i (i.e., the read request QP reception channel of the other processor U_j) can be represented as "Rt → Rr".

[0104] For example, in the embodiments of this application, the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the other end) can also be relayed as relay buffer nodes, namely the receiving buffer queue Rr corresponding to the read request in the first switching transceiver buffer queue group of the network switching device SW mentioned above, and the sending buffer queue Rt corresponding to the read request in the second switching transceiver buffer queue group. Furthermore, the process of streaming the read request in the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the other end) can also include data exchange from the receiving buffer queue Rr corresponding to the read request to the sending buffer queue Rt corresponding to the read request in the network switching device SW. That is, from the perspective of processor U_i, the process of streaming the read request in the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the other end) can be further expressed as "Rt → Rr - exchange - Rt → Rr".

[0105] For example, in an embodiment of this application, among the multiple sets of QP transceiver channels between processor U_i and other processors U_j, the read request QP receive channel for processor U_i to receive read requests from any other processor U_j (i.e., the read request QP receive channel for other processors U_j to send read requests to processor U_i) can be connected to the second bus logic channel (e.g., the AR channel of AXI) in processor U_i and other processors U_j respectively at both ends. Furthermore, it can be created between the receive buffer queue Rr corresponding to the read request in the first intra-chip transceiver buffer queue group of processor U_i and the send buffer queue Rt corresponding to the read request in the second intra-chip transceiver buffer queue group of other processors U_j. Therefore, from the perspective of processor U_i, the streaming transmission process of the read request in processor U_i's read request QP receive channel (i.e., the read request QP send channel of other processors U_j) can be exemplarily represented as "Rr <—Rt".

[0106] For example, in the embodiments of this application, the read request QP receiving channel of processor U_i (i.e., the read request QP sending channel of other processors U_j at the other end) can also be relayed as relay buffer nodes, namely the sending buffer queue Rt corresponding to the read request in the first switching buffer queue group of the network switching device SW mentioned above, and the receiving buffer queue Rr corresponding to the read request in the second switching buffer queue group. Furthermore, the process of streaming the read request in the read request QP receiving channel of processor U_i (i.e., the read request QP sending channel of other processors U_j at the other end) can also include data exchange from the receiving buffer queue Rr of the corresponding read request to the sending buffer queue Rt of the corresponding read request in the network switching device SW. That is, from the perspective of processor U_i, the process of streaming the read request in the read request QP sending channel of processor U_i (i.e., the read request QP receiving channel of other processors U_j at the other end) can be further expressed as "Rr<—Rt - exchange- Rr<—Rt".

[0107] For example, in an embodiment of this application, among the multiple sets of QP transceiver channels between processor U_i and other processors U_j, the read response QP transmission channel used by processor U_i to send a read response to any other processor U_j (i.e., the read response QP reception channel used by the other processor U_j to receive a read response from processor U_i) can be connected to the third bus logic channel (e.g., the R channel of AXI) in processor U_i and the other processor U_j respectively at both ends. Furthermore, it can be created between the corresponding read response transmission buffer queue Ct in the first intra-chip transceiver buffer queue group of processor U_i and the corresponding read response reception buffer queue Cr in the second intra-chip transceiver buffer queue group of other processor U_j. Therefore, from the perspective of processor U_i, the flow transmission process of the read response in the read response QP transmission channel of processor U_i (i.e., the read response QP reception channel of the other processor U_j) can be represented as "Ct → Cr".

[0108] For example, in the embodiments of this application, the read response QP sending channel of processor U_i (i.e., the read response QP receiving channel of other processors U_j at the other end) can also be relayed as relay buffer nodes, namely the receiving buffer queue Cr corresponding to the read response in the first switching transceiver buffer queue group of the network switching device SW mentioned above, and the sending buffer queue Ct corresponding to the read response in the second switching transceiver buffer queue group. Furthermore, the streaming transmission process of the read response in the read response QP sending channel of processor U_i (i.e., the read response QP receiving channel of other processors U_j at the other end) can also include data exchange from the receiving buffer queue Cr of the corresponding read response to the sending buffer queue Ct of the corresponding read response in the network switching device SW. That is, from the perspective of processor U_i, the streaming transmission process of the read response in the read response QP sending channel of processor U_i (i.e., the read response QP receiving channel of other processors U_j at the other end) can be further expressed as "Ct → Cr - exchange - Ct → Cr".

[0109] For example, in an embodiment of this application, among the multiple sets of QP transceiver channels between processor U_i and other processors U_j, the read response QP receiving channel for processor U_i to receive read responses from any other processor U_j (i.e., the read response QP receiving channel for other processors U_j to send read responses to processor U_i) can be connected to the third bus logic channel (e.g., the R channel of AXI) in processor U_i and other processors U_j respectively at both ends. Furthermore, it can be created between the receive buffer queue Cr corresponding to the read response in the first on-chip transceiver buffer queue group of processor U_i and the send buffer queue Ct corresponding to the read response in the second on-chip transceiver buffer queue group of other processors U_j. Therefore, from the perspective of processor U_i, the streaming transmission process of the read response in the read response QP receiving channel of processor U_i (i.e., the read response QP sending channel of other processors U_j) can be exemplarily represented as "Cr <—Ct".

[0110] For example, in the embodiments of this application, the read response QP receiving channel of processor U_i (i.e., the read response QP sending channel of other processors U_j at the other end) can also be relayed as relay buffer nodes, namely the sending buffer queue Ct corresponding to the read response in the first switching buffer queue group of the network switching device SW mentioned above, and the receiving buffer queue Cr corresponding to the read response in the second switching buffer queue group. Furthermore, the streaming transmission process of the read response in the read response QP receiving channel of processor U_i (i.e., the read response QP sending channel of other processors U_j at the other end) can also include data exchange from the receiving buffer queue Cr of the corresponding read response to the sending buffer queue Ct of the corresponding read response in the network switching device SW. That is, from the perspective of processor U_i, the streaming transmission process of the read response in the read response QP sending channel of processor U_i (i.e., the read response QP receiving channel of other processors U_j at the other end) can be further expressed as "Cr <—Ct - exchange - Cr <— Ct".

[0111] For example, in the embodiments of this application, each transmit buffer queue in the multiple sets of first intra-chip transmit / receive buffer queues of processor U_i (e.g., transmit buffer queue Wt corresponding to write requests and atomic requests, or transmit buffer queue Rt corresponding to read requests, or transmit buffer queue Ct corresponding to read responses) can be used to buffer interactive data of the corresponding type waiting to be transmitted from the corresponding QP transmit channel to other processors U_j; correspondingly, each receive buffer queue in the multiple sets of second intra-chip transmit / receive queues of other processors U_j (e.g., receive buffer queue Wr corresponding to write requests and atomic requests, or receive buffer queue Rr corresponding to read requests, or receive buffer queue Cr corresponding to read responses) can be used to buffer interactive data of the corresponding type successfully received from processor U_i from the corresponding QP transmit channel.

[0112] For example, in the embodiments of this application, each receive buffer queue in the multiple sets of first intra-chip transceiver buffer queues of processor U_i (e.g., receive buffer queue Wr corresponding to write requests and atomic requests, or receive buffer queue Rr corresponding to read requests, or receive buffer queue Cr corresponding to read responses) can be used to buffer interactive data of the corresponding type successfully received from other processors U_j from the corresponding QP receive channel; correspondingly, each receive buffer queue in the multiple sets of second intra-chip transceiver queues of other processors U_j (e.g., send buffer queue Wt corresponding to write requests and atomic requests, or send buffer queue Rt corresponding to read requests, or send buffer queue Ct corresponding to read responses) can be used to buffer interactive data of the corresponding type waiting to be transmitted from the corresponding QP send channel to processor U_i.

[0113] For example, in embodiments of this application, the forwarding direction of port switching forwarding between the first network switching port Ps_i and the second network switching port Ps_j may include:

[0114] A first forwarding direction from any receive buffer queue in the first exchange transmit / receive buffer queue (e.g., send buffer queue Wt corresponding to write requests and atomic requests, or send buffer queue Rt corresponding to read requests, or send buffer queue Ct corresponding to read responses) to the corresponding send buffer queue in the second exchange transmit / receive buffer queue (e.g., receive buffer queue Wr corresponding to write requests and atomic requests, or receive buffer queue Rr corresponding to read requests, or receive buffer queue Cr corresponding to read responses), that is, the first forwarding direction is in the same direction as the send direction of processor U_j and the receive direction of other processors U_j; and,

[0115] The second forwarding direction from the receive buffer queue in the second exchange transmit / receive buffer queue (e.g., receive buffer queue Wr corresponding to write requests and atomic requests, or receive buffer queue Rr corresponding to read requests, or receive buffer queue Cr corresponding to read responses) to the send buffer queue in the first exchange transmit / receive buffer queue (e.g., send buffer queue Wt corresponding to write requests and atomic requests, or send buffer queue Rt corresponding to read requests, or send buffer queue Ct corresponding to read responses) is that the first forwarding direction is in the same direction as the receive direction of processor U_j and the send direction of other processors U_j.

[0116] Therefore, in the embodiments of this application, for a stream transmission from any processor U_i to any other processor U_j, it may sequentially include segmented stream transmission from processor U_i to network switching device SW using multiple QP transmission channels in the transmission direction, segmented stream transmission within network switching device SW using multiple first switching channels in the first forwarding direction, and segmented stream transmission received by other processor U_j from network switching device SW using multiple QP transmission channels in the receiving direction; conversely, for a stream transmission received from any processor U_i from any other processor U_j, it may sequentially include segmented stream transmission from other processor U_j to network switching device SW using multiple QP transmission channels in the transmission direction, segmented stream transmission within network switching device SW using multiple second switching channels in the second forwarding direction, and segmented stream transmission received by processor U_i from network switching device SW in the receiving direction.

[0117] Based on the above embodiments of this application, processor U_i among multiple processors U_1~U_N and any other processor U_j are interconnected via a network switching device to achieve communication between the SWs. Data communication can be achieved using multiple sets of QP transceiver channels carried on the same port cascaded transmission link. The multiple sets of QP transceiver channels correspond to multiple types of interactive data involved in the data communication, and the multiple types of interactive data can be concurrently and independently streamed through the corresponding QP sending and receiving channels in the multiple sets of QP transceiver channels.

[0118] If processor U_i from multiple processors U_1 to U_N and any other processor U_j are used to stream multiple types of interactive data via a serial method through a time-division multiplexed port cascade transmission link, and if the receiver of the interactive data between processor U_i and other processors U_j experiences a processing interruption while processing a certain type of interactive data because it needs the processing results of other types of interactive data, then once this processing interruption causes a transmission blockage in the port cascade transmission link between processor U_i and other processors U_j, other types of interactive data that can clear the processing interruption will be unable to reach the receiver due to the transmission blockage, thus forming a transmission deadlock between processor U_i and other processors U_j.

[0119] Figure 5 This is a schematic diagram of a transport deadlock in a comparative example. Please refer to [link / reference]. Figure 5 Suppose that processor U_i from multiple processors U_1 to U_N and any other processor U_j are connected serially via a time-division multiplexed port cascaded transmission link to achieve streaming transmission of multiple types of interactive data, and:

[0120] At time T1, processor U_i sends a read request R_req to other processor U_j through the port cascade transmission link;

[0121] At time T2, which follows time T1, other processors U_j send several write requests W_req to processor U_i through the port cascade transmission link;

[0122] At time T3, which follows time T2, other processors U_j send the read response R_rsp corresponding to the read request R_req to processor U_i through the port cascading transmission link.

[0123] Therefore, in the flow transmission direction from other processors U_j to processor U_i via the port cascading transmission link, the read response R_rsp is queued after several write requests W_req. If processor U_i needs to wait for the read response R_rsp from other processors U_j after processing the write request W_req from other processors U_j, this waiting will cause congestion in the flow transmission direction from other processors U_j to processor U_i, for example, congestion caused by flow control mechanisms such as PFC (Priority Flow Control) or ECN (Explicit Congestion Notification). In this case, the read response R_rsp, which is queued after several write requests W_req, will cause congestion to persist because it cannot reach processor U_i, and the congestion will continue to prevent the read response R_rsp from reaching processor U_i, thus causing a transmission deadlock in the flow transmission direction from other processors U_j to processor U_i.

[0124] Figure 6 This diagram illustrates the effect of avoiding transmission deadlock in data communication between multiple processors in this embodiment of the application. Please refer to... Figure 6 Based on the embodiments of this application, in the direction of streaming transmission from other processors U_j to processor U_i via port cascading transmission links, the read response R_rsp can be transmitted concurrently with several write requests W_req independently through multiple sets of QP transceiver channels. Therefore, even if several write requests W_req cause congestion, the read response R_rsp can still reach processor U_i smoothly. Thus, after successfully processing the read response R_rsp received from other processors U_j, processor U_i (i.e., the chip processing core of processor U_i) starts processing several write requests W_req, thereby relieving the congestion of several write requests W_req.

[0125] Therefore, compared to the serial method of time-division multiplexing port cascade transmission links for streaming transmission of multiple types of interactive data, the embodiments of this application utilize multiple sets of QP transceiver channels to concurrently realize the independent streaming transmission of multiple types of interactive data, which can reduce the risk of transmission deadlock in data communication between any two of multiple processors U_1~U_N.

[0126] For example, in embodiments of this application, to further reduce the risk of transmission deadlock, the transmission priority of one set of read response QP transceiver channels among multiple sets of QP transceiver channels can preferably be higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel. That is, the transmission priority of the read response QP sending channel is preferably higher than the transmission priority of the write request QP sending channel and the read request QP sending channel; and the transmission priority of the read response QP receiving channel is preferably higher than the transmission priority of the write request QP receiving channel and the read request QP receiving channel.

[0127] Figure 7 This is a schematic diagram illustrating an exemplary internal structure of the processor in an embodiment of this application. Please refer to... Figure 7 In embodiments of this application, the port driver circuit MP_i of any processor U_i may include a port transmitting circuit TX_i and a port receiving circuit RX_i that are physically connected to or physically integrated into the chip communication port Pu_i. The port driver circuit MP_i of the processor U_i also includes a bus bridge Brag_i for physically connecting to the NOC_i of the chip processing core of the processor U_i. Multiple transmit buffer queues (e.g., transmit buffer queue Wt corresponding to write requests and atomic requests, transmit queue Rt and receive queue Rr corresponding to read requests, and transmit buffer queue Ct corresponding to read responses) in multiple sets of first on-chip transmit and receive buffer queues of the processor U_i are connected between the bus bridge Brag_i and the port transmitting circuit TX_i. In addition, multiple receive buffer queues (e.g., receive buffer queue Wr corresponding to write requests and atomic requests, receive queue Rr corresponding to read requests, and receive buffer queue Cr corresponding to read responses) in multiple sets of first on-chip transmit and receive buffer queues of the processor U_i are connected between the bus bridge Brag_i and the port receiving circuit RX_i.

[0128] For example, in the embodiments of this application, the multiple transmit buffer queues (e.g., transmit buffer queue Wt corresponding to write requests and atomic requests, transmit queue Rt and receive queue Rr corresponding to read requests, and transmit buffer queue Ct corresponding to read responses) in the multiple sets of first on-chip transmit buffer queues of the processor U_i and the port transmit circuit TX_i can be connected through a transmit arbitrator Atrtx_i, so that multiple types of interactive data cached in multiple parallel transmit buffer queues can be alternately transmitted by the port transmit circuit TX_i in a multiple-type polling manner based on the equal-weighted polling of the arbitrator Atrtx_i (i.e., the chance weight of multiple types of interactive data being polled is equal).

[0129] For example, in an embodiment of this application, in the transmission direction from chip communication port Pu_i to network switching port Ps_i of network switching device SW (i.e., the transmission direction from processor U_i to other processors U_j):

[0130] The transmission order of write requests and atomic requests in the stream transmission implemented by the write request QP transmission channel "Wt->Wr" can be the same as the transmission order of write requests and atomic requests in the on-chip transmission implemented by the first bus logic channel (e.g., at least one of AXI's AW channel and W channel), that is, write requests and atomic requests in the transmission direction are transmitted in order in the write request QP transmission channel "Wt->Wr".

[0131] The transmission order of read requests in the stream transmission implemented by the read request QP transmission channel “Rt->Rr” is the same as the transmission order of read requests in the on-chip transmission implemented by the second bus logic channel (e.g., AXI’s AR channel). That is, read requests in the transmission direction are transmitted in the order-preserving manner in the read request QP transmission channel “Rt->Rr”.

[0132] The transmission order of read responses in the streaming transmission implemented via the read response QP transmission channel "Ct->Cr" is the same as the transmission order of read responses in the on-chip transmission implemented via the third bus logic channel (e.g., AXI's Ar channel). That is, read responses in the transmitting direction are transmitted in order via the read response QP transmission channel "Ct->Cr". Each read response is generated in response to a previously received read request, and the generation order of the read responses does not necessarily have to be the same as the receiving order of the read requests. Furthermore, the transmission order of read responses in the on-chip transmission implemented via the third bus logic channel (e.g., AXI's R channel) does not necessarily have to be consistent with the receiving order of the read requests. Therefore, the transmission order of read responses in the streaming transmission implemented via the read response QP transmission channel can be associated with the receiving order of the corresponding read requests.

[0133] There is no order requirement between the stream transmissions implemented by the write request QP sending channel “Wt->Wr”, the read request QP sending channel “Rt->Rr”, and the read response QP sending channel “Ct->Cr”.

[0134] For example, in an embodiment of this application, in the receiving direction from the network switching port Ps_i of the network switching device SW to the chip communication port Pu_i (i.e., the transmission direction from other processor U_j to processor U_i):

[0135] Write requests using the same other processor U_j as the data source are transmitted in the same order in the on-chip transmission implemented on the first bus logical channel (e.g., at least one of AXI's AW channel and W channel) as in the stream transmission implemented on the write request QP receive channel "Wr<-Wt". That is, write requests in the receive direction are transmitted in the same order on the first bus logical channel (e.g., at least one of AXI's AW channel and W channel).

[0136] The transmission order of atomic requests that use the same other processor U_j as the data source in the on-chip transmission implemented on the first bus logical channel (e.g., at least one of AXI's AW channel and W channel) is related to the transmission order in the stream transmission implemented on the write request QP receive channel "Wr<-Wt". That is, since different atomic requests usually have different operation addresses in processor U_i, atomic requests in the receive direction can be transmitted out of order on the first bus logical channel (e.g., at least one of AXI's AW channel and W channel).

[0137] The transmission order of read requests that use the same other processor U_j as the data source in the on-chip transmission implemented on the second bus logic channel (e.g., AXI's AR channel) is related to the transmission order in the stream transmission implemented on the read request QP receive channel "Rr<-Rt". That is, since different read requests usually have different access addresses in the processor U_i, read requests in the receive direction can be transmitted out of order on the second bus logic channel (e.g., AXI's AR channel).

[0138] For read responses using the same other processor U_j as the data source, the transmission order in the on-chip transmission implemented on the third bus logic channel (e.g., AXI's R channel) is the same as the transmission order in the stream transmission implemented on the read response QP receive channel "Cr<—Ct". That is, read responses in the receive direction are transmitted in order on the third bus logic channel (e.g., AXI's R channel).

[0139] For example, in an embodiment of this application, the on-chip bus is configured to perform on-chip transmission of interactive data with the same bus identifier in an order-preserving manner. In this case:

[0140] In order to ensure that write requests in the receive direction are transmitted in order on the first bus logical channel (e.g., at least one of the AW and W channels of AXI), the bus identifier of the on-chip bus may include a first bus identifier applied to the first bus logical channel, and the port driver circuit MP_i of the processor U_i may also be used to: assign the same first bus identifier corresponding to the data source for all write requests that use the same other processor U_j as the data source, that is, to assign the first bus identifier at the granularity of the data source.

[0141] To enable out-of-order transmission of atomic requests in the receive direction on the first bus logical channel (e.g., at least one of the AW and W channels of AXI), the bus identifier of the on-chip bus of the processor U_i may include a first exclusive identifier applied to the first bus logical channel. The first exclusive identifier and the first bus identifier may belong to different identifier sequences or different identifier pools. The port driver circuit MP_i of the processor U_i (e.g., bus bridge BRG_i) may also be used to: allocate different first exclusive identifiers for different atomic requests, that is, allocate first exclusive identifiers at the granularity of atomic requests, and the first exclusive identifier allocated to each atomic request may be reclaimed in response to the successful operation of the atomic request.

[0142] For example, in an embodiment of this application, the port driver circuit MP_i of the processor U_i (e.g., bus bridge Brg_i) may include a first identifier generator Gw. The first identifier generator Gw may be located between the write request QP receive channel "Wr<—Wt" (i.e., the receive buffer queue Wr corresponding to the write request and the atomic request in multiple sets of first on-chip transceiver buffer queues) and the first bus logic channel (e.g., at least one of the AW channel and W channel of AXI). The first identifier generator Gw may generate a first bus identifier allocated at the data source granularity for each write request and a first exclusive identifier allocated at the atomic request granularity for each atomic request, based on the type of interactive data cached in the receive buffer queue Wr.

[0143] For example, in an embodiment of this application, in order to enable out-of-order transmission of read requests in the receiving direction on the second bus logic channel (e.g., the AR channel of AXI), the bus identifier of the processor U_i may further include a second exclusive identifier applied to the second bus logic channel, and the port driver circuit MP_i (e.g., the bus bridge Brg_i) of the processor U_i may further be used to: allocate different second exclusive identifiers for different read requests, that is, allocate the second exclusive identifier at the granularity of read requests, and the second exclusive identifier allocated to each read request is reclaimed in response to the successful operation of the read request (e.g., generating a read response returned in the sending direction corresponding to the read request).

[0144] For example, in an embodiment of this application, the port driver circuit MP_i of the processor U_i (e.g., bus bridge Brg_i) may further include a second identifier generator Gr, which may be located between the read request QP receive channel “Rr<—Rt” (i.e., the receive buffer queue Rr corresponding to the read request in multiple sets of first on-chip transmit / receive buffer queues) and the first bus logic channel (e.g., the AR channel of AXI), and the second identifier generator Gr may generate a second exclusive identifier allocated at the granularity of the read request for each read request.

[0145] For example, in an embodiment of this application, in order to achieve ordered transmission of read responses in the receiving direction on the third bus logic channel (e.g., the R channel of AXI), the bus identifier of the on-chip bus of the processor U_i may include a second bus identifier applied to the third bus logic channel. Furthermore, the port driver circuit MP_i (e.g., bus bridge Brg_i) of the processor U_i may also be used to: query the second bus identifier associated with the read operation tag of the read response, and the read response may be transmitted on-chip on the third bus logic channel using the queried second bus identifier. In this case, any read response may carry the same read operation tag as the corresponding read request. The second bus identifier is pre-allocated for the read response corresponding to the read request when a read request is sent to the same other processor U_j (i.e., the data source of the read response), and is associated with the read operation tag used by the read request and the corresponding read response. Therefore, whenever a read response responding to an issued read request is received, the pre-determined second bus identifier can be directly hit using the read operation tag.

[0146] For example, in the embodiments of this application, the port driver circuit MP_i of the processor U_i (e.g., the bus bridge Brg_i) may further include a third identifier generator Gc. The third identifier generator Gc may be located between the read response QP receive channel “Cr<—Ct” (i.e., the receive buffer queue Cr corresponding to the read response in multiple sets of first on-chip transceiver buffer queues) and the third bus logic channel (e.g., the R channel of AXI). Furthermore, the third identifier generator Gc may pre-generate a second bus identifier for each read request for the corresponding read response, which is allocated at the data source granularity and associated with the read operation tag of the read request and the corresponding read response.

[0147] For example, in the embodiments of this application, the multiple bus logic channels of the on-chip bus of the processor U_i may further include a fourth bus logic channel for transmitting write responses. For example, the fourth logic bus channel may include the B channel of AXI. Furthermore, the port driver circuit MP_i of the processor U_i (e.g., the bus bridge Brg_i) may also be used to respond to a write request received from the NOC_i of the chip processing core by returning a corresponding write response to the NOC_i of the chip processing core through the fourth bus logic channel. That is, the port driver circuit MP_i of the processor U_i (e.g., the bus bridge Brg_i) may be configured to predict the success result of the write request in the transmission direction.

[0148] For example, in the embodiments of this application, the write response corresponding to the write request received through the write request QP receiving channel "Wr<-Wt" can be generated internally by the other processor U_j that initiated the write request. That is, the other processor U_j can be configured as the successful result of the issued write request, and there is no need for the chip processing core of processor U_i to generate the corresponding write response and send it to the other processor U_j that initiated the write request in the sending direction.

[0149] Figure 8 This is a schematic diagram illustrating the extended principle of data communication between multiple processors in an embodiment of this application. Please refer to... Figure 8 If any one of the multiple processors U_1 to U_N, U_i, communicates with multiple different other processors U_j through a network switching device SW, then the first port serial link between the processor U_i and the first network switching port Ps_i of the network switching device SW can be multiplexed to carry multiple sets of QP transceiver channels between the processor U_i and the multiple different other processors U_j on the processor U_i side. Furthermore, it can be multiplexed to implement a segment of streaming transmission between the processor U_i and the multiple different other processors U_j on the first port serial link. In this case, each receive buffer queue of the multiple sets of first on-chip transceiver buffer queues of the processor U_i will buffer interactive data of the same corresponding type from different data sources (i.e., different other processors U_j). That is, there is a situation of multi-source interference in the port driver circuit MP_i (e.g., bus bridge Brag_i) of the processor U_i in the receiving direction, where multiple data sources of the same type of interactive data exist.

[0150] Figure 9 This is a schematic diagram of multi-source interference in a comparative example. Please refer to [link / reference]. Figure 9 The port driver circuit MP_i of processor U_i (e.g., bus bridge Brg_i) may also include a corresponding FIFO (First Input First Output) queue for each type of interactive data. Furthermore, the received data from different data sources (i.e., different other processors U_j) buffered in each of the multiple sets of first on-chip transmit / receive buffer queues of processor U_i are sequentially assigned bus identifiers through their respective FIFO queues and sent to the corresponding bus logic channel of the on-chip bus of processor U_i. That is:

[0151] The write request QP receive channel “Wr<—Wt” (i.e., the receive buffer queue Wr corresponding to the write request and atomic request in multiple sets of first on-chip transmit / receive buffer queues) and the first identifier generator Gw or the first bus logic channel (e.g., at least one of AXI’s AW channel and W channel) may have a write request FIFO queue corresponding to the write request and atomic request. Furthermore, write requests and atomic requests from different data sources (i.e., different other processors U_j) are sent to the first bus logic channel (e.g., at least one of AXI’s AW channel and W channel) one by one after being assigned a bus identifier through the write request FIFO queue in the order they arrive at the receive buffer queue Wr of the processor U_i.

[0152] Between the read request QP receive channel “Rr<—Rt” (i.e., the receive buffer queue Rr corresponding to the read request in multiple sets of first on-chip transmit / receive buffer queues) and the second identifier generator Gr or the second bus logic channel (e.g., AXI’s AR channel), there can be a read request FIFO queue corresponding to the write request. Furthermore, read requests from different data sources (i.e., different other processors U_j) are sent to the second bus logic channel (e.g., AXI’s AR channel) one by one after being assigned a bus identifier through the read request FIFO queue in the order they arrive at the receive buffer queue Rr of the processor U_i.

[0153] The read response QP receive channel “Cr<—Ct” (i.e., the receive buffer queue Cr corresponding to the read response in multiple sets of first on-chip transmit / receive buffer queues) and the third identifier generator Gc or the third bus logic channel (e.g., AXI’s R channel) can have a read response FIFO queue corresponding to the write request. Furthermore, read responses from different data sources (i.e., different other processors U_j) are sent to the third bus logic channel (e.g., AXI’s R channel) one by one after being assigned a bus identifier through the read response FIFO queue in the order they arrive at the receive buffer queue Cr of the processor U_i.

[0154] In this situation, if the chip processing core of processor U_i processes a certain type of interactive data from any data source slowly, it will affect the efficiency of the same type of interactive data from other data sources entering the on-chip bus of processor U_i.

[0155] Figure 10 This is a schematic diagram of the optimized structure of the chip communication port of the processor in an embodiment of this application. Please refer to... Figure 10In the embodiments of this application, among the multiple receive buffer queues of the multiple sets of first on-chip transmit / receive buffer queues of processor U_i, any one or at least one receive buffer queue can be connected to the corresponding bus logic channel in the multiple bus logic channels through a corresponding parallel FIFO queue group. The number of FIFO queues included in a parallel FIFO queue group corresponding to any receive buffer queue can be the same as the total number of other processors U_j (e.g., N-1). The number of FIFO queues in a parallel FIFO queue group corresponding to any receive buffer queue can correspond to different data sources (i.e., different other processors U_j). Furthermore, the interactive data cached in the receive queue from different data sources (i.e., different other processors U_j) can be distributed in order to the FIFO queues of the corresponding parallel FIFO queue group corresponding to the same data source (i.e., the same other processor U_j) by polling the look-up table (LUT) of different data sources (i.e., different other processors U_j). Among them, the interaction data distributed in order to multiple FIFO queues in the parallel FIFO queue group can be assigned bus identifiers and sent to the corresponding bus logic channel of the on-chip bus based on the equal-weighted polling method of different data sources (i.e., different other processors U_j) by the channel arbitrator.

[0156] Based on the above embodiments, interactive data of the same type from different data sources (i.e., different other processors U_j) can be independently cached in a parallel FIFO queue group by combining a polled LUT. Furthermore, the interactive data of the same type independently cached in the parallel FIFO queue group can be sent to the corresponding bus logic channel of the on-chip bus in a polling manner with equal weight (i.e., equal weight). Therefore, even if the chip processing core of processor U_i processes a certain type of interactive data from any data source slowly, it will not affect the efficiency of interactive data of the same type from other data sources entering the on-chip bus of processor U_i.

[0157] For example, in an embodiment of this application, the write request QP receive channel "Wr<—Wt" (i.e., the receive buffer queue Wr corresponding to the write request and atomic request in multiple sets of first on-chip transmit / receive buffer queues) and the first identifier generator Gw or the first bus logic channel (e.g., at least one of AXI's AW channel and W channel) may have a parallel FIFO queue group corresponding to the write request and atomic request. The parallel FIFO queue group may include multiple FIFO queues with the same total number (e.g., N-1) of other processors U_j. The multiple FIFO queues in the parallel FIFO queue group may correspond to different data sources (i.e., different other processors U_j). Furthermore, the multiple FIFO queues in the parallel FIFO queue group can be connected to the first identifier generator Gw or the first bus logic channel (e.g., at least one of AXI's AW channel and W channel) through the first channel arbitrator Atrw. In this scenario, write requests and atomic requests cached in the receive queue Wr from different data sources (i.e., different other processors U_j) can be distributed in order to the corresponding parallel FIFO queue group's FIFO queues corresponding to the same data source (i.e., the same other processor U_j) by polling the LUTs of the different data sources (i.e., different other processors U_j). Furthermore, write requests and atomic requests distributed in order to multiple FIFO queues in the corresponding parallel FIFO queue group via the LUTs can be transmitted through the first channel arbitrator Atrw to the first identifier generator Gw to assign corresponding bus identifiers in a polling manner of different data sources (i.e., different other processors U_j), and then sent to the first bus logic channel (e.g., at least one of AXI's AW and W channels).

[0158] For example, in an embodiment of this application, the read request receiving channel "Rr<—Rt" (i.e., the receive buffer queue Rr corresponding to the read request in multiple sets of first on-chip transceiver buffer queues) and the second identifier generator Gr or the second bus logic channel (e.g., AXI's AR channel) may have a parallel FIFO queue group corresponding to the write request. This parallel FIFO queue group may include multiple FIFO queues with the same total number (e.g., N-1) of other processors U_j. The multiple FIFO queues in this parallel FIFO queue group may correspond to different data sources (i.e., different other processors U_j). Furthermore, the multiple FIFO queues in this parallel FIFO queue group can be connected to the second identifier generator Gr or the second bus logic channel (e.g., AXI's AR channel) through the second channel arbitrator Atrr. In this case, read requests buffered in the receive queue Rr from different data sources (i.e., different other processors U_j) can be distributed in order to the corresponding parallel FIFO queue group corresponding to the same data source (i.e., the same other processor U_j) by polling the LUTs of different data sources (i.e., different other processors U_j). Furthermore, read requests that are distributed in order to multiple FIFO queues in the corresponding parallel FIFO queue group by the LUT can be transmitted to the second identifier generator Gr to allocate the corresponding bus identifier by the second channel arbitrator Atrr in the manner of polling different data sources (i.e. different other processors U_j), and then sent to the second bus logic channel (e.g., AXI's AR channel).

[0159] For example, in the embodiments of this application, the port driver circuit MP_i of the processor U_i (e.g., bus bridge Brg_i) can also maintain a corresponding receive status register group Reg_valid for any receive buffer queue (e.g., receive buffer queue Wr or Rr). The receive status register group Reg_valid can include register bits that are the same as the total number of data sources or the total number of other processors U_j (e.g., N-1). The multiple register bits of the receive status register group Reg_valid correspond to different total numbers of data sources or other processors U_j. Furthermore, each register bit of the receive status register group Reg_valid is used to characterize whether the corresponding receive buffer queue currently caches the polling result of the interaction data of the data source corresponding to the register bit. In this case, if the currently polled data source (i.e., other processor U_j) indicates that the corresponding register bit of the receive status register group Reg_valid is valid (i.e., there is currently cached interactive data of the corresponding type of the data source), then one interactive data of the corresponding type cached by the data source (i.e., other processor U_j) can be transferred through LUT to the FIFO queue of the corresponding parallel FIFO queue group corresponding to the same data source (i.e., the same other processor U_j); otherwise, jump to the next data source (i.e., another other processor U_j).

[0160] For example, in the embodiments of this application, the port driver circuit MP_i (e.g., bus bridge Brg_i) of processor U_i can also maintain a corresponding stock status register group Reg_full for any parallel FIFO queue group corresponding to any receive buffer queue (e.g., receive buffer queue Wr or Rr). The stock status register group Reg_full may include register bits that are the same as the total number of data sources or the total number of other processors U_j (e.g., N-1). The multiple register bits of the stock status register group Reg_full correspond to different total numbers of data sources or other processors U_j. Furthermore, each register bit of the stock status register group Reg_full is used to characterize whether the FIFO queue in the parallel FIFO queue group corresponding to the same data source (i.e., other processors U_j) is currently filled with the corresponding type of interactive data from that data source. In this scenario, when an interaction data of the corresponding type cached by any data source (i.e., another processor U_j) is triggered by a LUT transfer, the corresponding register bit in the Reg_full inventory status register group can be used to determine whether the FIFO queue corresponding to the same data source (i.e., the same other processor U_j) in the parallel FIFO queue group is currently full. Specifically, if the FIFO queue corresponding to any data source (i.e., another processor U_j) in the parallel FIFO queue group is currently full, the currently triggered LUT transfer is abandoned; if the FIFO queue corresponding to any data source (i.e., another processor U_j) in the parallel FIFO queue group is not currently full, the currently triggered LUT transfer is allowed to execute. That is, the execution scope of the LUT excludes the data source (i.e., another processor U_j) corresponding to the FIFO queue indicated as currently full by the Reg_full inventory status register group.

[0161] For example, in the embodiments of this application, since the data volume of the read response is small and has little impact on other types of interactive data, the read response QP receive channel "Cr<—Ct" (i.e., the receive buffer queue Cr corresponding to the read response in multiple sets of first on-chip transceiver buffer queues) and the third identifier generator Gc or the third bus logic channel (e.g., the R channel of AXI) can have only one FIFO queue set for the corresponding read response. In this case, read responses from different data sources (i.e., different other processors U_j) can be sent to the third bus logic channel (e.g., the R channel of AXI) one by one after being assigned bus identifiers according to the order in which they arrive at the receive buffer queue Cr of the processor U_i, or they can be sent to the FIFO in a round-robin manner to be reordered, and the read responses from different data sources (i.e., different other processors U_j) can be sent to the third bus logic channel (e.g., the R channel of AXI) one by one after being assigned bus identifiers according to the round-robin reordering.

[0162] For example, in the embodiments of this application, multiple processors U_1 to U_N can be assigned a unique global identifier (Global ID). Any type of interactive data carries a global identifier for uniquely representing the data source of the interactive data. Furthermore, the port driver circuit MP_i (e.g., bus bridge Brg_i) of processor U_i can identify the data source of the interactive data (i.e., the processor U_j that generated the interactive data) through the global identifier carried by the interactive data.

[0163] In another embodiment of this application, an electronic device is provided, which may include a network switching device and at least two computing devices. One of the at least two computing devices may include a processor U_i as described in the foregoing embodiments, and the other computing devices may include other processors U_j that perform data communication with the processor U_i based on communication interconnection.

[0164] In another embodiment of this application, a multiprocessor system is provided, which may include a first processor, a second processor, and a network switching device, wherein the first processor is configured as processor U_i as described in the foregoing embodiments, and the second processor may include other processors U_j that perform data communication based on communication interconnection with processor U_i.

[0165] Figure 11 This is an exemplary flowchart illustrating the data communication method in an embodiment of this application. Please refer to... Figure 11In another embodiment of this application, a data communication method is provided. This data communication method can be applied to a processor having a chip communication port. The chip communication port is used to enable communication interconnection between the processor and other processors via a network switching device. This communication interconnection is used for data communication between the processor and other processors. The communication interconnection between the processor and other processors may include a port cascaded transmission link between the processor and other processors based on port switching forwarding of the network switching device. The data communication between the processor and other processors may include the streaming transmission of multiple types of interactive data through the port cascaded transmission link. Furthermore, the data communication method may include:

[0166] S1110: Create multiple sets of QP transceiver channels based on RDMA, wherein the multiple sets of QP transceiver channels are carried in the same port cascade transmission link between the processor and other processors.

[0167] For example, in an embodiment of this application, the chip communication port of the processor applying the data communication method is connected to the first network switching port of the network switching device. The network switching device also includes a second network switching port connected to other chip communication ports of other processors. The port cascading transmission link between the processor applying the data communication method and other processors may include: a first port serial link between the chip communication port of the processor and the first network switching port of the network switching device, a second port serial link between the second network switching port of the network switching device and other chip communication ports of other processors, and a port switching link between the first network switching port and the second network switching port of the network switching device to realize port switching forwarding. In this case, the data communication method via S1110 may include creating multiple sets of QP transceiver channels between the chip communication port of the processor and other chip communication ports of other processors. The multiple sets of QP transceiver channels created by S1110 are segmented and carried on a first port serial link between the chip communication port of the processor and the first network switching port of the network switching device, and a second port serial link between other chip communication ports of other processors and the second network switching port of the network switching device. Furthermore, the two channel segments of the multiple sets of QP transceiver channels created by S1110 can be bridged by corresponding multiple sets of switching channels between the first network switching port and the second network switching port of the network switching device.

[0168] S1130: Based on the correspondence between multiple types and multiple sets of QP transceiver channels, multiple sets of QP transceiver channels are used to independently realize the streaming transmission of multiple types of interactive data.

[0169] Based on the data communication method described in the embodiments of this application, the communication interconnection between processors and other processors via a network switching device can utilize multiple sets of QP transceiver channels carried on the same port cascaded transmission link to achieve data communication. The multiple sets of QP transceiver channels correspond to multiple types of interactive data involved in the data communication, and the multiple types of interactive data can be concurrently and independently streamed through the multiple sets of QP transceiver channels. Therefore, compared to the serial method of time-division multiplexing port cascaded transmission links for streaming transmission of multiple types of interactive data, the risk of transmission deadlock in data communication between processors can be reduced.

[0170] For example, in the embodiments of this application, the on-chip bus (e.g., AXI bus) of the processor to which this data communication method is applied can carry multiple bus logical channels, and the data communication method may further include: using multiple bus logical channels to realize the on-chip transmission of multiple types of interactive data in the processor; wherein, the correspondence between multiple sets of QP transceiver channels and multiple types matches the correspondence between multiple bus logical channels and multiple types, so that the transmission connection between the streaming transmission of multiple types of interactive data and the on-chip transmission is independent of each other.

[0171] For example, in embodiments of this application, the multiple types of interactive data may include write requests, atomic requests, read requests, and read responses; the multiple bus logic channels of the processor's on-chip bus may include a first bus logic channel corresponding to write requests and atomic requests (e.g., at least one of the AW and W channels of the AXI bus), a second bus logic channel corresponding to read requests (e.g., the AR channel of the AXI bus), and a third bus logic channel corresponding to read responses (e.g., the R channel of the AXI bus). In this case, multiple sets of QP transceiver channels may include a set of write request QP transceiver channels (i.e., one write request QP send channel and one write request QP receive channel) corresponding to write requests and atomic requests, a set of read request QP transceiver channels (i.e., one read request QP send channel and one read request QP receive channel) corresponding to read requests, and a set of read response QP transceiver channels (i.e., one read response QP send channel and one read response QP receive channel) corresponding to read responses.

[0172] For example, in the embodiments of this application, the transmission priority of the read response QP transceiver channel may be higher than the transmission priority of the write request QP transceiver channel and the read request QP transceiver channel. That is, the transmission priority of the read response QP send channel is preferably higher than the transmission priority of the write request QP send channel and the read request QP send channel; and the transmission priority of the read response QP receive channel is preferably higher than the transmission priority of the write request QP receive channel and the read request QP receive channel.

[0173] For example, in the embodiments of this application, the multiple bus logic channels carried by the on-chip bus of the processor to which the data communication method is applied may further include a fourth bus logic channel (e.g., the B channel of the AXI bus) for transmitting write responses, and the data communication method may further include: in response to a write request generated from inside the processor on the fourth bus logic channel, returning a corresponding write response through the fourth bus logic channel.

[0174] For example, in the embodiments of this application, the write response corresponding to the write request received through the write request QP receiving channel can be generated internally by the other processor that initiated the write request, and the data communication method can be used to generate a corresponding write response for the write request received through the write request QP receiving channel without the need for this data communication method.

[0175] For example, in an embodiment of this application, S1130 of the data communication method may specifically include:

[0176] (a1) The transmission order of write requests and atomic requests in the stream transmission implemented by the write request QP transmission channel is kept the same as the transmission order of write requests and atomic requests in the on-chip transmission implemented by the first bus logic channel (e.g., at least one of the AW channel and W channel of AXI), that is, the write requests and atomic requests in the transmission direction are transmitted in order in the write request QP transmission channel.

[0177] (a2) The transmission order of read requests in the stream transmission implemented by the read request QP transmission channel is kept the same as the transmission order of read requests in the on-chip transmission implemented by the second bus logic channel (e.g., AXI's AR channel). That is, read requests in the transmission direction are transmitted in order in the read request QP transmission channel.

[0178] (a3) The transmission order of read responses in the streaming transmission implemented on the read response QP transmission channel is maintained to be the same as the transmission order of read responses in the on-chip transmission implemented on the third bus logic channel (e.g., AXI's Ar channel). That is, read responses in the transmission direction are transmitted in order on the read response QP transmission channel. It is understood that each read response is generated in response to a previously received read request, and the generation order of the read responses does not necessarily have to be the same as the receiving order of the read requests. Furthermore, the transmission order of read responses in the on-chip transmission implemented on the third bus logic channel (e.g., AXI's R channel) does not necessarily have to be consistent with the receiving order of the read requests. Therefore, the transmission order of read responses in the streaming transmission implemented on the read response QP transmission channel can be associated with the receiving order of the corresponding read requests.

[0179] For example, in an embodiment of this application, S1130 of the data communication method may specifically include:

[0180] (b1) The transmission order of write requests that use the same other processor as the data source in the on-chip transmission implemented on the first bus logical channel (e.g., at least one of AXI's AW channel and W channel) is maintained to be the same as the transmission order in the stream transmission implemented on the write request QP receive channel, that is, write requests in the receive direction are transmitted in the order of the first bus logical channel (e.g., at least one of AXI's AW channel and W channel).

[0181] (b2) The transmission order of atomic requests that use the same other processor as the data source in the on-chip transmission implemented on the first bus logical channel (e.g., at least one of the AW channel and W channel of AXI) is decoupled from the transmission order in the stream transmission implemented on the write request QP receive channel. That is, since different atomic requests usually have different operation addresses in the processor U_i, atomic requests in the receive direction can be transmitted out of order on the first bus logical channel (e.g., at least one of the AW channel and W channel of AXI).

[0182] (b3) The transmission order of read requests that use the same other processor as the data source in the on-chip transmission implemented on the second bus logic channel (e.g., AXI's AR channel) is kept in relation to the transmission order in the stream transmission implemented on the read request QP receive channel. That is, since different read requests usually have different access addresses in the processor, read requests in the receive direction can be transmitted out of order on the second bus logic channel (e.g., AXI's AR channel).

[0183] (b4) The transmission order of read responses with the same other processor as the data source in the on-chip transmission implemented on the third bus logic channel (e.g., AXI's R channel) is kept the same as the transmission order in the stream transmission implemented on the read response QP receive channel. That is, the read responses in the receive direction are transmitted in the order-preserving manner on the third bus logic channel (e.g., AXI's R channel).

[0184] For example, in an embodiment of this application, the on-chip bus of the processor using this data communication method can be configured to perform on-chip transmission of interactive data with the same bus identifier in an order-preserving manner. In this case:

[0185] The bus identifier of the on-chip bus of the processor using the data communication method may include a first bus identifier applied to the first bus logical channel, and the above-mentioned step (b1) in S1130 of the data communication method may include: assigning the same first bus identifier corresponding to the data source for all write requests that use the same other processor as the data source, that is, assigning the first bus identifier at the granularity of the data source.

[0186] The bus identifier of the on-chip bus of the processor using the data communication method may include a first exclusive identifier applied to the first bus logical channel. The first exclusive identifier and the first bus identifier may belong to different identifier sequences or different identifier pools. Furthermore, the above-mentioned step (b2) in S1130 of the data communication method may include: allocating different first exclusive identifiers for different atomic requests, that is, allocating first exclusive identifiers at the granularity of atomic requests. Moreover, the first exclusive identifier allocated to each atomic request may be reclaimed in response to the successful operation of the atomic request.

[0187] The bus identifier of the on-chip bus of the processor using this data communication method may further include a second exclusive identifier applied to the second bus logic channel. Furthermore, the above-mentioned step (b3) in S1130 of the data communication method may include: allocating different second exclusive identifiers for different read requests, that is, allocating second exclusive identifiers at the granularity of read requests, and the second exclusive identifier allocated to each read request is reclaimed in response to the successful operation of the read request (e.g., generating a read response corresponding to the read request in the sending direction).

[0188] The on-chip bus identifier of the processor using this data communication method may include a second bus identifier applied to the third bus logical channel. Furthermore, the above-mentioned step (b4) in S1130 of the data communication method may include: querying the second bus identifier associated with the read operation tag of the read response, and the read response may be transmitted on-chip in the third bus logical channel using the queried second bus identifier. In this case, any read response may carry the same read operation tag as the corresponding read request. The second bus identifier is pre-allocated for the read response corresponding to the read request when the read request is sent to the same other processor U_j (i.e., the data source of the read response), and is associated with the read operation tag used by the read request and the corresponding read response. Therefore, whenever a read response is received in response to the issued read request, the pre-determined second bus identifier can be directly hit using the read operation tag.

[0189] For example, in the embodiments of this application, the processor applying this data communication method can maintain multiple sets of first intra-chip transceiver buffer queues. These multiple sets of first intra-chip transceiver buffer queues are used to establish the association and connection between the multiple sets of QP transceiver channels created in S1110 and multiple bus logical channels in the processor. Furthermore, this association and connection is used for the transmission continuity between intra-chip transmission and streaming transmission in the processor. The multiple sets of first intra-chip transceiver buffer queues of the processor may include multiple receive buffer queues. Each receive buffer queue is used to buffer interactive data of the same corresponding type from different data sources. These different data sources include multiple different other processors. Any one of the receive buffer queues can be connected to a corresponding bus logical channel in the multiple bus logical channels through a parallel FIFO queue group. The parallel FIFO queue group includes multiple FIFO queues that correspond one-to-one with different data sources. In this case, the data communication method utilizes multiple bus logic channels to realize the on-chip transmission of multiple types of interactive data in the processor. Specifically, it can include: distributing interactive data from different data sources cached in any one of the multiple receive buffer queues to the corresponding FIFO queues of the parallel FIFO queue group in order by polling the lookup table of different data sources.

[0190] For example, in the embodiments of this application, any type of interactive data carries a network global identifier for uniquely representing the data source of the interactive data, and the processor applying the data communication method can identify the data source of the interactive data (i.e., other processors that generate the interactive data) through the network global identifier carried by the interactive data.

[0191] In the embodiments provided in this application, an electronic device is provided, which may include a network switching device, a processor for performing the data communication method as described above, and other processors that communicate with the processor via the network switching device based on communication interconnection.

[0192] It is understood that, in the embodiments of this application, the various parts described by example may be related by an "and / or" relationship. In this document, "and / or" means that the contexts connected by it may be a common "and" relationship or an alternative "or" relationship. Therefore, the various parts having an "and / or" relationship can be understood to include different combinations of situations where the "and / or" between each pair of parts represents a common "and" relationship or an alternative "or" relationship, and such combinations of different situations can be considered substantially equivalent to the scope of "at least one of the parts".

[0193] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A processor, characterized in that, The processor includes: The chip communication port is used to enable the processor to communicate and interconnect with other processors through a network switching device. The communication interconnect is used to enable data communication between the processor and the other processors. The communication interconnect includes a port cascaded transmission link between the processor and the other processor based on port switching forwarding of the network switching device. The data communication includes multiple types of interactive data streaming through the port cascaded transmission link, and the multiple types include: write request, atomic request, read request, and read response. A port driver circuit is used to create multiple sets of QP transceiver channels based on RDMA, and the multiple sets of QP transceiver channels are carried in the same port cascaded transmission link between the processor and the other processors; The chip processing core is connected to the port driver circuit through the processor's on-chip bus, which is an AMBA bus. The on-chip bus carries multiple bus logic channels, and the multiple bus logic channels are used to respectively realize the on-chip transmission of the multiple types of interactive data in the processor. The multiple types of interactive data are transmitted independently and concurrently through the multiple sets of QP transceiver channels based on the correspondence between the multiple types and the multiple sets of QP transceiver channels; and the transmission connection between the transmission of the multiple types of interactive data and the on-chip transmission is independent of each other.

2. The processor according to claim 1, characterized in that, The correspondence between the multiple sets of QP transceiver channels and the multiple types is matched with the correspondence between the multiple bus logic channels and the multiple types, so that the transmission connection between the streaming transmission and the on-chip transmission of the interactive data of the multiple types is independent of each other.

3. The processor according to claim 1, characterized in that, The multiple bus logical channels include: a first bus logical channel corresponding to the write request and the atomic request, a second bus logical channel corresponding to the read request, and a third bus logical channel corresponding to the read response; The multiple sets of QP transceiver channels include a set of write request QP transceiver channels corresponding to the write request and the atomic request, a set of read request QP transceiver channels corresponding to the read request, and a set of read response QP transceiver channels corresponding to the read response.

4. The processor according to claim 3, characterized in that, The transmission priority of the read response QP transceiver channel is higher than that of the write request QP transceiver channel and the read request QP transceiver channel. And / or, The multiple bus logic channels also include a fourth bus logic channel for transmitting write responses, and the port driver circuit is also used to respond to the write request received from the chip processing core by returning the corresponding write response to the chip processing core through the fourth bus logic channel; And / or, The write response corresponding to the write request received through the write request QP receiving channel is generated internally by the other processor that initiated the write request.

5. The processor according to claim 3, characterized in that, The write request QP transceiver channel includes a write request QP send channel, the read request QP transceiver channel includes a read request QP send channel, and the read response QP transceiver channel includes a read response QP send channel, wherein: The transmission order of the write request and the atomic request in the stream transmission implemented in the write request QP transmission channel is the same as the transmission order in the on-chip transmission implemented in the first bus logic channel. The transmission order of the read request in the stream transmission implemented in the read request QP transmission channel is the same as the transmission order in the on-chip transmission implemented in the second bus logic channel. The transmission order of the read response in the stream transmission implemented in the read response QP transmission channel is the same as the transmission order in the on-chip transmission implemented in the third bus logic channel.

6. The processor according to claim 3, characterized in that, The write request QP transceiver channel includes a write request QP receive channel, the read request QP transceiver channel includes a read request QP receive channel, and the read response QP transceiver channel includes a read response QP receive channel, wherein: The transmission order of the write request, which uses the same other processor as the data source, in the on-chip transmission implemented on the first bus logic channel is the same as the transmission order in the streaming transmission implemented on the write request QP receive channel. The transmission order of the atomic request that uses the same other processor as the data source in the on-chip transmission implemented in the first bus logic channel is decoupled from the transmission order in the stream transmission implemented in the write request QP receive channel. The transmission order of the read request, which uses the same other processor as a data source, in the on-chip transmission implemented in the second bus logic channel is decoupled from the transmission order in the stream transmission implemented in the read request QP receiving channel; The transmission order of the read response, which uses the same other processor as the data source, in the on-chip transmission implemented on the third bus logic channel is the same as the transmission order in the stream transmission implemented on the read response QP receive channel.

7. The processor according to claim 6, characterized in that, The on-chip bus is configured to perform on-chip transmission of interactive data with the same bus identifier in a pre-order manner, and: The bus identifier includes a first bus identifier applied to the first bus logical channel, and the port driver circuit is further configured to: allocate the same first bus identifier corresponding to the data source for all write requests that use the same other processor as the data source; The bus identifier includes a first exclusive identifier applied to the first bus logical channel. The port driver circuit is further configured to: allocate different first exclusive identifiers to different atomic requests, and the first exclusive identifier allocated to each atomic request is reclaimed in response to the successful operation of the atomic request. The bus identifier includes a second exclusive identifier applied to the second bus logical channel. The port driver circuit is further configured to: allocate different second exclusive identifiers for different read requests, and the second exclusive identifier allocated to each read request is reclaimed in response to the successful operation of the read request. The bus identifier includes a second bus identifier applied to the third bus logic channel. The port driver circuit is further configured to: query the second bus identifier stored in association with the read operation tag of the read response; wherein the read response and the corresponding read request carry the same read operation tag, and the second bus identifier is pre-allocated for the corresponding read response and stored in association with the corresponding read operation tag when the read request is sent to the same other processor.

8. The processor according to claim 1, characterized in that, The chip communication port is connected to the first network switching port of the network switching device. The network switching device also includes a second network switching port connected to the communication ports of other chips of the other processors. The port cascading transmission link includes a first port serial link between the chip communication port and the first network switching port, a second port serial link between the second network switching port and the other chip communication ports, and a port switching link between the first network switching port and the second network switching port to realize the port switching forwarding. The multiple sets of QP transceiver channels are created between the chip communication port and the other chip communication ports, and the multiple sets of QP transceiver channels are respectively carried on two segments of the first port serial link and the second port serial link, and are bridged through corresponding multiple sets of switching channels between the first network switching port and the second network switching port.

9. The processor according to claim 1, characterized in that, The port driver circuit is used to maintain multiple sets of first on-chip transceiver buffer queues. The multiple sets of first on-chip transceiver buffer queues are used to realize the association and connection between the multiple sets of QP transceiver channels and the multiple bus logic channels. Furthermore, the association and connection are used for the transmission connection between the on-chip transmission and the streaming transmission.

10. The processor according to claim 9, characterized in that, The multiple sets of first-chip intra-chip transceiver buffer queues include multiple receive buffer queues. Each of the multiple receive buffer queues is used to buffer interactive data of the same corresponding type from different data sources. The different data sources include multiple different other processors. Any one of the multiple receive buffer queues is connected to the corresponding bus logical channel in the multiple bus logical channels through a parallel FIFO queue group. Furthermore, the parallel FIFO queue group includes multiple FIFO queues that correspond one-to-one with different data sources. Interaction data from different data sources cached in any of the multiple receive buffer queues are distributed in order to the corresponding FIFO queues of the parallel FIFO queue group by polling the lookup tables of different data sources.

11. The processor according to claim 10, characterized in that, The multiple bus logical channels include: a first bus logical channel corresponding to the write request and the atomic request, a second bus logical channel corresponding to the read request, and a third bus logical channel corresponding to the read response; the multiple sets of QP transceiver channels include: a write request QP sending channel and a write request QP receiving channel corresponding to the write request and the atomic request, a read request QP sending channel and a read request QP receiving channel corresponding to the read request, and a read response QP sending channel and a read response QP receiving channel corresponding to the read response; the multiple sets of first on-chip transceiver buffer queues include: multiple receive buffer queues respectively corresponding to the write request QP receiving channel, the read request QP receiving channel, and the read response QP receiving channel; the receive buffer queue corresponding to the write request QP receiving channel is connected to the first bus logical channel, and the receive buffer queue corresponding to the read request QP receiving channel is connected to the second bus logical channel through different parallel FIFO queue groups; and the receive buffer queue corresponding to the read response QP receiving channel is connected to the third bus logical channel through a single FIFO queue. And / or, The port driver circuit also has a receive status register group corresponding to the plurality of receive buffer queues, and each register bit of the receive status register group is used to characterize whether the corresponding receive buffer queue in the plurality of receive buffer queues currently caches the polling result of the interaction data of the corresponding data source. And / or, The port driver circuit also has a stock status register group corresponding to the parallel FIFO queue group. Each register bit of the stock status register group is used to characterize whether the corresponding FIFO queue in the parallel FIFO queue group is currently filled with interactive data from the corresponding data source. Furthermore, the execution range of the lookup table excludes the data source corresponding to the FIFO queue indicated by the stock status register group as currently filled. And / or, Any type of interactive data carries a network-global identifier that uniquely represents the data source.

12. A multiprocessor system, characterized in that, The device includes a first processor, a second processor, and a network switching device, wherein the first processor is configured as the processor as described in any one of claims 1 to 11, and the second processor includes other processors that communicate with the processor as described in any one of claims 1 to 11.

13. A data communication method, characterized in that, The data communication method is applied to a processor; the processor has a chip communication port, which is used to realize communication interconnection between the processor and other processors through a network switching device. The communication interconnection is used for data communication between the processor and the other processors. The communication interconnection includes a port-cascaded transmission link between the processor and the other processors based on port switching forwarding of the network switching device. The data communication includes the streaming transmission of multiple types of interactive data through the port-cascaded transmission link. The multiple types include: write requests, atomic requests, read requests, and read responses. The processor's on-chip bus carries multiple bus logic channels. The on-chip bus is an AMBA bus. Furthermore, the data communication method includes: Create multiple sets of QP transceiver channels based on RDMA, wherein the multiple sets of QP transceiver channels are carried in the same port cascaded transmission link between the processor and the other processors; Based on the correspondence between the multiple data types and the multiple sets of QP transceiver channels, the independent streaming transmission of the interactive data of the multiple data types is achieved concurrently using the multiple sets of QP transceiver channels; and, The multiple bus logic channels are used to realize the on-chip transmission of the multiple types of interactive data in the processor, and the transmission connection between the streaming transmission and the on-chip transmission of the multiple types of interactive data is independent of each other.

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