Data processing method and system

Abstract

The invention discloses a data processing method and system. The method comprises the steps that in response to a data collection instruction of a processing system PS end, collected data are stored in a target cache according to the data type of the collected data, and the target cache belongs to a programmable logic PL end and corresponds to the data type; under the condition that the target cache is full, the collected data are stored in a target memory area according to the data type, and the target memory area belongs to the memory space mounted by the PS end and corresponds to the data type; and in response to the received analysis data, processing is carried out by adopting the target model based on the analysis data to obtain an exception identification result, the analysis data is obtained by analyzing the collected data by the PS end, and the PS end is used for generating an exception processing strategy based on the exception identification result. The technical problem that the data processing efficiency is not ideal in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of data processing and embedded chip technology, and in particular to a data processing method and system. Background Art

[0002] The operating environment of the well site is complex, the equipment operating status is changeable, and the monitoring and maintenance requirements of the equipment are extremely high. The acquisition of high-frequency signals is of great significance for timely detection of equipment failures and prevention of safety accidents. In related technologies, multiple devices such as data acquisition, data analysis, and data communication are independent, which leads to an increase in the overall procurement cost and occupies a large space, which is not conducive to layout in the limited space of the well site. In addition, the working environment of the well site is harsh, the network cable connection is easily damaged or disconnected, and the connection and maintenance between multiple devices are complicated, which not only increases the difficulty of troubleshooting and repair, but also easily leads to signal instability or network cable disconnection, which will cause the data acquisition process to be interrupted, resulting in data loss, resulting in a decrease in the data processing efficiency of the well site data.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present invention provide a data processing method and system to at least solve the technical problem of unsatisfactory data processing efficiency in the related art.

[0005] According to one aspect of an embodiment of the present invention, a data processing method is provided, including: in response to a data collection instruction from a processing system PS side, storing the collected data in a target cache according to the data type of the collected data, wherein the target cache belongs to a programmable logic PL side, and the target cache corresponds to the data type; when the target cache is full, storing the collected data in a target memory area according to the data type, wherein the target memory area belongs to a memory space mounted by the PS side, and the target memory area corresponds to the data type; in response to receiving parsed data, processing using a target model based on the parsed data to obtain an exception recognition result, wherein the parsed data is obtained by the PS side parsing the collected data, the target model is obtained by performing training on the PL side, the target model matches the data type, and the PS side is used to generate an exception handling strategy based on the exception recognition result.

[0006] Optionally, the method also includes: obtaining training data sent by the PS end, wherein the type of the training data matches the data type, and the training data is obtained by the PS end based on parsing historical data; based on the training data, performing training on the initial model deployed on the PL end to obtain the target model.

[0007] Optionally, the cache space of the PL end includes multiple caches, the multiple caches correspond to the data type, and the target cache is one of the multiple caches. The method also includes: when the target cache is full, storing new collected data in the next cache according to a predetermined cache order, wherein the next cache is the cache after the target cache in the multiple caches, wherein the multiple caches are configured based on the data period and the amount of collected data.

[0008] Optionally, the PL side further includes a direct memory access DMA control module, and the DMA control module is used for the PL side to interact with the memory space mounted on the PS side.

[0009] Optionally, the memory space mounted on the PS end includes multiple memory areas, the multiple memory areas correspond to the data type, and the target memory area is one of the multiple memory areas. The method also includes: when the target memory area is full, storing new collected data in the next memory area according to a predetermined memory order, wherein the next memory area is the memory area after the target memory area in the multiple memory areas, wherein the multiple memory areas are configured based on the data reading delay of the PS end.

[0010] Optionally, storing the collected data in a target memory area according to the data type includes: using the DMA control module to store the collected data from the target cache to the target memory area according to the data type; and sending a trigger interrupt instruction to the PS end when the target memory area is full, wherein the trigger interrupt instruction is used to instruct the PS end to read the collected data in the target memory area.

[0011] According to another aspect of an embodiment of the present invention, a data processing method is provided, comprising: reading collected data stored in a target memory area, wherein the target memory area belongs to a memory space mounted on a processing system PS side, the target memory area corresponds to a data type of the collected data, the collected data is stored in the target memory space by the target cache according to the data type when the target cache is full, the target cache belongs to a programmable logic PL side, the target cache corresponds to the data type, the PL side is used to respond to a data collection instruction of the PS side and store the collected data in the target cache according to the data type; parsing the collected data to obtain parsed data; and in response to receiving an exception recognition result, determining an exception handling strategy based on the exception recognition result.

[0012] Optionally, the memory space mounted on the PS end includes multiple memory areas, the multiple memory areas correspond to the data type, the target memory area is one of the multiple memory areas, and before reading the collected data stored in the target memory area, the method also includes: receiving a trigger interrupt instruction sent by the PL end, determining the flag position bit states corresponding to the multiple memory areas respectively; and determining a memory area in the multiple memory areas whose flag position bit state is a predetermined value as the target memory area.

[0013] According to another aspect of an embodiment of the present invention, a data processing method is provided, including: a programmable logic PL side responds to a data collection instruction of a processing system PS side, and stores the collected data in a target cache according to the data type of the collected data, wherein the target cache belongs to the PL side, and the target cache corresponds to the data type; when the target cache is full, the collected data is stored in a target memory area according to the data type, wherein the target memory area belongs to a memory space mounted by the PS side, and the target memory area corresponds to the data type; the PS side reads the collected data stored in the target memory area; the collected data is parsed to obtain parsed data; the PL side, in response to receiving the parsed data, uses a target model for processing based on the parsed data to obtain an exception recognition result; the PS side, in response to receiving the exception recognition result, determines an exception handling strategy based on the exception recognition result.

[0014] According to another aspect of an embodiment of the present invention, there is provided a data processing system, comprising: a programmable logic PL end applying any one of the above, and a processing system PS end applying any one of the above.

[0015] In an embodiment of the present invention, in response to a data collection instruction of a processing system PS end, the collected data is stored in a target cache according to the data type of the collected data, wherein the target cache belongs to a programmable logic PL end, and the target cache corresponds to the data type; when the target cache is full, the collected data is stored in a target memory area according to the data type, wherein the target memory area belongs to a memory space mounted by the PS end, and the target memory area corresponds to the data type; in response to receiving parsed data, based on the parsed data, a target model is used for processing to obtain an abnormality recognition result, wherein the parsed data is obtained by the PS end parsing the collected data, the target model is obtained by training performed on the PL end, the target model matches the data type, and the PS end is used to generate an abnormality handling strategy based on the abnormality recognition result. The purpose of reducing the delay of data processing and enhancing the ability to respond quickly to data anomalies is achieved, and the technical effect of improving data processing efficiency is achieved, thereby solving the technical problem of unsatisfactory data processing efficiency in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 is a flowchart of an optional data processing method provided according to an embodiment of the present invention;

[0018] Figure 2 is a memory reading flow chart of an optional data processing method provided according to an embodiment of the present invention;

[0019] Figure 3 is a flowchart of another optional data processing method provided according to an embodiment of the present invention;

[0020] Figure 4 is a flowchart of another optional data processing method provided according to an embodiment of the present invention;

[0021] Figure 5 is a structural block diagram of an optional data processing system provided according to an embodiment of the present invention;

[0022] Figure 6 is a transmission logic diagram of an optional data processing system provided according to an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of an optional data processing system provided according to an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of an optional data processing device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0028] Field Programmable Gate Array (FPGA) allows users to configure internal logic circuits through programming after manufacturing to achieve specific functions. FPGA is composed of a large number of logic units, which can perform multiple operations in parallel and provide high-speed parallel computing capabilities, giving FPGA a significant advantage in processing high-speed data signals.

[0029] Advanced RISC Machines (ARM) has an efficient instruction set and computing power. It is used to design low-power, high-performance microprocessors and microcontrollers and is the core of embedded systems.

[0030] AXI bus is an on-chip bus protocol for high performance, high bandwidth, and low latency. AXI bus supports high data throughput and achieves efficient data transmission through independent read and write address, data, and response channels, meeting the requirements of high performance and complex on-chip system design.

[0031] The ZYNQ (ZYNQ-7000 All Programmable SoC) chip is a fully programmable system-on-chip platform that integrates an ARM processor and FPGA (field programmable gate array) on a single chip, providing a high degree of flexibility and performance optimization.

[0032] According to an embodiment of the present invention, a method embodiment of data processing is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] Figure 1 is a flow chart of an optional data processing method according to an embodiment of the present invention. Figure 1 As shown, the optional execution subject is the PL end, and the method includes the following steps:

[0034] Step S102, in response to the data collection instruction of the processing system PS side, storing the collected data into a target cache according to the data type of the collected data, wherein the target cache belongs to the programmable logic PL side, and the target cache corresponds to the data type;

[0035] It can be understood that in response to the data acquisition instruction of the processing system (PS side), the collected data is stored in the target cache according to the data type of the collected data. The above-mentioned target cache is part of the programmable logic (PL side), and the setting of the target cache is corresponding to the data type. Storing data in the corresponding target cache according to the data type helps to manage data efficiently and avoid confusion between different types of data.

[0036] Optionally, by caching data of different types, more types of data caches can be flexibly expanded as needed to meet complex monitoring and analysis requirements.

[0037] Optionally, the PL end includes: a data acquisition cache module and a DMA control module. The data acquisition cache module is used to collect and cache data after the data passes through the A / D module. The data acquisition cache module communicates with the DMA control module through the AXI bus, and the data acquisition cache module transmits the cached data to the DMA control module. The DMA control module is used to receive data transmitted from the data acquisition cache module, and perform data movement based on the DMA control logic. Data movement is to write and store the collected data into the DDR storage space through the DDR bus protocol for easy reading by the PS end.

[0038] Optionally, the PS side is used as the main control module of the data processing system (also called the data acquisition system), and its functions include: controlling the state of the PL side; interacting with the PL side for control instructions, reading the collected data stored in the DDR; performing algorithm analysis and processing on the collected data, and realizing equipment fault diagnosis based on the processing results. The PS side is connected to the communication module for wired and wireless data transmission.

[0039] Optionally, the data interaction module between the PL side and the PS side includes: a state setting, an interrupt processing module and a Bram_Ctrl interaction module of AXI. The state setting is through the AXI bus, and the PS side performs reset (reset data acquisition), start (start data acquisition), stop (end data acquisition) and other state settings on the PL side. The interrupt processing module is a DMA control module that transmits the specified amount of collected data to the DDR storage area. After the data is stored, it notifies the PS side by triggering an interrupt instruction, and the PS side reads the specified amount of collected data from the DDR. The Bram_Ctrl interaction module is used to perform information interaction of two-way control instructions through the Bram_Ctrl interaction module after the data acquisition starts, so as to realize the effective control of the data acquisition process by the PS side.

[0040] Optionally, before executing data collection, the PS side needs to be initialized. The PS side sets the start state (starts data collection) of the PL side through the AXI bus, completes the initialization setting of the PL side and starts data collection.

[0041] During the data collection process, if the instrument skid backend or remote terminal wants to stop data collection, it can send a control command to the PS end through the communication module. The PS end executes the stop command and sets the stop state (ends data collection) to the PL end through the AXI bus. After the PL end executes the stop command, data collection stops.

[0042] During the data collection process, if the instrument skid backend or the remote terminal wants to reset data collection, it can send a control command to the PS side through the communication module. The PS side executes the reset command and sets the reset state (reset data collection) of the PL side through the AXI bus. The PL side executes the reset command to clear the buffer data, initialize the settings, and restart data collection.

[0043] Optionally, the PL side can be FPGA, and the PS side can be ARM. FPGA has powerful hardware programmability and parallel processing capabilities. During the data acquisition process, FPGA can process multiple data channels in parallel, greatly improving the efficiency of data acquisition and processing, and running stably in the application scenario of high-frequency data acquisition to meet real-time requirements. Designing the PL side as FPGA and the PS side as ARM fully utilizes the hardware acceleration, parallel processing and flexibility advantages of FPGA, as well as the complex algorithm processing and system control capabilities of ARM, to achieve an efficient, low-latency, and high-precision data acquisition and analysis system.

[0044] Step S104, when the target cache is full, the collected data is stored in the target memory area according to the data type, wherein the target memory area belongs to the memory space mounted on the PS end, and the target memory area corresponds to the data type;

[0045] It can be understood that when the target cache is full, the collected data is stored in the target memory area according to the data type. The above target memory area is part of the memory space mounted on the PS side and corresponds to the data type. Storing data in different memory areas by type helps subsequent parallel processing and data analysis and optimizes resource utilization. Automatically migrate data from the cache to the memory to avoid data loss due to cache overflow and ensure the continuity and integrity of data collection.

[0046] In an optional embodiment, the cache space of the PL end includes multiple caches, the multiple caches correspond to data types, and the target cache is one of the multiple caches. The method also includes: when the target cache is full, storing new collected data in the next cache according to a predetermined cache order, wherein the next cache is the cache after the target cache in the multiple caches, wherein the multiple caches are configured based on the data period and the amount of collected data.

[0047] It can be understood that when the processing system (PS side) issues a data collection instruction, the PL side starts to collect data according to the instruction. According to the data type of the collected data, the PL side stores the collected data in the corresponding target cache. The cache space of the PL side is divided into multiple caches, and multiple caches can be regarded as a group, corresponding to a data type. The configuration method is conducive to efficient management and storage of different types of data. When the target cache is full, the new collected data will be stored in the next cache according to the predetermined cache order, which is determined according to the arrangement order of the cache. This cache switching mechanism ensures the continuity of data collection and avoids data loss. It should be noted that the configuration of multiple caches is determined based on the data cycle of the collected data and the amount of collected data. The size and number of caches can be specifically adjusted according to the actual data collection needs to achieve optimal storage efficiency and performance.

[0048] In an optional embodiment, the memory space mounted on the PS end includes multiple memory areas, the multiple memory areas correspond to data types, and the target memory area is one of the multiple memory areas. The method also includes: when the target memory area is full, storing the new collected data in the next memory area according to a predetermined memory order, wherein the next memory area is the memory area after the target memory area among the multiple memory areas, wherein the multiple memory areas are configured based on the data reading delay of the PS end.

[0049] It can be understood that when the target memory area corresponding to the data type is full, the new collected data is automatically stored in the next memory area after the target memory area according to the predetermined memory order, which can ensure the continuity of data collection and avoid the collection interruption caused by the full load of a single memory area. The memory space mounted on the PS end is divided into multiple memory areas, and these multiple memory areas correspond to the same data type, which helps to improve the organization and manageability of the data and facilitates subsequent data processing and reading.

[0050] Optionally, the PS side allocates memory of the area according to the mounted memory space DDR. The memory area (also called channel) of the memory space can be allocated in the following manner. The storage space of each memory area in the DDR can be an integer multiple of the buffer storage space in the data acquisition cache module, that is, the total number of caches corresponding to different data types. For example, the memory space allocated to each buffer is 1K, and each memory space in the DDR is allocated 8M (megabytes). The above specific configuration can be adjusted according to specific needs to minimize the frequency of the PS side reading data from the DDR. This is because the interaction delay between the PS side and the DDR is large, and repeated data reading will reduce the efficiency of data processing.

[0051] The FIFO mode is used for data writing and reading in the memory space DDR. The DMA control module on the PL side writes the collected data into a memory area corresponding to the data type in the DDR, and the PS side reads the collected data from the corresponding memory area.

[0052] The total number of memory areas (i.e., the number of channels) in the above-mentioned DDR can be determined in the following manner, for example: the number of channels is equal to the number of data types, multiplied by the number of memory areas allocated to a single data type. For example, in this example, two data types (vibration signals and key phase signals) are used, and three memory areas are allocated to the collected data of one data type. The total number of memory areas for different data types is 2*3=6.

[0053] Optionally, the DMA control module writes the collected data to DDR, which can be done in the following way. For the case of collecting only one data type, according to the above example, DDR allocates three memory spaces for this data type, namely memory spaces 1, 2, and 3. The DMA control module stores the collected data in memory space 1, and stores it in memory space 2 after memory space 1 is full. The predetermined memory order is illustrated as memory areas 1, 2, 3, 1, 2..., and a loop traversal is performed.

[0054] In the case of collecting multiple data types, a flag bit is added when a memory area is opened for each data type. It can be a certain bit or several bits in the storage space, which is used for the data full flag bit (i.e., the flag bit). When the corresponding memory space is full, the data full flag bit will be set, such as set to 1. For ease of understanding, examples and explanations are given. For example, when collecting data of two data types, namely vibration signals and key phase signals, the memory space DDR allocates 6 memory areas, memory areas 1, 2, and 3 are used to store vibration signals, and memory areas 4, 5, and 6 are used to store key phase signals. The DMA control module stores the vibration signal data (corresponding to the data in buffer 1 and buffer 2 in the data acquisition cache module) in memory area 1. When memory area 1 is full, it will be stored in the storage space of memory area 2. The predetermined memory order is memory area 1, 2, 3, 1, 2..., and it is traversed in a loop.

[0055] The DMA module stores the key phase signal (data in buffer 3 and buffer 4 in the data acquisition cache module) data in memory area 4. When memory area 4 is full, it will be stored in memory area 5, and the memory areas will be traversed in a loop according to the predetermined memory order of memory areas 4, 5, 6, 4, 5...

[0056] In an optional embodiment, the PL side also includes a direct memory access DMA control module, and the DMA control module is used for the interaction between the PL side and the memory space mounted on the PS side.

[0057] It can be understood that the DMA control module receives data transmitted from the data acquisition cache module through the AXI bus, and the signals after A / D (analog signal / digital signal) conversion, such as vibration signals, key phase signals, etc. The DMA control module uses DMA technology to achieve high-speed data transmission, and directly writes the received data into the DDR (Double Data Rate Synchronous Dynamic Random Access Memory) memory plug-in on the PS side, without the intervention of the CPU, thereby greatly improving the data transmission efficiency.

[0058] Optionally, a FIFO (first-in, first-out) cache method is used to cache the collected data. The cache creation on the PL side is controlled by the PS side. For ease of understanding, an example of cache creation processing is given, for example: two buffer (cache) storage spaces are opened for data caching, and the collected A / D converted data (i.e., collected data) is pushed into buffer1 (i.e., the target cache) for cache. After buffer1 is full, the collected data is continued to be stored in buffer2 (i.e., the next cache). At this time, the full data stored in buffer1 is converted into an AXI transmittable format and transmitted to the DMA control module via the AXI bus. The above process is continued, that is, one buffer stores data, and the other full buffer data is transmitted to the DMA control module via the AXI bus. Multiple buffers are opened for use in order to improve efficiency. The number of buffers (i.e., the total number of multiple caches) can be increased during actual use.

[0059] For each buffer, the size of memory space allocated is used for storage. Taking pulse data collection as an example, the data volume of multiple sensors of the same data type with a specified pulse number is specified. For example, 8 vibration signal collection sensors are used for data collection. In one pulse (i.e., data cycle), each sensor transmits 4 bytes of data (i.e., the amount of collected data) to the data collection cache module. A buffer needs to store the data volume of 32 pulses. Then it can be calculated that the space required to allocate a buffer is 1K. It can be set to the memory space size corresponding to other pulse numbers according to specific needs. As the above group of buffers has two (i.e., multiple caches), a group of buffers can also choose a number greater than or equal to 2.

[0060] Optionally, the total number of buffers corresponding to different data types, that is, the number of buffers can be determined in the following manner: when data of multiple data types are collected simultaneously, the number of buffers is the number of types of data types multiplied by the number of buffers in a group (that is, multiple buffers of the same data type, set to 2 in this example); for example, when collecting data of two data types, vibration signal and key phase signal, at the same time, the total number of buffers corresponding to different data types is allocated as 2*2 (that is, 4), where every two buffers are multiple buffers of the same data type, as a group of buffers (such as buffer1 and buffer2), one group of data caches for vibration signals are written and read and sent to the DMA control module, and the other group of buffers (such as buffer3 and buffer4) are used for data caches for key phase signals are written and read and sent to the DMA control module.

[0061] In an optional embodiment, the collected data is stored in the target memory area according to the data type, including: using a DMA control module to store the collected data from the target cache to the target memory area according to the data type; when the target memory area is full, sending a trigger interrupt instruction to the PS end, wherein the trigger interrupt instruction is used to instruct the PS end to read the collected data in the target memory area.

[0062] It can be understood that in order to efficiently and orderly control the storage and transmission of data during the data acquisition process, the collected data is stored in the target memory area according to the data type. The DMA control module is used to directly write to the memory space mounted on the PS side, and the write location is determined as the target memory area according to the data type. When the target memory area is full of data, the DMA control module will immediately send a trigger interrupt instruction to the PS side, which not only indicates that the current target memory area of ​​the PS side is full of data, but also triggers the PS side to perform the next data reading operation. Through the trigger interrupt mechanism, the PS side can know in time which memory areas are ready to be read, thereby avoiding data processing delays and waste of resources. Through memory area division and triggering interrupt instructions, orderly storage and timely reading of data can be ensured, thereby improving the overall data processing capability and real-time performance.

[0063] Optionally, after the DMA control module writes a full memory area into the DDR, the PL side notifies the PS side by triggering an interrupt, and the PS side moves the data, that is, the PS side reads all the data in the memory area in the DDR that is full of data.

[0064] In the case of collecting only one type of data, after receiving the trigger interrupt, the PS end reads the full channel data according to the number sequence of the memory area. For example, three memory areas are allocated in DDR to store collected data, namely memory areas 1, 2, and 3. When the PS end receives the trigger interrupt for the first time, it indicates that the memory area 1 is full of data. The PS end reads all the data in the memory area 1 and erases the data in the memory area 1. When the trigger interrupt is received again, it indicates that the memory area 2 is full of data, and so on.

[0065] Figure 2 is a memory reading flow chart of an optional data processing method provided according to an embodiment of the present invention, such as Figure 2 As shown, for the case of collecting multiple data types, a flag bit is added when each memory area is opened up. It can be a certain bit or several bits in the storage space recorded as the flag bit. The same data type selects the suspected full area according to the numbering order of the memory area, for example: memory areas 1, 2, and 3 store vibration signals, and memory areas 4, 5, and 6 store key phase signals. When the PS end receives the trigger interrupt at the beginning, it may be that the vibration signal stored in memory area 1 is full, or it may be that the key phase signal stored in memory area 4 is full. Memory area 1 and memory area 4 are regarded as suspected full. For memory areas of suspected full data of different data types, which memory areas are full of data are determined according to the flag bit, that is, the PS end confirms the data full flag bit of memory area 1 and memory area 4. When the data full flag bit is set to a predetermined value, such as set to 1, it means that the data in the memory area is full. The PS end reads the data in the memory area and then erases the data. After the reading is completed, the data full flag bit is set to another predetermined value, such as set to 0. The PS end increases the memory area number sequence of the vibration signal by 1, that is, the next time the PS end receives a trigger interrupt, it uses memory area 2 and memory area 4 as suspected full areas, and further confirms which memory area is full based on the flag bit, and so on.

[0066] Step S106, in response to receiving the parsed data, the target model is used for processing based on the parsed data to obtain an exception recognition result, wherein the parsed data is obtained by parsing the collected data on the PS side, the target model is obtained by performing training on the PL side, the target model matches the data type, and the PS side is used to generate an exception handling strategy based on the exception recognition result.

[0067] It can be understood that in response to receiving the parsed data, the target model is used for processing based on the parsed data to obtain the abnormal identification result. The above parsed data is obtained by parsing the collected data on the PS side, and the target model is obtained by training on the PL side and matches the data type. By training the model on the PL side and using the powerful computing power of the PL side for efficient data processing and model reasoning, low-latency abnormal identification is achieved. Real-time data processing and model reasoning ensure a rapid response to abnormal situations and reduce the time delay from data collection to abnormal processing. The PS side is used to generate an abnormal handling strategy based on the abnormal identification results. The PS side autonomously generates a processing strategy based on the abnormal identification results, which improves the intelligence level and autonomous decision-making ability of the system, enabling the system to respond to equipment failures and abnormal situations more efficiently.

[0068] It should be noted that by utilizing the heterogeneous characteristics of the ZYNQ chip (including the FPGA high-speed performance on the PL side and the ARM low power consumption and control capabilities on the PS side), the full process of data collection, caching, transmission, processing and exception identification has been optimized.

[0069] In an optional embodiment, the method also includes: obtaining training data sent by the PS end, wherein the type of the training data matches the data type, and the training data is obtained by the PS end based on parsing historical data; based on the training data, performing training on the initial model deployed on the PL end to obtain the target model.

[0070] It can be understood that the training data sent by the PS end is obtained, and the type of training data matches the type of data involved in the data collection process to ensure the effectiveness and pertinence of the training process. The training data is obtained by the PS end after parsing and preprocessing the historically collected data. Historical data can include data on the normal operating status and various fault states of the equipment. By analyzing these data, features for model training can be extracted. Based on the training data obtained above, the training process is performed on the initial model deployed on the PL end, which utilizes the powerful computing power and programmability of the PL end to accelerate the training speed of the model. The target model obtained after the training is completed will have a higher fault diagnosis accuracy and faster reasoning speed, thereby improving the performance of the entire data acquisition and analysis system.

[0071] Optionally, the PS side reads the collected data and parses the data, parses the data of different data types and different sensors in the order of collection, and performs fault diagnosis analysis on the parsed data. The fault diagnosis analysis model (i.e., the target model) can be deployed on the PS side, or the fault diagnosis model can be deployed on the PL side by taking advantage of the fast calculation speed of the PL side.

[0072] Optionally, the PL-side model initialization and parameter setting can be in the following ways, for example: based on the Bram_Ctrl interaction module, the PS-side communicates with the PL-side, the PS-side sends a model initialization instruction to the PL-side, the parameters of the model can be set, or the relevant parameters can be set according to the control instructions of the remote terminal or the instrument skid background.

[0073] Optionally, the PS end temporarily opens a transmission channel on the DDR for the data used for data analysis on the PL end (i.e., parsed data). After the PS end writes the data required for analysis into the opened DDR channel, the PS end transmits a read data instruction to the PL end. After receiving the read data instruction, the PL end reads the data required for analysis from the specified DDR channel and stores it in the FIFO storage area. If the data required for analysis can only be completed through multiple transmissions through the DDR channel, the PS end sends a read instruction to the PL end each time it writes the data required for analysis into the specified DDR channel. After receiving the read completion information from the PL end, the PS end continues to write the data required for analysis into the DDR until the data required for analysis is transmitted from the PS end to the PL end. The PS end sends a data transmission completion instruction to the PL end. After the data transmission is completed, the PS end destroys the channel memory opened for the data transmission required for analysis.

[0074] After the PL receives the data completion instruction, it uses the trained target model to perform model reasoning for fault diagnosis based on the data required for analysis. After the reasoning result is calculated, it communicates with the PS through the Bram_Ctrl interaction module, notifying the PS of the completion of the calculation and the memory size required to transmit the calculation result. After the PS has opened the specified channel memory on the DDR, it sends the channel address number of the memory opened and the instruction requiring the PL to send the calculation result to the PL through the Bram_Ctrl interaction module. The PL writes the calculation result (i.e., the abnormal identification result) to the DDR and informs the PS through the Bram_Ctrl module. The PS reads the data in the instruction channel memory (i.e., the abnormal identification result) and releases the opened memory after reading.

[0075] Optionally, during the training process, the parameters of the model can be adjusted according to the characteristics of the training data, and through multiple iterations of optimization, the model can more accurately identify the type of equipment failure based on the collected data.

[0076] Through the above step S102, in response to the data collection instruction of the processing system PS end, the collected data is stored in the target cache according to the data type of the collected data, wherein the target cache belongs to the programmable logic PL end, and the target cache corresponds to the data type; step S104, when the target cache is full, the collected data is stored in the target memory area according to the data type, wherein the target memory area belongs to the memory space mounted by the PS end, and the target memory area corresponds to the data type; step S106, in response to receiving the parsed data, based on the parsed data, the target model is used for processing to obtain the abnormal recognition result, wherein the parsed data is obtained by the PS end parsing the collected data, the target model is obtained by performing training on the PL end, the target model matches the data type, and the PS end is used to generate an abnormality handling strategy based on the abnormal recognition result. The purpose of reducing the delay of data processing and enhancing the ability to respond quickly to data anomalies can be achieved, and the technical effect of improving data processing efficiency is achieved, thereby solving the technical problem of unsatisfactory data processing efficiency in the related technology.

[0077] Figure 3 is a flowchart of another optional data processing method according to an embodiment of the present invention. Figure 3 As shown, the optional execution subject is the PS end, and the method includes the following steps:

[0078] Step S302, reading the collected data stored in the target memory area, wherein the target memory area belongs to the memory space mounted on the PS side of the processing system, the target memory area corresponds to the data type of the collected data, and the collected data is stored in the target memory space by the target cache according to the data type when the target cache is full, the target cache belongs to the programmable logic PL side, the target cache corresponds to the data type, and the PL side is used to respond to the data collection instruction of the PS side and store the collected data in the target cache according to the data type;

[0079] It can be understood that a target memory area is specified in the memory space mounted by the processing system (PS side). The target memory area corresponds to the data type and is used to store the collected data transmitted from the PL side. When the data in the target cache (located on the PL side) reaches the storage limit, the collected data will be automatically transferred to this target memory area according to its data type. The read operation is executed through the control logic of the PS side to ensure that the collected data in the target memory area can be accessed efficiently. By storing the collected data in a specially set target memory area, effective management and fast access to the collected data are achieved, which is conducive to improving the transmission efficiency of the data, reducing the risk of loss due to data overflow, and ensuring the integrity and reliability of the data.

[0080] In an optional embodiment, the memory space mounted on the PS end includes multiple memory areas, the multiple memory areas correspond to data types, the target memory area is one of the multiple memory areas, and before reading the collected data stored in the target memory area, the method also includes: receiving a trigger interrupt instruction sent by the PL end, determining the flag position bit states corresponding to the multiple memory areas respectively; determining a memory area in the multiple memory areas whose flag position bit state is a predetermined value as the target memory area.

[0081] It can be understood that when the PL end completes a data acquisition and successfully stores the data in the target cache (belonging to the PL end), when it is full, it is considered that the collected data is ready to be read by the PS end (processing system end). The PL end will send a trigger interrupt instruction to the PS end to notify the PS end that it can read the collected data stored in the target memory area. After receiving the trigger interrupt instruction, the PS end will check the flag bits associated with the multiple memory areas included in the memory space mounted on it. The flag bits are used to indicate the storage status of each memory area, such as whether it is full. The PS end determines which memory areas can perform read processing by reading the flag bit status. By using flag bits to track the status of each memory area and synchronizing the operations between the PL end and the PS end by triggering interrupt instructions, it can ensure that data is read from the correct memory area at the right time, which helps to reduce the risk of data loss or erroneous reading and improve the accuracy and real-time performance of data.

[0082] Step S304, analyzing the collected data to obtain analyzed data;

[0083] It can be understood that after successfully reading the collected data in the target memory area, the PS side will perform data analysis on the collected data to obtain analyzed data.

[0084] Optionally, there may be multiple data parsing methods, such as identifying the format, structure and possible encoding methods of the data so as to convert the data into a format that is easier to understand and process (i.e., parsing the data), and performing operations such as data decoding, field extraction, and format conversion.

[0085] Step S306, in response to receiving the abnormality identification result, determining an abnormality handling strategy based on the abnormality identification result.

[0086] It can be understood that based on the anomaly identification results, the PS side will determine the most appropriate processing strategy, ie, the anomaly handling strategy, according to factors such as the type and severity of the anomaly.

[0087] Optionally, the above exception handling strategy may include multiple measures such as alarm notification, data re-collection, device restart, fault isolation, etc.

[0088] Through the above step S302, the collected data stored in the target memory area is read, wherein the target memory area belongs to the memory space mounted on the PS side of the processing system, the target memory area corresponds to the data type of the collected data, and the collected data is stored in the target memory space by the target cache according to the data type when the target cache is full, the target cache belongs to the programmable logic PL side, the target cache corresponds to the data type, and the PL side is used to respond to the data collection instruction of the PS side and store the collected data in the target cache according to the data type; step S304, the collected data is parsed to obtain parsed data; step S306, in response to receiving the abnormal identification result, the abnormality handling strategy is determined based on the abnormal identification result. The purpose of reducing the delay of data processing and enhancing the ability to respond quickly to data abnormalities can be achieved, and the technical effect of improving data processing efficiency is achieved, thereby solving the technical problem of unsatisfactory data processing efficiency in the related technology.

[0089] Figure 4 is a flowchart of another optional data processing method provided according to an embodiment of the present invention. Figure 4 As shown, the method comprises the following steps:

[0090] Step S402, the programmable logic PL side responds to the data collection instruction of the processing system PS side, and stores the collected data in the target cache according to the data type of the collected data, wherein the target cache belongs to the PL side, and the target cache corresponds to the data type; when the target cache is full, the collected data is stored in the target memory area according to the data type, wherein the target memory area belongs to the memory space mounted by the PS side, and the target memory area corresponds to the data type;

[0091] Step S404, the PS end reads the collected data stored in the target memory area; and is used to parse the collected data to obtain parsed data;

[0092] Step S406, in response to receiving the parsed data, the PL terminal uses the target model to process based on the parsed data to obtain an abnormality recognition result;

[0093] Step S408: In response to receiving the abnormality identification result, the PS side determines an abnormality handling strategy based on the abnormality identification result.

[0094] It can be understood that after the PL side receives the data collection instruction from the PS side, the PL side will start to collect the corresponding data according to the data type specified in the instruction. The collected data is first stored in a target cache inside the PL side, and the target cache is set corresponding to the data type. When the target cache reaches its storage capacity limit, the PL side will automatically or according to preset rules transfer the collected data in the target cache to a target memory area in the memory space mounted on the PS side according to the data type. This target memory area is also determined according to the data type to ensure that the collected data of the data type can be stored correctly for subsequent processing.

[0095] The PS side is used to confirm that there is data available for reading in the target memory area. The PS side will perform a read operation and take the collected data out of the target memory area. After reading the collected data, the PS side will parse the collected data. The parsing process may include operations such as data format conversion, error checking, and field extraction to generate parsed data that is easy to understand and process. After receiving the parsed data from the PS side, the PL side is used to process the collected data using the target model, identify anomalies in the collected data, and generate corresponding anomaly identification results. After receiving the anomaly identification results from the PL side, the PS side will determine the appropriate exception handling strategy based on these results, which may include alarm notification, data re-collection, equipment restart, fault isolation, and other measures.

[0096] Through the above step S402, the programmable logic PL side responds to the data collection instruction of the processing system PS side, and stores the collected data in the target cache according to the data type of the collected data, wherein the target cache belongs to the PL side, and the target cache corresponds to the data type; when the target cache is full, the collected data is stored in the target memory area according to the data type, wherein the target memory area belongs to the memory space mounted by the PS side, and the target memory area corresponds to the data type; step S404, the PS side reads the collected data stored in the target memory area; used to parse the collected data to obtain parsed data; step S406, the PL side responds to receiving the parsed data, based on the parsed data, uses the target model for processing to obtain an abnormality recognition result; step S408, the PS side responds to receiving the abnormality recognition result, and determines the abnormality handling strategy based on the abnormality recognition result. The purpose of reducing the delay of data processing and enhancing the ability to respond quickly to data abnormalities can be achieved, and the technical effect of improving data processing efficiency is achieved, thereby solving the technical problem of unsatisfactory data processing efficiency in related technologies.

[0097] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0098] A data processing system is also provided in an embodiment of the present invention. The data processing system provided in the embodiment of the present invention is introduced below.

[0099] Figure 5 is a structural block diagram of an optional data processing system provided according to an embodiment of the present invention, such as Figure 5 As shown, the system includes: a programmable logic PL end 502 provided by any of the above embodiments, and a processing system PS end 504 provided by any of the above embodiments.

[0100] As an optional embodiment, the data processing system further includes a communication module, which includes a remote communication part and a local communication part. The remote communication part transmits the collected data and data analysis results to the remote terminal via a mobile wireless network, and performs data storage, display, and subsequent model iterative optimization at the remote terminal. The local communication part transmits the collected data and data analysis results to the display system in the instrument skid at the well site via a wired or local wireless network for display.

[0101] Optionally, local communication transmission includes a wired network, or a wireless LAN network established based on a wireless access point AP, which transmits the collected data and the analyzed data to the local area, that is, to be displayed on the background system of the instrument skid. When a device failure is identified, the background in the instrument skid is connected to an alarm module to issue voice and sound and light alarms to remind the personnel of the instrument skid to confirm and handle the abnormality of the equipment failure.

[0102] Optionally, remote communication transmission is performed by means of a mobile wireless communication network device (i.e., a communication module, which may have a built-in mobile process card) for wireless data transmission, which is used for timely detection of equipment failures and optimization of fault diagnosis and analysis models. Figure 6 is a transmission logic diagram of an optional data processing system provided according to an embodiment of the present invention, such as Figure 6 As shown in the figure, due to the bandwidth limitation of mobile wireless communication, the application scenario cannot meet the real-time collected data. To complete the real-time remote data transmission, a large amount of collected data will be stored in the storage medium (such as a mobile hard disk) before the data transmission. Since the well site operation usually takes a break after a few hours of continuous operation, remote data transmission can continue based on the backup battery (without data collection).

[0103] As an optional embodiment, the data processing system further includes an alarm prompt module. The display system in the instrument skid is connected to the alarm prompt module. When data analysis determines that there is an equipment failure, a fault alarm prompt is issued. The alarm prompt includes voice and sound and light alarms, prompting the staff in the instrument skid to confirm and handle the equipment failure.

[0104] As an optional embodiment, the above-mentioned data processing system also includes a backup battery. When the well site is operating, the external AC power supply on the well site operation equipment will power the entire data acquisition system after AC to DC conversion. At this time, the backup battery will not power the system, but will be in a charging state. When it is detected that the well site operation is over and the external power supply is cut off, the backup battery will power the system. In order to reduce power consumption in other locations, for example, the PS end will send a stop status setting to the PL end at this time, and the PL end will stop running, leaving only the PS end and the above-mentioned communication module running to ensure that there is sufficient power for data transmission.

[0105] By setting the programmable logic PL terminal 502 provided in any of the above embodiments and the processing system PS terminal 504 provided in any of the above embodiments, the purpose of reducing the delay of data processing and enhancing the ability to respond quickly to data anomalies is achieved, and the technical effect of improving data processing efficiency is achieved, thereby solving the technical problem of unsatisfactory data processing efficiency in related technologies.

[0106] According to the above embodiments and optional embodiments, the present application also provides an optional implementation mode: Figure 7 is a schematic diagram of an optional data processing system provided according to an embodiment of the present invention, such as Figure 7 As shown, the data processing system used is a data acquisition and analysis system, which adopts the ZYNQ chip. The ZYNQ chip includes a PL end (FPGA) and a PS end (ARM). The main modules involved include a PL end, a PS end, a PL-PS end data interaction module, a communication module, and an alarm prompt module.

[0107] The PL side includes: data acquisition cache module and DMA control module. The data acquisition cache module is used to collect and cache data after the data passes through the A / D module. The data acquisition cache module communicates with the DMA control module through the AXI bus, and the data acquisition cache module transmits the cached data to the DMA control module. The DMA control module is used to receive data transmitted from the data acquisition cache module and perform data movement based on the DMA control logic. Data movement is to write the collected data into the DDR storage space through the DDR bus protocol for easy reading by the PS side.

[0108] The PS side is the main control module of the data processing system (also called the data acquisition system). Its functions include: controlling the state of the PL side; interacting with the PL side for control instructions, reading the collected data stored in the DDR; performing algorithm analysis and processing on the collected data, and realizing equipment fault diagnosis based on the processing results. The PS side is connected to the communication module for wired and wireless data transmission.

[0109] The data interaction module between the PL and PS ends includes: state setting, interrupt processing module and Bram_Ctrl interaction module of AXI. The state setting is through the AXI bus, and the PS end performs reset (reset data acquisition), start (start data acquisition), stop (end data acquisition) and other state settings on the PL end. The interrupt processing module is a DMA control module that transfers the specified amount of collected data to the DDR storage area. After the data is stored, it notifies the PS end by triggering the interrupt instruction, and the PS end reads the specified amount of collected data from the DDR. The Bram_Ctrl interaction module is used to perform information interaction of two-way control instructions through the Bram_Ctrl interaction module after the data acquisition starts, so as to realize the effective control of the data acquisition process by the PS end.

[0110] The communication module includes: remote communication part and local communication part. The remote communication part transmits the collected data and data analysis results to the remote terminal through the mobile wireless network, and the remote terminal stores and displays the data and performs iterative optimization of the subsequent model. The local communication part transmits the collected data and data analysis results to the display system in the instrument skid at the well site through wired and local wireless networks for display.

[0111] The alarm prompt module is connected to the display system in the instrument skid. When data analysis determines that there is equipment failure, a fault alarm prompt is issued. The alarm prompt includes voice and sound and light alarms, prompting the staff in the instrument skid to confirm and handle the equipment failure.

[0112] In order to facilitate the understanding of the entire data collection and analysis process, the following explanation is given:

[0113] 1. Data acquisition status setting: The PS end is initialized before the data acquisition system starts. The PS end sets the start state (starts data acquisition) of the PL end through the AXI bus, completes the initialization setting of the PL end and starts data acquisition.

[0114] During the data collection process, if the instrument skid backend or remote terminal wants to stop data collection, it can send a control command to the PS end through the communication module. The PS end executes the stop command and sets the stop state (ends data collection) to the PL end through the AXI bus. After the PL end executes the stop command, data collection stops.

[0115] During the data collection process, if the instrument skid backend or the remote terminal wants to reset data collection, it can send a control command to the PS side through the communication module. The PS side executes the reset command and sets the reset state (reset data collection) of the PL side through the AXI bus. The PL side executes the reset command to clear the buffer data, initialize the settings, and restart data collection.

[0116] 2. Data acquisition cache. In the data acquisition process based on ZYNQ, the data acquisition cache module uses the powerful hardware programmable performance advantage of the FPGA on the PL side to collect data collected by various sensors. These data can be analog signals or digital signals. The digital signals collected after A / D conversion can be vibration signals, key phase signals, etc. FIFO cache is used to cache the data.

[0117] The cache creation on the PL side is controlled by the PS side. For ease of understanding, the cache creation process is illustrated by an example, for example: two buffer (cache) storage spaces are created for data caching, and the collected A / D converted data (i.e., collected data) is pushed into buffer1 (i.e., the target cache) for cache. When buffer1 is full, the collected data is continued to be stored in buffer2 (i.e., the next cache). At this time, the full data stored in buffer1 is converted into an AXI transmittable format and transmitted to the DMA control module via the AXI bus. The above process is continued, that is, one buffer stores data, and the other full buffer data is transmitted to the DMA control module via the AXI bus. Multiple buffers are created to improve efficiency. The number of buffers (i.e., the total number of multiple caches) can be increased during actual use.

[0118] For each buffer, the size of memory space allocated is used for storage. Taking pulse data collection as an example, the data volume of multiple sensors of the same data type with a specified pulse number is specified. For example, 8 vibration signal collection sensors are used for data collection. In one pulse (i.e., data cycle), each sensor transmits 4 bytes of data (i.e., the amount of collected data) to the data collection cache module. A buffer needs to store the data volume of 32 pulses. Then it can be calculated that the space required to allocate a buffer is 1K. It can be set to the memory space size corresponding to other pulse numbers according to specific needs. As the above group of buffers has two (i.e., multiple caches), a group of buffers can also choose a number greater than or equal to 2.

[0119] The total number of buffers corresponding to different data types, that is, the number of buffers can be determined in the following way. When data of multiple data types are collected simultaneously, the number of buffers is the number of types of data types multiplied by the number of buffers in a group (that is, multiple buffers of the same data type, which is set to 2 in this example). For example, when collecting data of two data types, vibration signal and key phase signal, at the same time, the total number of buffers corresponding to different data types is allocated as 2*2 (that is, 4), where every two buffers are multiple buffers of the same data type, as a group of buffers (such as buffer1 and buffer2), one group of data buffers for vibration signals are written and read and sent to the DMA control module, and the other group of buffers (such as buffer3 and buffer4) are used for data buffers for key phase signals are written and read and sent to the DMA control module.

[0120] 3. DMA data transmission: In order to improve data transmission efficiency, DMA technology is used to achieve high-speed data transmission. DMA can directly access the memory without CPU involvement, which can greatly improve the data transmission speed. After receiving the data transmitted by the data acquisition cache module, DMA stores the data to the DDR memory plug-in on the PS side via the DDR address bus protocol.

[0121] (1) DDR memory allocation. The PS side allocates memory to the area according to the mounted memory space DDR. The memory area (also called channel) of the memory space can be allocated in the following way. The storage space of each memory area in DDR can be an integer multiple of the buffer storage space in the data acquisition cache module, that is, the total number of caches corresponding to different data types. For example, the memory space allocated to each buffer is 1K, and each memory space in DDR is allocated 8M (megabytes). The above specific configuration can be adjusted according to specific needs to minimize the frequency of the PS side reading data from DDR. This is because the interaction delay between the PS side and DDR is large, and repeated data reading will reduce the efficiency of data processing.

[0122] The FIFO mode is used for data writing and reading in the memory space DDR. The DMA control module on the PL side writes the collected data into a memory area corresponding to the data type in the DDR, and the PS side reads the collected data from the corresponding memory area.

[0123] The total number of memory areas (i.e., the number of channels) in the above-mentioned DDR can be determined in the following manner, for example: the number of channels is equal to the number of data types, multiplied by the number of memory areas allocated to a single data type. For example, in this example, two data types (vibration signals and key phase signals) are used, and three memory areas are allocated to the collected data of one data type. The total number of memory areas for different data types is 2*3=6.

[0124] (2) The process of DMA module writing data to DDR. For the case of collecting only one data type, according to the above example, DDR allocates three memory spaces for this data type, namely memory spaces 1, 2, and 3. The DMA control module stores the collected data in memory space 1. When memory space 1 is full, it stores it in memory space 2. The predetermined memory order is shown as memory areas 1, 2, 3, 1, 2..., and a loop traversal is executed.

[0125] In the case of collecting multiple data types, a flag bit is added when a memory area is opened for each data type. It can be a certain bit or several bits in the storage space, which is used for the data full flag bit (i.e., the flag bit). When the corresponding memory space is full, the data full flag bit will be set, such as set to 1. For ease of understanding, examples and explanations are given. For example, when collecting data of two data types, namely vibration signals and key phase signals, the memory space DDR allocates 6 memory areas, memory areas 1, 2, and 3 are used to store vibration signals, and memory areas 4, 5, and 6 are used to store key phase signals. The DMA control module stores the vibration signal data (corresponding to the data in buffer 1 and buffer 2 in the data acquisition cache module) in memory area 1. When memory area 1 is full, it will be stored in the storage space of memory area 2. The predetermined memory order is memory area 1, 2, 3, 1, 2..., and it is traversed in a loop.

[0126] The DMA module stores the key phase signal (data in buffer 3 and buffer 4 in the data acquisition cache module) data in memory area 4. When memory area 4 is full, it will be stored in memory area 5, and the memory areas will be traversed in a loop according to the predetermined memory order of memory areas 4, 5, 6, 4, 5...

[0127] (3) Triggering the interrupt process: After the DMA control module writes a full memory area into the DDR, the PL side notifies the PS side by triggering an interrupt, and the PS side performs data movement, that is, the PS side reads all the data in the memory area in the DDR that is full of data.

[0128] In the case of collecting only one type of data, after receiving the trigger interrupt, the PS end reads the full channel data according to the number sequence of the memory area. For example, three memory areas are allocated in DDR to store collected data, namely memory areas 1, 2, and 3. When the PS end receives the trigger interrupt for the first time, it indicates that the memory area 1 is full of data. The PS end reads all the data in the memory area 1 and erases the data in the memory area 1. When the trigger interrupt is received again, it indicates that the memory area 2 is full of data, and so on.

[0129] For the case of collecting multiple data types, a flag bit is added when each memory area is opened. It can be a certain bit or several bits in the storage space recorded as the flag bit. The same data type selects the suspected full area according to the numbering order of the memory area. For example: memory areas 1, 2, and 3 store vibration signals, and memory areas 4, 5, and 6 store key phase signals. When the PS end receives the trigger interrupt at the beginning, it may be that the vibration signal stored in memory area 1 is full, or it may be that the key phase signal stored in memory area 4 is full. Memory area 1 and memory area 4 are regarded as suspected full. For memory areas of suspected full data of different data types, which memory areas are full of data are determined according to the flag bit. That is, the PS end confirms the data full flag bit of memory area 1 and memory area 4. When the data full flag bit is set to a predetermined value, such as set to 1, it means that the data in the memory area is full. The PS end reads the data in the memory area and then erases the data. After the reading is completed, the data full flag bit is set to another predetermined value, such as set to 0. The PS end increases the memory area number sequence of the vibration signal by 1, that is, the next time the PS end receives a trigger interrupt, it uses memory area 2 and memory area 4 as suspected full areas, and further confirms which memory area is full based on the flag bit, and so on.

[0130] (5) Data analysis: After the PS reads the collected data, it analyzes the data. The data of different data types and different sensors are analyzed in the order of collection. The analyzed data is used for fault diagnosis and analysis. The fault diagnosis and analysis model (i.e., the target model) can be deployed on the PS side, or the fault diagnosis model can be deployed on the PL side due to the fast computing speed of the PL side.

[0131] PL-side model initialization and parameter setting: Based on the communication between the PS and PL ends of the Bram_Ctrl interaction module, the PS end sends a model initialization instruction to the PL end, which can set the model parameters. It can also set relevant parameters according to the control instructions of the remote terminal or the background of the instrument skid.

[0132] Allocate DDR space: The PS end temporarily opens a transmission channel on the DDR for the data used for data analysis on the PL end (i.e., parsed data). After the PS end writes the data required for analysis into the opened DDR channel, the PS end transmits a read data instruction to the PL end. After receiving the read data instruction, the PL end reads the data required for analysis from the specified DDR channel and stores it in the FIFO storage area. If the data required for analysis can only be completed through multiple transmissions through the DDR channel, the PS end sends a read instruction to the PL end each time it writes the data required for analysis into the specified DDR channel. After receiving the read completion information from the PL end, the PS end continues to write the data required for analysis into the DDR until the data required for analysis is transmitted from the PS end to the PL end. The PS end sends a data transmission completion instruction to the PL end. After the data transmission is completed, the PS end destroys the channel memory opened for the data transmission required for analysis.

[0133] Model reasoning: After the PL receives the data completion instruction, it uses the trained target model to perform model reasoning for fault diagnosis based on the data required for analysis. After calculating the reasoning result, it communicates with the PS side through the Bram_Ctrl interaction module to inform the PS side of the completion of the calculation and the memory size required to transmit the calculation result. After the PS side has opened the specified channel memory on the DDR, it sends the channel address number of the memory opened and the instruction requiring the PL side to send the calculation result to the PL side through the Bram_Ctrl interaction module. The PL side writes the calculation result (i.e., the abnormal identification result) to the DDR and informs the PS side through the Bram_Ctrl module. The PS side reads the data in the instruction channel memory (i.e., the abnormal identification result) and releases the opened memory after reading.

[0134] 6. Communication: The collected data and analyzed data are transmitted through data communication as needed. Data transmission includes local communication transmission and remote communication transmission. Local communication transmission includes wired network or wireless LAN network established based on wireless access point AP, which transmits the collected data and analyzed data to the local, that is, the backend system of the instrument skid for display. When the equipment failure is identified, the backend in the instrument skid is connected to the alarm module, and voice and sound and light alarms are issued to remind the personnel of the instrument skid to confirm and handle the abnormal equipment failure.

[0135] Remote communication transmission is wireless data transmission with the help of mobile wireless communication network equipment (i.e. communication module, which can have built-in mobile process card), which is used to timely discover equipment failures and optimize fault diagnosis and analysis models. Due to the bandwidth limitation of mobile wireless communication, the application scenario cannot meet the real-time collected data. To complete the real-time remote data transmission, a large amount of collected data will be stored in the storage medium (such as mobile hard disk) before data transmission. Since well site operations usually take a break after several hours of continuous operation, remote data transmission can continue based on the backup battery (without data collection).

[0136] There are two power supply modes for the entire data acquisition system. One is the external AC power supply on the well site operation equipment, which powers the entire data acquisition system after AC to DC conversion. The other is to use a backup battery. When the well site is operating, the backup battery will not power the data acquisition system, but will be in a charging state. When it is detected that the well site operation is over and the external power supply is cut off, the backup battery will power the data acquisition system. In order to reduce power consumption in other locations, the PS end will send a stop status setting to the PL end at this time, and the PL end will stop running, leaving only the PS and communication module running.

[0137] When the PS side obtains data, it determines whether to transmit directly. The standard for direct transmission can be distinguished according to the amount of data. The amount of collected data is generally large, and the amount of calculated equipment fault information is generally small. Fault information data with a small amount of data does not need to be stored in the storage medium in sequence waiting for transmission. After obtaining the fault information data, it is directly transmitted to the remote terminal via the wireless communication module. The collected data with a large amount of data is written into the storage medium. When the PS side detects that the communication module is idle, it transmits data through the communication module; when the PS side detects that the communication module is not idle, it waits for the next query cycle to transmit data.

[0138] Through the above processing, the control logic of inter-core communication between the PL and PS ends for data acquisition, the writing and reading logic of the DDR storage area for various data types, and the communication transmission logic in the mobile wireless scenario with limited bandwidth are set up, which effectively solves the problems caused by the independent operation of multiple devices in the well site operation, improves the stability and reliability of data acquisition, analysis and communication, and provides a strong guarantee for the safe production of the well site operation.

[0139] In this embodiment, a data processing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the terms "module" and "device" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0140] According to an embodiment of the present invention, there is also provided an apparatus embodiment for implementing the data processing method. Figure 8 is a schematic diagram of an optional data processing device according to an embodiment of the present invention. Figure 8 As shown, the above-mentioned data processing device includes: a data acquisition module 802, a transfer module 804, and a model processing module 806. The device is described below.

[0141] The data acquisition module 802 is used to respond to the data acquisition instruction of the processing system PS end and store the collected data into the target cache according to the data type of the collected data, wherein the target cache belongs to the programmable logic PL end and the target cache corresponds to the data type;

[0142] The transfer module 804 is connected to the data acquisition module 802 and is used to store the collected data to the target memory area according to the data type when the target cache is full, wherein the target memory area belongs to the memory space mounted on the PS end, and the target memory area corresponds to the data type;

[0143] The model processing module 806 is connected to the transfer module 804, and is used to respond to the received parsed data and, based on the parsed data, use the target model to process to obtain an exception recognition result, wherein the parsed data is obtained by parsing the collected data on the PS side, and the target model is obtained by performing training on the PL side. The target model matches the data type, and the PS side is used to generate an exception handling strategy based on the exception recognition result.

[0144] In a data processing device provided by an embodiment of the present invention, a data acquisition module 802 is set to respond to the data acquisition instruction of the processing system PS end, and the collected data is stored in the target cache according to the data type of the collected data, wherein the target cache belongs to the programmable logic PL end, and the target cache corresponds to the data type; a transfer module 804 is connected to the data acquisition module 802, and is used to store the collected data in the target memory area according to the data type when the target cache is full, wherein the target memory area belongs to the memory space mounted by the PS end, and the target memory area corresponds to the data type; a model processing module 806 is connected to the transfer module 804, and is used to respond to the received parsed data, and based on the parsed data, use the target model for processing to obtain an abnormal recognition result, wherein the parsed data is obtained by the PS end parsing the collected data, the target model is obtained by performing training on the PL end, the target model matches the data type, and the PS end is used to generate an abnormality processing strategy based on the abnormal recognition result. The purpose of reducing the delay of data processing and enhancing the ability to respond quickly to data anomalies is achieved, thereby solving the technical problem of unsatisfactory data processing efficiency in the related art.

[0145] It should be noted that the above modules can be implemented by software or hardware. For example, for the latter, it can be implemented in the following ways: the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0146] It should be noted that the data acquisition module 802, the transfer module 804, and the model processing module 806 correspond to steps S102 to S106 in the embodiment, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiment. It should be noted that the modules as part of the device can be run in a computer terminal.

[0147] It should be noted that the optional or preferred implementation of this embodiment can refer to the relevant description in the embodiment, which will not be repeated here.

[0148] The above-mentioned data processing device may also include a processor and a memory. The data acquisition module 802, the transfer module 804, the model processing module 806, etc. are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize the corresponding functions.

[0149] The processor includes a kernel, which retrieves the corresponding program unit from the memory. There can be one or more kernels. The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one storage chip.

[0150] An embodiment of the present invention provides a non-volatile storage medium on which a program is stored. When the program is executed by a processor, a data processing method is implemented.

[0151] An embodiment of the present invention provides an electronic device, which includes a processor, a memory, and a program stored in the memory and can be run on the processor. When the processor executes the program, the following steps are implemented: in response to a data acquisition instruction of a processing system PS end, the collected data is stored in a target cache according to the data type of the collected data, wherein the target cache belongs to the programmable logic PL end, and the target cache corresponds to the data type; when the target cache is full, the collected data is stored in a target memory area according to the data type, wherein the target memory area belongs to the memory space mounted on the PS end, and the target memory area corresponds to the data type; in response to receiving parsed data, based on the parsed data, a target model is used for processing to obtain an abnormal recognition result, wherein the parsed data is obtained by the PS end parsing the collected data, the target model is obtained by training performed on the PL end, the target model matches the data type, and the PS end is used to generate an abnormality handling strategy based on the abnormality recognition result. The device in this article can be a server, a PC, etc.

[0152] The present invention also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program that is initialized with the following method steps: in response to a data acquisition instruction at a processing system PS end, the acquired data is stored in a target cache according to the data type of the acquired data, wherein the target cache belongs to a programmable logic PL end, and the target cache corresponds to the data type; when the target cache is full, the acquired data is stored in a target memory area according to the data type, wherein the target memory area belongs to a memory space mounted on the PS end, and the target memory area corresponds to the data type; in response to receiving parsed data, based on the parsed data, a target model is used for processing to obtain an exception recognition result, wherein the parsed data is obtained by parsing the acquired data at the PS end, the target model is obtained by training at the PL end, the target model matches the data type, and the PS end is used to generate an exception handling strategy based on the exception recognition result.

[0153] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0154] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0155] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0157] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0158] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0159] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0160] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0161] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0162] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A data processing method, characterized in that: include: In response to a data collection instruction from a processing system PS, storing the collected data in a target cache according to a data type of the collected data, wherein the target cache belongs to a programmable logic PL, and the target cache corresponds to the data type; When the target cache is full, storing the collected data in a target memory area according to the data type, wherein the target memory area belongs to the memory space mounted by the PS end, and the target memory area corresponds to the data type; In response to receiving the parsed data, a target model is used for processing based on the parsed data to obtain an exception recognition result, wherein the parsed data is obtained by the PS end parsing the collected data, the target model is obtained by performing training on the PL end, the target model matches the data type, and the PS end is used to generate an exception handling strategy based on the exception recognition result.

2. The method according to claim 1, characterized in that The method further comprises: Acquire training data sent by the PS end, wherein a type of the training data matches the data type, and the training data is obtained by the PS end based on parsing historical data; Based on the training data, training is performed on the initial model deployed on the PL end to obtain the target model.

3. The method according to claim 1, characterized in that The cache space of the PL end includes a plurality of caches, the plurality of caches correspond to the data type, the target cache is one of the plurality of caches, and the method further includes: When the target cache is full, new collected data is stored in a next cache in a predetermined cache order, wherein the next cache is a cache after the target cache among the multiple caches, wherein the multiple caches are configured based on the data period and the amount of collected data.

4. The method according to claim 1, characterized in that: The memory space mounted on the PS end includes multiple memory areas, the multiple memory areas correspond to the data types, the target memory area is one of the multiple memory areas, and the method further includes: When the target memory area is full, new collected data is stored in a next memory area according to a predetermined memory order, wherein the next memory area is a memory area after the target memory area among the multiple memory areas, wherein the multiple memory areas are configured based on the data reading latency of the PS end.

5. The method according to any one of claims 1 to 4, characterized in that: The PL end also includes a direct memory access DMA control module, and the DMA control module is used for the PL end to interact with the memory space mounted on the PS end.

6. The method according to claim 5, characterized in that According to the data type, storing the collected data into a target memory area includes: Using the DMA control module, according to the data type, the collected data is stored from the target cache to the target memory area; When the target memory area is fully stored, a trigger interrupt instruction is sent to the PS end, wherein the trigger interrupt instruction is used to instruct the PS end to read the collected data in the target memory area.

7. A data processing method, characterized in that: include: Reading the collected data stored in the target memory area, wherein the target memory area belongs to the memory space mounted on the PS side of the processing system, the target memory area corresponds to the data type of the collected data, and the collected data is stored in the target memory space by the target cache according to the data type when the target cache is full, the target cache belongs to the programmable logic PL side, the target cache corresponds to the data type, and the PL side is used to respond to the data collection instruction of the PS side and store the collected data in the target cache according to the data type; Parsing the collected data to obtain parsed data; In response to receiving the abnormality identification result, an abnormality handling strategy is determined based on the abnormality identification result.

8. The method according to claim 7, characterized in that The memory space mounted on the PS end includes multiple memory areas, the multiple memory areas correspond to the data types, the target memory area is one of the multiple memory areas, and before reading the collected data stored in the target memory area, the method further includes: receiving a trigger interrupt instruction sent by the PL terminal, and determining the flag bit states corresponding to the multiple memory areas respectively; A memory area in which a flag bit state is a predetermined value is determined among the multiple memory areas as the target memory area.

9. A data processing method, characterized in that: include: The programmable logic PL side responds to the data collection instruction of the processing system PS side, and stores the collected data in a target cache according to the data type of the collected data, wherein the target cache belongs to the PL side, and the target cache corresponds to the data type; when the target cache is full, the collected data is stored in a target memory area according to the data type, wherein the target memory area belongs to the memory space mounted by the PS side, and the target memory area corresponds to the data type; The PS end reads the collected data stored in the target memory area; parses the collected data to obtain parsed data; In response to receiving the parsed data, the PL terminal processes the parsed data using a target model to obtain an abnormality recognition result; In response to receiving the abnormality identification result, the PS terminal determines an abnormality handling strategy based on the abnormality identification result.

10. A data processing system, characterized in that: include: A programmable logic PL side that applies the data processing method described in any one of claims 1 to 6, and a processing system PS side that applies the data processing method described in claim 7 or 8.

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