A processing method and system for metal-based thermoelectric integrated PCB board

Abstract

The present invention relates to the technical field of circuit boards, and a processing method and system for a metal-based thermoelectric integrated PCB board, comprising: obtaining a set of simulated components corresponding to the business requirements of the PCB board; using a PCB board layout generator pre-constructed in the generative adversarial PCB board layout model to perform feature extraction and PCB layout operations based on a genetic algorithm on the set of simulated components to obtain a primary PCB layout structure diagram; using a layout evaluation discriminator pre-constructed in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram to obtain an index score set; when the comprehensive score is greater than a qualified threshold, the final optimized primary PCB layout structure diagram is used as a target PCB layout diagram, and a PCB board processing operation is performed according to the target PCB layout diagram to obtain a target PCB board corresponding to the business requirements of the PCB board. The present invention can solve the problems of unreasonable PCB board layout and uneven heat dissipation performance.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and in particular to a processing method and system for a metal-based thermoelectric integrated PCB board. Background Art

[0002] In modern electronic devices, thermal management and optimization of electrical performance have become key factors. As the integration of electronic components continues to increase, heat dissipation issues become more and more prominent, resulting in reduced device performance and shortened lifespan. In this context, metal-based thermoelectric integrated PCB boards, as a new type of heat dissipation solution, have gradually attracted widespread attention.

[0003] Metal-based PCBs have excellent thermal conductivity and electrical insulation, which can effectively reduce thermal resistance and improve heat dissipation efficiency. At the same time, the versatility of its structure enables it to not only provide electrical connections, but also achieve thermal energy conversion through the thermoelectric effect. However, existing metal-based PCBs generally face problems such as unreasonable layout and uneven heat dissipation performance during design and processing. These problems not only affect the overall performance of the PCB, but also restrict its application in high-power electronic devices. Summary of the invention

[0004] The present invention provides a processing method and system for a metal-based thermoelectric integrated PCB board, the main purpose of which is to solve the problems of unreasonable PCB board layout and uneven heat dissipation performance.

[0005] To achieve the above object, the present invention provides a method for processing a metal-based thermoelectric integrated PCB board, comprising:

[0006] According to the pre-built PCB board business requirements, a set of electronic components is screened and obtained, and a simulation component of the set of electronic components is obtained to obtain a simulation component set;

[0007] Using a pre-trained generative adversarial PCB layout model, feature extraction is performed on the set of simulated components to obtain a set of component feature sequences;

[0008] Using the pre-built PCB layout generator in the generative adversarial PCB layout model to perform a genetic algorithm-based PCB layout operation on the component feature sequence set to obtain a primary PCB layout structure diagram;

[0009] Using the layout evaluation discriminator pre-built in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index scoring set, and obtain a comprehensive score of the index scoring set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance;

[0010] Determining whether the comprehensive score is greater than a preset qualified threshold;

[0011] When the comprehensive score is less than or equal to the qualified threshold, returning to the step of performing a genetic algorithm-based PCB layout operation on the component feature sequence set using the PCB layout generator pre-constructed in the generative adversarial PCB layout model, and iteratively optimizing the primary PCB layout structure diagram using the PCB layout generator according to the indicator score set corresponding to the comprehensive score;

[0012] When the comprehensive score is greater than the qualified threshold, the final optimized primary PCB layout structure diagram is used as the target PCB layout diagram, and a PCB board processing operation is performed according to the target PCB layout diagram to obtain a target PCB board corresponding to the PCB board business demand.

[0013] Optionally, the electronic component set is screened and obtained according to the pre-built PCB board business requirements, including:

[0014] Perform text quantification on the pre-built PCB board business requirements to obtain a word segmentation vector set;

[0015] Performing semantic recognition on the word segmentation vector set to obtain a business intent label set;

[0016] From a pre-built technical product database, filter the electronic component set corresponding to the business intent tag set.

[0017] Optionally, the acquiring the simulation component of the electronic component set to obtain the simulation component set includes:

[0018] Determining the types of electronic components in the electronic component set;

[0019] When the electronic component is a linear component, a parameter set of the electronic component is queried using a pre-built technical manual, and a simulation component is constructed according to the parameter set;

[0020] When the electronic component is a nonlinear component, the electronic component is simulated using a current-voltage characteristic curve to obtain a simulated component.

[0021] Optionally, before using the PCB layout generator pre-built in the generative adversarial PCB layout model to perform a genetic algorithm-based PCB layout operation on the component feature sequence set, the method further includes:

[0022] Obtain a generative adversarial PCB layout model including a PCB layout generator and a layout evaluation discriminator, and obtain a training sample set including historical business requirements-manual PCB layout-manual evaluation labels;

[0023] Extracting a training sample from the training sample set in turn, sending the training sample to the generative adversarial PCB layout model, and using the PCB layout generator to perform a forward network layout calculation based on thermal and electrical balance on the training sample to obtain a predicted PCB layout;

[0024] Using the layout evaluation discriminator, the predicted PCB layout is evaluated to obtain a predicted layout evaluation result, and the manual PCB layout is evaluated to obtain a label layout evaluation result;

[0025] According to the predicted layout evaluation result, a fitness function of the predicted PCB layout is obtained, and according to the fitness function, the PCB board layout generator is optimized to obtain an updated PCB board layout generator;

[0026] According to a pre-constructed cross entropy loss algorithm and the manual evaluation labels of the training samples, a first loss value of the predicted layout evaluation result and a second loss value of the label layout evaluation result are calculated, and the sum of the first loss value and the second loss value is calculated to obtain a discriminator loss value;

[0027] According to the pre-built gradient descent algorithm and the discriminator loss value, the network reverse parameter update of the layout evaluation discriminator is performed to obtain an updated layout evaluation discriminator;

[0028] Determining whether the discriminator loss value converges;

[0029] When the discriminator loss value has not converged, return to the above step of extracting one training sample from the training sample set in turn, and iteratively update the updated PCB board layout generator and the updated layout evaluation discriminator;

[0030] When the discriminator loss value converges, the training process is stopped to obtain a trained generative adversarial PCB board layout model.

[0031] Optionally, the fitness function is expressed as:

[0032] F G =D(G(z))

[0033] In the formula, F G represents the fitness function, G represents the PCB layout generator, G(·) represents the layout calculation function of the PCB layout generator, D(·) represents the evaluation calculation function of the layout evaluation discriminator, D(·) includes but is not limited to the thermoelectric balance loss function and the characteristic impedance loss function, and z represents the historical business demand of the training sample.

[0034] Optionally, the discriminator loss value is expressed as:

[0035]

[0036] Where, L D represents the discriminator loss value, D represents the layout evaluation discriminator, represents the second loss value, represents the first loss value, x real represents the artificial PCB layout of the training sample.

[0037] Optionally, the PCB layout generator pre-built in the generative adversarial PCB layout model is used to perform a genetic algorithm-based PCB layout operation on the component feature sequence set to obtain a primary PCB layout structure diagram, including:

[0038] Using the pre-built PCB layout generator in the generative adversarial PCB layout model to randomly splice the component feature sequence set to obtain various random PCB layouts;

[0039] Calculating the fitness value of the random PCB layout, and selecting the random PCB layout with a fitness value greater than a preset threshold as the parent layout, to obtain a parent layout set;

[0040] Performing a crossover operation based on component position exchange on the parent layout set to obtain a child layout set;

[0041] Performing a mutation operation on the descendant layout set based on random changes in component positions and connection modes to obtain a mutant layout set;

[0042] Using the variant layout set, the parent layout set is merged and updated to obtain an optimized parent layout set;

[0043] Determine whether the number of layouts in the parent layout set is less than a preset retention threshold, wherein the retention threshold may be one or more;

[0044] When the number of layouts in the parent layout set is greater than or equal to the retention threshold, return to the above step of calculating the fitness value of the random PCB layout, and update the parent layout set;

[0045] When the number of layouts in the parent layout set is less than the retention threshold, the parent layout set is output to obtain a primary PCB layout structure diagram.

[0046] Optionally, the layout evaluation discriminator pre-built in the generative adversarial PCB board layout model is used to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram to obtain an index scoring set, including:

[0047] Using the pre-built layout evaluation discriminator in the generative adversarial PCB board layout model to perform feature recognition on the primary PCB layout structure diagram, and obtain a component feature set and a connection relationship feature sequence set;

[0048] Performing a binary classification operation of characteristic impedance characteristics on the connection relationship characteristic sequence set to obtain a microstrip line characteristic impedance and a stripline characteristic impedance;

[0049] Obtaining characteristic impedance formulas of the microstrip line characteristic impedance and the stripline characteristic impedance, substituting the component feature set into the characteristic impedance formula to obtain a layout characteristic impedance value, and calculating an impedance normalization result of the layout characteristic impedance value;

[0050] Performing an evaluation operation based on preset thermoelectric indicators on the component feature set and the connection relationship feature sequence set to obtain an evaluation score sequence, and performing weighted calculation on the evaluation score sequence to obtain a thermoelectric balance score;

[0051] The impedance normalization result and the thermoelectric balance score are uniformly output to obtain an index score set.

[0052] Optionally, the layout characteristic impedance value is expressed as:

[0053] Z comblined =α·Z miter +(1-α)·Z strip

[0054]

[0055] In the formula, Z comblined Represents the layout characteristic impedance value, Z miter represents the characteristic impedance of the microstrip line, Z strip represents the stripline characteristic impedance, e r represents the relative dielectric constant, H represents the dielectric thickness, W represents the wire width, and T represents the wire thickness, wherein H, W and T are all in the component feature set, and α represents a weight coefficient between 0 and 1.

[0056] To achieve the above object, the present invention also provides a processing system for a metal-based thermoelectric integrated PCB board, comprising:

[0057] A component acquisition module is used to screen and obtain an electronic component set according to pre-built PCB board business requirements, and obtain simulation components of the electronic component set to obtain a simulation component set, and use a pre-trained generative adversarial PCB board layout model to extract features from the simulation component set to obtain a component feature sequence set;

[0058] A PCB layout module is used to perform a genetic algorithm-based PCB layout operation on the component feature sequence set using a PCB layout generator pre-built in the generative adversarial PCB layout model to obtain a primary PCB layout structure diagram;

[0059] A layout evaluation module, used to use the layout evaluation discriminator pre-constructed in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index score set, and obtain a comprehensive score of the index score set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance, and to determine whether the comprehensive score is greater than a preset qualified threshold, and when the comprehensive score is less than or equal to the qualified threshold, return to the above-mentioned step of using the PCB board layout generator pre-constructed in the generative adversarial PCB board layout model to perform a PCB layout operation based on a genetic algorithm on the component feature sequence set, and use the PCB board layout generator to iteratively optimize the primary PCB layout structure diagram according to the index score set corresponding to the comprehensive score;

[0060] The PCB board processing module is used to use the final optimized primary PCB layout structure diagram as the target PCB layout diagram when the comprehensive score is greater than the qualified threshold, and perform PCB board processing operations according to the target PCB layout diagram to obtain the target PCB board corresponding to the PCB board business demand.

[0061] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising:

[0062] a memory storing at least one instruction; and

[0063] The processor executes the instructions stored in the memory to implement the above-mentioned method for processing the metal-based thermoelectric integrated PCB board.

[0064] In order to solve the above problems, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned metal-based thermoelectric integrated PCB board processing method.

[0065] The present invention is to solve the problem described in the background technology. The present invention first obtains the business demand of the PCB board. According to the business demand of the PCB board, the information such as the types and quantities of components required by the PCB board can be understood, and a set of electronic components can be obtained; in the embodiment of the present invention, in order to ensure that the electronic components can be better feature extracted, such as more complex features such as electrical characteristics, the components are processed by simulation; further, the present invention performs layout by generating an adversarial PCB board layout model to obtain a primary PCB layout structure diagram; wherein the generated adversarial PCB board layout model is a generated adversarial network, the layout part adopts a genetic algorithm for optimization, and the layout evaluation discriminator part adopts two aspects of thermoelectric balance and characteristic impedance to evaluate the primary PCB layout structure diagram, thereby further improving the layout superiority of the genetic algorithm, and finally obtaining a target PCB layout diagram, thereby using the processing process to obtain a target PCB board corresponding to the business demand of the PCB board. Therefore, the present invention can solve the problems of unreasonable PCB board layout and uneven heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 A schematic flow chart of a method for processing a metal-based thermoelectric integrated PCB board provided in one embodiment of the present invention;

[0067] Figure 2 A functional module diagram of a metal-based thermoelectric integrated PCB board processing system provided by an embodiment of the present invention;

[0068] Figure 3 A schematic structural diagram of an electronic device for implementing the method for processing the metal-based thermoelectric integrated PCB board provided in one embodiment of the present invention.

[0069] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0070] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0071] The embodiment of the present application provides a method for processing a metal-based thermoelectric integrated PCB board. The execution subject of the method for processing the metal-based thermoelectric integrated PCB board includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided in the embodiment of the present application. In other words, the method for processing the metal-based thermoelectric integrated PCB board can be executed by software or hardware installed in a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0072] Reference Figure 1FIG. 1 is a schematic diagram of a process flow of a method for processing a metal-based thermoelectric integrated PCB board provided by an embodiment of the present invention. In this embodiment, the method for processing a metal-based thermoelectric integrated PCB board includes:

[0073] S1. According to the pre-built PCB board business requirements, a set of electronic components is screened and a simulation component of the set of electronic components is obtained to obtain a simulation component set.

[0074] In the embodiment of the present invention, the PCB board business requirements include circuit design, size requirements, layer number requirements, substrate selection, production process, industry standards, etc.

[0075] In detail, in the embodiment of the present invention, the electronic component set is screened and obtained according to the pre-built PCB board business requirements, including:

[0076] Perform text quantification on the pre-built PCB board business requirements to obtain a word segmentation vector set;

[0077] Performing semantic recognition on the word segmentation vector set to obtain a business intent label set;

[0078] From a pre-built technical product database, filter the electronic component set corresponding to the business intent tag set.

[0079] The technical product database is a database that stores commonly used technical means in the industry and the technical means of the company's internal product models, for example, including: how many capacitors, how many resistors, and how many drilling processes are needed to achieve target A.

[0080] In an embodiment of the present invention, the PCB board business requirements are first segmented and quantized by a Chinese word segmentation tool to obtain a word segmentation vector set. Then, the contextual attention enhancement algorithm is used to sort the word segmentation vector set and add context features. Then, the enhanced word segmentation vector set is identified by semantic recognition to obtain an intention label set. Among them, the intention label set is such as [substrate selection: aluminum substrate, conductive material: copper, production process: etching, purpose: support complex circuits and high-frequency signals,...]. Then, in an embodiment of the present invention, the screening of electronic components is achieved by querying the technical product database to obtain an electronic component set. Among them, electronic components also include substrates.

[0081] It should be known that simulation is often used to verify the functionality and performance of a design to ensure that the layout can work properly in actual applications. For example, electrical characteristics, signal integrity, thermal analysis, etc. When designing PCBs, simulation can help designers identify and solve potential problems before final manufacturing.

[0082] In the embodiment of the present invention, the feature extraction capability of the generator is limited and may not be able to fully capture the electrical characteristics and physical constraints of the electronic components based on the names of the electronic components. Therefore, simulation is necessary.

[0083] In detail, in the embodiment of the present invention, the step of obtaining the simulation component of the electronic component set to obtain the simulation component set includes:

[0084] Determining the types of electronic components in the electronic component set;

[0085] When the electronic component is a linear component, a parameter set of the electronic component is queried using a pre-built technical manual, and a simulation component is constructed according to the parameter set;

[0086] When the electronic component is a nonlinear component, the electronic component is simulated using a current-voltage characteristic curve to obtain a simulated component.

[0087] Among them, the technical manual refers to a database consisting of the models, introductions, uses and principles of various components in the industry.

[0088] Specifically, in the embodiment of the present invention, the type of each electronic component is first determined. When encountering linear components, such as resistors, capacitors, and inductors, they can be directly constructed according to the parameters (such as resistance value, capacitance value, inductance, etc.) provided in the technical manual; when encountering nonlinear components, such as diodes, transistors, etc., more complex models are required, such as using current-voltage (IV) characteristic curves and other dynamic characteristics to complete the simulation.

[0089] S2. Using a pre-trained generative adversarial PCB layout model, extract features from the simulation component set to obtain a component feature sequence set.

[0090] In an embodiment of the present invention, the generative adversarial PCB layout model is a generative adversarial network, including a PCB layout generator and a layout evaluation discriminator. The PCB layout generator is a neural network based on a genetic algorithm, which is used to layout a set of simulation components selected by user needs and meet the layout monitoring of electric and thermal integration; the layout evaluation discriminator is a recognition network based on a neural network, which is used to evaluate the primary PCB layout structure diagram generated by the PCB layout generator based on two aspects of thermal and electrical balance and signal transmission performance.

[0091] In the embodiment of the present invention, a component feature sequence set is obtained through a feature extraction network in a PCB board layout generator through common feature extraction operations such as convolution, pooling, and flattening.

[0092] S3. Using the pre-built PCB layout generator in the generative adversarial PCB layout model, a genetic algorithm-based PCB layout operation is performed on the component feature sequence set to obtain a primary PCB layout structure diagram.

[0093] In detail, in an embodiment of the present invention, the PCB layout generator pre-built in the generative adversarial PCB layout model is used to perform a genetic algorithm-based PCB layout operation on the component feature sequence set to obtain a primary PCB layout structure diagram, including:

[0094] Using the pre-built PCB layout generator in the generative adversarial PCB layout model to randomly splice the component feature sequence set to obtain various random PCB layouts;

[0095] Calculating the fitness value of the random PCB layout, and selecting the random PCB layout with a fitness value greater than a preset threshold as the parent layout, to obtain a parent layout set;

[0096] Performing a crossover operation based on component position exchange on the parent layout set to obtain a child layout set;

[0097] Performing a mutation operation on the descendant layout set based on random changes in component positions and connection modes to obtain a mutant layout set;

[0098] Using the variant layout set, the parent layout set is merged and updated to obtain an optimized parent layout set;

[0099] Determine whether the number of layouts in the parent layout set is less than a preset retention threshold, wherein the retention threshold may be one or more;

[0100] When the number of layouts in the parent layout set is greater than or equal to the retention threshold, return to the above step of calculating the fitness value of the random PCB layout, and update the parent layout set;

[0101] When the number of layouts in the parent layout set is less than the retention threshold, the parent layout set is output to obtain a primary PCB layout structure diagram.

[0102] Specifically, in an embodiment of the present invention, a PCB board layout is performed by a genetic algorithm, and first an electrothermal balance index is defined to evaluate the electrothermal balance performance of the PCB board layout structure. The index can be calculated based on factors such as the power consumption, heat transfer characteristics, and board surface temperature distribution of components. It happens that the layout evaluation discriminator in this model has an evaluation function, so the result of the layout evaluation discriminator can be directly used as the fitness function of the genetic algorithm. Among them, the result of the fitness function is the fitness value, which reflects the individual's quality, and the larger the fitness value, the better.

[0103] The present invention performs a selection operation according to the fitness value, selects a part of excellent individuals as the parent generation, and obtains a parent generation layout set; then, a crossover operation is performed on the selected parent generation individuals to generate new individuals, i.e., a child generation layout set; then, the present invention performs a mutation operation on the newly generated individuals, introduces some randomness, and increases the diversity of individuals; then, the parent generation individuals and the newly generated individuals are combined into a new population, and the above process is repeated to continuously screen the parent generation and update the parent generation layout set. When the number of layouts in the parent generation layout set meets certain conditions, such as setting a retention threshold (one or three), or giving certain layout qualification conditions. When the layout qualification conditions are met, the parent generation layout set will be output to obtain a primary PCB layout structure diagram.

[0104] Further, in an embodiment of the present invention, before using the pre-built PCB layout generator in the generative adversarial PCB layout model to perform a genetic algorithm-based PCB layout operation on the component feature sequence set, the method further includes:

[0105] Obtain a generative adversarial PCB layout model including a PCB layout generator and a layout evaluation discriminator, and obtain a training sample set including historical business requirements-manual PCB layout-manual evaluation labels;

[0106] Extracting a training sample from the training sample set in turn, sending the training sample to the generative adversarial PCB layout model, and using the PCB layout generator to perform a forward network layout calculation based on thermal and electrical balance on the training sample to obtain a predicted PCB layout;

[0107] Using the layout evaluation discriminator, the predicted PCB layout is evaluated to obtain a predicted layout evaluation result, and the manual PCB layout is evaluated to obtain a label layout evaluation result;

[0108] According to the predicted layout evaluation result, a fitness function of the predicted PCB layout is obtained, and according to the fitness function, the PCB board layout generator is optimized to obtain an updated PCB board layout generator;

[0109] According to a pre-constructed cross entropy loss algorithm and the manual evaluation labels of the training samples, a first loss value of the predicted layout evaluation result and a second loss value of the label layout evaluation result are calculated, and the sum of the first loss value and the second loss value is calculated to obtain a discriminator loss value;

[0110] According to the pre-built gradient descent algorithm and the discriminator loss value, the network reverse parameter update of the layout evaluation discriminator is performed to obtain an updated layout evaluation discriminator;

[0111] Determining whether the discriminator loss value converges;

[0112] When the discriminator loss value has not converged, return to the above step of extracting one training sample from the training sample set in turn, and iteratively update the updated PCB board layout generator and the updated layout evaluation discriminator;

[0113] When the discriminator loss value converges, the training process is stopped to obtain a trained generative adversarial PCB board layout model.

[0114] In the embodiment of the present invention, the training sample includes historical business demand-manual PCB layout-manual evaluation label. The PCB layout generator adopts a network based on a genetic algorithm. The predicted PCB layout of the PCB layout generator does not need to be compared and optimized according to the manual PCB layout of the sample, but needs to comprehensively evaluate its own results, so as to calculate the fitness to optimize the genetic algorithm. The layout evaluation discriminator in the embodiment of the present invention can perform the evaluation work, so the predicted layout evaluation result can be directly used as the fitness function.

[0115] In detail, in the embodiment of the present invention, the fitness function is expressed as:

[0116] F G =D(G(z))

[0117] In the formula, F G represents the fitness function, G represents the PCB layout generator, G(·) represents the layout calculation function of the PCB layout generator, D(·) represents the evaluation calculation function of the layout evaluation discriminator, D(·) includes but is not limited to the thermoelectric balance loss function and the characteristic impedance loss function, and z represents the historical business demand of the training sample.

[0118] Furthermore, in the embodiment of the present invention, although the layout evaluation discriminator is a common neural network, it is an evaluation of the predicted PCB layout, not an evaluation of the artificial PCB layout, and therefore cannot be directly compared with the artificial evaluation label. In the embodiment of the present invention, the goal of the layout evaluation discriminator is to distinguish between real samples and generated samples as accurately as possible. Therefore, the present invention adopts a method of synchronously calculating the loss value of the predicted PCB layout and the artificial PCB layout.

[0119] In detail, in the embodiment of the present invention, the discriminator loss value is expressed as:

[0120]

[0121] Where, L D represents the discriminator loss value, D represents the layout evaluation discriminator, represents the second loss value, represents the first loss value, x real represents the artificial PCB layout of the training sample.

[0122] In the embodiment of the present invention, according to the discriminator loss value, it is expected that the output of the real sample is close to 1, while the output of the generated sample is close to 0, so as to achieve the most accurate distinction between the real sample and the generated sample.

[0123] In the embodiment of the present invention, the PCB board layout generator is updated according to the fitness function and the layout evaluation discriminator is updated according to the discriminator loss value in an alternating updating manner; then the PCB board layout generator is updated, the discriminator loss value is updated, and so on, thereby continuously optimizing the generative adversarial PCB board layout model.

[0124] Finally, in order to avoid overfitting of the model, the present invention uses the convergence of the discriminator loss value to control the model training progress. When the discriminator loss value converges, it indicates that the model progress effect is not great, then the training process is stopped, and a trained generative adversarial PCB layout model is obtained.

[0125] S4. Using the layout evaluation discriminator pre-constructed in the generative adversarial PCB board layout model, perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram to obtain an index scoring set, and obtain a comprehensive score of the index scoring set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance.

[0126] In the embodiment of the present invention, the signal transmission performance is obtained by detecting characteristic impedance.

[0127] It should be known that when the signal is transmitted on the PCB, the characteristic impedance value of the printed circuit board must match the electronic impedance of the head and tail components. Once the characteristic impedance value exceeds the tolerance, the transmitted signal energy will be reflected, scattered, attenuated or delayed, seriously affecting the signal integrity.

[0128] However, in the actual processing process, the characteristic impedance tester can only select the characteristic holes for characteristic impedance testing after the printed circuit board is finished. The result cannot be changed regardless of whether it meets the impedance matching requirements. There is a serious lag, which leads to blind processing. The test results can only serve as a reference for subsequent processing and cannot provide any guidance for this processing.

[0129] Therefore, in addition to considering the thermal and electrical balance in advance during the PCB layout process, the present invention also predicts the characteristic impedance.

[0130] In detail, in an embodiment of the present invention, the layout evaluation discriminator pre-built in the generative adversarial PCB board layout model is used to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram to obtain an index scoring set, including:

[0131] Using the pre-built layout evaluation discriminator in the generative adversarial PCB board layout model to perform feature recognition on the primary PCB layout structure diagram, and obtain a component feature set and a connection relationship feature sequence set;

[0132] Performing a binary classification operation of characteristic impedance characteristics on the connection relationship characteristic sequence set to obtain a microstrip line characteristic impedance and a stripline characteristic impedance;

[0133] Obtaining characteristic impedance formulas of the microstrip line characteristic impedance and the stripline characteristic impedance, substituting the component feature set into the characteristic impedance formula to obtain a layout characteristic impedance value, and calculating an impedance normalization result of the layout characteristic impedance value;

[0134] Performing an evaluation operation based on preset thermoelectric indicators on the component feature set and the connection relationship feature sequence set to obtain an evaluation score sequence, and performing weighted calculation on the evaluation score sequence to obtain a thermoelectric balance score;

[0135] The impedance normalization result and the thermoelectric balance score are uniformly output to obtain an index score set.

[0136] Specifically, in the embodiment of the present invention, firstly, a component feature set and a connection relationship feature sequence set are obtained through feature recognition. The component feature set includes information such as the model and parameters of each component, and the connection relationship feature sequence set includes the connection relationship of each component, such as capacitor B connected to resistor C connected to inductor D...

[0137] The present invention can identify and evaluate the thermoelectric balance and characteristic impedance respectively through the component feature set and the connection relationship feature sequence set. On the one hand, the present invention classifies the connection relationship feature sequence set into microstrip line characteristic impedance and stripline characteristic impedance through classification judgment, and obtains the layout characteristic impedance value in the entire circuit layout through weighted calculation of each microstrip line characteristic impedance and stripline characteristic impedance.

[0138] In detail, in the embodiment of the present invention, the layout characteristic impedance value is expressed as:

[0139] Z comblined =α·Z miter +(1-α)·Z strip

[0140]

[0141] In the formula, Z comblined Represents the layout characteristic impedance value, Z miter represents the characteristic impedance of the microstrip line, Z strip represents the stripline characteristic impedance, e r represents the relative dielectric constant, H represents the dielectric thickness, W represents the wire width, and T represents the wire thickness, wherein H, W and T are all in the component feature set, and α represents a weight coefficient between 0 and 1.

[0142] On the other hand, the present invention obtains an evaluation score sequence through an evaluation operation based on preset thermoelectric indicators. The preset thermoelectric indicators include thermal efficiency, heat loss, electric energy conversion efficiency, comprehensive thermoelectric efficiency and specific heat. Then, the scores of each indicator are weighted to obtain a thermoelectric balance score.

[0143] Finally, the embodiment of the present invention uniformly outputs the normalized layout characteristic impedance value and the thermoelectric balance score to obtain an index scoring set. The index scoring set includes relevant evaluations of thermoelectric balance and characteristic impedance. Therefore, the genetic algorithm in the PCB layout generator can be guided to develop in the direction of thermoelectric balance and appropriate characteristic impedance.

[0144] S5. Determine whether the comprehensive score is greater than a preset qualified threshold.

[0145] In the embodiment of the present invention, the generative adversarial PCB board layout model is a generative adversarial network. When applied, only the PCB board layout generator should be used without using a layout evaluation discriminator.

[0146] Considering that the business requirements of the PCB board and electronic components are constantly changing with the times, the adversarial PCB board layout model is generated to handle new component parameters at any time. In order to ensure the staged training optimization of the model and the reliability of the model results, the present invention retains the layout evaluation discriminator and evaluates the model results once.

[0147] When the comprehensive score is less than or equal to the qualified threshold, return to the above step of performing a genetic algorithm-based PCB layout operation on the component feature sequence set using the PCB board layout generator pre-constructed in the generative adversarial PCB board layout model, and use the PCB board layout generator to iteratively optimize the primary PCB layout structure diagram according to the indicator score set corresponding to the comprehensive score.

[0148] When the comprehensive score is greater than the qualified threshold, S6, the final optimized primary PCB layout structure diagram is used as the target PCB layout diagram, and a PCB board processing operation is performed according to the target PCB layout diagram to obtain a target PCB board corresponding to the PCB board business demand.

[0149] In the embodiment of the present invention, the primary PCB layout structure diagram with a comprehensive score greater than the qualified threshold is selected as the target PCB layout diagram. Then, according to the target PCB layout diagram, automatic processing is performed by equipment such as CNC machine tools to obtain the target PCB board corresponding to the PCB board business demand.

[0150] The present invention is to solve the problem described in the background technology. The present invention first obtains the business demand of the PCB board. According to the business demand of the PCB board, the information such as the types and quantities of components required by the PCB board can be understood, and a set of electronic components can be obtained; in the embodiment of the present invention, in order to ensure that the electronic components can be better feature extracted, such as more complex features such as electrical characteristics, the components are processed by simulation; further, the present invention performs layout by generating an adversarial PCB board layout model to obtain a primary PCB layout structure diagram; wherein the generated adversarial PCB board layout model is a generated adversarial network, the layout part adopts a genetic algorithm for optimization, and the layout evaluation discriminator part adopts two aspects of thermoelectric balance and characteristic impedance to evaluate the primary PCB layout structure diagram, thereby further improving the layout superiority of the genetic algorithm, and finally obtaining a target PCB layout diagram, thereby using the processing process to obtain a target PCB board corresponding to the business demand of the PCB board. Therefore, the present invention can solve the problems of unreasonable PCB board layout and uneven heat dissipation performance.

[0151] like Figure 2 , which is a functional module diagram of a processing system for a metal-based thermoelectric integrated PCB board provided in one embodiment of the present invention.

[0152] The processing system 100 of the metal-based thermoelectric integrated PCB board of the present invention can be installed in an electronic device. According to the functions to be implemented, the processing system 100 of the metal-based thermoelectric integrated PCB board can include a component acquisition module 101, a PCB board layout module 102, a layout evaluation module 103 and a PCB board processing module 104. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0153] The component acquisition module 101 is used to screen and obtain an electronic component set according to the pre-built PCB board business requirements, and obtain the simulation components of the electronic component set to obtain a simulation component set, and use the pre-trained generative adversarial PCB board layout model to extract features from the simulation component set to obtain a component feature sequence set;

[0154] The PCB layout module 102 is used to perform a PCB layout operation based on a genetic algorithm on the component feature sequence set using a PCB layout generator pre-built in the generative adversarial PCB layout model to obtain a primary PCB layout structure diagram;

[0155] The layout evaluation module 103 is used to use the layout evaluation discriminator pre-constructed in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index score set, and obtain a comprehensive score of the index score set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance, and to determine whether the comprehensive score is greater than a preset qualified threshold, and when the comprehensive score is less than or equal to the qualified threshold, return to the above-mentioned step of using the PCB board layout generator pre-constructed in the generative adversarial PCB board layout model to perform a PCB layout operation based on a genetic algorithm on the component feature sequence set, and use the PCB board layout generator to iteratively optimize the primary PCB layout structure diagram according to the index score set corresponding to the comprehensive score;

[0156] The PCB board processing module 104 is used to use the final optimized primary PCB layout structure diagram as the target PCB layout diagram when the comprehensive score is greater than the qualified threshold, and perform PCB board processing operations according to the target PCB layout diagram to obtain the target PCB board corresponding to the PCB board business demand.

[0157] In detail, the modules in the metal-based thermoelectric integrated PCB processing system 100 of the embodiment of the present invention are used in the same manner as described above. Figure 1The same technical means as the processing method of the metal-based thermoelectric integrated PCB board described in the above can produce the same technical effects, so I will not go into details here.

[0158] like Figure 3 FIG. 1 is a schematic diagram of the structure of an electronic device for implementing a method for processing a metal-based thermoelectric integrated PCB board provided by an embodiment of the present invention.

[0159] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a processing method program for a metal-based thermoelectric integrated PCB board.

[0160] Wherein, the memory 11 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (for example: SD or DX memory, etc.), magnetic memory, disk, optical disk, etc. The memory 11 may be an internal storage unit of the electronic device 1 in some embodiments, such as a mobile hard disk of the electronic device 1. The memory 11 may also be an external storage device of the electronic device 1 in other embodiments, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1. Further, the memory 11 also includes an internal storage unit of the electronic device 1 and an external storage device. The memory 11 can not only be used to store application software and various types of data installed in the electronic device 1, such as the code of the processing method program of the metal-based thermoelectric integrated PCB board, but also can be used to temporarily store data that has been output or is to be output.

[0161] The processor 10 may be composed of an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules stored in the memory 11 (such as a processing method program for a metal-based thermoelectric integrated PCB board, etc.), and calls data stored in the memory 11 to execute various functions of the electronic device 1 and process data.

[0162] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize connection and communication between the memory 11 and at least one processor 10, etc.

[0163] Figure 3 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0164] For example, although not shown, the electronic device 1 may also include a power source (such as a battery) for supplying power to each component. Preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that the power management device can realize functions such as charging management, discharging management, and power consumption management. The power source may also include any components such as one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, etc. The electronic device 1 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0165] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0166] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0167] It should be understood that the embodiment is for illustration only and the scope of the patent application is not limited to this structure.

[0168] The metal-based thermoelectric integrated PCB processing method program stored in the memory 11 in the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve:

[0169] According to the pre-built PCB board business requirements, a set of electronic components is screened and obtained, and a simulation component of the set of electronic components is obtained to obtain a simulation component set;

[0170] Using a pre-trained generative adversarial PCB layout model, feature extraction is performed on the set of simulated components to obtain a set of component feature sequences;

[0171] Using the pre-built PCB layout generator in the generative adversarial PCB layout model to perform a genetic algorithm-based PCB layout operation on the component feature sequence set to obtain a primary PCB layout structure diagram;

[0172] Using the layout evaluation discriminator pre-built in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index scoring set, and obtain a comprehensive score of the index scoring set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance;

[0173] Determining whether the comprehensive score is greater than a preset qualified threshold;

[0174] When the comprehensive score is less than or equal to the qualified threshold, returning to the step of performing a genetic algorithm-based PCB layout operation on the component feature sequence set using the PCB layout generator pre-constructed in the generative adversarial PCB layout model, and iteratively optimizing the primary PCB layout structure diagram using the PCB layout generator according to the indicator score set corresponding to the comprehensive score;

[0175] When the comprehensive score is greater than the qualified threshold, the final optimized primary PCB layout structure diagram is used as the target PCB layout diagram, and a PCB board processing operation is performed according to the target PCB layout diagram to obtain a target PCB board corresponding to the PCB board business demand.

[0176] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0177] Furthermore, if the module / unit integrated in the electronic device 1 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0178] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement:

[0179] According to the pre-built PCB board business requirements, a set of electronic components is screened and obtained, and a simulation component of the set of electronic components is obtained to obtain a simulation component set;

[0180] Using a pre-trained generative adversarial PCB layout model, feature extraction is performed on the set of simulated components to obtain a set of component feature sequences;

[0181] Using the pre-built PCB layout generator in the generative adversarial PCB layout model to perform a genetic algorithm-based PCB layout operation on the component feature sequence set to obtain a primary PCB layout structure diagram;

[0182] Using the layout evaluation discriminator pre-built in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index scoring set, and obtain a comprehensive score of the index scoring set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance;

[0183] Determining whether the comprehensive score is greater than a preset qualified threshold;

[0184] When the comprehensive score is less than or equal to the qualified threshold, returning to the step of performing a genetic algorithm-based PCB layout operation on the component feature sequence set using the PCB layout generator pre-constructed in the generative adversarial PCB layout model, and iteratively optimizing the primary PCB layout structure diagram using the PCB layout generator according to the indicator score set corresponding to the comprehensive score;

[0185] When the comprehensive score is greater than the qualified threshold, the final optimized primary PCB layout structure diagram is used as the target PCB layout diagram, and a PCB board processing operation is performed according to the target PCB layout diagram to obtain a target PCB board corresponding to the PCB board business demand.

[0186] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and actual implementation may have other division methods.

[0187] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0188] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0189] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0190] In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in the system claim can also be implemented by one unit or device through software or hardware. The second and other words are used to indicate names, but not to indicate any particular order.

[0191] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for processing a metal-based thermoelectric integrated PCB board, characterized in that: The method comprises: According to the pre-built PCB board business requirements, a set of electronic components is screened and obtained, and simulation components of the set of electronic components are obtained to obtain a set of simulation components; Using a pre-trained generative adversarial PCB layout model, feature extraction is performed on the set of simulated components to obtain a set of component feature sequences; Using the PCB layout generator pre-built in the generative adversarial PCB layout model to perform a PCB layout operation based on a genetic algorithm on the component feature sequence set to obtain a primary PCB layout structure diagram; Using the layout evaluation discriminator pre-built in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index scoring set, and obtain a comprehensive score of the index scoring set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance; Determining whether the comprehensive score is greater than a preset qualified threshold; When the comprehensive score is less than or equal to the qualified threshold, returning to the step of performing a genetic algorithm-based PCB layout operation on the component feature sequence set using the PCB layout generator pre-constructed in the generative adversarial PCB layout model, and iteratively optimizing the primary PCB layout structure diagram using the PCB layout generator according to the indicator score set corresponding to the comprehensive score; When the comprehensive score is greater than the qualified threshold, the final optimized primary PCB layout structure diagram is used as the target PCB layout diagram, and a PCB board processing operation is performed according to the target PCB layout diagram to obtain a target PCB board corresponding to the PCB board business demand.

2. The method for processing a metal-based thermoelectric integrated PCB board according to claim 1, characterized in that: The electronic component set is screened and obtained according to the pre-built PCB board business requirements, including: Perform text quantification on the pre-built PCB board business requirements to obtain a word segmentation vector set; Performing semantic recognition on the word segmentation vector set to obtain a business intent label set; From a pre-built technical product database, filter the electronic component set corresponding to the business intent tag set.

3. The method for processing a metal-based thermoelectric integrated PCB board according to claim 2, characterized in that: The step of obtaining the simulation component of the electronic component set to obtain the simulation component set includes: Determining the types of electronic components in the electronic component set; When the electronic component is a linear component, a parameter set of the electronic component is queried using a pre-built technical manual, and a simulation component is constructed according to the parameter set; When the electronic component is a nonlinear component, the electronic component is simulated using a current-voltage characteristic curve to obtain a simulated component.

4. The method for processing a metal-based thermoelectric integrated PCB board according to claim 3, characterized in that: Before performing a genetic algorithm-based PCB layout operation on the component feature sequence set using a pre-built PCB layout generator in the generative adversarial PCB layout model, the method further includes: Obtain a generative adversarial PCB layout model including a PCB layout generator and a layout evaluation discriminator, and obtain a training sample set including historical business requirements-manual PCB layout-manual evaluation labels; Extracting a training sample from the training sample set in turn, sending the training sample to the generative adversarial PCB layout model, and using the PCB layout generator to perform a forward network layout calculation based on thermal and electrical balance on the training sample to obtain a predicted PCB layout; Using the layout evaluation discriminator, the predicted PCB layout is evaluated to obtain a predicted layout evaluation result, and the manual PCB layout is evaluated to obtain a label layout evaluation result; According to the predicted layout evaluation result, a fitness function of the predicted PCB layout is obtained, and according to the fitness function, the PCB board layout generator is optimized to obtain an updated PCB board layout generator; According to a pre-constructed cross entropy loss algorithm and the manual evaluation labels of the training samples, a first loss value of the predicted layout evaluation result and a second loss value of the label layout evaluation result are calculated, and the sum of the first loss value and the second loss value is calculated to obtain a discriminator loss value; According to the pre-built gradient descent algorithm and the discriminator loss value, the network reverse parameter update of the layout evaluation discriminator is performed to obtain an updated layout evaluation discriminator; Determining whether the discriminator loss value converges; When the discriminator loss value has not converged, return to the above step of extracting one training sample from the training sample set in turn, and iteratively update the updated PCB board layout generator and the updated layout evaluation discriminator; When the discriminator loss value converges, the training process is stopped to obtain a trained generative adversarial PCB board layout model.

5. The method for processing a metal-based thermoelectric integrated PCB board according to claim 4, characterized in that: The fitness function is expressed as: F G =D(G(z)) In the formula, F G represents the fitness function, G represents the PCB layout generator, G(·) represents the layout calculation function of the PCB layout generator, D(·) represents the evaluation calculation function of the layout evaluation discriminator, D(·) includes but is not limited to the thermoelectric balance loss function and the characteristic impedance loss function, and z represents the historical business demand of the training sample.

6. The method for processing a metal-based thermoelectric integrated PCB board according to claim 5, characterized in that: The discriminator loss value is expressed as: Where, L D represents the discriminator loss value, D represents the layout evaluation discriminator, represents the second loss value, represents the first loss value, x real represents the artificial PCB layout of the training sample.

7. The method for processing a metal-based thermoelectric integrated PCB board according to claim 6, characterized in that: The method of using the pre-built PCB layout generator in the generative adversarial PCB layout model to perform a PCB layout operation based on a genetic algorithm on the component feature sequence set to obtain a primary PCB layout structure diagram includes: Using the pre-built PCB layout generator in the generative adversarial PCB layout model to randomly splice the component feature sequence set to obtain various random PCB layouts; Calculating the fitness value of the random PCB layout, and selecting the random PCB layout with a fitness value greater than a preset threshold as the parent layout, to obtain a parent layout set; Performing a crossover operation based on component position exchange on the parent layout set to obtain a child layout set; Performing a mutation operation on the descendant layout set based on random changes in component positions and connection modes to obtain a mutant layout set; Using the variant layout set, the parent layout set is merged and updated to obtain an optimized parent layout set; Determine whether the number of layouts in the parent layout set is less than a preset retention threshold, wherein the retention threshold is one or more; When the number of layouts in the parent layout set is greater than or equal to the retention threshold, return to the above step of calculating the fitness value of the random PCB layout, and update the parent layout set; When the number of layouts in the parent layout set is less than the retention threshold, the parent layout set is output to obtain a primary PCB layout structure diagram.

8. The method for processing a metal-based thermoelectric integrated PCB board according to claim 7, characterized in that: The method of using the pre-built layout evaluation discriminator in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram to obtain an index scoring set includes: Using the pre-built layout evaluation discriminator in the generative adversarial PCB board layout model to perform feature recognition on the primary PCB layout structure diagram, and obtain a component feature set and a connection relationship feature sequence set; Performing a binary classification operation of characteristic impedance characteristics on the connection relationship characteristic sequence set to obtain a microstrip line characteristic impedance and a stripline characteristic impedance; Obtaining characteristic impedance formulas of the microstrip line characteristic impedance and the stripline characteristic impedance, substituting the component feature set into the characteristic impedance formula to obtain a layout characteristic impedance value, and calculating an impedance normalization result of the layout characteristic impedance value; Performing an evaluation operation based on preset thermoelectric indicators on the component feature set and the connection relationship feature sequence set to obtain an evaluation score sequence, and performing weighted calculation on the evaluation score sequence to obtain a thermoelectric balance score; The impedance normalization result and the thermoelectric balance score are uniformly output to obtain an index score set.

9. The method for processing a metal-based thermoelectric integrated PCB board according to claim 8, characterized in that: The layout characteristic impedance value is expressed as: WITH comblined =α Z miter +(1-α)·Z strip In the formula, Z comblined Represents the layout characteristic impedance value, Z miter represents the characteristic impedance of the microstrip line, Z strip represents the stripline characteristic impedance, e r represents the relative dielectric constant, H represents the dielectric thickness, W represents the wire width, and T represents the wire thickness, wherein H, W and T are all in the component feature set, and α represents a weight coefficient between 0 and 1.

10. A processing system for a metal-based thermoelectric integrated PCB board, characterized in that: The system comprises: A component acquisition module is used to screen and obtain an electronic component set according to pre-built PCB board business requirements, and obtain simulation components of the electronic component set to obtain a simulation component set, and use a pre-trained generative adversarial PCB board layout model to extract features from the simulation component set to obtain a component feature sequence set; A PCB layout module is used to perform a genetic algorithm-based PCB layout operation on the component feature sequence set using a PCB layout generator pre-built in the generative adversarial PCB layout model to obtain a primary PCB layout structure diagram; A layout evaluation module, used to use the layout evaluation discriminator pre-constructed in the generative adversarial PCB board layout model to perform a layout evaluation operation based on a preset evaluation index set on the primary PCB layout structure diagram, obtain an index score set, and obtain a comprehensive score of the index score set, wherein the evaluation index set includes but is not limited to thermal and electrical balance and signal transmission performance, and to determine whether the comprehensive score is greater than a preset qualified threshold, and when the comprehensive score is less than or equal to the qualified threshold, return to the above-mentioned step of using the PCB board layout generator pre-constructed in the generative adversarial PCB board layout model to perform a PCB layout operation based on a genetic algorithm on the component feature sequence set, and use the PCB board layout generator to iteratively optimize the primary PCB layout structure diagram according to the index score set corresponding to the comprehensive score; The PCB board processing module is used to use the final optimized primary PCB layout structure diagram as the target PCB layout diagram when the comprehensive score is greater than the qualified threshold, and perform PCB board processing operations according to the target PCB layout diagram to obtain the target PCB board corresponding to the PCB board business demand.

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