Winding method, winding device and readable storage medium based on test structure design

Abstract

The present application relates to a winding method, a winding device and a readable storage medium based on test structure design. The method obtains a layout, determines a target area, and obtains multiple winding tasks in the target area, wherein the winding tasks include pins and corresponding pads of a test structure to be connected by winding; in the target area, the shortest path of each winding task is calculated; based on preset wiring information and the shortest path, a winding path is generated for each winding task in turn until all winding tasks are completed, thereby solving the problem of large test structure measurement errors caused by large winding arbitrariness of a bit line / word line connection method, and realizing sequential optimization of the winding path based on the shortest path, which not only improves the calculation efficiency of the winding path, but also improves the reliability of the winding path.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design and manufacturing, and in particular to a winding method, a winding device and a readable storage medium based on a test structure design. Background Art

[0002] The design and testing of the test structure (Testkey) can be used to perform integrity and reliability tests in WAT testing to ensure that the chip meets specification requirements and quality standards. This helps to improve product quality and reliability and reduce defective product rates. The key to testkey design is to determine the layout and distribution of the testkey to ensure that it has the right location and quantity on the chip. This will involve a balance between the actual chip wiring, area limitations, and test requirements. For example, an array testkey refers to a testkey with high repeatability and scalability.

[0003] Traditional wire-wrap design is limited to two pads connected to a test structure, see Figure 1 , place a maximum of N-1 test structures (where N is the number of pads). If connected in the form of bit line / word line, see Fig. 9 (The winding path is omitted for clear presentation), that is, a bit line BL signal (bit line 1 / bit line 2 / bit line 3 / bit line 4 / bit line 5 / bit line 6) and a word line WL signal (word line 1 / word line 2 / word line 3 / word line 4 / word line 5) are used to jointly select a test structure, and the number of test structures can be increased to a maximum of (N / 2)^2.

[0004] However, there is no unified routing rule for bit line / word line connection. The routing given by designers is often arbitrary, which not only leads to low path calculation efficiency but also poor path reliability, which can easily lead to uneven parasitic effects of the test structure and affect the accuracy of the test results of the test structure. Summary of the invention

[0005] In this embodiment, a winding method, a winding device and a readable storage medium based on a test structure design are provided to solve the problems of low efficiency and poor reliability of winding design in the related art.

[0006] In a first aspect, a winding method based on test structure design is provided in this embodiment, and the method includes:

[0007] Acquire a layout, determine a target area, and acquire a plurality of wiring tasks in the target area, wherein the wiring tasks include pins of a test structure to be connected by wiring and corresponding pads;

[0008] In the target area, calculating the shortest path of each of the detour tasks;

[0009] Based on the preset wiring information and the shortest path, winding paths are generated for each of the winding tasks in turn until all winding tasks are completed.

[0010] In some of the embodiments, the target area is divided into networks of the same size; the target area is defined with a prohibited area, an occupied area and a routing area;

[0011] Wherein, the forbidden area includes the edge grid of the target area, the grid occupied by the test structure and the grid occupied by the pad;

[0012] The occupied area includes grids occupied by existing windings;

[0013] The remaining area after excluding the prohibited area and the occupied area in the target area is the routing area.

[0014] In some embodiments, calculating the shortest path of each of the detour tasks in the target area includes:

[0015] Based on a uniform grid winding algorithm, in the routing area of ​​the target area, respectively calculate the shortest path of each winding task;

[0016] The shortest path is a connection path that occupies the least number of grids, and the connection path is a path connecting the pin of the test structure and the corresponding pad; the path width of the shortest path is one grid;

[0017] The uniform grid winding algorithm includes: starting from the starting grid where the center of the pin is located in the routing area, by ascending numbering of adjacent grids, finally searching for the terminating grid where the center of the pad is located, and taking the path with the smallest number in the terminating grid as the shortest path.

[0018] In some of the embodiments, the uniform grid winding algorithm further includes:

[0019] The pin-out direction of the starting grid and / or the ending grid is defined, and the adjacent grids of the starting grid and / or the ending grid refer to the adjacent grids within the pin-out direction.

[0020] In some embodiments, generating a winding path for each of the winding tasks in sequence based on the preset wiring information and the shortest path until all the winding tasks are completed includes:

[0021] Acquire the unfinished winding task as the current task;

[0022] Confirming and / or optimizing the shortest path of the current task based on the routing area;

[0023] Based on the preset wiring information and the routing area, generating a winding path according to the confirmed shortest path;

[0024] Perform grid filling based on the winding path, complete the current task, and update the routing area;

[0025] Continue to obtain the unfinished winding tasks as current tasks for processing until all the winding tasks are completed.

[0026] In some of the embodiments, the obtaining of the unfinished detour task as the current task includes: obtaining the unfinished detour task corresponding to the shortest path with the longest path length as the current task.

[0027] In some of the embodiments, the method further includes obtaining preset wiring information, which specifically includes:

[0028] Get the winding width information, including the maximum and minimum winding widths of different metal layers;

[0029] Get the wiring spacing;

[0030] Obtain path resistance information, including sheet resistance values ​​of different metal layers, resistance values ​​of vias of different sizes, and winding resistance baseline values;

[0031] Wherein, one of the blocks refers to a grid;

[0032] The different metal layers include a first metal layer along a transverse routing and a second metal layer along a longitudinal routing, and the through hole is used to connect the metal routings in the first metal layer and the second metal layer.

[0033] In some embodiments, obtaining the winding resistance reference value includes:

[0034] Among all the winding tasks, the shortest path with the largest path length is used as a reference path;

[0035] Based on the maximum winding width of the different metal layers, the wiring width of the reference path is expanded to obtain a corresponding reference winding path;

[0036] According to the path resistance information, the winding resistance values ​​and through-hole resistance values ​​of different metal layers in the reference winding path are calculated to obtain the total winding resistance value of the reference winding path, which is used as the winding resistance reference value.

[0037] In some of the embodiments, after obtaining the corresponding reference winding path, the method further includes:

[0038] Grid filling is performed based on the reference winding path to complete the corresponding winding task and update the routing area.

[0039] In some embodiments, the confirming and / or optimizing the shortest path of the current task based on the routing area includes:

[0040] Based on the routing area, the shortest path of the current task is confirmed, or the shortest path of the current task is optimized and then confirmed; specifically including:

[0041] Step 1): Determine whether the grids of the shortest path of the current task are all within the routing area:

[0042] If yes, confirm the shortest path;

[0043] If not, abandoning the shortest path, and updating the routing area based on the abandoned shortest path;

[0044] Step 2): Recalculate the shortest path for the current task and go back to step 1) for processing.

[0045] In some embodiments, based on the preset wiring information and the routing area, generating a routing path according to the confirmed shortest path includes:

[0046] A winding path that meets preset rules is generated based on the shortest path and the wiring information, and the winding path is confirmed based on the routing area; wherein the preset rules include preset rules set based on the winding width information and preset rules set based on the winding resistance reference value; specifically including:

[0047] Step 3): Based on the winding width information and the path resistance information, the wiring width of the shortest path is expanded to generate a winding path; wherein the difference between the path resistance value of the winding path and the winding resistance reference value meets a preset condition;

[0048] Step 4): Determine whether all grids of the winding path are within the routing area:

[0049] If yes, confirm the detour path of the current task;

[0050] If not, the routing path is abandoned and the process goes back to step 3); or the shortest path is abandoned and the routing area is updated, and the shortest path is reconfirmed and / or optimized based on the routing area.

[0051] In some embodiments, extending the wiring width of the shortest path to generate a routing path includes:

[0052] The Lagrange multiplier method is used to calculate the wiring widths of different metal layers in the shortest path to generate a winding path, wherein the difference in the wiring widths of adjacent metal layers is within a preset range.

[0053] In some of the embodiments, after extending the wiring width of the shortest path to generate a routing path, the method further includes:

[0054] If the wiring width is smaller than the minimum winding width of the corresponding metal layer in the winding width information, the shortest path is abandoned and the routing area is updated, and then the shortest path is re-confirmed and / or optimized based on the routing area;

[0055] If the wiring width is greater than the maximum winding width of the corresponding metal layer in the winding width information, determine whether the wiring width is within the preset redundancy value range: if so, confirm the winding path of the current task; if not, report an exception.

[0056] In a second aspect, a winding device based on a test structure design is provided in this embodiment, and the device includes:

[0057] A task acquisition module, used to acquire a layout, determine a target area, and acquire a plurality of winding tasks in the target area, wherein the winding tasks include pins of a test structure to be connected by winding and corresponding pads;

[0058] A shortest path calculation module, used for calculating the shortest path of each of the detour tasks in the target area;

[0059] The path optimization module is used to generate a winding path for each of the winding tasks in sequence based on the preset wiring information and the shortest path until all the winding tasks are completed.

[0060] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the winding method based on the test structure design described in the first aspect is implemented.

[0061] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the winding method based on test structure design described in the first aspect is implemented.

[0062] Compared with the related art, the winding method, winding device and readable storage medium for test structure design provided in the present embodiment determine the target area by acquiring a layout, and obtain multiple winding tasks in the target area, wherein the winding tasks include the pins of the test structure to be connected by winding and the corresponding pads; in the target area, the shortest path of each winding task is calculated; based on the preset wiring information and the shortest path, a winding path is generated for each winding task in turn until all winding tasks are completed, thereby solving the problem of large measurement errors of the test structure caused by the large randomness of the winding of the bit line / word line connection method, and realizing the optimization of the winding path in turn based on the shortest path, which not only improves the calculation efficiency of the winding path, but also improves the reliability of the winding path.

[0063] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0065] Figure 1 A schematic diagram of a conventional test structure winding method in one embodiment;

[0066] Figure 2 A hardware structure block diagram of a terminal of a winding method based on a test structure design in one embodiment;

[0067] Figure 3 A schematic flow chart of a winding method based on a test structure design in one embodiment;

[0068] Figure 4 A schematic flow chart of a winding method based on test structure design in a preferred embodiment;

[0069] Figure 5 is a schematic diagram of a gridded target area in a preferred embodiment;

[0070] Figure 6 is a schematic diagram of a test structure and a pad in a preferred embodiment;

[0071] Figure 7 A schematic diagram of a connection path between a test structure and a pad in a target area in a preferred embodiment;

[0072] Figure 8 A structural block diagram of a winding device based on a test structure design in one embodiment;

[0073] Fig. 9 FIG. 1 is a schematic diagram of a wiring method of a bit line / word line based test structure in one embodiment.

[0074] Reference numerals: 102, processor; 104, memory; 106, transmission device; 108, input / output device; 10, task acquisition module; 20, shortest path calculation module; 30, path optimization module. DETAILED DESCRIPTION

[0075] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0076] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0077] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. For example, running on a terminal, Figure 2 is a hardware structure block diagram of a terminal of the winding method based on the test structure design of this embodiment. Figure 2 As shown, the terminal may include one or more ( Figure 2Only one is shown in the figure) a processor 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 2 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 2 More or fewer components as shown, or with Figure 2 Different configurations shown.

[0078] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the winding method based on the test structure design in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0079] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0080] In this embodiment, a winding method based on test structure design is provided. Figure 3 is a flow chart of the winding method based on the test structure design of this embodiment, such as Figure 3 As shown, the process includes the following steps:

[0081] Step S210, obtaining a layout, determining a target area, and obtaining a plurality of wiring tasks in the target area, wherein the wiring tasks include pins of a test structure to be wired and connected and corresponding pads.

[0082] Specifically, in the layout, a certain area is used as the maximum area that can be drawn in this layout, that is, the target area, and it is preferably a rectangle. The area where the test structure and the pad are located is determined in the target area. The test structure and the pad are arranged in an array in a regular manner. Therefore, when determining the test structure in the target area, a starting test structure (such as a test structure located in the lower left corner of the target area) can be defined. The area of ​​the pad is also defined based on the same principle. Compared with the traditional form of two pads connecting a test structure, more test structures can be connected to the same pad in the embodiment of the present application. However, the present application does not limit the connection method of the specific pads and test structures, and can be applied to different application scenarios. The present application only requires the limitation of the winding task formed between the pins and the pads.

[0083] Step S220, calculating the shortest path of each detour task in the target area.

[0084] Specifically, the shortest connection path between the pins of the test structure and the corresponding pads, i.e., the shortest path, is explored. At this time, there may be overlaps between different shortest paths, and the overlapping shortest paths will be optimized in subsequent steps. The shortest path includes a first path along the horizontal routing and a second path along the vertical routing. The path length of the shortest path is the sum of the lengths of the first path and the second path.

[0085] Step S230, generating a winding path for each winding task in turn based on the preset wiring information and the shortest path until all winding tasks are completed.

[0086] Specifically, the winding path is generated for each winding task in turn, including: adjusting the wiring width based on the shortest path, determining the winding path of each winding task, and filling the grid based on the winding path to complete each winding task.

[0087] Among them, the wiring information includes winding width information, and the line width information includes the maximum winding width and the minimum winding width of different metal layers; the wiring information also includes path resistance information, and the path resistance information includes the block resistance values ​​of different metal layers and the resistance values ​​of through holes of different sizes; among them, the different metal layers include a first metal layer along the horizontal routing and a second metal layer along the vertical routing, and the through holes are used to connect the metal routings in the first metal layer and the second metal layer.

[0088] The optimization of the winding path includes: expanding the width of the shortest path within the range indicated by the winding width information, including expanding the wiring width of the first path and the wiring width of the second path, and determining the number and size of the through holes. Generally, making the widths of the first path and the second path equal or similar will be more conducive to the layout design, so the wiring width of the first path and the second path will be uniformly represented by the wiring width below. At the same time, it is also considered whether the total resistance value of the path after the wiring width is expanded meets the preset requirements. Generally, the total resistance value will be equal to or close to the set winding resistance reference value.

[0089] The method for calculating the total resistance value of the winding path includes: calculating the resistance value of the horizontal routing, calculating the resistance value of the vertical routing, calculating the resistance value of the through hole connecting the horizontal routing and the vertical routing; adding the resistance value of the horizontal routing, the resistance value of the vertical routing and the resistance value of the through hole to obtain the total resistance value of the winding path. Among them, the resistance value of the horizontal routing can be calculated by the method of (length × width × block resistance value), that is, the resistance value of the horizontal routing is obtained based on the multiplication result of the wiring width, the length of the first path and the block resistance value of the first metal layer; the resistance value of the vertical routing can be calculated in the same way; the resistance value of the through hole is calculated by (number of through holes × resistance value of through holes of corresponding size), and the through hole of appropriate size is selected based on the wiring width, and / or resistance reference value, winding method, etc. to obtain the resistance value of the through hole.

[0090] After determining the final wiring width, the winding path is generated based on the corresponding shortest path expansion, and the grid is filled based on the winding path to complete the corresponding winding task.

[0091] In this embodiment, by acquiring a layout, determining a target area, and acquiring multiple winding tasks in the target area, the winding tasks include pins of a test structure to be connected by winding and corresponding pads; in the target area, calculating the shortest path of each winding task; optimizing the winding path of each winding task in turn based on preset wiring information and the shortest path until all winding tasks are completed, thereby solving the problem of large measurement errors of the test structure caused by the large randomness of the winding of the bit line / word line connection method, and optimizing the winding path in turn based on the shortest path, which not only improves the calculation efficiency of the winding path, but also improves the reliability of the winding path.

[0092] In some of the embodiments, the target area is divided into networks of the same size, that is, the target area is evenly gridded. The target area is defined as a prohibited area, an occupied area, and a routing area, wherein the prohibited area includes the edge grid of the target area, the grid occupied by the test structure, and the grid occupied by the pad; the occupied area includes the grid occupied by the existing winding; and the remaining area in the target area after excluding the prohibited area and the occupied area is the routing area.

[0093] Specifically, in the subsequent process of optimizing the routing path, the occupied area and the routing area will be continuously updated, and even the prohibited area can be adjusted according to needs.

[0094] In this embodiment, the target area is gridded to efficiently locate the test results, pads, paths and other areas within the target area, and by defining prohibited areas, occupied areas and routing areas, it is possible to automatically avoid areas where routing is not possible, thereby improving the reliability of path calculation.

[0095] In some of the embodiments, calculating the shortest path of each detour task in the target area includes:

[0096] Based on the uniform grid winding algorithm, the shortest path of each winding task is calculated in the routing area of ​​the target area; wherein the shortest path is the connection path that occupies the least number of grids, and the connection path is the path connecting the pins of the test structure and the corresponding pads; the path width of the shortest path is one grid, that is, the path length of the shortest path is characterized by the number of grids occupied by the shortest path in the metal layer.

[0097] The uniform grid routing algorithm includes: starting from the starting grid where the center of the pin is located in the routing area, by numbering the adjacent grids in ascending order, and finally searching for the terminating grid where the center of the pad is located, and taking the path with the smallest number of the terminating grid as the shortest path.

[0098] In some of the embodiments, the uniform grid winding algorithm further includes:

[0099] Define the pin-out direction of the start grid and / or the end grid. The adjacent grids of the start grid and / or the end grid refer to the adjacent grids within the pin-out direction.

[0100] Specifically, by defining the pin direction, it is possible to exclude the selection of some starting grids for connection, thereby reducing the calculation time and storage space of the winding.

[0101] In some embodiments, the winding path optimization is performed on each winding task in turn based on the preset wiring information and the shortest path until all winding tasks are completed, including:

[0102] Step S231, obtaining the unfinished winding task as the current task.

[0103] Step S232: confirming and / or optimizing the shortest path of the current task based on the routing area.

[0104] Specifically, based on the routing area, the shortest path of the current task is confirmed, or the shortest path of the current task is optimized and then confirmed.

[0105] Step S233, based on the preset wiring information and routing area, a winding path is calculated according to the confirmed shortest path.

[0106] Step S234, performing grid filling based on the winding path, completing the current task, and updating the routing area.

[0107] Step S235, continue to obtain the unfinished winding tasks as the current tasks to step S232 for processing until all winding tasks are completed.

[0108] In this embodiment, the reliability of the final winding path is guaranteed by repeatedly confirming the shortest path and the winding path.

[0109] In some of the embodiments, step S231, obtaining an unfinished detour task as the current task, includes: obtaining an unfinished detour task corresponding to the shortest path with the longest path length as the current task.

[0110] Specifically, each time the current task is selected, the winding task that occupies the largest number of grids is used as the current task, so that the winding calculation is performed in descending order of the number of grids occupied.

[0111] In some of the embodiments, the method further includes obtaining preset wiring information, which specifically includes:

[0112] Get the wire width information, including the maximum and minimum wire widths of different metal layers.

[0113] Get the wiring spacing of the wiring. After confirming a winding path, occupy the grid where the winding path is located and the surrounding grids within the winding spacing as occupied areas based on the winding spacing to update the routing area, thereby avoiding interference between multiple winding paths.

[0114] Get path resistance information, including sheet resistance values ​​of different metal layers, resistance values ​​of vias of different sizes, and winding resistance baseline values.

[0115] In this embodiment, a square refers to a grid; however, in other embodiments, a square is not necessarily equivalent to a grid, and this application does not make specific limitations. The different metal layers include a first metal layer along the horizontal routing and a second metal layer along the vertical routing, and the through hole is used to connect the metal routing in the first metal layer and the second metal layer.

[0116] The winding resistance reference value may be set in advance, or obtained based on calculation of the first winding task when the first winding task is performed. The winding resistance reference value set in advance may be pre-set based on prior knowledge, or may be pre-calculated based on the winding task.

[0117] In some embodiments, obtaining the winding resistance reference value includes:

[0118] Step S310: Among all the winding tasks, the shortest path with the largest path length is used as the reference path.

[0119] Specifically, the path width of the shortest path is one grid, so the path length is counted by the number of grids occupied. The path with the most occupied grids has the longest path length.

[0120] Step S320 , based on the maximum winding widths of different metal layers, the wiring width of the reference path is expanded to obtain a corresponding reference winding path.

[0121] Step S330, calculating the winding resistance values ​​and through-hole resistance values ​​of different metal layers in the reference winding path according to the path resistance information, and obtaining the total winding resistance value of the reference winding path, which is used as the winding resistance reference value.

[0122] In some of the embodiments, after obtaining the corresponding reference winding path, the method further includes: performing grid filling based on the reference winding path, completing the corresponding winding task, and updating the routing area.

[0123] Specifically, according to the wiring width confirmed in the reference winding path, the first metal layer and the second metal layer are filled respectively, and the first metal layer and the second metal layer are connected through through holes matching the wiring width, so as to complete the corresponding winding task. The winding task corresponding to the reference winding path is the first winding task to be filled and completed. The grid occupied by the reference winding path is updated in the occupied area, and the routing area is obtained based on the updated occupied area.

[0124] It should be noted that the winding task corresponding to the reference winding path, as the first winding task processed in this embodiment, after the wiring width is expanded based on the shortest path, the grid is directly filled based on the winding reference path to complete the winding task. However, in other embodiments, the grid after the wiring width is expanded based on the shortest path may be an occupied grid. For example, the maximum winding width defined is large and extends to the boundary of the test structure or the target area. Therefore, it is necessary to perform the specific grid filling after the processing of steps S232 and S233 as the detour task processed later. However, before the winding, the present embodiment avoids these problems by setting the routing area. For example, the regional grid within a certain distance range (greater than the maximum wiring width) of the test structure and the edge grid of the target area are set as prohibited areas to avoid this problem. Therefore, the first winding task of this embodiment, that is, the winding reference path, can directly perform grid filling. However, in other embodiments, if this limitation is not made before winding, the first winding task also needs to perform the processing judgment of steps S232 and S233 before performing the grid occupancy filling.

[0125] In some embodiments, step S232, adjusting, confirming and / or optimizing the shortest path of the current task based on the routing area, includes:

[0126] Step S410, determine whether the grids of the shortest path of the current task are all within the routing area: if so, confirm the shortest path; end the processing of the current task in step S232; if not, abandon the shortest path and update the routing area based on the abandoned shortest path.

[0127] Step S420, recalculate the shortest path of the current task and go back to step S410 for processing.

[0128] Specifically, based on the abandoned shortest path, the occupied area in the target area is updated to obtain an updated routing area, wherein the grid points in the middle section of the abandoned shortest path may be partially occupied to complete the update of the occupied area.

[0129] In this embodiment, the best routing path between the pins and the pads can be automatically laid out, and the areas with existing routing and areas that cannot be routed can be automatically avoided.

[0130] In some embodiments, step S233, based on the preset wiring information and the routing area, the winding path is calculated according to the confirmed shortest path, including:

[0131] Step S510, based on the winding width information and the path resistance information, the wiring width of the shortest path is expanded to generate a winding path; wherein the difference between the path resistance value of the winding path and the winding resistance reference value meets a preset condition.

[0132] Specifically, the difference between the wiring widths of adjacent metal layers is within a preset range.

[0133] Step S520, determine whether the grids of the winding path are all within the routing area: if so, confirm the winding path of the current task; end the processing of the current task in step S233; if not, abandon the winding path and re-process step S510; or abandon the shortest path and update the routing area, and re-confirm and / or optimize the shortest path based on the routing area.

[0134] In this embodiment, an optimal solution is provided for each winding width, so that the winding width is more reasonable and the process performance is more stable; and resistance calculation is provided for each winding section, so that the resistance value of each winding path is close.

[0135] In some of the embodiments, expanding the wiring width of the shortest path to generate a winding path includes: using a Lagrange multiplier method to calculate the wiring widths of different metal layers in the shortest path to generate the winding path, wherein the difference in wiring widths of adjacent metal layers is within a preset range.

[0136] Specifically, the principle of calculating the path width using the Lagrange multiplier method is as follows: We need to calculate the optimal solution for the width Wx of the horizontal routing and the width Wy of the vertical routing according to the following formula:

[0137] R=R1×Lx / Wx+R2×Ly / Wy+m×Rv_nxn;

[0138] That is, R-(R1×Lx / Wx+R2×Ly / Wy+m×Rv_nxn)=0;

[0139] Let g(x,y)=R-(R1×Lx / x+R2×Ly / y+m×Rv_nxn);

[0140] Wherein, R is the total resistance of the winding path, Lx is the path length of the horizontal routing (that is, the number of grids of the horizontal routing in this embodiment), Ly is the path length of the vertical routing (that is, the number of grids of the vertical routing in this embodiment), Rv_nxn is the resistance value of the through hole (that is, the resistance value of through holes of different sizes), R1 is the square resistance value of the first metal layer Mn corresponding to the horizontal routing, R2 is the square resistance value of the second metal layer Mn+1 corresponding to the vertical routing, m is the number of times the through hole array via array is called, and n is the through hole array via array that needs to be matched. Array type (that is, different through-hole sizes), these two values ​​are easy to obtain in the winding path, so we only need to determine the optimal solution of Wx and Wy. We set the condition of the optimal solution to be f(Wx, Wy)=|Wx-Wy| minimum (in the following description, x and y are used instead of Wx and Wy, and this optimal solution condition is abbreviated as f(x, y)=|xy|); the setting of this optimal solution is due to the fact that when designing the test structure testkey, the design rules of adjacent metal layers (Mn and Mn+1) are generally similar, and generally making their widths similar is more conducive to layout design.

[0141] Let L(x,y,λ)=f(x,y)-λ×g(x,y); where λ is the Lagrange multiplier.

[0142] L(x,y,λ) is derived with respect to x,y,λ respectively, that is ( L / x, L / y, L / λ), and set its three values ​​to 0, and obtain the values ​​of x, y, and λ, and then you can get the minimum value of f(x, y).

[0143] In this embodiment, the Lagrange multiplier method is used to handle the optimization problem of equality constraints to realize the calculation of path width; however, in other embodiments, based on different application scenario requirements and different constraints, other constraint optimization methods can also be selected to realize the calculation of path width, such as KKT conditions (Karush-Kuhn-Tucker Conditions) applicable to optimization problems of nonlinear inequalities and equality constraints, multiplier update methods applicable to complex constraint optimization problems combined with penalty functions and Lagrange multiplier methods, and even other sequential quadratic programming, interior point methods, etc., to handle specific constraint optimization problems, which are not specifically limited in this application. In some of the embodiments, after expanding the wiring width of the shortest path to generate a winding path, it also includes:

[0144] Step S610, if the wiring width is smaller than the minimum winding width of the corresponding metal layer in the winding width information, the shortest path is abandoned and the routing area is updated, and the current task is reprocessed to step S232.

[0145] Specifically, if the winding width is less than the minimum winding width, the path is abandoned (partially occupying the grid points in the middle section), and then the winding path is replanned, and the iterative operation is performed until the winding width meets the minimum width requirement, and a winding path that is not the optimal path is obtained, so as to expand it and fill the grid points.

[0146] In addition, a length threshold of the shortest path can be limited. When calculating using the uniform grid winding algorithm, the shortest path shorter than this length threshold is discarded, and exploration continues until the shortest path that meets the limited length threshold is found.

[0147] Step S620, if the wiring width is greater than the maximum winding width of the corresponding metal layer in the winding width information, determine whether the wiring width is within the preset redundancy value range: if so, confirm the winding path of the current task; if not, report an exception.

[0148] Specifically, the wiring width is greater than the maximum winding width. The reason for this phenomenon is that due to the occupation of the baseline winding path, the subsequent winding path changes, and there is a probability that its winding path is longer than the longest winding path defined in the previous order. The solution to this situation is to set a redundant value for the maximum width (for example, the maximum width defined in the process is 4.5um, and we define the maximum width as 4.0um in the algorithm, leaving a redundancy of 0.5um). In this way, even if the width of the winding path exceeds the maximum winding width, based on the calculation of the first pass of the uniform grid winding algorithm, even if the path width exceeds, it will not exceed by much. Therefore, retaining a redundant value allows the path to expand and fill normally without violating the rules in the process. In addition, the probability of the redundant value plus the situation that it also exceeds is extremely small and can be ignored.

[0149] The present embodiment is described and illustrated below through preferred embodiments.

[0150] Figure 4 is a preferred flow chart of the winding method based on the test structure design of this embodiment, such as Figure 5 As shown, the winding method based on the test structure design includes the following steps:

[0151] S1, set a certain area as the target area for drawing this time, generally a rectangular area. Define the size of the grid, see Figure 5, divide the target area into m×n grids (the number of grid points in actual applications will be much larger than the number of grid points in the diagram). Define the prohibited area and occupied area in the grid of the target area, and assign the grid value of the prohibited area and occupied area to 1; the grid outside the prohibited area is the routing area, and the grid value of the routing area is assigned to 0. Figure 5 The border position of the target area in the figure (the grid marked in yellow) is one of the prohibited areas. The grids occupied by the subsequent test structures and the grids occupied by the pads will all be regarded as prohibited areas.

[0152] S2, see Figure 6 and Figure 7 , define the area of ​​the test structure and pad, and automatically calculate the center position of the pin and pad of the test structure, and calculate the length and width of the current metal layer where the pin is located (this data may be used in the subsequent setting of the wiring width and calculation of the path resistance value to optimize the calculation results of the pin width and resistance value). Define the connection relationship between each pin and the pad, that is, obtain the wiring task, such as Figure 7 The connection relationship between pad 1 and pin 1, and pad 2 and pin 2.

[0153] S3. Using the Li Maze routing algorithm (this embodiment is implemented using the Li Maze routing algorithm, but other winding algorithms based on uniform grids can also be implemented and can be selected according to different application scenario requirements), one grid is used as the winding unit, and the shortest path between each pin and pad is calculated one by one. (At this time, the path width is only one grid, and different paths may overlap), see Figure 7 , pin1 represents pin 1, pin2 represents pin 2, pad1 represents pad 1, pad2 represents pad 2, and the number of grids in the X / Y direction of each shortest path is stored as Lx / Ly. Figure 7 In the shortest path corresponding to pin 2 and pad 2, Lx=X1+X2, Ly=Y1+Y2; the total winding path length Length=Lx+Ly.

[0154] S4. Define wiring information: Set the wiring spacing, and specify the metal layer and through-hole information for horizontal and vertical routing, and define the block resistance value of the metal layer. For example:

[0155] The horizontal metal trace is Mn; R1Ω / square, and the maximum / minimum width is Wmax1 / Wmin1 respectively.

[0156] The vertical metal trace is Mn+1, R2Ω / square, and the maximum / minimum width is Wmax2 / Wmin2.

[0157] The through hole is ViaX, and the resistance of the through hole with a size of 1×1 is about Rv_1×1Ω, the resistance of the through hole with a size of 2×2 is about Rv_2×2Ω, and the resistance of the through hole with a size of 5×5 is about Rv_5×5Ω; the through holes are divided into arrays of 1×1, 2×2, and 5×5 (arrays, that is, different through hole sizes) in order to adapt to windings of different widths. In practical applications, the specific value of n×n can be taken according to actual needs and is not limited to these three types; the script will automatically configure a suitable through hole array for each winding section by comparing the winding width with the width of different through hole arrays.

[0158] S5. Sort the values ​​of Length = Lx + Ly calculated in step S3 from large to small, and give priority to filling the largest winding path, and set its width to the maximum winding width (with the grid line occupied by the path as the center line and expanding to both sides), and occupy the grid points occupied by the expanded line segment (including the winding spacing required in the process), that is, change the value of the occupied grid points from 0 to 1, and the value of the unoccupied grid points remains 0; and fill the occupied grid points with the metal layer defined in 7.

[0159] The number of block resistors of the lateral winding in the winding path is calculated to be Nsq_x=Lx / Wmax1.

[0160] Calculate the total resistance of the transverse winding Rx=Nsq_x×R1.

[0161] The number of block resistors of the longitudinal winding in the winding path is calculated to be Nsq_y=Ly / Wmax2.

[0162] Calculate the total resistance of the longitudinal winding Ry=Nsq_y×R2.

[0163] The winding path calls a 5×5 through-hole array m times, so the total through-hole resistance Rv=m×Rv_5x5.

[0164] The total resistance of the winding is R=Rx+Ry+Rv.

[0165] S6. Sort the winding paths by path length (except the longest path that has been calculated) and perform calculations one by one in order. Considering that the previous winding will affect the subsequent winding path, the winding path may be recalculated using the Li maze wiring algorithm to recalculate the shortest path, and the resistance value of the maximum winding path is used as a reference to calculate the width of this winding (try to make the total resistance of this winding the same as the resistance value of the maximum winding path or the difference does not exceed the preset threshold), and finally fill the required grid points. Specifically including:

[0166] The following judgment processes are performed in sequence starting from the second path:

[0167] Determine whether the grid that the path needs to occupy is already occupied:

[0168] If so, the shortest path is recalculated using the Li maze wiring algorithm, and the winding width is calculated using the Lagrange multiplier method and the winding path is expanded, and then the winding path judgment process is performed; if not, the winding width is calculated using the Lagrange multiplier method and the winding path is expanded, and then the winding path judgment process is performed.

[0169] The winding path judgment process includes: judging whether the grid to be occupied by the expanded winding path is already occupied:

[0170] If not, the grid of the winding path is occupied to complete the winding task; if so, the winding width is recalculated using the Lagrange multiplier method and expanded to obtain a new winding path, or the Li maze wiring algorithm is used to recalculate the shortest path and the winding width is calculated using the Lagrange multiplier method and expanded to obtain a new winding path, until the new winding path meets the winding path judgment processing, that is, the grid required by it is not occupied, and the winding task is completed after occupation.

[0171] Through this preferred embodiment, it is possible to automatically layout the optimal winding path between the pins and the pads when the array-type test structure is connected in the bit line / word line manner; automatically avoid existing windings and areas where winding is not allowed; provide the optimal solution for each winding width, so that the winding width is more reasonable and the process performance is more stable; provide resistance calculation for each winding section, so that the resistance value of each winding path is close.

[0172] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0173] In the present embodiment, a winding device based on the test structure design is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "subunit" and the like used below can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0174] Figure 8 is a structural block diagram of the winding device based on the test structure design of this embodiment, such as Figure 8 As shown, the device includes: a task acquisition module 10, a shortest path calculation module 20, and a path optimization module 30.

[0175] The task acquisition module 10 is used to acquire a layout, determine a target area, and acquire a plurality of wiring tasks in the target area. The wiring tasks include pins of a test structure to be connected by wiring and corresponding pads.

[0176] The shortest path calculation module 20 is used to calculate the shortest path of each detour task in the target area.

[0177] The path optimization module 30 is used to optimize the winding path for each winding task in turn based on the preset wiring information and the shortest path until all the winding tasks are completed.

[0178] In some of the embodiments, the interior of the target area is divided into networks of the same size; a prohibited area, an occupied area and a routing area are defined within the target area, wherein the prohibited area includes edge grids of the target area, grids occupied by test structures and grids occupied by pads; the occupied area includes grids occupied by existing windings; and the remaining area in the target area after excluding the prohibited area and the occupied area is the routing area.

[0179] In some of the embodiments, the shortest path calculation module 20 is further configured to calculate the shortest path of each winding task in the routing area of ​​the target area based on a uniform grid winding algorithm.

[0180] Among them, the shortest path is a connection path that occupies the least number of grids, and the connection path is a path connecting the pins of the test structure and the corresponding pads; the path width of the shortest path is one grid.

[0181] The uniform grid routing algorithm includes: starting from the starting grid where the center of the pin is located in the routing area, by numbering the adjacent grids in ascending order, and finally searching for the terminating grid where the center of the pad is located, and taking the path with the smallest number of the terminating grid as the shortest path.

[0182] In some of the embodiments, the uniform grid winding algorithm further includes: defining a pin-out direction of a starting grid and / or a terminating grid, wherein the adjacent grids of the starting grid and / or the terminating grid refer to adjacent grids within the pin-out direction.

[0183] In some of the embodiments, the path optimization module 30 is also used to obtain an unfinished winding task as the current task; confirm and / or optimize the shortest path of the current task based on the routing area; calculate the winding path based on the preset wiring information and the routing area according to the confirmed shortest path; fill the grid based on the winding path, complete the current task, and update the routing area; continue to obtain the unfinished winding task as the current task for processing until all winding tasks are completed.

[0184] In some of the embodiments, the path optimization module 30 is further used to obtain an unfinished detour task corresponding to the shortest path with the longest path length as the current task.

[0185] In some embodiments, the path optimization module 30 is further used to obtain preset routing information, specifically including:

[0186] Obtain winding width information, including the maximum winding width and minimum winding width of different metal layers; obtain the winding spacing of the wiring; obtain path resistance information, including block resistance values ​​of different metal layers, resistance values ​​of through holes of different sizes, and winding resistance reference values; wherein a square refers to a grid; different metal layers include a first metal layer along the horizontal routing and a second metal layer along the vertical routing, and the through holes are used to connect the metal routing in the first metal layer and the second metal layer.

[0187] In some embodiments, the path optimization module 30 is also used to obtain a reference value of the winding resistance, including:

[0188] In all winding tasks, the shortest path with the largest path length is taken as the reference path; based on the maximum winding width of different metal layers, the wiring width of the reference path is expanded to obtain the corresponding reference winding path; according to the path resistance information, the winding resistance values ​​and through-hole resistance values ​​of different metal layers in the reference winding path are calculated to obtain the total winding resistance value of the reference winding path, which is used as the winding resistance reference value.

[0189] In some of the embodiments, the path optimization module 30 is further used to perform grid filling based on the reference routing path, complete the corresponding routing task, and update the routing area.

[0190] In some of the embodiments, the path optimization module 30 is also used to confirm the shortest path of the current task based on the routing area, or to complete the confirmation after optimizing the shortest path of the current task; specifically including: Step 1): Determine whether the grids of the shortest path of the current task are all within the routing area: if so, confirm the shortest path; if not, abandon the shortest path and update the routing area based on the abandoned shortest path.

[0191] Step 2): Recalculate the shortest path for the current task and go back to step 1) for processing.

[0192] In some of the embodiments, the path optimization module 30 is also used to implement the following: Step 3): based on the winding width information and the path resistance information, the wiring width of the shortest path is expanded to generate a winding path; wherein the difference between the path resistance value of the winding path and the winding resistance baseline value satisfies a preset condition.

[0193] Step 4): Determine whether all grids of the winding path are within the routing area: if so, confirm the winding path of the current task; if not, abandon the winding path and go back to step 3); or abandon the shortest path and update the routing area, and re-confirm and / or optimize the shortest path based on the routing area.

[0194] In some of the embodiments, the path optimization module 30 is further configured to include: using a Lagrange multiplier method to calculate the wiring widths of different metal layers in the shortest path to generate a winding path, wherein the difference in wiring widths of adjacent metal layers is within a preset range.

[0195] In some of the embodiments, the path optimization module 30 is also used to implement: if the wiring width is smaller than the minimum winding width of the corresponding metal layer in the winding width information, the shortest path is abandoned and the routing area is updated, and then the shortest path is reconfirmed and / or optimized based on the routing area; if the wiring width is greater than the maximum winding width of the corresponding metal layer in the winding width information, it is determined whether the wiring width is within a preset redundancy value range: if so, the winding path of the current task is confirmed; if not, an exception is reported.

[0196] It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0197] In this embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0198] Optionally, the computer device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0199] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0200] In addition, in combination with the winding method based on test structure design provided in the above embodiments, a storage medium can also be provided in this embodiment to implement the winding method based on test structure design. The storage medium stores a computer program; when the computer program is executed by the processor, any winding method based on test structure design in the above embodiments is implemented.

[0201] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0202] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0203] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0204] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A winding method based on test structure design, characterized in that: The method comprises: Acquire a layout, determine a target area, and acquire a plurality of wiring tasks in the target area, wherein the wiring tasks include pins of a test structure to be connected by wiring and corresponding pads; In the target area, calculating the shortest path of each of the detour tasks; Generating a winding path for each of the winding tasks in sequence based on the preset wiring information and the shortest path until all the winding tasks are completed, including: Based on determining whether the shortest path grids of the detour task are all within the routing area of ​​the target area, the shortest path of the detour task is confirmed, or the shortest path of the detour task is optimized and then confirmed; Based on the preset wiring information and the routing area, generating a winding path according to the confirmed shortest path; Performing grid filling based on the winding path, completing the winding task, and updating the routing area; The shortest path of the winding task is optimized and confirmed, specifically including: Abandon the shortest path, and update the routing area based on the abandoned shortest path; recalculate the shortest path of the routing task, and re-determine whether the shortest path grids are all within the routing area, until the shortest path of the routing task is confirmed.

2. The winding method based on test structure design according to claim 1, characterized in that: The target area is internally divided into networks of the same size; The target area is internally defined with a prohibited area, an occupied area and a routing area; Wherein, the forbidden area includes the edge grid of the target area, the grid occupied by the test structure and the grid occupied by the pad; The occupied area includes grids occupied by existing windings; The remaining area after excluding the prohibited area and the occupied area in the target area is the routing area.

3. The winding method based on test structure design according to claim 2, characterized in that: Calculating the shortest path of each of the detour tasks in the target area includes: Based on a uniform grid winding algorithm, in the routing area of ​​the target area, respectively calculate the shortest path of each winding task; The shortest path is a connection path that occupies the least number of grids, and the connection path is a path connecting the pin of the test structure and the corresponding pad; the path width of the shortest path is one grid; The uniform grid winding algorithm includes: starting from the starting grid where the center of the pin is located in the routing area, by ascending numbering of adjacent grids, finally searching for the terminating grid where the center of the pad is located, and taking the path with the smallest number in the terminating grid as the shortest path.

4. The winding method based on test structure design according to claim 3 is characterized in that: The uniform grid winding algorithm further includes: The pin-out direction of the starting grid and / or the ending grid is defined, and the adjacent grids of the starting grid and / or the ending grid refer to the adjacent grids within the pin-out direction.

5. The winding method based on test structure design according to claim 2, characterized in that: Generating a winding path for each of the winding tasks in sequence based on the preset wiring information and the shortest path until all the winding tasks are completed, further comprising: The unfinished winding tasks are acquired in sequence as current tasks for processing until all the winding tasks are completed.

6. The winding method based on test structure design according to claim 5, characterized in that: The obtaining of the unfinished winding task as the current task includes: Get the unfinished detour task corresponding to the shortest path with the longest path length as the current task.

7. The winding method based on test structure design according to claim 5, characterized in that: It also includes obtaining preset wiring information, including: Get the winding width information, including the maximum and minimum winding widths of different metal layers; Get the wiring spacing; Obtain path resistance information, including sheet resistance values ​​of different metal layers, resistance values ​​of vias of different sizes, and winding resistance baseline values; Wherein, one of the blocks refers to a grid; The different metal layers include a first metal layer along a transverse routing and a second metal layer along a longitudinal routing, and the through hole is used to connect the metal routings in the first metal layer and the second metal layer.

8. The winding method based on test structure design according to claim 7, characterized in that: The acquisition of the winding resistance reference value includes: Among all the winding tasks, the shortest path with the largest path length is used as a reference path; Based on the maximum winding width of the different metal layers, the wiring width of the reference path is expanded to obtain a corresponding reference winding path; According to the path resistance information, the winding resistance values ​​and through-hole resistance values ​​of different metal layers in the reference winding path are calculated to obtain the total winding resistance value of the reference winding path, which is used as the winding resistance reference value.

9. The winding method based on test structure design according to claim 8, characterized in that: After obtaining the corresponding reference winding path, it also includes: Grid filling is performed based on the reference winding path to complete the corresponding winding task and update the routing area.

10. The winding method based on test structure design according to claim 7, characterized in that: Based on determining whether the shortest path grids of the detour task are all within the routing area of ​​the target area, the shortest path of the detour task is confirmed, or the shortest path of the detour task is optimized and then confirmed, further comprising: Step 1): Determine whether the grids of the shortest path of the current task are all within the routing area: If yes, confirm the shortest path; If not, abandoning the shortest path, and updating the routing area based on the abandoned shortest path; Step 2): Recalculate the shortest path of the current task and go back to step 1) for processing.

11. The winding method based on test structure design according to claim 10, characterized in that: Based on the preset wiring information and the routing area, generating a winding path according to the confirmed shortest path includes: A winding path that meets preset rules is generated based on the shortest path and the wiring information, and the winding path is confirmed based on the routing area; wherein the preset rules include preset rules set based on the winding width information and preset rules set based on the winding resistance reference value; specifically including: Step 3): Based on the winding width information and the path resistance information, the wiring width of the shortest path is expanded to generate a winding path; wherein the difference between the path resistance value of the winding path and the winding resistance reference value meets a preset condition; Step 4): Determine whether all grids of the winding path are within the routing area: If so, confirming the detour path of the current task; If not, the routing path is abandoned and the process goes back to step 3); or the shortest path is abandoned and the routing area is updated, and the shortest path is reconfirmed and / or optimized based on the routing area.

12. The winding method based on test structure design according to claim 11, characterized in that: Expanding the routing width of the shortest path to generate a routing path includes: The Lagrange multiplier method is used to calculate the wiring widths of different metal layers in the shortest path to generate a winding path, wherein the difference in the wiring widths of adjacent metal layers is within a preset range.

13. The winding method based on test structure design according to claim 11, characterized in that: After expanding the wiring width of the shortest path to generate a routing path, the method further includes: If the wiring width is smaller than the minimum winding width of the corresponding metal layer in the winding width information, the shortest path is abandoned and the routing area is updated, and then the shortest path is re-confirmed and / or optimized based on the routing area; If the wiring width is greater than the maximum winding width of the corresponding metal layer in the winding width information, determine whether the wiring width is within the preset redundancy value range: if so, confirm the winding path of the current task; if not, report an exception.

14. A winding device based on a test structure design, characterized in that: The device comprises: A task acquisition module, used to acquire a layout, determine a target area, and acquire a plurality of winding tasks in the target area, wherein the winding tasks include pins of a test structure to be connected by winding and corresponding pads; A shortest path calculation module, used for calculating the shortest path of each of the detour tasks in the target area; A path optimization module, used to generate a winding path for each of the winding tasks in turn based on the preset wiring information and the shortest path until all the winding tasks are completed, including: Based on determining whether the shortest path grids of the detour task are all within the routing area of ​​the target area, the shortest path of the detour task is confirmed, or the shortest path of the detour task is optimized and then confirmed; Based on the preset wiring information and the routing area, generating a winding path according to the confirmed shortest path; Performing grid filling based on the winding path, completing the winding task, and updating the routing area; The shortest path of the winding task is optimized and confirmed, specifically including: Abandon the shortest path, and update the routing area based on the abandoned shortest path; recalculate the shortest path of the routing task, and re-determine whether the shortest path grids are all within the routing area, until the shortest path of the routing task is confirmed.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 13 are implemented.

Images