Display device and driving method of display device

Abstract

The invention relates to a display device and a driving method of the display device. The display device comprises a display panel, and the display panel comprises pixels. The pixel includes a light emitting element, a first capacitor connected to a first node, a second capacitor connected between a second node and a voltage line, a first transistor connected to the first node, the second node, and a third node, a second transistor connected between the third node and the first node, a third transistor connected between the second node and the data line, a fourth transistor connected between the second node and the voltage line, a fifth transistor connected between the third node and the light emitting element, and a sixth transistor connected between the light emitting element and the reference voltage line.

Description

Technical Field

[0001] The embodiments of the present disclosure described herein relate to a display device and a method of driving the display device, and more particularly, to a display device having uniform light emitting characteristics and a method of driving the display device. Background Art

[0002] Among the display devices, a light emitting display device displays an image by using a light emitting diode that generates light by recombination of electrons and holes. The light emitting display device can be driven with low power while providing a fast response speed.

[0003] The light-emitting display device generally includes pixels connected to data lines and scan lines. Each of the pixels generally includes a light-emitting diode and a circuit unit for controlling the amount of current flowing to the light-emitting diode. In response to a data signal, the circuit unit can control the amount of current flowing from a terminal to which a first driving voltage is applied to a terminal to which a second driving voltage is applied via the light-emitting diode. In this case, light of a predetermined brightness is generated to correspond to the amount of current flowing through the light-emitting diode. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device having improved overall display quality by employing pixels having consistent light emitting characteristics even when an operating frequency varies, and a method of driving the display device.

[0005] According to an embodiment, a display device includes a display panel including a pixel. In such an embodiment, the pixel includes: a light-emitting element; a first capacitor connected to a first node; a second capacitor connected between a second node and a voltage line; a first transistor connected to a first node, a second node, and a third node; a second transistor connected between a third node and the first node, and the second transistor receives a first scan signal; a third transistor connected between a second node and a data line, and the third transistor receives a second scan signal; a fourth transistor connected between a second node and a voltage line, and the fourth transistor receives a first emission control signal; a fifth transistor connected between a third node and the light-emitting element, and the fifth transistor receives a second emission control signal; and a sixth transistor connected between the light-emitting element and a reference voltage line, and the sixth transistor receives a third scan signal.

[0006] According to an embodiment, a display device includes a display panel including pixels and a panel driver driving the display panel.

[0007] In such an embodiment, the pixel includes: a light-emitting element; a first capacitor connected between a carrier capture induction line to which a carrier capture induction signal is applied and a first node; a first transistor connected between a second node and a third node, and the first transistor operates based on the potential of the first node; a second transistor connected between the third node and the first node, and the second transistor operates based on a first scanning signal; and a third transistor connected between the second node and the data line, and the third transistor operates based on a second scanning signal.

[0008] In such an embodiment, the display panel displays an image during a plurality of frames, and at least one of the plurality of frames includes a write frame and a hold frame. In such an embodiment, the carrier capture inducing signal has a first level during the write frame, and the carrier capture inducing signal has a second level different from the first level during a carrier capture inducing period prior to an emission period of the hold frame.

[0009] According to an embodiment, in a driving method of a display device, the display device includes a display panel including a pixel. In such an embodiment, the pixel includes: a light emitting element; a first capacitor connected between a carrier capture induction line and a first node; a first transistor connected between a second node and a third node; a second transistor connected between the third node and the first node; and a third transistor connected between the second node and a data line. In such an embodiment, the display panel displays an image during a plurality of frames, and at least one of the plurality of frames includes a write frame and a hold frame.

[0010] In such an embodiment, a driving method of a display device includes: applying a carrier capture inducing signal having a first level to a carrier capture inducing line during a write frame; determining whether a hold frame starts; when it is determined that the hold frame starts, applying a carrier capture inducing signal having a second level lower than the first level to the carrier capture inducing line during a carrier capture inducing period before an emission period of the hold frame; and applying the carrier capture inducing signal having the first level to the carrier capture inducing line during an emission period of the hold frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of embodiments of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0014] Figure 3A and Figure 3Bis a signal timing diagram for describing the operation of the display device according to an embodiment of the present disclosure.

[0015] Figure 4A and Figure 4B is a diagram for describing an operation of a pixel during a first period according to an embodiment of the present disclosure.

[0016] Figure 5A and Figure 5B is a diagram for describing an operation of a pixel during a second period according to an embodiment of the present disclosure.

[0017] Fig. 6A and Figure 6B is a diagram for describing an operation of a pixel during a third period according to an embodiment of the present disclosure.

[0018] Fig. 7A and Figure 7B is a diagram for describing an operation of a pixel during a fourth period according to an embodiment of the present disclosure.

[0019] Figure 7C is a diagram for describing a current deviation compensation process according to an embodiment of the present disclosure.

[0020] Fig. 8A and Figure 8B is a diagram for describing an operation of a pixel during a fifth period according to an embodiment of the present disclosure.

[0021] Fig.9A and Fig. 9B is a diagram for describing an operation of a pixel during a sixth period according to an embodiment of the present disclosure.

[0022] Fig. 10A and Fig. 10B is a waveform diagram illustrating a reduction in emission current variation according to a carrier trap inducing signal according to an embodiment of the present disclosure.

[0023] Fig.11 is a flowchart illustrating an operation process of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0025] In this specification, the statement that a first component (or region, layer, part, portion, etc.) is "on" a second component, "connected to" a second component, or "coupled to" a second component means that the first component is directly on, directly connected to, or directly coupled to the second component, or that a third component is between the first and second components.

[0026] The same reference numerals represent the same components. Moreover, in the drawings, the thickness, proportion and size of the components are exaggerated for the effectiveness of the description of the technical content. The expression "and / or" includes one or more combinations that the related components can define.

[0027] Although the terms "first", "second", etc. may be used to describe various components, the components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles "one", "a (kind / person)", and "the (the)" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0028] Furthermore, the terms "under," "beneath," "on," "over," etc., are used to describe the relationship of components shown in the drawings. These terms are relative and are described with reference to the directions shown in the drawings.

[0029] The terms used herein are only for the purpose of describing specific embodiments, rather than being intended to limit. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent a limitation on quantity, and are intended to include both the singular and the plural. Therefore, the reference to "described" element after the reference to "one" element in the claims includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as limiting "one (person)" or "a kind". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will be further understood that when used in this specification, the terms "include" and / or "comprise" or "have" and / or "have" indicate the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning.

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0033] Reference Figure 1 An embodiment of the display device DD may be a device that is activated according to an electrical signal to display an image. The display device DD may be applied to an electronic device such as a smart watch, a computer (such as a tablet personal computer (PC), a notebook computer), or a smart TV.

[0034] The display device DD includes a display panel DP and a panel driver PDD driving the display panel DP. In an embodiment of the present disclosure, the panel driver PDD may include a driving controller 100, a data driving circuit 200, a scan driving circuit 300, an emission driving circuit 350, a carrier capture control circuit 400, and a voltage generator 500.

[0035] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the image signal RGB into an interface specification suitable for the data driving circuit 200. The driving controller 100 outputs the scanning control signal SCS, the data control signal DCS, the emission driving signal ECS and the carrier capture control signal TCS based on the control signal CTRL.

[0036] The data driving circuit 200 receives the data control signal DCS and the image data DATA from the driving controller 100. The data driving circuit 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1, DL2, ... and DLm to be described later, where m is a positive integer. The data signal is an analog voltage corresponding to the grayscale value of the image data DATA. The data signal may be referred to as a "data voltage".

[0037] The voltage generator 500 generates voltages for operating the display panel DP. In an embodiment of the present disclosure, the voltage generator 500 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and a reference voltage VREF. The reference voltage VREF may have a lower voltage level than the first driving voltage ELVDD.

[0038] The display panel DP includes a plurality of scan lines SCL1 to SCLn and SWL1 to SWLn, a plurality of emission control lines EML0 to EMLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX, where n is a positive integer. A display area DA and a non-display area NDA are defined in the display panel DP. The scan lines SCL1 to SCLn and SWL1 to SWLn, the emission control lines EML0 to EMLn, the data lines DL1 to DLm, and the pixels PX may be disposed in the display area DA. The scan lines SCL1 to SCLn and SWL1 to SWLn extend in a first direction DR1 and are arranged spaced apart from each other in a second direction DR2. The emission control lines EML0 to EMLn extend in a first direction DR1 and are arranged spaced apart from each other in a second direction DR2. The data lines DL1 to DLm extend in a second direction DR2 and are arranged spaced apart from each other in a first direction DR1.

[0039] In the embodiment of the present disclosure, the scan lines SCL1 to SCLn and SWL1 to SWLn may include compensation scan lines SCL1 to SCLn and write scan lines SWL1 to SWLn. However, the present disclosure is not limited thereto, and the display panel DP may further include other scan lines.

[0040] In an embodiment of the present disclosure, the display panel DP further includes a plurality of carrier trap induction lines SDL1 to SDLn. The carrier trap induction lines SDL1 to SDLn extend in the first direction DR1 and are arranged at intervals in the second direction DR2. The carrier trap induction lines SDL1 to SDLn may be positioned at intervals from the compensation scan lines SCL1 to SCLn and the write scan lines SWL1 to SWLn.

[0041] The scan driving circuit 300 and the emission driving circuit 350 may be disposed in the non-display area NDA of the display panel DP. In an embodiment of the present disclosure, the scan driving circuit 300 is positioned adjacent to one side of the display area DA, and the emission driving circuit 350 is positioned adjacent to the other side of the display area DA opposite to the one side. Figure 1 As shown in , the scan driving circuit 300 and the emission driving circuit 350 may be positioned at opposite sides of the display area DA, respectively, but the present disclosure is not limited thereto. In an embodiment, for example, each of the scan driving circuit 300 and the emission driving circuit 350 may be positioned adjacent to one of one side and the other side of the display panel DP. In an embodiment, the scan driving circuit 300 and the emission driving circuit 350 may be integrated into one circuit. The carrier capture control circuit 400 may be disposed in the non-display area NDA of the display panel DP to be adjacent to the scan driving circuit 300 or the emission driving circuit 350.

[0042] A plurality of pixels PX may be positioned in a display area DA of a display panel DP. The plurality of pixels PX are electrically connected to compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, emission control lines EML0 to EMLn, data lines DL1 to DLm, and carrier capture induction lines SDL1 to SDLn. Each of the plurality of pixels PX may be electrically connected to two scan lines, two emission control lines, and one carrier capture induction line. In an embodiment, for example, Figure 1 As shown in , the pixels of the first row can be connected to the first compensation scan line SCL1, the first write scan line SWL1, the dummy emission control line EML0, the first emission control line EML1 and the first carrier capture induction line SDL1. In such an embodiment, the pixels of the second row can be connected to the second compensation scan line SCL2, the second write scan line SWL2, the first emission control line EML1, the second emission control line EML2 and the second carrier capture induction line SDL2. However, the number of scan lines connected to each of the pixels and the number of emission control lines connected to each of the pixels are not limited thereto. In an embodiment of the present disclosure, for example, the number of scan lines and the number of emission control lines can be changed.

[0043] Each of the plurality of pixels PX includes a light emitting element ED (see Figure 2 ) and a pixel circuit unit PXC (see Figure 2 ). The pixel circuit unit PXC may include one or more transistors and one or more capacitors. In an embodiment, the scan driving circuit 300, the emission driving circuit 350, and the carrier capture control circuit 400 may be directly formed in the non-display area NDA of the display panel DP by the same process as the transistor of the pixel circuit unit PXC.

[0044] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and a reference voltage VREF from the voltage generator 500 .

[0045] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. The scan driving circuit 300 may output a compensation scan signal and a write scan signal to the compensation scan lines SCL1 to SCLn and the write scan lines SWL1 to SWLn, respectively, in response to the scan control signal SCS. The emission driving circuit 350 may output an emission control signal to the emission control lines EML0 to EMLn in response to the light emission driving signal ECS from the driving controller 100. The carrier capture control circuit 400 may output a carrier capture induction signal to the carrier capture induction lines SDL1 to SDLn in response to the carrier capture control signal TCS from the driving controller 100.

[0046] According to an embodiment of the present disclosure, the driving controller 100 may determine an operating frequency, and may control operations of the data driving circuit 200, the scan driving circuit 300, the emission driving circuit 350, and the carrier capture control circuit 400 according to the determined operating frequency. In an embodiment of the present disclosure, the emission driving circuit 350 and the carrier capture control circuit 400 may operate at a frequency higher than or equal to that of the scan driving circuit 300.

[0047] Figure 2 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0048] Figure 2 shows the connection to Figure 1 The i-th data line DLi among the data lines DL1 to DLm shown in FIG. Figure 1 The j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn shown in FIG. Figure 1 The j-th write scan line SWLj among the write scan lines SWL1 to SWLn shown in FIG. Figure 1 The (j-1)th emission control line EMLj-1 and the jth emission control line EMLj among the emission control lines EML0 to EMLn shown in FIG. Figure 1 The equivalent circuit diagram of the pixel PXij of the j-th carrier trapping induction line SDLj among the carrier trapping induction lines SDL1 to SDLn shown in FIG. 1 is a positive integer less than or equal to m, and j is a positive integer less than or equal to n. Figure 1 Each of the plurality of pixels PX shown in FIG. Figure 2 The circuit configuration of the pixel PXij shown in FIG. 1 is the same as the circuit configuration, so any repeated detailed description of the remaining pixels will be omitted.

[0049] Reference Figure 2 , the pixel PXij according to the embodiment includes a pixel circuit unit PXC and a light emitting element ED. In the embodiment of the present disclosure, the pixel circuit unit PXC may include six transistors and two capacitors. Hereinafter, the six transistors will be referred to as "a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6", respectively. The two capacitors will be referred to as "a first capacitor C1 and a second capacitor C2", respectively.

[0050] In an embodiment, each of the first transistor T1 to the sixth transistor T6 is a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Optionally, each of the first transistor T1 to the sixth transistor T6 may be an N-type transistor. In addition, at least one of the first transistor T1 to the sixth transistor T6 may be an N-type transistor, and the other transistors of the first transistor T1 to the sixth transistor T6 may be a P-type transistor. Optionally, at least one of the first transistor T1 to the sixth transistor T6 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, some of the first transistor T1 to the sixth transistor T6 may be oxide semiconductor transistors, and the other transistors of the first transistor T1 to the sixth transistor T6 may be LTPS transistors.

[0051] The circuit configuration of the pixel PXij according to the embodiment of the present disclosure is not limited to Figure 2 The circuit configuration shown in . Figure 2 The pixel PXij shown in FIG. 1 is merely an example, and various modifications and implementations may be made to the circuit configuration of the pixel PXij.

[0052] The jth compensation scan line SCLj and the jth write scan line SWLj supply the jth compensation scan signal SCj and the jth write scan signal SWj to the pixel PXij, respectively. The (j-1)th emission control line EMLj-1 and the jth emission control line EMLj supply the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj to the pixel PXij, respectively. The jth carrier capture induction line SDLj supplies the jth carrier capture induction signal SDj to the pixel PXij. The i-th data line DLi transmits the i-th data voltage Vdata to the pixel PXij. The i-th data voltage Vdata may have a value similar to that input to the display device DD (see Figure 1 )’s image signal RGB corresponding to the voltage level.

[0053] The pixel PXij can be connected to a first voltage line VL1, a second voltage line VL2, and a reference voltage line VL3. Figure 1 The first driving voltage ELVDD supplied from the voltage generator 500 shown in FIG. 1 is transferred to the pixel PXij. The second voltage line VL2 transfers the second driving voltage ELVSS supplied from the voltage generator 500 to the pixel PXij. The reference voltage line VL3 can transfer the reference voltage VREF supplied from the voltage generator 500 to the pixel PXij.

[0054] The first capacitor C1 is connected between the j-th carrier trap inducing line SDLj and the first node NA. The second capacitor C2 is connected between the second node NB and the first voltage line VL1.

[0055] The first transistor T1 is connected to the first node NA, the second node NB, and the third node NC, and can operate according to the potential difference between the first node NA and the second node NB. The first transistor T1 includes a first electrode connected to the second node NB, a second electrode connected to the third node NC, and a gate electrode connected to the first node NA. The first transistor T1 electrically connects the second node NB and the third node NC to each other in response to the potential of the first node NA.

[0056] The second transistor T2 is connected between the first node NA and the third node NC, and receives the first scan signal. The second transistor T2 includes a first electrode connected to the third node NC, a second electrode connected to the first node NA, and a gate electrode receiving the first scan signal. In an embodiment of the present disclosure, the second transistor T2 may be connected to the j-th compensation scan line SCLj to receive the j-th compensation scan signal SCj as the first scan signal. The second transistor T2 is turned on in response to the first scan signal, and the signal output from the second electrode of the first transistor T1 is transferred to the first node NA. In an embodiment of the present disclosure, the second transistor T2 may include a plurality of sub-transistors connected in series between the first node NA and the third node NC. The gate electrodes of the plurality of sub-transistors may be commonly connected to the j-th compensation scan line SCLj.

[0057] The third transistor T3 is connected between the second node NB and the i-th data line DLi, and receives the second scan signal. The third transistor T3 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the second node NB, and a gate electrode receiving the second scan signal. In an embodiment of the present disclosure, the third transistor T3 may be connected to the j-th write scan line SWLj, and may receive the j-th write scan signal SWj as the second scan signal. The third transistor T3 is turned on in response to the second scan signal, and outputs the i-th data voltage Vdata supplied through the i-th data line DLi to the second node NB.

[0058] The fourth transistor T4 is connected between the first voltage line VL1 receiving the first driving voltage ELVDD and the second node NB, and receives the first emission control signal. The fourth transistor T4 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the second node NB, and a gate electrode receiving the first emission control signal. The fourth transistor T4 can be connected to the (j-1)th emission control line EMLj-1 to receive the (j-1)th emission control signal EMj-1 as the first emission control signal. The fourth transistor T4 electrically connects the second node NB and the first voltage line VL1 to each other in response to the first emission control signal.

[0059] The fifth transistor T5 is connected between the third node NC and the light emitting element ED, and receives the second emission control signal. The fifth transistor T5 includes a first electrode connected to the third node NC, a second electrode connected to the light emitting element ED, and a gate electrode receiving the second emission control signal. In an embodiment of the present disclosure, the fifth transistor T5 may be connected to the j-th emission control line EMLj, and may receive the j-th emission control signal EMj as the second emission control signal. The fifth transistor T5 electrically connects the third node NC and the light emitting element ED to each other in response to the second emission control signal.

[0060] The sixth transistor T6 is connected between the reference voltage line VL3 and the light emitting element ED, and receives the third scan signal. The sixth transistor T6 includes a first electrode connected to the light emitting element ED, a second electrode connected to the reference voltage line VL3, and a gate electrode receiving the third scan signal. In an embodiment of the present disclosure, the sixth transistor T6 may be connected to the j-th compensation scan line SCLj, and may receive the j-th compensation scan signal SCj as the third scan signal. The sixth transistor T6 electrically connects the anode of the light emitting element ED and the reference voltage line VL3 to each other in response to the third scan signal. In an embodiment of the present disclosure, the first scan signal and the third scan signal may be signals that are identical to each other. In such an embodiment, the first scan signal and the third scan signal may be signals that are activated before the second scan signal.

[0061] The light emitting element ED is connected between the second voltage line VL2 receiving the second driving voltage ELVSS and the fifth transistor T5. The anode of the light emitting element ED is connected to the second electrode of the fifth transistor T5. The cathode of the light emitting element ED is connected to the second voltage line VL2.

[0062] Figure 3A and Figure 3B is a signal timing diagram for describing the operation of the display device according to an embodiment of the present disclosure. Specifically, Figure 3A is a signal timing diagram for describing the operation of the display device at a first operating frequency according to an embodiment of the present disclosure, and Figure 3B is a signal timing diagram for describing the operation of the display device at the second operating frequency according to an embodiment of the present disclosure.

[0063] Reference Figures 1 to 3B , the operating frequency of the display device DD can be changed. In an embodiment of the present disclosure, the first operating frequency may be the highest operating frequency at which the display device DD can operate. In an embodiment, for example, the first operating frequency may be 360 ​​Hz. The first operating frequency may be referred to as a “reference frequency” or a “maximum frequency”.

[0064] like Figure 3AAs shown in , when the display device DD operates at the first operating frequency, the scan driving circuit 300 may sequentially activate the compensation scan signals SC1, SCj, and SCn (i.e., the compensation scan signals SC1, ..., SCj, ..., and SCn) and the write scan signals SW1, SWj, and SWn (i.e., the write scan signals SW1, ..., SWj, ..., and SWn) during each of the plurality of first frames F1 to be at a low level. During each of the plurality of first frames F1, the emission driving circuit 350 may sequentially disable the first emission control signals EM1, EMj, and EMn (i.e., the first emission control signals EM1, ..., EMj, ..., and EMn) to be at a high level. Figure 3A An embodiment is shown in which the activation level of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn is a low level and the deactivation level of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn is a high level, but the present disclosure is not limited thereto. For example, in Figure 2 In the embodiment where the first to sixth transistors T1 to T6 shown in FIG. 1 are N-type transistors, the activation levels of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn may be high levels, and the deactivation levels of the compensation scan signals SC1, SCj and SCn, the write scan signals SW1, SWj and SWn, and the first emission control signals EM1, EMj and EMn may be low levels.

[0065] When the first operating frequency is the maximum frequency, each first frame F1 may include only the first write frame WF1. In this case, the duration of the first write frame WF1 may be substantially equal to the duration of each first frame F1. When the display device DD operates at the first operating frequency, the carrier capture inducing signals SD1, SDj, and SDn (i.e., the carrier capture inducing signals SD1, ..., SDj, ..., and SDn) may be maintained at a first level during the first write frame WF1. In an embodiment of the present disclosure, the first level of the carrier capture inducing signals SD1, SDj, and SDn may be the same as the disable level (i.e., high level) of the compensation scan signals SC1, SCj, and SCn.

[0066] Reference Figures 1 to 3B, the display device DD may operate at a second operating frequency lower than the first operating frequency. In an embodiment of the present disclosure, the second operating frequency is 90 Hz, but the second operating frequency is not limited thereto. The operating frequency of the display device DD may be changed in various ways. In an embodiment, the operating frequency of the display device DD may be determined according to the characteristics of the image signal RGB (e.g., a video or a still image).

[0067] When the display device DD operates at a second operating frequency lower than the first operating frequency, the duration of each second frame F2 may be greater than Figure 3A In the embodiment of the present disclosure, the duration of each second frame F2 may be substantially four times the duration of each first frame F1. Each second frame F2 may include a second write frame WF2 and hold frames HF1, HF2, and HF3. The second write frame WF2 may have the same Figure 3A The duration of the first write frame WF1 shown in is the same duration.

[0068] During the second write frame WF2, the scan driving circuit 300 may sequentially activate the compensation scan signals SC1, SCj, and SCn and the write scan signals SW1, SWj, and SWn to be at an activation level (e.g., a low level). During the second write frame WF2, the emission driving circuit 350 may sequentially disable the first emission control signals EM1, EMj, and EMn to be at a disable level (e.g., a high level).

[0069] During the holding frames HF1, HF2, and HF3, the scan driving circuit 300 maintains the compensation scan signals SC1, SCj, and SCn and the write scan signals SW1, SWj, and SWn at a disabled level (e.g., a high level). During the holding frames HF1, HF2, and HF3, the emission driving circuit 350 may sequentially disable the first emission control signals EM1, EMj, and EMn to be at a disabled level (e.g., a high level). That is, even when the operating frequency of the display device DD is changed to the second operating frequency, the first emission control signals EM1, EMj, and EMn may still be output at the maximum frequency (i.e., the first operating frequency). Figure 3B An embodiment in which three holding frames HF1, HF2, and HF3 are included in the second frame F2 is shown, but the present disclosure is not limited thereto. In an embodiment, for example, the number of holding frames included in the second frame F2 may vary depending on the size of the second operating frequency.

[0070] In an embodiment, during the holding frames HF1, HF2, and HF3, the i-th data voltage Vdata may be maintained as a bias voltage Vb. The bias voltage Vb may be a voltage maintained at a constant voltage level during the holding frames HF1, HF2, and HF3. In an embodiment of the present disclosure, the bias voltage Vb may have a voltage level corresponding to a black grayscale, but is not limited thereto.

[0071] When the display device DD operates at the second operating frequency, the carrier capture control circuit 400 may maintain the carrier capture inducing signals SD1, SDj and SDn at the first level (e.g., a high level) during the second write frame WF2. In such an embodiment, during the hold frames HF1, HF2 and HF3, the carrier capture inducing signals SD1, SD1 and SDn may not be maintained at the first level, but may be sequentially changed to a second level (e.g., a low level) different from the first level. In an embodiment of the present disclosure, the second level may be the same as the activation level (i.e., a low level) of each of the compensation scan signals SC1, SCj and SCn. That is, the second level may be lower than the first level. However, the present disclosure is not limited thereto. In an embodiment, for example, during Figure 2 In the case where the first to sixth transistors T1 to T6 shown in FIG. 5 are N-type transistors, the second level may be higher than the first level.

[0072] Figure 4A and Figure 4B is a diagram for describing an operation of a pixel during a first period according to an embodiment of the present disclosure. Figure 5A and Figure 5B is a diagram for describing an operation of a pixel during a second period according to an embodiment of the present disclosure. Fig. 6A and Figure 6B is a diagram for describing an operation of a pixel during a third period according to an embodiment of the present disclosure. Fig. 7A and Figure 7B is a diagram for describing an operation of a pixel during a fourth period according to an embodiment of the present disclosure. Figure 7C is a diagram for describing a current deviation compensation process according to an embodiment of the present disclosure. Fig. 8A and Figure 8B is a diagram for describing an operation of a pixel during a fifth period according to an embodiment of the present disclosure.

[0073] Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B shows the pixel PXij at Figure 3BThe operation during the second writing frame WF2 is shown in FIG. In such an embodiment, the operation of the pixel PXij can be equally implemented during the first writing frame WF1. Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B , the second writing frame WF2 includes a first period Ti, a second period Tw, a third period Tc1, a fourth period Tc2 and a fifth period Te.

[0074] Reference Figure 4A and Figure 4B During the first period Ti of the second writing frame WF2, each of the j-th compensation scan signal SCj (i.e., the first scan signal and the third scan signal) and the j-th emission control signal EMj (i.e., the second emission control signal) has an activation level. Therefore, during the first period Ti, the second transistor T2 and the sixth transistor T6 are turned on in response to the j-th compensation scan signal SCj, and the fifth transistor T5 is turned on in response to the j-th emission control signal EMj.

[0075] The reference voltage VREF is applied to the anode of the light emitting element ED through the turned-on sixth transistor T6. Therefore, the anode of the light emitting element ED may be initialized to the reference voltage VREF. In addition, the reference voltage VREF is applied to the first node NA and the third node NC through the turned-on second transistor T2 and the fifth transistor T5. When the first transistor T1 is turned on in response to the reference voltage VREF applied to the first node NA, the reference voltage VREF may be applied to the second node NB through the turned-on first transistor T1. That is, the first period Ti may be an initialization period in which the anode of the light emitting element ED, the first node NA, the second node NB, and the third node NC are initialized to the reference voltage VREF.

[0076] During the first period Ti of the second write frame WF2, each of the (j-1)th emission control signal EMj-1 (i.e., the first emission control signal), the j-th write scan signal SWj (i.e., the second scan signal), and the j-th carrier capture inducing signal SDj has a disable level. Therefore, during the first period Ti, the fourth transistor T4 is turned off in response to the (j-1)th emission control signal EMj-1, and the third transistor T3 is turned off in response to the j-th write scan signal SWj.

[0077] The jth compensation scan signal SCj may be activated for a duration of the first period Ti (eg, one horizontal scan period (1H period)) before the jth write scan signal SWj. The (j-1)th emission control signal EMj-1 may be deactivated for a duration of the first period Ti before the jth emission control signal EMj.

[0078] Reference Figure 5A and Figure 5B During the second period Tw of the second write frame WF2, each of the j-th compensation scan signal SCj and the j-th write scan signal SWj has an activation level. Therefore, the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned on during the second period Tw. During the second period Tw of the second write frame WF2, each of the (j-1)th emission control signal EMj-1 and the j-th emission control signal EMj has a disable level. Therefore, during the second period Tw, the fourth transistor T4 and the fifth transistor T5 are turned off in response to the (j-1)th emission control signal EMj-1 and the j-th emission control signal EMj, respectively.

[0079] The potential of the anode of the light emitting element ED may be maintained as the reference voltage VREF by the sixth transistor T6 , which is turned on even during the second period Tw.

[0080] The i-th data voltage Vdata may be applied to the second node NB through the turned-on third transistor T3, and may be stored in the second capacitor C2. Moreover, the i-th data voltage Vdata is applied to the first node NA via the turned-on first transistor T1 and the second transistor T2. Therefore, the potential of the first node NA is changed to "Vdata-Vth". Here, "Vth" may be the threshold voltage of the first transistor T1. The second period Tw may be a writing period in which the data voltage Vdata is written to the first node NA.

[0081] In an embodiment of the present disclosure, the second period Tw may be a period continuous with the first period Ti, and the duration of the second period Tw may be substantially equal to the duration of the first period Ti. When the duration of the second period Tw is short, the potential of the first node NA may not have a sufficient voltage value corresponding to the deviation and change of the threshold voltage (Vth) of the first transistor T1. Therefore, after the second period Tw, a third period Tc1 for compensating for the deviation and change of the threshold voltage may be continuously provided.

[0082] Reference Fig. 6A and Figure 6B, during the third period Tc1 of the second writing frame WF2, the j-th compensation scanning signal SCj has an activation level, and the j-th writing scanning signal SWj has a disable level. During the third period Tc1, the second transistor T2 and the sixth transistor T6 may be turned on in response to the j-th compensation scanning signal SCj. Moreover, even when the third transistor T3 is turned off during the third period Tc1, the potential of the second node NB may be maintained by the second capacitor C2 while the i-th data voltage Vdata. Here, the potential of the second node NB may be lower than the potential of the i-th data voltage Vdata by the capacitance of the second capacitor C2 and the magnitude of the current flowing through the first transistor T1.

[0083] During the third period Tc1, the voltage of the second node NB can be applied to the first node NA through the turned-on first transistor T1 and second transistor T2. In this case, the duration of the third period Tc1 can be greater than the duration of the second period Tw. In an embodiment of the present disclosure, the duration of the third period Tc1 can be three times or more of the duration of the second period Tw. Therefore, during the third period Tc1, the deviation and change of the threshold voltage (Vth) of the first transistor T1 can be fully reflected in the potential of the first node NA.

[0084] The potential of the anode of the light emitting element ED may be maintained as the reference voltage VREF by the sixth transistor T6 , which is turned on even during the third period Tc1 .

[0085] During the third period Tc1 of the second writing frame WF2, each of the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj has a disable level. Therefore, during the third period Tc1, the fourth transistor T4 and the fifth transistor T5 are turned off in response to the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj, respectively.

[0086] Reference 7A to 7C During the fourth period Tc2 of the second write frame WF2, the j-th compensation scan signal SCj has an activation level, and the j-th write scan signal SWj has a disable level. In addition, during the fourth period Tc2, the (j-1)-th emission control signal EMj-1 has an activation level, and the j-th emission control signal EMj has a disable level. Therefore, during the fourth period Tc2, the second transistor T2 and the sixth transistor T6 may be turned on in response to the j-th compensation scan signal SCj, and the fourth transistor T4 may be turned on in response to the (j-1)-th emission control signal EMj-1.

[0087] When the duration of the third period Tc1 becomes longer, a voltage (eg, Vth) higher than the threshold voltage (Vth) of the first transistor T1 may be sensed at the gate-source node of the first transistor T1. Figure 7C The gate-source voltage Vgs is shown in FIG. 1 . Therefore, as Figure 7C As shown in , when the i-th data voltage Vdata of a high gray level is applied, a deviation of the drain current Id (ie, a current deviation) may occur due to a slope deviation at a threshold voltage (Vth) or less of the first transistor T1.

[0088] In an embodiment, the fourth transistor T4 may be turned on during the fourth period Tc2 to compensate for the current deviation. The first drive voltage ELVDD is applied to the second node NB through the turned-on fourth transistor T4. When the potential of the second node NB changes to the first drive voltage ELVDD, a current path from the second node NB to the first node NA is formed through the turned-on first transistor T1 and the second transistor T2. In this case, the current drained to the first node NA through the first transistor T1 and the second transistor T2 can be referred to as a "sink current". The magnitude of the sink current depends on the slope deviation at or below the threshold voltage (Vth) of the first transistor T1. The potential of the first node NA during the fourth period Tc2 can be changed to "Vdata-Vth-Vss" by the sink current. Here, "Vss" can be a voltage corresponding to the slope deviation at or below the threshold voltage (Vth) of the first transistor T1. Therefore, a voltage corresponding to the slope deviation at or below the threshold voltage (Vth) of the first transistor T1 can be stored (or reflected) at the first node NA.

[0089] Reference Fig. 8A and Figure 8B During the fifth period Te of the second writing frame WF2, each of the j-th compensation scanning signal SCj and the j-th writing scanning signal SWj has a disable level. Therefore, the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned off during the fifth period Te.

[0090] During the fifth period Te of the second write frame WF2, each of the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj has an activation level. Therefore, during the fifth period Te, the fourth transistor T4 and the fifth transistor T5 are turned on in response to the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj. When the fourth transistor T4 is turned on, the first drive voltage ELVDD is supplied to the second node NB. Therefore, the current flowing from the second node NB to the third node NC through the first transistor T1 can be applied to the light emitting element ED through the turned-on fifth transistor T5. The emission current Ied flowing to the light emitting element ED can be controlled according to the voltage level of the first node NA, and the light emitting element ED can output light with a brightness corresponding to the emission current Ied. Therefore, the fifth period Te can be an emission period in which the light emitting element ED emits light. In such an embodiment, the first period Ti, the second period Tw, the third period Tc1, and the fourth period Tc2 can be non-emission periods in which the light emitting element ED does not emit light.

[0091] The emission current Ied depends on the threshold voltage (Vth) of the first transistor T1. The threshold voltage (Vth) of the first transistor T1 may vary depending on the pixel PX (see Figure 1 ) position, and may be offset due to degradation according to operation time. In detail, since the degree of change (or degradation) of the threshold voltage (Vth) of the first transistor T1 is different for each pixel PX, the degree of offset of the threshold voltage (Vth) of the first transistor T1 is also different for each pixel PX.

[0092] In an embodiment, as described above in Fig. 6A and Figure 6B As described in , since the duration of the third period Tc1 is long enough, the deviation of the threshold voltage (Vth) and the change of the threshold voltage (Vth) can be fully compensated regardless of the operating frequency. Fig. 7A and Figure 7B As shown in , the current deviation can be compensated by turning on the fourth transistor T4 during the fourth period Tc2, so that the voltage (Vss) corresponding to the slope deviation at the threshold voltage (Vth) or less of the first transistor T1 is stored or reflected in the first node NA. Therefore, it is possible to effectively prevent the brightness deviation from being generated for each pixel PX due to the current deviation in the high grayscale area.

[0093] In an embodiment of the present disclosure, the j-th carrier capture inducing signal SDj has a first level Vhigh during the second write frame WF2. The j-th carrier capture inducing signal SDj maintains the first level Vhigh during the first period Ti, the second period Tw, the third period Tc1, the fourth period Tc2, and the fifth period Te. Here, the first level Vhigh may be a level corresponding to the disable level of the j-th compensation scan signal SCj and the j-th write scan signal SWj.

[0094] Fig.9A and Fig. 9B is a diagram for describing an operation of a pixel during a sixth period according to an embodiment of the present disclosure.

[0095] Reference Fig.9A and Fig. 9B , while holding frames HF1, HF2 and HF3 (see Figure 3B ), at the beginning of the first hold frame HF1 among the (j-1) first hold frame HF1, the i-th data voltage Vdata may be maintained as a bias voltage Vb. The bias voltage Vb may be a voltage maintained at a constant voltage level during the hold frames HF1, HF2, and HF3. In an embodiment of the present disclosure, the bias voltage Vb may have a voltage level corresponding to a black grayscale, but is not limited thereto. During the hold frames HF1, HF2, and HF3, each of the j-th compensation scan signal SCj and the j-th write scan signal SWj maintains a disable level. During the sixth period Tti (also referred to as the carrier capture induction period Tti) of the (j-1) first hold frame HF1, each of the emission control signal EMj-1 and the j-th emission control signal EMj has a disable level.

[0096] During the sixth period Tti, the j-th carrier capture inducing signal SDj has a second level Vlow different from the first level Vhigh. In an embodiment of the present disclosure, the second level Vlow may be a voltage level lower than the first level Vhigh. However, the present disclosure is not limited thereto. In an embodiment in which the first transistor T1 is an N-type transistor, the second level Vlow may be a voltage level higher than the first level Vhigh.

[0097] The sixth period Tti may be a period during the first hold frame HF1 in which both the (j-1)th emission control signal EMj-1 and the jth emission control signal EMj are in a disabled state. In an embodiment of the present disclosure, the duration of the sixth period Tti may be greater than the first period Ti (see Figure 4B In an embodiment of the present disclosure, the duration of the sixth time period Tti may be four times or more the duration of the first time period Ti.

[0098] When the voltage level of the j-th carrier capture inducing signal SDj is reduced to the second level Vlow lower than the first level Vhigh during the sixth period Tti, the potential of the first node NA may also be reduced due to the coupling of the first capacitor C1. When the potential of the first node NA is reduced, a carrier capture phenomenon in which electrons or holes are captured between the channel of the first transistor T1 and the gate insulator may be induced.

[0099] After the sixth period Tti, the seventh period Te_H may begin. The seventh period Te_H may be Fig. 8A and Figure 8B The fifth period Te shown in FIG. 1 is a period in which the operation is performed in the same manner. That is, the seventh period Te_H can also be defined as an emission period, and the seventh period Te_H can also be referred to as an emission period Te_H. Since the carrier capture phenomenon is first induced during the sixth period Tti before the start of the seventh period Te_H, the magnitude of the current change due to the carrier capture phenomenon during the seventh period Te_H can be reduced. The sixth time period Tti can be set in two seventh time periods. Between segments Te_H.

[0100] Fig. 9B Only the first hold frame HF1 among the hold frames HF1 , HF2 , and HF3 is shown, but the second hold frame HF2 and the third hold frame HF3 may also be operated in the same manner as the first hold frame HF1 .

[0101] Fig. 10A and Fig. 10B is a waveform diagram illustrating a reduction in emission current variation according to a carrier trap inducing signal according to an embodiment of the present disclosure. Fig. 10A It is shown that when the frames HF1, HF2 and HF3 (see Figure 3B ) period, the jth carrier capture induction signal SDj (see Fig. 9B ) is maintained at the first level Vhigh (see Fig. 9B ) when the emission current Ied (see Fig. 8A ) changes. Fig. 10B It is shown that when the frames HF1, HF2 and HF3 (see Figure 3B ) of the sixth period Tti (see Fig. 9B ) during which the j-th carrier capture induction signal SDj is changed to the second level Vlow (see Fig. 9B ) is the change of the emission current Ied measured at . Fig. 10A and Fig. 10B, the first waveform W1 and the third waveform W3 respectively represent the emission current Ied actually measured thereby, and the second waveform W2 and the fourth waveform W4 respectively represent values ​​obtained by integrating the first waveform W1 and the third waveform W3 in units of a preset reference time and then dividing the integrated values ​​by the reference time.

[0102] Reference Fig. 9B and Fig. 10A , when the j-th carrier capture inducing signal SDj does not change to the second level Vlow and remains at the first level Vhigh before the seventh period Te_H of the first hold frame HF1 starts, the carrier capture phenomenon may not occur. Then, when the seventh period Te_H starts, the carrier capture phenomenon occurs from the start time point of the seventh period Te_H. During the seventh period Te_H, the emission current Ied may occur (see Fig. 8A ) The current variation phenomenon that gradually decreases due to the carrier trapping phenomenon. When the carrier trapping phenomenon occurs after the start time point of the seventh period Te_H, the amount of variation of the emission current Ied may be approximately 4 nanoamperes (nA) (=56nA-52nA).

[0103] Reference Fig. 9B and Fig. 10B , during the sixth period Tti before the start of the seventh period Te_H of the first hold frame HF1, the j-th carrier capture inducing signal SDj may be reduced to the second level Vlow. In other words, before the start time point of the seventh period Te_H, the carrier capture phenomenon may occur in advance due to the j-th carrier capture inducing signal SDj. Therefore, the sixth period Tti may be referred to as a "carrier capture inducing period". When the seventh period Te_H starts after the carrier capture phenomenon has been performed during a predetermined time period (i.e., during the sixth period Tti), the emission current Ied reduced by the carrier capture phenomenon may be reduced (see Fig. 8A That is, when the carrier capture phenomenon occurs in advance before the start time point of the seventh period Te_H, the amount of change in the emission current Ied may be approximately 2 nA (=55 nA-53 nA).

[0104] Flow to the light emitting element ED (see Fig. 8A ) changes the emission current Ied in the frame HF1, HF2 and HF3 (see FIG. 1 ). Figure 3B ) generates a carrier capture phenomenon before the seventh period Te_H to reduce the variation of the emission current Ied during the seventh period Te_H. As a result, the flicker phenomenon can be effectively prevented or significantly reduced.

[0105] Fig.11 is a flowchart illustrating an operation process of a display device according to an embodiment of the present disclosure.

[0106] Reference Figure 1 , Figure 3A , Figure 3B and Fig.11 , an embodiment of the display device DD displays an image during a plurality of frames. At least one frame (eg, the second frame F2) among the plurality of frames includes a second writing frame WF2 and holding frames HF1, HF2, and HF3.

[0107] According to an embodiment of the driving method of the display device DD, the carrier capture control circuit 400 may generate a first level Vhigh (see FIG. 1 ) during the first writing frame WF1 and the second writing frame WF2. Fig. 9B ) is applied to the carrier-trapping inducing lines SDL1 to SDLn (step S110).

[0108] Then, the display device DD may determine whether at least one of the hold frames HF1, HF2, and HF3 (eg, the first hold frame HF1) starts (step S120).

[0109] When the start of the first holding frame HF1 is determined, the transmission period Te_H (see Fig. 9B ) before the carrier capture induction period Tti (see Fig. 9B ), the carrier capture control circuit 400 may have a second level Vlow (see Fig. 9B ) is sequentially applied to the carrier capture inducing lines SDL1 to SDLn (e.g., the level of the carrier capture inducing signal is changed to the second level Vlow during the carrier capture inducing period Tti of the hold frames HF1, HF2, and HF3) (step S130). However, when it is not determined that the hold frames HF1, HF2, and HF3 start, the process may proceed to operation S110, and the carrier capture control circuit 400 may maintain the carrier capture inducing signal at the first level Vhigh.

[0110] Then, when the carrier trap inducing period Tti ends and then the emission period Te_H starts, the carrier trap control circuit 400 may change the level of the carrier trap inducing signal to the first level Vhigh (step S140 ).

[0111] Then, the display device DD may determine whether the next hold frame (eg, the second hold frame HF2) starts (step S150). When it is determined that the second hold frame HF2 starts, the process may proceed to operation S130, and in the emission period Te_H of the second hold frame HF2 (see Fig. 9B ), the carrier trap inducing control circuit 400 may sequentially apply a carrier trap inducing signal having a second level Vlow lower than the first level Vhigh to the carrier trap inducing lines SDL1 to SDLn.

[0112] However, when the second hold frame HF2 does not start, the process may proceed to operation S110, and the carrier trap control circuit 400 may maintain the carrier trap inducing signal at the first level Vhigh.

[0113] In the embodiment of the present disclosure, the variation of the emission current Ied during the emission period Te_H can be reduced by generating a carrier capture phenomenon before the emission period Te_H during the holding frames HF1, HF2 and HF3. As a result, the flicker phenomenon can be effectively prevented or significantly reduced.

[0114] According to an embodiment of the present disclosure, even in high-speed operation, a sufficient compensation period can be ensured to compensate for the deviation or change of the threshold voltage of the first transistor, thereby minimizing the deviation of the current supplied to the light-emitting element when a low grayscale image is displayed at a high operating frequency. In such an embodiment, when a high grayscale image is displayed, a current deviation occurring at a voltage less than the threshold voltage is compensated by current injection, thereby preventing a brightness deviation from occurring due to the current deviation.

[0115] In such an embodiment, the variation of the emission current during the emission period can be reduced by generating a carrier capture phenomenon before the emission period during the hold frame. As a result, the flicker phenomenon can be effectively prevented or significantly reduced.

[0116] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0117] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, wherein: The display device comprises: Display panel, including pixels, Wherein, the pixels include: Light emitting element; a first capacitor connected to the first node; a second capacitor connected between the second node and the voltage line; a first transistor connected to the first node, the second node and a third node; a second transistor connected between the third node and the first node, wherein the second transistor receives a first scan signal; A third transistor is connected between the second node and the data line, wherein the third transistor receives a second scanning signal; a fourth transistor connected between the second node and the voltage line, wherein the fourth transistor receives a first emission control signal; a fifth transistor connected between the third node and the light emitting element, wherein the fifth transistor receives a second emission control signal; and A sixth transistor is connected between the light emitting element and the reference voltage line, wherein the sixth transistor receives a third scanning signal.

2. The display device according to claim 1, wherein: During a first period, each of the first scan signal and the third scan signal has an activation level, and Wherein, during the first period, the first emission control signal has a disable level, and the second emission control signal has the activate level.

3. The display device according to claim 2, wherein: During the first period, the first node, the second node, and the third node are initialized to a reference voltage applied through the reference voltage line.

4. The display device according to claim 2, wherein: The first scanning signal and the third scanning signal are the same signal as each other, and The first scanning signal and the third scanning signal are activated for a duration of the first period before the second scanning signal.

5. The display device according to claim 4, wherein: The second period is after the first period, wherein, during the second period, each of the first scan signal, the second scan signal, and the third scan signal has the activation level, and During the second period, each of the first emission control signal and the second emission control signal has the disable level.

6. The display device according to claim 5, wherein: During the second period, the data voltage applied to the data line is applied to the first node by sequentially passing through the third transistor, the first transistor, and the second transistor, which are turned on in response to the first scan signal and the second scan signal.

7. The display device according to claim 5, wherein: The third period is after the second period, wherein, during the third period, each of the first scan signal and the third scan signal has the activation level, and During the third period, each of the second scan signal, the first emission control signal, and the second emission control signal has the disable level.

8. The display device according to claim 7, wherein: The duration of the first period is equal to the duration of the second period, and The duration of the third time period is greater than the duration of each of the first time period and the second time period.

9. The display device according to claim 7, wherein: The fourth period is after the third period, wherein, during the fourth period, each of the first scan signal, the third scan signal, and the first emission control signal has the activation level, and During the fourth period, each of the second scan signal and the second emission control signal has the disable level.

10. The display device according to claim 9, wherein: The duration of the fourth period is equal to the duration of the second period, and The duration of the third time period is greater than the duration of each of the first time period and the second time period.

11. The display device according to claim 10, wherein: During the fourth period, the second transistor and the fourth transistor are turned on in response to the first scan signal and the first emission control signal, respectively, and The current is discharged to the first node through the turned-on fourth transistor, the first transistor and the second transistor.

12. The display device according to claim 9, wherein: The fifth period is after the fourth period. wherein, during the fifth period, each of the first emission control signal and the second emission control signal has the activation level, and During the fifth period, each of the first scan signal, the second scan signal, and the third scan signal has the disable level.

13. The display device according to claim 1, wherein: The display panel displays an image during a plurality of frames, and at least one of the plurality of frames includes a writing frame and a holding frame, wherein each of the first scanning signal, the second scanning signal, and the third scanning signal has an activation level within the write frame and maintains a disabled state during the hold frame, and Wherein, each of the first emission control signal and the second emission control signal has the activation level in the write frame and the hold frame.

14. The display device according to claim 13, wherein: The first capacitor is connected between a carrier trap induction line receiving a carrier trap induction signal and the first node, and The carrier capture inducing signal has a first level during the write frame and has a second level different from the first level during the hold frame.

15. The display device according to claim 14, wherein: During the holding frame, the sixth time period is before the seventh time period, wherein, during the sixth period, each of the first scan signal, the second scan signal, the third scan signal, the first emission control signal, and the second emission control signal has a disable level, and During the sixth period, the carrier capture inducing signal has the second level.

16. The display device according to claim 15, wherein: During the seventh period, each of the first emission control signal and the second emission control signal has the activation level, and Wherein, the carrier capture inducing signal has the first level.

17. The display device according to claim 1, wherein: The display device further includes: A panel driver drives the display panel. Wherein, the panel driver comprises: a scan driving circuit, the scan driving circuit outputting the first scan signal, the second scan signal and the third scan signal; and an emission driving circuit, the emission driving circuit outputting the first emission control signal and the second emission control signal, and Wherein, the emission driving circuit operates at a frequency higher than or equal to the frequency of the scan driving circuit.

18. The display device according to claim 17, wherein: The first capacitor is connected between a carrier trap induction line receiving a carrier trap induction signal and the first node, and Wherein, the panel driver further includes: A carrier capture control circuit supplies the carrier capture inducing signal to the carrier capture inducing line.

19. The display device according to claim 18, wherein: The display panel displays an image during a plurality of frames, and at least one of the plurality of frames includes a writing frame and a holding frame, and The carrier capture inducing signal has a first level during the write frame and has a second level lower than the first level during the hold frame.

20. A display device, wherein: The display device comprises: A display panel including pixels; and A panel driver drives the display panel. Wherein, the pixels include: Light emitting element; A first capacitor connected between a carrier capture induction line receiving a carrier capture induction signal and a first node; a first transistor connected between the second node and a third node, wherein the first transistor operates according to a potential of the first node; a second transistor connected between the third node and the first node, wherein the second transistor operates according to a first scan signal; and a third transistor connected between the second node and the data line, wherein the third transistor operates according to a second scanning signal, wherein the display panel displays an image during a plurality of frames, and at least one of the plurality of frames includes a writing frame and a holding frame, and wherein the carrier capture inducing signal has a first level during the writing frame, and has a second level different from the first level during a carrier capture induction period prior to an emission period of the holding frame.

21. The display device according to claim 20, wherein: The second level is lower than the first level, and The carrier capture inducing signal has the first level during the emission period of the holding frame.

22. The display device according to claim 20, wherein: The panel driver comprises: a carrier capture control circuit, the carrier capture control circuit supplying the carrier capture induction signal to the carrier capture induction line; and a scanning driving circuit, the scanning driving circuit outputting the first scanning signal and the second scanning signal, and Wherein, each of the first scan signal and the second scan signal has a disable level during the carrier capture induction period.

23. The display device according to claim 20, wherein: The pixel also includes: a second capacitor connected between the second node and the voltage line; a fourth transistor connected between the second node and the voltage line, wherein the fourth transistor operates according to a first emission control signal; and A fifth transistor is connected between the third node and the light emitting element, wherein the fifth transistor operates according to a second emission control signal.

24. The display device according to claim 23, wherein: The write frame includes: a first time period, during which the first scan signal and the second emission control signal are activated, and the second scan signal and the first emission control signal are disabled; a second period, during which the first scan signal and the second scan signal are activated, and the first emission control signal and the second emission control signal are disabled; a third period, in which the first scan signal is activated, and the second scan signal, the first emission control signal, and the second emission control signal are disabled; a fourth period, in which the first scan signal and the first emission control signal are activated, and the second scan signal and the second emission control signal are disabled; and and a fifth period in which the first scan signal and the second scan signal are disabled and the first emission control signal and the second emission control signal are activated.

25. The display device according to claim 24, wherein: The second level is lower than the first level, and During the first period, the second period, the third period, the fourth period and the fifth period, the carrier capture inducing signal has the first level.

26. A method for driving a display device, the display device comprising a display panel, the display panel comprising pixels, wherein: The pixels include: Light emitting element; A first capacitor connected between the carrier trapping induction line and the first node; a first transistor connected between the second node and the third node; a second transistor connected between the third node and the first node; and a third transistor connected between the second node and the data line, wherein the display panel displays an image during a plurality of frames, and at least one of the plurality of frames includes a writing frame and a holding frame, and Wherein, the driving method comprises: applying a carrier trap inducing signal having a first level to the carrier trap inducing line during the write frame; Determine whether the hold frame starts; When it is determined that the hold frame starts, applying the carrier capture inducing signal having a second level lower than the first level to the carrier capture inducing line during a carrier capture inducing period before an emission period of the hold frame; and The carrier trap inducing signal having the first level is applied to the carrier trap inducing line during the emission period of the hold frame.

27. The driving method according to claim 26, wherein: The pixel also includes: a second capacitor connected between the second node and the voltage line; a fourth transistor connected between the second node and the voltage line, wherein the fourth transistor operates according to a first emission control signal; and a fifth transistor connected between the third node and the light emitting element, wherein the fifth transistor operates according to a second emission control signal, and The second transistor operates according to a first scan signal, and the third transistor operates according to a second scan signal.

28. The driving method according to claim 27, wherein: The driving method further includes: During a first period of the write frame, activating the first scan signal and the second emission control signal, and deactivating the second scan signal and the first emission control signal; During a second period of the write frame, activating the first scan signal and the second scan signal, and disabling the first emission control signal and the second emission control signal; During a third period of the write frame, activating the first scan signal, and deactivating the second scan signal, the first emission control signal, and the second emission control signal; During a fourth period of the write frame, activating the first scan signal and the first emission control signal, and deactivating the second scan signal and the second emission control signal; and During a fifth period of the write frame, the first scan signal and the second scan signal are disabled, and the first emission control signal and the second emission control signal are activated.

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