Pixel and display device

Abstract

The invention relates to a pixel and a display device. The pixel may include: a first transistor including a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor including a second electrode, a first electrode electrically connected to the data line, and a gate electrode electrically connected to the first scan line; a third transistor connected between the first node and the data line, and including a gate electrode electrically connected to a second scan line; a first capacitor including a first electrode connected to the second electrode of the second transistor and a second electrode connected to the first node; a second capacitor connected between the first power line and the first node; and a light emitting element connected between a second power line and the first transistor, and including a second electrode electrically connected to the second power line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0082999, filed on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a pixel and a display device including the pixel. Background Art

[0004] As information technology has developed, display devices such as liquid crystal display devices and organic light-emitting display devices have become increasingly important. Recently, head-mounted display devices (HMDs) have been developed. A head-mounted display device (HMD) is a display device that a user can wear in the form of glasses or a helmet, and the HMD is generally used to create a virtual reality (VR) experience or an augmented reality (AR) experience that forms a focus at a short distance in front of the user's eyes. Therefore, a head-mounted display device may adopt a high-resolution panel, requiring pixels suitable for the high-resolution panel. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a pixel that can be applied to a high-resolution panel and a display device including the pixel.

[0006] An embodiment of the present disclosure may provide a pixel, comprising: a first transistor, comprising a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor, comprising a second electrode, a first electrode electrically connected to a data line, and a gate electrode electrically connected to a first scan line; a third transistor, connected between the first node and the data line, and the third transistor comprising a gate electrode electrically connected to the second scan line; a first capacitor, comprising a first electrode connected to the second electrode of the second transistor and a second electrode connected to the first node; a second capacitor, connected between the first power line and the first node; and a light-emitting element, connected between the second power line and the first transistor, and the light-emitting element comprising a second electrode electrically connected to the second power line.

[0007] In an embodiment, the first transistor may be a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode.

[0008] In an embodiment, a voltage of a first driving power may be supplied to the first power line, and the voltage of the first driving power may be supplied to the body electrode.

[0009] In an embodiment, the pixel may further include: a fourth transistor connected between the first node and a second node connected to the second electrode of the first transistor, and the fourth transistor includes a gate electrode electrically connected to a third scan line; a fifth transistor connected between the second node and the first electrode of the light-emitting element, and the fifth transistor includes a gate electrode electrically connected to an emission control line; and a sixth transistor including a first electrode electrically connected to the first electrode of the light-emitting element, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to a fourth scan line.

[0010] In an embodiment, each of the first to sixth transistors may be a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode.

[0011] In an embodiment, a voltage of a first driving power may be supplied to the first power line, and the voltage of the first driving power may be supplied to the body electrode of each of the first to sixth transistors.

[0012] In an embodiment, the second scan line may be set as a third scan line positioned on a previous horizontal line.

[0013] In an embodiment, a second driving power having a voltage lower than the voltage of the first driving power may be supplied to the second power line.An initialization power having a voltage value at which the light emitting element does not emit light may be supplied to the third power line.

[0014] In an embodiment, a voltage value obtained by subtracting the voltage of the second driving power from a voltage obtained by adding the absolute threshold voltage of the fifth transistor to the voltage of the initialization power may be set to a voltage lower than a threshold voltage of the light emitting element.

[0015] In an embodiment, the initialization power may be set to ground power (GND).

[0016] In an embodiment, a single horizontal period of operation of the pixel may include a first period and a second period. A voltage of a reference power between the voltage of the first drive power and the voltage of the second drive power may be supplied to the data line during the first period, and a voltage of a data signal may be supplied to the data line during the second period. During the first period, the second transistor, the fourth transistor, and the sixth transistor may be set to a conducting state, and the third transistor and the fifth transistor may be set to a cut-off state. During the second period, the second transistor and the sixth transistor may be set to the conducting state, and the third transistor, the fourth transistor, and the fifth transistor may be set to the cut-off state.

[0017] In an embodiment, during a zeroth period before the first period, the third transistor and the sixth transistor may be set to the on state, and the second transistor, the fourth transistor, and the fifth transistor may be set to the off state. During the zeroth period, the voltage of the reference power may be supplied to the data line.

[0018] In an embodiment, during a third period after the second period, the first transistor, the fifth transistor, and the sixth transistor may be set to the on state, and the second transistor, the third transistor, and the fourth transistor may be set to the off state. During a fourth period after the third period, the first transistor and the fifth transistor may be set to the on state, and the second transistor, the third transistor, the fourth transistor, and the sixth transistor may be set to the off state.

[0019] An embodiment of the present disclosure may provide a pixel, the pixel comprising: a light-emitting element comprising a second electrode electrically connected to a second power line; a first transistor comprising a second electrode, a first electrode electrically connected to the first power line, and a gate electrode connected to a first node; a second transistor comprising a second electrode, a first electrode electrically connected to a data line, and a gate electrode electrically connected to a first scan line; a third transistor comprising a first electrode connected to the first node, a second electrode electrically connected to a fourth power line to which a voltage of a reference power is supplied, and a gate electrode electrically connected to the second scan line; a fourth transistor connected between the first node and a second node connected to the second electrode of the first transistor, and the fourth transistor comprising a gate electrode electrically connected to the third scan line; a fifth transistor connected between the second node and the first electrode of the light-emitting element, and the fifth transistor comprising a gate electrode electrically connected to an emission control line; a sixth transistor comprising a first electrode electrically connected to the first electrode of the light-emitting element, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the fourth scan line; a first capacitor connected between the second electrode of the second transistor and the first node; and a second capacitor connected between the first power line and the first node.

[0020] An embodiment of the present disclosure may provide a display device including: a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of fourth scan lines, a plurality of data lines, and a plurality of emission control lines. Among the multiple pixels, a pixel positioned in the i-th pixel row (i is an integer greater than 0) and the j-th pixel column (j is an integer greater than 0) may include: a first transistor including a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor including a second electrode and a first electrode electrically connected to a j-th data line among the multiple data lines, and the second transistor is configured to be turned on when a first scan signal is supplied to an i-th first scan line among the multiple first scan lines; a third transistor connected between the first node and the j-th data line, and the third transistor is configured to be turned on when a second scan signal is supplied to an i-th second scan line among the multiple second scan lines; a first capacitor connected between the second electrode of the second transistor and the first node; a second capacitor connected between the first power line and the first node; and a light-emitting element connected between the second power line and the first transistor, and the light-emitting element includes a second electrode electrically connected to the second power line.

[0021] In an embodiment, the first transistor may be configured as a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode, and the body electrode may be electrically connected to the first power line.

[0022] In an embodiment, the pixel positioned in the i-th pixel row and the j-th pixel column may further include: a fourth transistor connected between a second node connected to the second electrode of the first transistor and the first node, and the fourth transistor is configured to be turned on when a third scan signal is supplied to the i-th third scan line among the multiple third scan lines; a fifth transistor connected between the second node and the first electrode of the light-emitting element, and the fifth transistor is configured to be turned off when an emission control signal is supplied to the k-th emission control line among the multiple emission control lines (wherein k is an integer greater than 0); and a sixth transistor including a first electrode electrically connected to the first electrode of the light-emitting element and a second electrode electrically connected to a third power line, and the sixth transistor is configured to be turned off when a fourth scan signal is supplied to the i-th fourth scan line among the multiple fourth scan lines.

[0023] In an embodiment, each of the first to sixth transistors may be configured as a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode, and the body electrode of each of the first to sixth transistors may be electrically connected to the first power line.

[0024] In an embodiment, the display device may further include: a data driver configured to supply a data signal to the plurality of data lines; a first scan driver configured to supply the first scan signal to the plurality of first scan lines; a second scan driver configured to supply the second scan signal to the plurality of second scan lines; a third scan driver configured to supply the third scan signal to the plurality of third scan lines; a fourth scan driver configured to supply the fourth scan signal to the plurality of fourth scan lines; and an emission driver configured to supply the emission control signal to the plurality of emission control lines.

[0025] In an embodiment, the horizontal period during which the pixels positioned in the i-th pixel row and the j-th pixel column are driven may include a first period and a second period. The data driver may supply a voltage of a reference power to the j-th data line during the first period and supply the data signal to the j-th data line during the second period. The first scan driver may supply the first scan signal to the i-th first scan line during the first period and the second period. The second scan driver may supply the second scan signal to the i-th second scan line during the zeroth period before the first period. The third scan driver may supply the third scan signal to the i-th third scan line during the first period. The fourth scan driver may supply the fourth scan signal to the i-th fourth scan line during the zeroth period, the first period, the second period, and the third period after the second period. The emission driver may supply the emission control signal to the k-th emission control line during the zeroth period, the first period, and the second period.

[0026] The objects of the present disclosure are not limited to the objects stated above, and other unmentioned objects will be clearly understood by those skilled in the art from the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram showing a transistor according to an embodiment of the present disclosure.

[0028] Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 3 It is shown Figure 2 An embodiment of a scan driver and an emission driver is shown in FIG.

[0030] Figure 4 is an equivalent circuit diagram showing a pixel according to an embodiment of the present disclosure.

[0031] Figure 5 Is shown driving Figure 4 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0032] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E is shown with Figure 5 A driving waveform corresponds to a diagram of an embodiment of a process of operating a pixel.

[0033] Figure 7 is shown in response to Figure 4FIG. 5 is a graph showing a change in driving current as a function of a change in the threshold voltage of the first transistor in the pixel shown in FIG.

[0034] Figure 8 It is shown Figure 4 Graph of the current error of the pixel shown in .

[0035] Fig. 9 is a circuit diagram showing a pixel according to an embodiment of the present disclosure.

[0036] Fig.10 is a circuit diagram showing a pixel according to an embodiment of the present disclosure.

[0037] Fig.11 is a circuit diagram showing a pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the disclosed embodiments. The present disclosure may be implemented in various forms and is not limited to the embodiments to be described below herein.

[0039] In the accompanying drawings, parts not related to the present disclosure may be omitted in order to more clearly illustrate the present disclosure. Reference should be made to the accompanying drawings in which similar reference numerals are used in different drawings to designate similar components. Therefore, the aforementioned reference numerals may be used in other drawings.

[0040] For reference, for the purpose of explanation, the size of each component and the thickness of the line showing the component may be arbitrarily represented, and the present disclosure is not limited to the contents shown in the drawings. In the drawings, the thickness of the components may be exaggerated to clearly depict multiple layers and regions.

[0041] Furthermore, the expression “is the same” may mean “is substantially the same.” In other words, the expression “is the same” may include a tolerable range. Other expressions may also be expressions from which the term “substantially” has been omitted.

[0042] Some embodiments are described in conjunction with functional blocks, units and / or modules shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules can be physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. These can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and can be selectively driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform different functions. In addition, in some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules can be physically divided into two or more separate blocks, units and / or modules that interact with each other. In some embodiments, without departing from the scope of the present invention, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules.

[0043] The term "connection" between two components may cover both electrical and physical connections, but the present disclosure is not limited thereto. For example, the term "connection" used when describing with reference to a circuit diagram may refer to an electrical connection, and the term "connection" used when describing with reference to a cross-sectional view or a plan view may refer to a physical connection.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0045] The present disclosure is not limited to the following embodiments and may be modified in various forms. Each embodiment to be described below may be implemented alone or at least combined with another embodiment to make various combinations of the embodiments.

[0046] Figure 1 is a diagram showing a transistor 1 according to an embodiment of the present disclosure.

[0047] refer to Figure 1 , the transistor 1 may include a first electrode 2, a second electrode 4, a gate electrode 6, and a body electrode 8. For example, the transistor 1 may be a metal oxide semiconductor field effect transistor (MOSFET). The transistor 1 (e.g., MOSFET) including the body electrode 8 may be suitable for realizing a high-resolution pixel due to its reduced mounting area.

[0048] The transistor 1 may be formed on a silicon wafer. For example, a panel may be realized by stacking layers such as a transistor layer, an emission layer, and a capping layer on a silicon wafer. However, the foregoing description is illustrative, and the transistor 1 may be formed on various known substrates (e.g., a glass substrate).

[0049] The first electrode 2 of the transistor 1 may be set as a source electrode (or a drain electrode), and the second electrode 4 of the transistor 1 may be set as a drain electrode (or a source electrode). In the case where the transistor 1 includes a body electrode 8, the threshold voltage of the transistor 1 may be changed by a body effect. The body effect refers to the change in the threshold voltage of the transistor 1 due to the voltage difference between the body electrode 8 and the first electrode 2 of the transistor 1. For example, as the voltage difference (e.g., VBS) between the body electrode 8 and the first electrode (e.g., source electrode) 2 increases, the threshold voltage of the transistor 1 may also increase.

[0050] In the driving transistor of the pixel, the first electrode 2 and the body electrode 8 of the transistor 1 may be required to be set to the same voltage during the threshold voltage compensation period and the emission period. However, during the threshold voltage compensation period and the emission period, different voltages are usually supplied to the first electrode of the driving transistor. In this case, if the body electrode is not used, the threshold voltage of the driving transistor during the threshold voltage compensation period is set to a value different from the threshold voltage of the driving transistor during the emission period. As a result, the threshold voltage of the driving transistor may not be compensated. Therefore, in an embodiment of the present disclosure, the pixel uses a transistor 1 including a body electrode 8 as a driving transistor, and is capable of compensating the threshold voltage.

[0051] Figure 2 is a diagram illustrating a display device 100 according to an embodiment of the present disclosure. Figure 3 It is shown Figure 2 1. An embodiment of the scan driver 130 and the emission driver 150 is shown in FIG.

[0052] refer to Figure 2 , also refer to Figures 3 to 5 , the display device 100 according to an embodiment of the present disclosure may include a pixel component 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, an emission driver 150, and a power supply 160. The aforementioned components may be implemented as separate integrated circuits. Two or more of the aforementioned components may be implemented in a single integrated circuit. The scan driver 130 and the emission driver 150 may be included in the pixel component 110.

[0053] The pixel assembly 110 may include pixels PX (wherein n, m and o are integers greater than 0) connected to first scan lines SL11, SL12, ...SL1n, second scan lines SL21, SL22, ...SL2n, third scan lines SL31, SL32, ...SL3n, fourth scan lines SL41, SL42, ...SL4n, data lines DL1, DL2, ...DLm, emission control lines EL1, EL2, ...ELo, and power lines PL1, PL2 and PL3.

[0054] The pixels PX may form an array. For example, the pixels PXij (refer to Figure 4 ) can be connected to the i-th first scan line SL1i (hereinafter, also referred to as the first scan line SL1i), the i-th second scan line SL2i (hereinafter, also referred to as the second scan line SL2i), the i-th third scan line SL3i (hereinafter, also referred to as the third scan line SL3i), the i-th fourth scan line SL4i (hereinafter, also referred to as the fourth scan line SL4i), the k-th emission control line ELk (hereinafter, also referred to as the emission control line ELk) and the j-th data line DLj (hereinafter, also referred to as the data line DLj) (wherein i is an integer greater than 0 and less than or equal to n, j is an integer greater than 0 and less than or equal to m, and k is an integer greater than 0 and less than or equal to o). Here, k is an integer greater than 0 and less than or equal to i. For example, in the case where each of the emission control lines EL1 to ELo is connected to the pixels PX positioned on one horizontal line, k is the same number as i. For example, in the case where each of the emission control lines EL1 to ELo is connected to the pixels PX positioned on two or more horizontal lines, k is an integer greater than 0 and less than i.

[0055] When the first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX may be selected based on horizontal lines (for example, the pixels PX connected to the same scan line may be grouped into one horizontal line (or one pixel row)). Each of the pixels PX selected by the first scan signal may receive a data signal from a corresponding data line (one of the data lines DL1 to DLm) connected to the pixel PX. The pixel PX receiving the data signal may generate light of a specific level of brightness in response to the voltage of the data signal.

[0056] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required to drive the scan driver 130. The scan driver 130 may generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal while shifting the scan start signal in response to the clock signal.

[0057] In order to achieve the above purpose, Figure 3 As shown in FIG. 1 , the scan driver 130 may include a first scan driver 132 , a second scan driver 134 , a third scan driver 136 , and a fourth scan driver 138 .

[0058] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 may sequentially supply the first scan signal to first scan lines SL11 to SL1n among the first scan lines SL1.

[0059] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially supply the second scan signal to the second scan lines SL21 to SL2n among the second scan lines SL2.

[0060] The third scan driver 136 may receive the third scan start signal FLM3 and generate a third scan signal while shifting the third scan start signal FLM3 in response to the clock signal The third scan driver 136 may sequentially supply the third scan signal to third scan lines SL31 to SL3n among the third scan lines SL3.

[0061] The fourth scan driver 138 may receive the fourth scan start signal FLM4 and generate a fourth scan signal while shifting the fourth scan start signal FLM4 in response to the clock signal. The fourth scan driver 138 may sequentially supply the fourth scan signal to fourth scan lines SL41 to SL4n among the fourth scan lines SL4.

[0062] Each of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal may be set to a gate-on voltage to turn on a transistor included in the pixel PX.

[0063] For example, a low-level first scan signal, a second scan signal, a third scan signal, and a fourth scan signal may be supplied to a P-type transistor. A high-level first scan signal, a second scan signal, a third scan signal, and a fourth scan signal may be supplied to an N-type transistor. A transistor supplied with the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal may be turned on in response to the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal.

[0064] Supplying the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal to one of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 may mean that a gate-on voltage is supplied to the first scan line SL1, the second scan line SL2, the third scan line SL3, or the fourth scan line SL4. Not supplying the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal may mean that a gate-off voltage is supplied to the first scan line SL1, the second scan line SL2, the third scan line SL3, or the fourth scan line SL4.

[0065] although Figure 3 It is shown that the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 are connected to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4, respectively, but the embodiments of the present disclosure are not limited thereto. For example, a single scan driver may be connected to two or more of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 and drive the two or more of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4. In particular, at least two of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 may be driven by a single scan driver.

[0066] Figure 2 The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required to drive the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale value or intensity value of the output data Dout. The data driver 140 may generate a grayscale value or an intensity value of the output data Dout in one horizontal period 1H (reference Figure 5 ) during which the voltage of the reference power Vref and the voltage Vdata of the data signal are sequentially supplied to the data lines DL1 to DLm. The voltage of the reference power Vref may be set to a constant voltage.

[0067] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. The emission driving signal ECS may include an emission start signal and a clock signal required to drive the emission driver 150. The emission driver 150 may generate an emission control signal EM (reference signal EM) while shifting the emission start signal in response to the clock signal. Figure 4 or Figure 5 ).

[0068] For example, Figure 3 As shown in , the emission driver 150 may receive the emission start signal EFLM and generate the emission control signal EM while shifting the emission start signal EFLM in response to the clock signal. The emission driver 150 may sequentially supply the emission control signal EM to the emission control lines EL1 to ELo. The emission control signal EM may be set to a gate-off voltage so that the transistor included in the pixel PX is turned off.

[0069] For example, a high-level emission control signal may be supplied to a P-type transistor, and a low-level emission control signal may be supplied to an N-type transistor. The transistor supplied with the emission control signal may be turned off in response to the emission control signal. Thereafter, supplying an emission control signal to one of the emission control lines EL may mean that a gate-off voltage is supplied to the emission control line EL. Not supplying an emission control signal may indicate that a gate-on voltage is supplied to the emission control line EL.

[0070] The timing controller 120 may receive input data Din and a control signal CS from a host system through an interface. For example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals including a clock signal.

[0071] The timing controller 120 may generate a scan drive signal SCS, a data drive signal DCS, and an emission drive signal ECS based on the control signal CS. As described above, the scan drive signal SCS, the data drive signal DCS, and the emission drive signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0072] The timing controller 120 may rearrange the input data Din to match the specifications of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate output data Dout, and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result obtained during a manufacturing process for the display device 100.

[0073] The power supply 160 may generate various power voltages required to drive the display device 100. For example, the power supply 160 may generate a first driving power VDD, a second driving power VSS, and an initialization power Vint.

[0074] The first driving power VDD may be provided to supply a driving current to the pixel PX. The second driving power VSS may be provided to receive a driving current from the pixel PX. During a period in which the pixel PX is set to an emission state, a voltage of the first driving power VDD may be set to a voltage higher than a voltage of the second driving power VSS.

[0075] The voltage of the initialization power Vint may be a voltage provided to initialize the light emitting element LD included in each of the pixels PX (refer to Figure 4 ) is a voltage of a first electrode (or anode electrode). The voltage of the initialization power Vint may have a voltage value that turns off the light emitting element LD when the voltage of the initialization power Vint is supplied to the first electrode of the light emitting element LD. For example, the voltage of the initialization power Vint may be set to the ground potential GND.

[0076] A voltage of the first driving power VDD generated from the power source 160 may be supplied to the first power line PL1, a voltage of the second driving power VSS generated from the power source 160 may be supplied to the second power line PL2, and a voltage of the initialization power Vint generated from the power source 160 may be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0077] In an embodiment, the first power line PL1 may include a plurality of first power lines. The plurality of first power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may include a plurality of second power lines. The plurality of second power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may include a plurality of third power lines. The plurality of third power lines may be connected to different pixels PX. In other words, in an embodiment of the present disclosure, the pixel PX may be connected to any one of the first power line PL1, any one of the second power line PL2, and any one of the third power line PL3.

[0078] Figure 4 is an equivalent circuit diagram showing a pixel PXij according to an embodiment of the present disclosure. Figure 4 , the pixel PXij may represent a pixel PX positioned on an i-th horizontal line and a j-th vertical line in the array of pixels PX.

[0079] refer to Figure 4 , the pixel PXij according to an embodiment of the present disclosure may be connected to corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk and DLj. For example, the pixel PXij may be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXij may also be connected to the first power line PL1, the second power line PL2 and the third power line PL3.

[0080] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit configured to control the amount of current to be supplied to the light emitting element LD.

[0081] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. For example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the third node N3, the fifth transistor M5, the second node N2, and the first transistor M1. The second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a specific brightness corresponding to the amount of current supplied from the first power line PL1 to the light emitting element LD (or the second power line PL2) via the pixel circuit.

[0082] An organic light emitting diode may be selected as the light emitting element LD. Alternatively, an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode may be selected as the light emitting element LD. The light emitting element LD may be an element formed by a combination of an organic material and an inorganic material. Figure 4 It is shown that the pixel PXij includes a single light emitting element LD, but the pixel PXij in the embodiment may include a plurality of light emitting elements LD. The plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0083] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0084] Each of the first transistor M1 to the sixth transistor M6 may be a MOSFET including a body electrode. In this case, the first transistor M1 to the sixth transistor M6 may be mounted in a relatively small area, so that the pixel PXij is applied to a high-resolution panel. The first transistor M1 to the sixth transistor M6 may have respective body electrodes supplied with a voltage of the first drive power VDD. For example, the body electrodes of the first transistor M1 to the sixth transistor M6 may be electrically connected to the first power line PL1.

[0085] In an embodiment, each of the first to sixth transistors M1 to M6 may be formed of a P-type transistor. However, this is illustrative, and at least one of the first to sixth transistors M1 to M6 may be an N-type transistor instead.

[0086] The first transistor M1 (the first transistor M1 is a driving transistor) may include a first electrode electrically connected to the first power line PL1 and a second electrode connected to the second node N2. Here, the term "connection" implies electrical connection or electrical engagement. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current to be supplied from the first power line PL1 to which the voltage of the first drive power VDD is supplied to the second power line PL2 to which the voltage of the second drive power VSS is supplied via the light emitting element LD in response to the voltage of the first node N1.

[0087] The second transistor M2 may be connected between the data line DLj and the first electrode of the first capacitor C1. The gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. When the first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned on to electrically connect the data line DLj to the first electrode of the first capacitor C1.

[0088] The third transistor M3 may be connected between the data line DLj and the first node N1. A gate electrode of the third transistor M3 may be electrically connected to the second scan line SL2i. When the second scan signal GI is supplied to the second scan line SL2i, the third transistor M3 may be turned on to electrically connect the data line DLj to the first node N1.

[0089] The fourth transistor M4 may be connected between the first node N1 and the second node N2. The gate electrode of the fourth transistor M4 may be electrically connected to the third scan line SL3i. When the third scan signal GC is supplied to the third scan line SL3i, the fourth transistor M4 may be turned on to electrically connect the first node N1 and the second node N2. In this case, the gate electrode of the first transistor M1 (i.e., the first node N1) and the second electrode of the first transistor M1 (i.e., the second node N2) may be electrically connected to each other, so that the first transistor M1 is connected in a diode manner, i.e., connected to form a diode or operate as a diode.

[0090] The fifth transistor M5 may be connected between the second node N2 and the third node N3 (i.e., the first electrode of the light emitting element LD). The gate electrode of the fifth transistor M5 may be electrically connected to the emission control line ELk. The fifth transistor M5 may be turned off when the emission control signal EM is supplied to the emission control line ELk, and may be turned on when the emission control signal EM is not supplied to the emission control line ELk. If the fifth transistor M5 is turned off, the first transistor M1 and the light emitting element LD may be electrically disconnected from each other.

[0091] The sixth transistor M6 may include a first electrode connected to the third node N3 and a second electrode electrically connected to the third power line PL3. The gate electrode of the sixth transistor M6 may be electrically connected to the fourth scan line SL4i. When the fourth scan signal GB is supplied to the fourth scan line SL4i, the sixth transistor M6 may be turned on. If the sixth transistor M6 is turned on, the voltage of the initialization power Vint may be supplied to the third node N3. Here, the voltage of the initialization power Vint may be set to the ground potential GND.

[0092] The first electrode of the first capacitor C1 may be connected to the second electrode of the second transistor M2. The second electrode of the first capacitor C1 may be connected to the first node N1. The first capacitor C1 may change the voltage of the first node N1 in response to the voltage supplied from the second transistor M2. For example, the first capacitor C1 may be driven as a coupling capacitor.

[0093] The second capacitor C2 may include a first electrode electrically connected to the first power line PL1 and a second electrode connected to the first node N1. In other words, the second capacitor C2 may be connected between the first power line PL1 and the first node N1. The second capacitor C2 may store or maintain a voltage of the first node N1, particularly when the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off.

[0094] Figure 5 Is shown driving Figure 4 0045] A waveform diagram of an embodiment of the method for a pixel PXij is shown in FIG.

[0095] refer to Figure 5 , also refer to Figures 2 to 4 , a horizontal period 1H (or a specific horizontal period) in which data signals are supplied to pixels PXij positioned on an i-th horizontal line and a j-th vertical line may be divided into a first period T1 and a second period T2.

[0096] The data driver 140 may supply a voltage of a reference power Vref to the data line DLj during a first period T1, and may supply a voltage Vdata(i) of a data signal to the data line DLj during a second period T2. The voltage of the reference power Vref may be set to a voltage between a voltage of the first driving power VDD and a voltage of the second driving power VSS, for example, a specific voltage within a voltage range of the data signal. The voltage Vdata(i) of the data signal may be set to a voltage corresponding to a grayscale value and within a voltage range of the data signal.

[0097] The scan driver 130 (or the first scan driver 132 ) may supply the first scan signal GW to the first scan line SL1 i during the first period T1 and the second period T2 .

[0098] The scan driver 130 (or the second scan driver 134) may supply the second scan signal GI to the second scan line SL2i during a zeroth period T0 before the first period T1. The zeroth period T0 may be a period included in a previous horizontal period (e.g., a period in which data signals are supplied to pixels positioned on an i-1th horizontal line).

[0099] The scan driver 130 (or the third scan driver 136 ) may supply the third scan signal GC to the third scan line SL3 i during the first period T1 .

[0100] The scan driver 130 (or the fourth scan driver 138) may supply the fourth scan signal GB to the fourth scan line SL4i during the zeroth period T0 to the third period T3. The third period T3 may be a period included in a subsequent horizontal period (e.g., a period in which data signals are supplied to pixels positioned on the i+1th horizontal line).

[0101] The emission driver 150 may supply the emission control signal EM to the emission control line ELk during the zeroth period T0 to the second period T2 .

[0102] During the zeroth period T0, the voltage of the reference power Vref is supplied to the data line DLj. During the zeroth period T0, the voltage of the reference power Vref may be supplied to the first node N1 included in the pixel PXij, and the voltage of the initialization power Vint may be supplied to the third node N3. During the zeroth period T0, the first node N1 may be initialized by the voltage of the reference power Vref, and the third node N3 may be initialized by the voltage of the initialization power Vint. The zeroth period T0 may be referred to as an initialization period.

[0103] The first period T1 may be a period in which a voltage corresponding to the threshold voltage of the first transistor M1 is stored in the second capacitor C2. The first period T1 may be referred to as a threshold voltage compensation period.

[0104] The second period T2 may be a period in which a voltage Vdata(i) of a data signal is supplied from a data line DLj to a pixel PXij. During the second period T2, a voltage corresponding to the data signal may be applied to the first node N1. The second period T2 may be referred to as a data write period.

[0105] During the third period T3, the first transistor M1 can control the amount of current to be supplied from the first power line PL1 to which the voltage of the first driving power VDD is supplied to the third power line PL3 to which the voltage of the initialization power Vint is supplied in response to the voltage of the first node N1. In this case, the light emitting element LD can be prevented from emitting light due to an undesired current. The third period T3 can be referred to as a brightness control period.

[0106] During the fourth period T4, the first transistor M1 may control the amount of current flowing from the first power line PL1 to which the voltage of the first driving power VDD is supplied to the second power line PL2 to which the voltage of the second driving power VSS is supplied via the light emitting element LD in response to the voltage of the first node N1. During the fourth period T4, the light emitting element LD may emit light at a brightness corresponding to the amount of current. The fourth period T4 may be referred to as an emission period.

[0107] FIG. 6A to FIG. 6E is shown with Figure 5 The driving waveform corresponding to the operation pixel PXij (see Figure 4 ) is a diagram of an embodiment of a process.

[0108] refer to Fig. 6A During the zeroth period T0 to the second period T2, the emission control signal EM is supplied to the emission control line ELk, thereby turning off the fifth transistor M5. If the fifth transistor M5 is turned off, the first transistor M1 and the light emitting element LD can be electrically disconnected from each other, so that the light emitting element LD can be set to a non-emission state.

[0109] During the zeroth period T0 to the third period T3, the fourth scan signal GB is supplied to the fourth scan line SL4i. If the fourth scan signal GB is supplied to the fourth scan line SL4i, the sixth transistor M6 is turned on. If the sixth transistor M6 is turned on, the voltage of the initialization power Vint is supplied to the third node N3.

[0110] If the voltage of the initialization power Vint is supplied to the third node N3, the light emitting element LD may be initialized by the voltage of the initialization power Vint. Here, the voltage of the initialization power Vint may be set to a voltage at which the light emitting element LD does not emit light. As a result, the light emitting element LD may be set to a non-emitting state. For example, a voltage obtained by subtracting the voltage of the second driving power VSS from the sum of the voltage of the initialization power Vint and the absolute threshold voltage of the fifth transistor M5 may be set to a value lower than the threshold voltage of the light emitting element LD. For example, the voltage of the initialization power Vint may be set to the ground potential GND.

[0111] During the zeroth period T0, the second scan signal GI is supplied to the second scan line SL2i. If the second scan signal GI is supplied to the second scan line SL2i, the third transistor M3 is turned on. As a result, the voltage of the reference power Vref is supplied from the data line DLj to the first node N1. Here, the voltage of the first node N1 may be initialized to the voltage of the reference power Vref regardless of the voltage supplied during the previous period (or previous frame period).

[0112] Between the end of the zeroth period T0 and the beginning of the first period T1, the voltage Vdata(i-1) of the data signal may be supplied to the data line DLj. Here, because the second transistor M2 included in the pixel PXij is set to a cut-off state, the voltage Vdata(i-1) of the data signal is not supplied to the pixel PXij.

[0113] refer to Figure 6B , during the first period T1, the third scan signal GC is supplied to the third scan line SL3i, and the first scan signal GW is supplied to the first scan line SL1i.

[0114] If the first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 is turned on. If the second transistor M2 is turned on, the voltage of the reference power Vref is supplied from the data line DLj to the first electrode of the first capacitor C1.

[0115] If the third scan signal GC is supplied to the third scan line SL3i, the fourth transistor M4 is turned on. If the fourth transistor M4 is turned on, the first transistor M1 is connected to form a diode. If the first transistor M1 is connected in the form of a diode, a voltage obtained by subtracting an absolute threshold voltage of the first transistor M1 from a voltage of the first driving power VDD may be applied to the first node N1.

[0116] During the first period T1, the voltage of the reference power Vref is applied to the first electrode of the first capacitor C1, and the voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the voltage of the first drive power VDD can be applied to the second electrode of the first capacitor C1. In this case, regardless of the voltage supplied during the previous period (or the previous frame period), the first capacitor C1 can be initialized by the voltage of the reference power Vref and the voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the voltage of the first drive power VDD. In addition, during the first period T1, a voltage corresponding to the threshold voltage of the first transistor M1 can be stored in each of the first capacitor C1 and the second capacitor C2.

[0117] refer to Figure 6C During the second period T2, the first scan signal GW is supplied to the first scan line SL1i so that the second transistor M2 may remain turned on.

[0118] If the second transistor M2 is set to the on state, the voltage Vdata(i) of the data signal is supplied from the data line DLj to the first electrode of the first capacitor C1. If the voltage Vdata(i) of the data signal is supplied to the first electrode of the first capacitor C1, the first electrode of the first capacitor C1 changes from the voltage of the reference power Vref to the voltage Vdata(i) of the data signal. In this case, due to the coupling of the first capacitor C1, the voltage of the first node N1 may also change.

[0119] Here, the voltage change of the first node N1 may be determined in response to the ratio of the first capacitor C1 and the second capacitor C2. For example, the voltage of the first node N1 may be changed from the voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the voltage of the first driving power VDD by a value obtained by multiplying the voltage change of the first electrode of the first capacitor C1 by c1 / (c1+c2), where c1 is the first capacitance of the first capacitor C1, and c2 is the second capacitance of the second capacitor C2. In the case where the voltage change of the first node N1 is controlled by the ratio of the first capacitor c1 and the second capacitor c2, the voltage range of the data signal may be sufficiently widened.

[0120] For example, in the case where the data signal is directly supplied to the gate electrode of the first transistor M1, the voltage range of the data signal can be set to a relatively small range. In the case where the data signal has a small voltage range, it is necessary to use a small voltage range to implement various grayscale values ​​(e.g., 256 values). Therefore, it becomes difficult to represent an accurate grayscale value.

[0121] On the other hand, as described in the embodiments of the present disclosure, in the case where the voltage to be supplied to the gate electrode of the first transistor M1 is controlled by the ratio of the first capacitor c1 and the second capacitor c2, the voltage range of the data signal can be set to a sufficiently large range. For example, a voltage corresponding to a value obtained by multiplying the voltage of the data signal by c1 / (c1+c2) is transmitted to the gate electrode of the first transistor M1. Therefore, the voltage range of the data signal can be set to a larger range. In the case where the data signal has a larger voltage range, grayscale values ​​can be more easily implemented and distinguished from each other.

[0122] During the second period T2, the second capacitor C2 stores the voltage of the first node N1. Here, the voltage of the first node N1 may be determined by the threshold voltage of the first transistor M1 and the voltage Vdata(i) of the data signal. Therefore, during the second period T2, a voltage corresponding to the threshold voltage of the data signal and the first transistor M1 may be stored in the second capacitor C2.

[0123] refer to Fig.6D During the third period T3, the supply of the emission control signal EM to the emission control line ELk is interrupted. If the supply of the emission control signal EM to the emission control line ELk is interrupted, the fifth transistor M5 is turned on. If the fifth transistor M5 is turned on, the second node N2 and the third node N3 are electrically connected to each other.

[0124] During the third period T3, the fifth transistor M5 positioned on the current path for supplying current to the light emitting element LD is set to an on state. Therefore, the first transistor M1 can control the amount of current to be supplied from the first power line PL1 to which the voltage of the first driving power VDD is supplied to the third node N3 in response to the voltage applied to the first node N1. Here, because the sixth transistor M6 is set to an on state, the current supplied to the third node N3 can be supplied to the third power line PL3 to which the voltage of the initialization power Vint is supplied. In other words, during the third period T3, the light emitting element LD can be set to a non-emitting state, thereby improving the display device 100 (see Figure 2 )’s grayscale representation performance.

[0125] In more detail, as the first period T1 and the second period T2 pass, the voltage of the second node N2 can be set to be approximately the voltage of the first driving power VDD. In the case where the voltage of the second node N2 is set to the voltage of the first driving power VDD, after the fifth transistor M5 is turned on, unnecessary current may be supplied to the light emitting element LD. For example, even when the pixel PXij realizes the black grayscale, the light emitting element LD may emit light due to the voltage of the second node N2. Therefore, in an embodiment of the present disclosure, during the third period T3 before the light emitting element LD emits light, the current supplied from the first transistor M1 can be provided to the third power line PL3 to which the voltage of the initialization power Vint is supplied. Therefore, the grayscale representation performance of the display device 100 can be improved.

[0126] refer to Fig. 6E During the fourth period T4, the supply of the fourth scan signal GB to the fourth scan line SL4i is interrupted, so that the sixth transistor M6 is turned off. If the sixth transistor M6 is turned off, the driving current supplied from the first transistor M1 is supplied to the light emitting element LD, so that the light emitting element LD can generate light with a brightness corresponding to the driving current.

[0127] In addition, as shown in Equation 1, the amount of current supplied from the first transistor M1 to the light emitting element LD during the fourth period T4 may be determined regardless of the threshold voltage of the first transistor M1 .

[0128] [Equation 1]

[0129]

[0130] In Equation 1, ILD represents a current supplied to the light emitting element LD, and K represents a proportionality constant determined by mobility, parasitic capacitance, channel capacitance, and the like of the first transistor M1.

[0131] Referring to Equation 1, it can be understood that the amount of current supplied from the first transistor M1 is determined by the voltage Vdata(i) of the data signal and the voltage of the reference power Vref regardless of the threshold voltage of the first transistor M1.

[0132] In an embodiment of the present disclosure, during the first period T1 in which the threshold voltage of the first transistor M1 is compensated and the fourth period T4 in which the light emitting element LD emits light, the voltage of the first electrode of the first transistor M1 may be set to the same value. For example, during the first period T1 and the fourth period T4, the voltage of the first electrode of the first transistor M1 may be set to the voltage of the first driving power VDD. In this case, the threshold voltage of the first transistor M1 may be reliably compensated.

[0133] Figure 7 is shown in response to Figure 4 FIG. 1 is a graph showing a change in the driving current as a function of the threshold voltage Vth of the first transistor M1 in the pixel PXij. Figure 7 In the figure, the horizontal axis represents time [ms]. Figure 7 , the vertical axis of the first node N1 represents voltage [V], and the vertical axis of the current ILD represents current [nA].

[0134] Figure 7 Statistical graphs are shown for the case where the threshold voltage Vth of the first transistor M1 changes from the nominal value by approximately -20 mV and +20 mV, and show how the voltage of the first node N1 may change in response to the threshold voltage Vth of the first transistor M1. In other words, the voltage of the first node N1 may change in response to the threshold voltage Vth of the first transistor M1, thereby compensating for the threshold voltage Vth of the first transistor M1.

[0135] In addition, even if the threshold voltage Vth of the first transistor M1 changes, the voltage supplied to the light emitting element LD (see Figure 4 ) may also have substantially similar (or identical) current values.

[0136] Figure 8 It is shown Figure 4 The current error of the pixel PXij is shown in FIG. Figure 8 , the horizontal axis represents the voltage (or grayscale value) of the data signal, and the vertical axis represents the current error. The current error is expressed as a percentage [%] and represents the current error in response to the first transistor M1 (see Figure 4 ) changes in the threshold voltage Vth. For example, Figure 8 The current error when the threshold voltage Vth of the first transistor M1 changes by -0.02V or 0.02V is shown.

[0137] refer to Figure 8 , when the threshold voltage Vth of the first transistor M1 changes by -0.02 V and 0.02 V, the current error may only be approximately -3% to 2.2%. In other words, with the embodiment of the present disclosure, the threshold voltage Vth of the first transistor M1 may be reliably compensated.

[0138] Fig. 9 is a circuit diagram showing a pixel PXaij according to an embodiment of the present disclosure. Fig. 9 In the description of Figure 4 Description of the duplicate description.

[0139] refer to Fig. 9, the pixel PXaij according to an embodiment of the present disclosure can be connected to the corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk and DLj. For example, the pixel PXaij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXaij can also be connected to the first power line PL1, the second power line PL2 and the third power line PL3.

[0140] The pixel PXaij according to an embodiment of the present disclosure may include a pixel circuit and a light emitting element LD, and the pixel circuit may be configured to control the amount of current to be supplied to the light emitting element LD.

[0141] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light of a specific brightness corresponding to the amount of current supplied by the pixel circuit from the first power line PL1 to the second power line PL2 through the light emitting element LD.

[0142] The pixel circuit may include a first transistor M1, a second transistor Ma2, a third transistor Ma3, a fourth transistor Ma4, a fifth transistor Ma5, a sixth transistor Ma6, a first capacitor C1, and a second capacitor C2.

[0143] The first transistor M1 may be a MOSFET including a body electrode. In this case, the first transistor M1 may be mounted in a relatively small area so that the pixel PXaij is applied to a high-resolution panel. The body electrode of the first transistor M1 may be supplied with a voltage of the first drive power VDD. For example, the body electrode of the first transistor M1 may be electrically connected to the first power line PL1.

[0144] The second transistor Ma2 to the sixth transistor Ma6 may be formed by a transistor of a type different from that of the first transistor M1. For example, the second transistor Ma2 to the sixth transistor Ma6 may be a transistor that does not include a body electrode. For example, the second transistor Ma2 to the sixth transistor Ma6 may be configured in various forms including a thin film transistor (TFT), a field effect transistor (FET), a bipolar junction transistor (BJT), etc.

[0145] drive Fig. 9 The pixel PXaij shown in the method can be driven with Figure 4 The method for performing the pixel PXij shown in FIG. 1 is substantially the same; therefore, a detailed description thereof will be omitted.

[0146] Fig.10 is a circuit diagram showing a pixel PXbij according to an embodiment of the present disclosure. Fig.10 In the description of Figure 4 Description of the duplicate description.

[0147] refer to Fig.10 , the pixel PXbij according to an embodiment of the present disclosure can be connected to the corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk and DLj. For example, the pixel PXbij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXbij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3 and the fourth power line PL4.

[0148] The pixel PXbij according to an embodiment of the present disclosure may include a pixel circuit and a light emitting element LD, and the pixel circuit may be configured to control the amount of current to be supplied to the light emitting element LD.

[0149] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light of a specific brightness corresponding to the amount of current supplied by the pixel circuit from the first power line PL1 to the second power line PL2 through the light emitting element LD.

[0150] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor Mb3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0151] The third transistor Mb3 may include a first electrode connected to the first node N1, and a second electrode electrically connected to the fourth power line PL4 to which the voltage of the reference power Vref is supplied. The gate electrode of the third transistor Mb3 may be electrically connected to the second scan line SL2i. When the second scan signal GI is supplied to the second scan line SL2i, the third transistor Mb3 may be turned on so that the voltage of the reference power Vref may be supplied to the first node N1.

[0152] In addition to being connected to the fourth power line PL4 to which the voltage of the reference power Vref is supplied, the third transistor Mb3 may be connected to Figure 4 The third transistor M3 shown in FIG. 1 has substantially the same operation process.

[0153] Fig.11 1 is a circuit diagram showing a pixel PXcij according to an embodiment of the present disclosure. Fig.11 In the description of Figure 4 Description of the duplicate description.

[0154] refer to Fig.11 , the pixel PXcij according to the embodiment of the present disclosure can be connected to the corresponding signal lines SL1i, SL3(i-1), SL3i, SL4i, ELk and DLj. For example, the pixel PXcij can be connected to the i-th first scan line SL1i, the i-1-th third scan line SL3(i-1), the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXcij can also be connected to the first power line PL1, the second power line PL2 and the third power line PL3.

[0155] The pixel PXcij according to an embodiment of the present disclosure may include a pixel circuit and a light emitting element LD, and the pixel circuit may be configured to control the amount of current to be supplied to the light emitting element LD.

[0156] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light of a specific brightness corresponding to the amount of current supplied by the pixel circuit from the first power line PL1 to the second power line PL2 through the light emitting element LD.

[0157] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor Mc3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0158] The third transistor Mc3 may be connected between the data line DLj and the first node N1. A gate electrode of the third transistor Mc3 may be coupled to the i-1th third scan line SL3(i-1). When the third scan signal GC-1 is supplied to the i-1th third scan line SL3(i-1), the third transistor Mc3 may be turned on to electrically connect the data line DLj to the first node N1.

[0159] In other words, Fig.11 As shown in Figure 4 The connection with the second scan line SL2i in the pixel PXij shown in FIG. 1 can be replaced with the connection with the i-1th third scan line SL3(i-1) for the previous horizontal line. In this case, the second scan line SL2i can be removed, and Figure 2 The display device 100 may not need the second scan line SL2. Fig.11 The pixel PXcij shown in the method can be driven with Figure 4 The method for performing the pixel PXij shown in FIG. 1 is substantially the same; therefore, a detailed description thereof will be omitted.

[0160] According to a pixel and a display device including the pixel according to an embodiment of the present disclosure, the pixel may be implemented using a transistor suitable for high resolution, for example, a metal oxide semiconductor field effect transistor (MOSFET).

[0161] In addition, the pixel according to the embodiment of the present disclosure may include a driving transistor having a body electrode, and the threshold voltage of the driving transistor may be reliably compensated.

[0162] In addition, the pixel according to the embodiment of the present disclosure may transmit the data signal using capacitor coupling, whereby the voltage range of the data signal may be a relatively large range.

[0163] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications may be made without departing from the spirit and scope of the present disclosure.

[0164] Although embodiments of the present disclosure have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as claimed in the accompanying claims.

Claims

1. A pixel, wherein The pixels include: a first transistor including a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor including a second electrode, a first electrode electrically connected to the data line, and a gate electrode electrically connected to the first scan line; a third transistor connected between the first node and the data line, the third transistor comprising a gate electrode electrically connected to a second scan line; a first capacitor including a first electrode connected to the second electrode of the second transistor and a second electrode connected to the first node; a second capacitor connected between the first power line and the first node; and A light emitting element is connected between a second power line and the first transistor, and includes a second electrode electrically connected to the second power line.

2. The pixel according to claim 1, wherein: The first transistor is a metal oxide semiconductor field effect transistor including a body electrode, and Here, a voltage of a first driving power is supplied to the first power line, and the voltage of the first driving power is supplied to the body electrode.

3. The pixel according to claim 1, wherein: The pixel also includes: a fourth transistor connected between the first node and a second node connected to the second electrode of the first transistor, the fourth transistor comprising a gate electrode electrically connected to a third scan line; a fifth transistor connected between the second node and the first electrode of the light emitting element, the fifth transistor including a gate electrode electrically connected to an emission control line; and a sixth transistor including a first electrode electrically connected to the first electrode of the light emitting element, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to a fourth scan line; and wherein each of the first to sixth transistors is a metal oxide semiconductor field effect transistor including a body electrode; and Here, a voltage of a first driving power is supplied to the first power line, and the voltage of the first driving power is supplied to the body electrode of each of the first to sixth transistors.

4. The pixel according to claim 3, wherein: The second scan line is set as a third scan line positioned on a previous horizontal line.

5. The pixel according to claim 3, in, A second driving power having a voltage lower than the voltage of the first driving power is supplied to the second power line, and wherein a voltage of initialization power having a voltage value at which the light emitting element does not emit light is supplied to the third power line, and wherein a voltage value obtained by subtracting the voltage of the second driving power from a voltage obtained by adding an absolute threshold voltage of the fifth transistor to the voltage of the initialization power is set to a voltage lower than a threshold voltage of the light emitting element.

6. The pixel according to claim 5, wherein: The initialization power is set to ground power.

7. The pixel according to claim 5, in, A single horizontal period of operation of the pixel includes a first period and a second period, wherein a voltage of a reference power between the voltage of the first driving power and the voltage of the second driving power is supplied to the data line during the first period, and a voltage of a data signal is supplied to the data line during the second period, wherein, during the first period, the second transistor, the fourth transistor and the sixth transistor are set to an on state, and the third transistor and the fifth transistor are set to an off state, and During the second period, the second transistor and the sixth transistor are set to the on state, and the third transistor, the fourth transistor and the fifth transistor are set to the off state.

8. The pixel according to claim 7, in, During a zeroth period before the first period, the third transistor and the sixth transistor are set to the on state, and the second transistor, the fourth transistor, and the fifth transistor are set to the off state, and During the zeroth period, the voltage of the reference power is supplied to the data line.

9. The pixel according to claim 7, in, During a third period after the second period, the first transistor, the fifth transistor, and the sixth transistor are set to the on state, and the second transistor, the third transistor, and the fourth transistor are set to the off state, and During a fourth period after the third period, the first transistor and the fifth transistor are set to the on state, and the second transistor, the third transistor, the fourth transistor and the sixth transistor are set to the off state.

10. A display device, wherein: The display device includes: a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of fourth scan lines, a plurality of data lines and a plurality of emission control lines, Among the plurality of pixels, the pixels located in the i-th pixel row and the j-th pixel column include: a first transistor including a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor including a second electrode and a first electrode electrically connected to a j-th data line among the plurality of data lines, the second transistor being configured to be turned on when a first scan signal is supplied to an i-th first scan line among the plurality of first scan lines; a third transistor connected between the first node and the j-th data line, the third transistor being configured to be turned on when a second scan signal is supplied to an i-th second scan line among the plurality of second scan lines; a first capacitor connected between the second electrode of the second transistor and the first node; a second capacitor connected between the first power line and the first node; and a light emitting element connected between a second power line and the first transistor, the light emitting element including a second electrode electrically connected to the second power line; and The pixels located in the i-th pixel row and the j-th pixel column further include: a fourth transistor connected between a second node connected to the second electrode of the first transistor and the first node, the fourth transistor being configured to be turned on when a third scan signal is supplied to an i-th third scan line among the plurality of third scan lines; a fifth transistor connected between the second node and the first electrode of the light emitting element, the fifth transistor being configured to be turned off when an emission control signal is supplied to a kth emission control line among the plurality of emission control lines; and a sixth transistor including a first electrode electrically connected to the first electrode of the light emitting element and a second electrode electrically connected to a third power line, the sixth transistor being configured to be turned off when a fourth scan signal is supplied to an i-th fourth scan line among the plurality of fourth scan lines; and wherein each of the first to sixth transistors is configured as a metal oxide semiconductor field effect transistor including a body electrode, and the body electrode of each of the first to sixth transistors is electrically connected to the first power line, wherein i is an integer greater than 0, j is an integer greater than 0, and k is an integer greater than 0.

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