Shift register, gate drive circuit, display panel and display device

Abstract

The invention provides a shift register, a gate driving circuit, a driving method of the gate driving circuit, a display panel and a display device.The shift register comprises an input sub-circuit, a first control sub-circuit, an output sub-circuit, an output control sub-circuit and a second control sub-circuit, the input sub-circuit electrically connects an input end with a first node based on a signal of a first clock signal end; the output sub-circuit outputs a signal of a second clock signal end to an output end based on a signal of a third node; the output control sub-circuit electrically connects a second power supply signal end with the output end based on the signal of the second node; the second control sub-circuit is used for electrically connecting the second power supply signal end with the second node based on the signals of the third clock signal end and the first node, and the effective level time segment of the signal of the third clock signal end and the effective level time segment of the signal of the second power supply signal end have an overlapping time period of at least 1H. According to the embodiment of the invention, the reset time of the first node can be controlled through the overlapping of the signals of the clock signal line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit and a driving method thereof, a display panel and a display device. Background Art

[0002] Gate Driver on Array (GOA) circuits are widely used in display products. GOA circuits are integrated on array substrates and prepared simultaneously with other display components on the array substrate, which can reduce the cost of display products.

[0003] The GOA circuit outputs a row scan signal to the transistor in the pixel driving circuit to control the writing of the data signal. However, as the refresh frequency of the display product increases, the writing time of one row is shortened. Therefore, there is a problem that the data cannot be fully written under high frequency conditions, and high-frequency display products are difficult to implement. Summary of the invention

[0004] In order to solve at least one of the above problems, the first aspect of the present disclosure provides a shift register, comprising:

[0005] an input subcircuit electrically connected to the input terminal, the first node and the first clock signal terminal, and configured to electrically connect the input terminal to the first node based on a signal at the first clock signal terminal;

[0006] a first control subcircuit, electrically connected to the first power signal terminal, the second node and the first clock signal terminal, and configured to electrically connect the first power signal terminal to the second node based on a signal at the first clock signal terminal;

[0007] an output subcircuit, electrically connected to the third node, the second clock signal terminal and the output terminal, configured to output the signal of the second clock signal terminal to the output terminal based on the signal of the third node;

[0008] an output control subcircuit, electrically connected to the second node, the second power signal terminal and the output terminal, and configured to electrically connect the second power signal terminal to the output terminal based on a signal at the second node;

[0009] The second control subcircuit is electrically connected to the third clock signal terminal, the second power signal terminal, the second node, and the first node, and is configured to electrically connect the second power signal terminal to the second node based on the signal of the third clock signal terminal and the first node.

[0010] There is an overlap period of at least 1H between the effective level period of the signal at the third clock signal end and the effective level period of the signal at the second power signal end, where H represents the time required for the shift register to scan a row of pixels.

[0011] Optionally, the shift register further includes: a first voltage stabilizing subcircuit, the first voltage stabilizing subcircuit including: a first transistor and a first capacitor,

[0012] The first electrode of the first capacitor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the first electrode of the first transistor, the second electrode of the first transistor is electrically connected to the third node, and the control electrode is electrically connected to the second node.

[0013] Optionally, the shift register further includes: a third control subcircuit electrically connected to the first node, the second node and the first clock signal terminal, and configured to electrically connect the first clock signal terminal to the second node based on a signal of the first node.

[0014] Optionally, the shift register further includes: a second voltage stabilizing subcircuit electrically connected to the first node, the third node and the first power signal terminal, and configured to electrically connect the third node to the first node based on a signal at the first power signal terminal.

[0015] Optionally, the input subcircuit includes a second transistor, a first electrode of the second transistor is electrically connected to the input terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the first clock signal terminal.

[0016] The first control subcircuit includes a third transistor, a first electrode of the third transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the second node, and a control terminal is electrically connected to the first clock signal terminal.

[0017] The output subcircuit includes a fourth transistor and a second capacitor, wherein a first electrode of the fourth transistor is electrically connected to the second clock signal terminal, a second electrode is electrically connected to the output terminal, and a control electrode is electrically connected to the third node, a first electrode of the second capacitor is electrically connected to the third node, and a second electrode is electrically connected to the output terminal.

[0018] The output control subcircuit includes a fifth transistor and a third capacitor, wherein a first electrode of the fifth transistor is electrically connected to the output terminal, a second electrode is electrically connected to the second power signal terminal, and a control electrode is electrically connected to the second node, a first electrode of the third capacitor is electrically connected to the second node, and a second electrode is electrically connected to the second power signal terminal.

[0019] The second control subcircuit includes a sixth transistor and a seventh transistor,

[0020] The first electrode of the sixth transistor is electrically connected to the first node, the second electrode is electrically connected to the first electrode of the seventh transistor, the control electrode is electrically connected to the third clock signal terminal, the second electrode of the seventh transistor is electrically connected to the second power signal terminal, and the control electrode is electrically connected to the second node.

[0021] Optionally, the third control subcircuit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node.

[0022] A second aspect of the present disclosure provides a gate driving circuit, comprising a plurality of cascaded shift registers as described above, wherein an output terminal or a carry terminal of an n-th shift register is electrically connected to an input terminal of another shift register, wherein n is a positive integer greater than or equal to 1,

[0023] The input end of the first stage shift register is electrically connected to the first initial signal line, and the input end of the second stage shift register is electrically connected to the second initial signal line.

[0024] The effective level period of the signal connected to the first initial signal line and the effective level period of the signal connected to the second initial signal line overlap for at least 1H.

[0025] The output terminal of the nth stage shift register is electrically connected to the input terminal of the (n+2)th shift register.

[0026] Optionally, the first clock signal terminal of the 4m-3 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line.

[0027] The first clock signal terminal of the 4m-2 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line.

[0028] The first clock signal terminal of the 4m-1th stage shift register is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line.

[0029] The first clock signal terminal of the 4mth stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line, wherein m is a positive integer.

[0030] Optionally, the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1th level shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-th level shift register for at least 1H, the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1th level shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-th level shift register for at least 1H, and the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1th level shift register overlaps with the effective level signal period of the signal connected to the second clock signal terminal of the 2m-th level shift register for at least 1H.

[0031] A third aspect of the present disclosure provides a display panel, comprising the gate driving circuit as described above.

[0032] Optionally, the display panel further includes: at least one pixel circuit, the pixel circuit including: a driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a first resetting subcircuit and a light emitting unit,

[0033] a driving sub-circuit, electrically connected to the fourth node, the fifth node and the sixth node, configured to generate a driving current based on a data signal inputted from the fourth node,

[0034] a light emitting control subcircuit, electrically connected to the fourth power signal terminal, the fifth node, the sixth node, the first and second light emitting control terminals, and the anode of the light emitting unit, and configured to transmit the driving current to the anode based on the signals of the first and second light emitting control terminals,

[0035] The write subcircuit is electrically connected to the fourth node, the data signal terminal and the write control terminal, and is configured to transmit the data signal connected to the data signal terminal to the fourth node based on the signal of the write control terminal.

[0036] The first reset subcircuit is electrically connected to the first reset control terminal, the first reset signal terminal and the sixth node, and is configured to electrically connect the first reset signal terminal to the sixth node based on a signal at the first reset control terminal.

[0037] The first reset signal terminal is connected to a DC signal or an AC signal with a potential change.

[0038] Optionally, the image display process of the light-emitting unit includes a refresh frame and a hold frame, the first reset signal terminal is connected to a signal with a first amplitude in the refresh frame and is connected to a signal with a second amplitude in the hold frame,

[0039] The first amplitude is greater than the second amplitude.

[0040] Optionally, the output terminal of the shift register is electrically connected to the write control terminal of the pixel circuit of the corresponding row.

[0041] A fourth aspect of the present disclosure provides a driving method for the gate driving circuit described above.

[0042] In the first stage of the n-stage shift register, based on the signal connected to the first clock signal terminal being at a valid level and the signal connected to the second clock signal terminal being at an invalid level, the input subcircuit and the output subcircuit of the n-stage shift register are turned on, and the first power signal terminal and the second node are turned on through the first control subcircuit of the n-stage shift register;

[0043] In the second stage of the n-th shift register, the output sub-circuit of the n-th shift register is turned on to output a valid level signal, and based on the signal connected to the second clock signal terminal of another shift register cascaded with the n-th shift register becoming a valid level, the output sub-circuit of the other shift register is turned on to output a valid level signal.

[0044] A fifth aspect of the present disclosure provides a display device, comprising the display panel described above.

[0045] The beneficial effects of the present disclosure are as follows:

[0046] In response to the existing problems, the present disclosure develops a shift register, a gate drive circuit and a driving method thereof, a display panel and a display device, and provides a shift register with a second control sub-circuit, and the effective level period of the signal connected to the third clock signal terminal as the control terminal in the control sub-circuit overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit for at least 1H, thereby being able to control the reset time of the first node, improve the regulation flexibility of the first node, increase the output drive capability, and improve the display effect, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 is a timing relationship diagram of a clock signal terminal and an output terminal of a shift register according to an embodiment of the present disclosure;

[0049] Figure 2 is a schematic block diagram of a shift register according to an embodiment of the present disclosure;

[0050] Figure 3 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0051] Figure 4 A schematic timing diagram showing each signal line of the gate driving circuit according to an embodiment of the present disclosure is shown;

[0052] Figure 5 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;

[0053] Figure 6 is a schematic circuit diagram of a shift register according to another embodiment of the present disclosure;

[0054] Figure 7 Based on Figure 6 The key port timing diagram of the simulation of the shift register shown;

[0055] Figure 8 Based on Figure 5 and Figure 6 The output simulation comparison diagram of the shift register shown;

[0056] Fig. 9 is an output simulation diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0057] Fig.10 A circuit schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure is shown;

[0058] Fig.11 Show according to Fig.10 The key port timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0059] In order to more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present disclosure.

[0060] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limit, but indicate that there is at least one. "Include" or "comprises" and other similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0061] The transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the gate of the transistor is called the control electrode, one of the source and drain is called the first electrode, and the other is called the second electrode. In the embodiments of the present disclosure, the first electrode of the transistor is called the drain electrode, and the second electrode is called the source electrode. For example, it is explained. In addition, the shift register unit of the embodiment of the present disclosure adopts N-type transistors, and is improved for the drive compensation architecture based on NMOS transistors. Therefore, the conduction condition of the transistor is that the control electrode is connected to a high-level signal, which will not be repeated below. It can be imagined that when the transistor adopts a P-type crystal, the conduction condition of the transistor is opposite. When the gate inputs a low level, the source and drain are turned on. It only needs to adjust the signal level of the corresponding port, so the implementation method of the P-type transistor should also be within the protection scope of the embodiment of the present disclosure.

[0062] It should also be noted that the gate drive circuit disclosed in the present invention can be used for row-by-row scanning of the control electrode of the write transistor of the output LPTS display panel, and can also be used for row-by-row scanning of the control electrode of the write transistor of the output LPTO display panel (where both N-type TFT and P-type TFT exist in the pixel circuit).

[0063] In order to solve at least one of the above problems, refer to Figure 1 and Figure 2 As shown, the embodiment of the present disclosure provides a shift register, comprising:

[0064] An input sub-circuit 10, electrically connected to an input terminal STV, a first node N1 and a first clock signal terminal CK, and configured to electrically connect the input terminal STV to the first node N1 based on a signal of the first clock signal terminal CK;

[0065] A first control subcircuit 20, electrically connected to the first power signal terminal VGH, the second node N2 and the first clock signal terminal CK, and configured to electrically connect the first power signal terminal VGH to the second node N2 based on a signal of the first clock signal terminal CK;

[0066] The output sub-circuit 30 is electrically connected to the third node N3, the second clock signal terminal CB and the output terminal OUT, and is configured to output the signal of the second clock signal terminal CB to the output terminal OUT based on the signal of the third node N3;

[0067] an output control subcircuit 40, electrically connected to the second node N2, the second power signal terminal VGL and the output terminal OUT, and configured to electrically connect the second power signal terminal VGL to the output terminal OUT based on a signal of the second node N2;

[0068] The second control subcircuit 50 is electrically connected to the third clock signal terminal CB-2, the second power signal terminal VGL, the second node N2, and the first node N1, and is configured to electrically connect the second power signal terminal VGL to the second node N2 based on the signal of the third clock signal terminal CB-2 and the first node N1.

[0069] The effective level period of the signal at the third clock signal terminal CB-2 overlaps with the effective level period of the signal at the second power signal terminal VGL for at least 1H, where H represents the time required for the shift register to scan a row of pixels.

[0070] In this embodiment, a shift register having a second control sub-circuit is provided, and the effective level period of the signal connected to the third clock signal terminal as the control terminal in the control sub-circuit overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit by at least 1H, thereby being able to control the reset time of the first node, improve the regulation flexibility of the first node, increase the output driving capability, and improve the display effect.

[0071] In order to help understand the role of the shift register of the embodiment of the present disclosure, firstly, an application scenario and implementation function of the shift register are illustrated by a block diagram of a gate driving circuit formed by cascading the shift registers of the embodiment of the present disclosure.

[0072] Reference Figure 3 As shown, Figure 3 The gate drive circuit block diagram is exemplarily shown as a cascade of four shift registers GOA-1, GOA-2, GOA-3 and GOA-4, wherein the structure of each shift register satisfies Figure 2 Block diagram shown.

[0073] It should be understood that Figure 3 This is only intended to be illustrative and not intended to limit the present disclosure, and the number of the specific cascaded shift registers depends on the needs.

[0074] Reference Figure 3 As shown, the output terminal Out of the first-level shift register GOA-1 is electrically connected to the input terminal STV of the third-level shift register GOA-3, the output terminal Out of the second-level shift register GOA-2 is electrically connected to the input terminal STV of the fourth-level shift register GOA-4, the input terminal STV of the first-level shift register GOA-1 is electrically connected to the first initial signal line stv1, the input terminal STV of the second-level shift register GOA-2 is electrically connected to the second initial signal line stv2, the output terminal Out of the current-level shift register is electrically connected to the input terminal STV of the next-level shift register, and the input terminal of the first-level shift register is electrically connected to the initial signal line stv.

[0075] That is, the output terminal Out of the current shift register is electrically connected to the input terminal STV of the next shift register of the next stage with one row interval. This is because, in order to realize the effective output period length by utilizing the period overlap of the effective level of the signal line, the start time of the signal output by the adjacent next shift register is delayed relative to the signal required by the input terminal of the adjacent next shift register. Therefore, when the shift registers of the embodiment of the present disclosure are cascaded, the input terminals of the first and second shift registers need two initial signal lines to provide input signals.

[0076] Continue to refer to Figure 3 As shown, the first clock signal terminal CK of the first-stage shift register GOA-1 is electrically connected to the first clock signal line CK1, the second clock signal terminal CB is electrically connected to the third clock signal line CB1, and the third clock signal line CB-2 is electrically connected to the fourth clock signal line CB2; the first clock signal terminal CK of the second clock signal line GOA-2 is electrically connected to the second clock signal line CK2, the second clock signal terminal CB is electrically connected to the fourth clock signal line CB2, and the third clock signal line CB-2 is electrically connected to the third clock signal line CB1; the first clock signal terminal CK of the third clock signal line GOA-3 is electrically connected to the third clock signal line CB1, the second clock signal terminal CB is electrically connected to the first clock signal line CK1, and the third clock signal line CB-2 is electrically connected to the second clock signal line CK2; the first clock signal terminal CK of the fourth clock signal line GOA-4 is electrically connected to the fourth clock signal line CB2, the second clock signal terminal CB is electrically connected to the second clock signal line CK2, and the third clock signal line CB-2 is electrically connected to the first clock signal line CK1.

[0077] In the embodiment of the present disclosure, when the number of cascaded shift registers is greater, cascading is sequentially implemented in the above manner with four shift registers as a group.

[0078] It can be seen that the shift register of the embodiment of the present disclosure can use at least 4 signal lines when cascading, and use one of the clock signal lines to cooperate with the other two clock signal lines to provide each stage of shift register with a suitable timing and a clock signal that overlaps in the effective level period, so that the effective time extension effect of each stage output can be achieved with as few clock signal lines as possible when cascading.

[0079] Combine the following Figure 2 , Figures 5 to 8 The specific structure and function of the shift register according to the embodiment of the present disclosure are described with reference to specific embodiments.

[0080] Reference Figure 2 and Figure 5As shown, the shift register includes an input sub-circuit 10 , a first control sub-circuit 20 , an output sub-circuit 30 , an output control sub-circuit 40 and a second control sub-circuit 50 .

[0081] The input sub-circuit 10 is electrically connected to the input terminal STV, the first node N1 and the first clock signal terminal CK, and is configured to electrically connect the input terminal STV with the first node N1 based on a signal of the first clock signal terminal CK.

[0082] Specifically, the input subcircuit includes a second transistor T2, a first electrode of the second transistor T2 is electrically connected to the input terminal STV, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the first clock signal terminal CK. When the first clock signal terminal CK is connected to a high-level signal, the second transistor T2 is turned on and the signal of the input terminal STV is input to the first node N1.

[0083] The first control sub-circuit 20 is electrically connected to the first power signal terminal VGH, the second node N2 and the first clock signal terminal CK, and is configured to electrically connect the first power signal terminal VGH with the second node N2 based on a signal of the first clock signal terminal CK.

[0084] Specifically, the first control subcircuit 20 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to the first power signal terminal VGH, a second electrode is electrically connected to the second node N2, and a control terminal is electrically connected to the first clock signal terminal CK. In response to the first clock signal terminal CK receiving a high level signal, the third transistor T3 is turned on, and the potential of the first power signal terminal VGH is input to the second node N2.

[0085] The output sub-circuit 30 is electrically connected to the third node N3 , the second clock signal terminal CB and the output terminal Out, and is configured to output the signal of the second clock signal terminal CB to the output terminal Out based on the signal of the third node N3 .

[0086] Specifically, the output subcircuit 30 includes a fourth transistor T4 and a second capacitor C2, wherein a first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, a second electrode is electrically connected to the output terminal Out, and a control electrode is electrically connected to the third node N3, and a first electrode of the second capacitor C2 is electrically connected to the third node N3, and a second electrode is electrically connected to the output terminal Out. In response to the potential of the third node N3 being at a high level, the fourth transistor T4 is turned on and transmits the signal connected to the second clock signal terminal CB to the output terminal Out, and in addition, the second capacitor C2 is used to maintain the potential of the control electrode of the fourth transistor T4.

[0087] The output control sub-circuit 40 is electrically connected to the second node N2 , the second power signal terminal and the output terminal, and is configured to electrically connect the second power signal terminal VGL to the output terminal Out based on a signal of the second node N2 .

[0088] The output control subcircuit 40 includes a fifth transistor T5 and a third capacitor C3, wherein a first electrode of the fifth transistor T5 is electrically connected to the output terminal Out, a second electrode is electrically connected to the second power signal terminal VGL, and a control electrode is electrically connected to the second node N2, and a first electrode of the third capacitor C3 is electrically connected to the second node N2, and a second electrode is electrically connected to the second power signal terminal VGL. In response to the potential of the second node N2 being at a high level, the fifth transistor T5 is turned on and transmits the signal connected to the second power signal terminal VGL to the output terminal Out, and in addition, the third capacitor C3 is used to maintain the potential of the control electrode of the fifth transistor T5.

[0089] In particular, the shift register also includes: a second control subcircuit 50, electrically connected to the third clock signal terminal CB-2, the second power signal terminal VGL, the second node N2, and the first node N1, and configured to electrically connect the second power signal terminal VGL to the second node N2 based on the signal of the third clock signal terminal CB-2 and the first node N1.

[0090] In an embodiment of the present disclosure, the effective level period of the signal at the third clock signal terminal CB-2 overlaps with the effective level period of the signal at the second power signal terminal CB for at least 1H, where H represents the time required for the shift register to scan a row of pixels.

[0091] Specifically, the second control subcircuit 50 includes a sixth transistor T6 and a seventh transistor T7. A first electrode of the sixth transistor T6 is electrically connected to the first node N1, a second electrode is electrically connected to the first electrode of the seventh transistor N7, and a control electrode is electrically connected to the third clock signal terminal CB-2. A second electrode of the seventh transistor T7 is electrically connected to the second power signal terminal VGL, and a control electrode is electrically connected to the second node N2. When the signal of the third clock signal terminal CB-2 is at a high level, the sixth transistor T6 is turned on to transmit the potential of the first node N1 to the fourth node N4. When the potential of the second node N2 is at a high level, the seventh transistor T7 is turned on to transmit the potential of the second power signal terminal VGL to the fourth node N4. When both the sixth transistor T6 and the seventh transistor T7 are turned on, the potential of the second power signal terminal VGL is written to the first node N1.

[0092] Through this setting, by setting the signal connected to the third clock signal terminal CB-2 to be different from the clock signal connected to the second clock signal terminal CB, the two can be separately regulated, so that the reset time of the first node N1 can be controlled, making the regulation of the first node N1 more flexible, and the overlap time of the effective level period of the signal of the third clock signal terminal CB-2 and the effective level of the signal of the second clock signal terminal CB is the reset time of the first node N1. In addition, by setting the signal connected to the third clock signal terminal CB-2 to be different from the clock signal connected to the second clock signal terminal CB, the RC of the current shift register can be reduced, and the output driving capability of the second clock signal terminal CB can be increased.

[0093] In particular, considering that the effective level periods of the clock signals between stages overlap, when the signal at the second clock signal terminal CB jumps from a low level to a high level, the voltage change will be coupled to the third node N3, and the voltage jump of the third node N3 will cause the fourth transistor T4 as the output transistor to be mis-conducted, thereby affecting the potential of the output terminal Out and generating erroneous output. In the embodiment of the present disclosure, the shift register further includes a first voltage stabilizing sub-circuit 60.

[0094] Reference Figure 5 As shown, the first voltage stabilizing subcircuit 60 includes: a first transistor T1 and a first capacitor C1. The first electrode of the first capacitor C1 is electrically connected to the first power signal terminal VGH, the second electrode is electrically connected to the first electrode of the first transistor T1, the second electrode of the first transistor T1 is electrically connected to the third node N3, and the control electrode is electrically connected to the second node N2. As long as the potential of the second node N2 is at a high level, the first transistor T1 is turned on, and the high level potential coupled to the second electrode via the first electrode of the first capacitor C1 is transmitted to the third node N3, thereby stabilizing the third node N3 at a high level signal.

[0095] Optionally, continue to refer to Figure 5 As shown, the shift register further includes a third control subcircuit, the third control subcircuit is electrically connected to the first node N1, the second node N2 and the first clock signal terminal CK, and is configured to electrically connect the first clock signal terminal CK to the second node N2 based on the signal of the first node N1. The third control subcircuit includes a transistor T8, a first electrode of the transistor T8 is electrically connected to the first clock signal terminal CK, a second electrode is electrically connected to the second node N2, and a control electrode is electrically connected to the first node N1. The transistor T8 is turned on in response to the first node N1 being at a high level, and the signal of the first clock signal terminal CK is written to the second node N2.

[0096] Optionally, refer to Figure 5As shown, the shift register further includes a second voltage stabilizing subcircuit. The second voltage stabilizing subcircuit is electrically connected to the first node N1, the third node N3 and the first power signal terminal VGH, and is configured to electrically connect the third node N3 to the first node N1 based on the signal of the first power signal terminal VGH. The second voltage stabilizing subcircuit includes a transistor T9, a first electrode of the transistor T9 is electrically connected to the first node N1, a second electrode is electrically connected to the third node, and a control electrode is electrically connected to the first power signal terminal VGH. Under the potential of the first power signal terminal VGH, the transistor T9 is continuously turned on, which can prevent the third node N3 from leaking through the path of the second transistor T2 and the sixth transistor T6, reduce the stress of the third node N3 on the first node N1, and is conducive to the voltage stability of the third node N3, which is not easy to fluctuate, so that the fourth transistor T4 as the output transistor is fully turned on.

[0097] Alternatively, refer to Figure 6 As shown, in another example, the shift register further includes an auxiliary output subcircuit and an auxiliary output control subcircuit. The auxiliary output control subcircuit includes a transistor T10, a first electrode of the transistor T10 is electrically connected to the carry terminal CR, a second electrode is electrically connected to the second power signal terminal VGL, a control electrode is electrically connected to the second node N2, and the transistor T10 is turned on in response to the potential of the second node N2 being a high level, and the potential of the second power signal terminal VGL is transmitted to the carry terminal CR. The auxiliary output subcircuit includes a transistor T11 and a fourth capacitor C4. The first electrode of the transistor T11 is electrically connected to the second clock signal terminal CB, the second electrode is electrically connected to the carry terminal CR, and the control terminal is electrically connected to the third node N3. The transistor T11 is turned on in response to the potential of the third node N3 being a high level, and the signal of the second clock signal terminal CB is transmitted to the carry terminal CR. The fourth capacitor C4 is used to store the potential of the third node N3.

[0098] It can be seen that the signal output by the carry terminal CR is the same as the signal output by the output terminal Out, and can be used to cascade with another stage of shift register. Figure 5 As shown, because the auxiliary output subcircuit includes the fourth capacitor C4, the second capacitor C2 may not be included in the output subcircuit 30, and the function of the fourth capacitor C4 is the same as that of the second capacitor C2. In addition, the auxiliary control subcircuit may include a capacitor connected across the second node N2 and the second power signal terminal VGL, while the output control subcircuit may not include the third capacitor C3.

[0099] In addition, although Figure 6 The example does not include the first voltage stabilizing sub-circuit, but is not limited thereto. The shift register may include Figure 5 The first voltage stabilizing sub-circuit 60 composed of the first transistor T1 and the first capacitor C1 shown in FIG. 1 can prevent the output terminal Out and the carry terminal CR from being affected by the voltage jump of the second clock signal terminal CB.

[0100] In order to further understand the structural relationship of each cascade shift register in the gate drive circuit, the driving process of the gate drive circuit is described below through the driving process of the shift register in combination with the timing diagram of the shift register.

[0101] Figure 7 Show Figure 6 The timing diagram of the shift register is shown in FIG. 1. For a single-stage shift register, the driving process includes: a first stage T1, a second stage T2, a third stage T3 and a fourth stage T4.

[0102] In the first stage T1, the signal of the first clock signal terminal CK is high, the signal of the second clock signal terminal CB is low, the signal of the third clock signal terminal CB-2 is low, the signal of the input terminal STV is high, and the high level period of the signal connected to the third clock signal terminal CB-2 overlaps with the high level period of the signal connected to the second clock signal terminal CB2 for at least 1H. The signal synchronized by the fourth clock signal line CB2.

[0103] Specifically, in response to the signal of the first clock signal terminal CK being at a high level, the second transistor T2 is turned on, and the high level signal connected to the input terminal STV is input to the first node N1. Because the transistor T9 is continuously turned on, the high level signal is written to the third node N3 via the turned-on transistor T9 and is maintained by charging the fourth capacitor C4. In response to the third node N3 being at a high level, the fourth transistor T4 is turned on, and the low level signal of the second clock signal terminal CB is transmitted to the output terminal Out.

[0104] At the same time, the third transistor T3 is turned on, connecting the first power signal terminal VGH and the second node N2, the fifth transistor T5 is turned on, and the output control subcircuit also transmits a low level signal to the output terminal Out.

[0105] In the second stage T2, the signal of the first clock signal terminal CK is at a low level, the signal of the second clock signal terminal CB is at a high level, the signal connected to the third clock signal terminal CB-2 changes from a low level to a high level, and the signal of the input terminal STV is a low level signal. The second transistor T2 is turned off, the third transistor T3 is turned off, and due to the effect of the fourth capacitor C4, the third node N3 maintains a high potential, and the fourth transistor T4 is still turned on, outputting the high level signal of the second clock signal terminal CB to the output terminal Out. In addition, due to the bootstrap effect of the fourth capacitor C4, the potential of the third node N3 is higher than that of the first stage T1.

[0106] In addition, because the transistor T9 is continuously turned on, the potential change of the first node N1 is roughly the same as that of the third node N3. The transistor T8 in the third control subcircuit is turned on, and the low-level signal of the first clock signal terminal CK is written into the second node N2, and the fifth transistor T5 is turned off in response to the low-level signal. At this stage, because the third clock signal terminal CB-2 changes from a low level to a high level, the fourth node N4 controls the sixth transistor T6 to turn on when the third clock signal terminal CB-2 changes to a high level, and writes the high-level signal into the fourth node N4.

[0107] In the third stage T3, the signal at the first clock signal terminal CK is high, the signal at the second clock signal terminal CB is low, the signal at the third clock signal terminal CB-2 changes from high to low, and the signal at the input terminal STV is still a low signal.

[0108] At this time, the third transistor T3 is turned on, and the high level signal of the first power signal terminal VGH is written into the second node N2. When the second node N2 and the third clock signal terminal CB-2 are both at high levels, the sixth transistor T6 and the seventh transistor T7 are turned on, and the low level of the second power signal terminal VGL is written into the first node N1. Therefore, the first node N1, the third node N3 and the fourth node N4 are all at low levels. The fourth transistor T4 is turned off, and the fifth transistor T5 is turned on, and the low level of the second power signal terminal VGL is output to the output terminal Out, thereby resetting the shift register of this stage.

[0109] In the fourth stage T4, the first clock signal terminal CK is at a low level, the second clock signal terminal CB changes to a high level, the third clock signal terminal CB-2 changes from a low level to a high level, and the input terminal STV is still a low level signal.

[0110] The second transistor T2 is turned off, the third transistor T3 is turned on, the transistor T9 is continuously turned on, the second node N2 is at a high level, and under the action of the fourth capacitor C4, the third node N3 and the first node N1 are at a low level, the seventh transistor T7 is turned on and the fifth transistor T5 is turned on, the fourth node N4 is at a low level, and the output terminal Out still outputs a low level.

[0111] In the first stage T1, the second stage T2 and the fourth stage T4, the signal connected to the third clock signal terminal CB-2 overlaps with the high level period of the second clock signal terminal CB for at least 1H, so that the overlapping period can be used to complete the resetting of the first node N1 and flexibly adjust the potential of the first node N1. In addition, by setting the signal connected to the third clock signal terminal CB-2 to be different from the clock signal connected to the second clock signal terminal CB, the RC of the current shift register can be reduced and the output driving capability of the second clock signal terminal CB can be increased.

[0112] In addition, for any stage of the shift register, in the first stage T1, a high level signal is written to the first node N1 under the control of the high level period of the first clock signal CK, and in the second stage T2, the output terminal Out segment outputs a high level signal when the second clock signal terminal CB is at a high level.

[0113] Combination Figure 1 and Figure 7 The timing diagram shown in the figure is further combined with Figure 3 It can be seen from the structure diagram of the gate drive circuit shown that if n represents the current stage and n+1 represents the next stage cascaded with the current stage, when the first clock signal terminal CK of the n-th stage shift register is at a high level (i.e., the signal of the first clock signal line CK1 is at a high level), the n-th stage shift register starts to write a valid level signal. During this period, by setting the third clock signal line CK2 connected to the first clock signal terminal CK of the n+1-th stage shift register to overlap with the first clock signal line CK1, the n+1-th stage shift register enters the input terminal writing stage in advance. At the same time, since the period when the second clock signal terminal CB of the n-th stage shift register is at a high level (i.e., the signal of the second clock signal line CB1 is at a high level) overlaps with the period when the signal of the third clock signal line CK2 connected to the first clock signal terminal CK of the n+1-th stage shift register is at a high level, the n+1-th stage shift register ends the input signal writing in advance. Furthermore, in the second half of the second stage T2 (i.e., the second clock signal line CB) of the n-th shift register, that is, the overlapping period of the high-level period of the fourth clock signal line CB2 electrically connected to the second clock signal terminal CB of the n+1-th shift register and the period when the second clock signal line CB is at a high level, the n+1-th shift register outputs a high-level signal in advance, so that the scanning signals output by each shift register have an overlapping period.

[0114] Through this setting, during the high-frequency display panel display process, while maintaining a high refresh rate, the output duration of the scanning signal is extended by utilizing the overlapping period, thereby ensuring that the transistors in the pixel circuit connected thereto can be fully turned on, ensuring effective writing of the data signal.

[0115] In addition, it should be noted that in the fourth stage T4 when the access signal at the second clock signal terminal CB changes from a low level to a high level, the third node N3 is mistakenly raised due to the coupling effect of the second clock signal CB.

[0116] Reference Figure 8 As shown, Figure 8 for Figure 5 The output terminal of the shift register including the first voltage stabilizing subcircuit and Figure 6The output simulation comparison diagram of the shift register without the first voltage stabilization subcircuit is shown. Among them, the period with significantly higher amplitude is the effective output period, during which the output terminal signals coincide, and the waveform with larger amplitude fluctuation in other non-effective output periods is Figure 6 The shift register shown has an almost ripple-free waveform. Figure 5 It can be seen that when the first voltage stabilizing sub-circuit is not provided, the output end is significantly affected by the jump of the signal of the second clock signal end CB due to the overlap of the clock signal. When the first voltage stabilizing sub-circuit is provided, the output can be effectively stabilized, and the interference of the coupling effect of the clock signal of the output transistor on the output signal can be reduced.

[0117] Based on the same inventive concept, an embodiment of the present disclosure further provides a gate driving circuit, the gate driving circuit comprising a plurality of shift registers described in the above embodiments connected in cascade, the output end or carry end of the n-th shift register being electrically connected to the input end of another shift register, wherein n is a positive integer greater than or equal to 1,

[0118] The input end of the first stage shift register is electrically connected to the first initial signal line stv1, and the input end of the second stage shift register is electrically connected to the second initial signal line stv2.

[0119] The effective level period of the signal connected to the first initial signal line and the effective level period of the signal connected to the second initial signal line overlap for at least 1H.

[0120] The output terminal of the nth stage shift register is electrically connected to the input terminal of the (n+2)th shift register.

[0121] Optionally, the first clock signal terminal CK of the 4m-3th level shift register is electrically connected to the first clock signal line CK1, the second clock signal terminal CB is electrically connected to the third clock signal line CB1, and the third clock signal terminal CB-2 is electrically connected to the fourth clock signal line CB2, the first clock signal terminal CK of the 4m-2th level shift register is electrically connected to the second clock signal line CK2, the second clock signal terminal CB is electrically connected to the fourth clock signal line CB2, and the third clock signal terminal CB-2 is electrically connected to the third clock signal line CB1, the first clock signal terminal CK of the 4m-1th level shift register is electrically connected to the third clock signal line CB1, the second clock signal terminal CB is electrically connected to the first clock signal line, and the third clock signal terminal CB-2 is electrically connected to the second clock signal line CK2, the first clock signal terminal of the 4m-level shift register is electrically connected to the fourth clock signal line CB2, the second clock signal terminal CB is electrically connected to the second clock signal line CK2, and the third clock signal terminal CB-2 is electrically connected to the first clock signal line CK1, wherein m is a positive integer.

[0122] It can be understood that when m=1, the structure of the gate drive circuit is as follows Figure 3 As shown, of course, this implementation is not limited to this, and the specific value of m can be selected as needed.

[0123] Optionally, the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1th level shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-th level shift register for at least 1H, the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1th level shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-th level shift register for at least 1H, and the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1th level shift register overlaps with the effective level signal period of the signal connected to the second clock signal terminal of the 2m-th level shift register for at least 1H.

[0124] Through this arrangement, at least the first to fourth clock signal lines are used to provide clock signals, and the effective level periods between the corresponding clock signals provided to adjacent stages of shift registers overlap by at least 1H, thereby making the effective level periods of the output signals of adjacent stages of shift register circuits overlap, thereby increasing the output effective level time length and ensuring that the data signal can be fully written at a high scanning frequency.

[0125] Reference Fig. 9 As shown in FIG. 1 , the output simulation diagram of the gate drive circuit of the embodiment of the present disclosure is given. Fig. 9 As shown, the simulation process adopts a gate drive circuit composed of a cascade of 5-stage shift registers. Through the design of overlapping effective level periods at the clock signal end, the signals output by each output end have overlapping periods. Compared with the output signal without overlapping periods, it can ensure that the duration of each output end is increased within a limited period of time, so that the pixel circuit controlled by the output signal increases the conduction time of the transistor, ensuring that the data signal is fully written.

[0126] Based on the same inventive concept, an embodiment of the present disclosure further provides a driving method applied to the gate driving circuit described above, comprising:

[0127] In the first stage of the n-stage shift register, based on the signal connected to the first clock signal terminal being at a valid level and the signal connected to the second clock signal terminal being at an invalid level, the input subcircuit and the output subcircuit of the n-stage shift register are turned on, and the first power signal terminal and the second node are turned on through the first control subcircuit of the n-stage shift register;

[0128] In the second stage of the n-th shift register, the output sub-circuit of the n-th shift register is turned on to output a valid level signal, and based on the signal connected to the second clock signal terminal of another shift register cascaded with the n-th shift register becoming a valid level, the output sub-circuit of the other shift register is turned on to output a valid level signal.

[0129] Those skilled in the art should understand that the specific process of the above method has been described in detail in conjunction with various timing diagrams when describing the specific circuit principle of the shift register above, and will not be repeated here.

[0130] In this embodiment, a shift register having a second control sub-circuit is provided, and the effective level period of the signal connected to the third clock signal terminal as the control terminal in the control sub-circuit overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit by at least 1H, thereby being able to control the reset time of the first node, improve the regulation flexibility of the first node, increase the output driving capability, and improve the display effect.

[0131] In addition, at least the first to fourth clock signal lines are used to provide clock signals, and the effective level periods between the corresponding clock signals provided to adjacent stages of shift registers overlap by at least 1H, so that the effective level periods of the output signals of adjacent stages of shift register circuits overlap, thereby increasing the output effective level time length and ensuring that the data signal can be fully written at a high scanning frequency.

[0132] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the gate driving circuit described in the above embodiment.

[0133] The display panel can effectively realize high-frequency display by including the gate driving circuit.

[0134] Optionally, refer to Fig.10 As shown in the example diagram, the display panel includes: at least one pixel driving circuit, the pixel circuit includes: a driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a first resetting subcircuit and a light emitting unit,

[0135] A driving sub-circuit, electrically connected to the fourth node Q4, the fifth node Q5 and the sixth node Q6, configured to generate a driving current based on a data signal input from the fourth node Q4,

[0136] The light emitting control subcircuit is electrically connected to the fourth power signal terminal, the fifth node Q5, the sixth node Q6, the first and second light emitting control terminals EM1 and EM2, and the anode of the light emitting unit D, and is configured to transmit the driving current to the anode based on the signals of the first and second light emitting control terminals EM1 and EM2,

[0137] The write subcircuit is electrically connected to the fourth node Q4, the data signal terminal Vdata and the write control terminal Gate, and is configured to transmit the data signal connected to the data signal terminal Vdata to the fourth node Q4 based on the signal of the write control terminal Gate.

[0138] The first reset sub-circuit is electrically connected to the first reset control terminal Reset1, the first reset signal terminal Vint2 and the sixth node Q6, and is configured to electrically connect the first reset signal terminal Vint2 to the sixth node Q6 based on the signal of the first reset control terminal Reset1,

[0139] The first reset signal terminal Vint2 is connected to a DC signal or an AC signal with a potential change.

[0140] In this embodiment, by setting the reset signal terminal signal for resetting the sixth node of the driving sub-circuit to a DC signal or an AC signal with a changing potential, different reset signals can be output according to the threshold offset conditions in the driving sub-circuit at different display stages, so that the reset effects in different time periods can be consistent, ensuring consistent display brightness in different time periods and improving the display effect.

[0141] Specifically, refer to Fig.10 As shown, the driving sub-circuit includes: an eighth transistor M8, a first electrode of the eighth transistor M8 is electrically connected to the fifth node Q5, a second electrode is electrically connected to the sixth node Q6, and a control electrode is electrically connected to the fourth node Q4.

[0142] The light-emitting control subcircuit includes: a ninth transistor M9 and a tenth transistor M10, wherein a first electrode of the ninth transistor M9 is electrically connected to a fourth power signal terminal VDD, a second electrode is electrically connected to a fifth node Q5, and a control electrode is electrically connected to a first light-emitting control terminal EM1, and a first electrode of the tenth transistor is electrically connected to a sixth node Q6, a second electrode is electrically connected to an anode, and a control electrode is electrically connected to a second light-emitting control terminal EM2.

[0143] The first reset sub-circuit includes an eleventh transistor M11 , a first electrode of the eleventh transistor M11 is electrically connected to the first reset signal terminal Vinit2 , a second electrode is electrically connected to the sixth node Q6 , and a control electrode is electrically connected to the first reset control terminal Reset1 .

[0144] Optionally, refer to Fig.10 As shown, the pixel circuit is a discrete compensation circuit. The pixel circuit also includes: a writing subcircuit and a compensation subcircuit, the writing subcircuit is electrically connected to the fourth node, the data signal terminal and the writing control terminal, and is configured to transmit the data signal connected to the data signal terminal to the fourth node based on the signal of the writing control terminal,

[0145] The compensation subcircuit is electrically connected to the set signal terminal, the set control terminal and the fourth node, and is configured to transmit the signal of the set signal terminal to the fourth node based on the signal of the set control terminal to perform threshold voltage compensation.

[0146] Continue to refer to Fig.10 As shown, the writing sub-circuit includes a twelfth transistor M12, a first electrode of the twelfth transistor M12 is electrically connected to the data signal terminal Vdata, a second electrode is electrically connected to the fourth node Q4, and a control electrode is electrically connected to the writing control terminal Gate. The compensation sub-circuit includes: a thirteenth transistor M13. The first electrode of the thirteenth transistor M13 is electrically connected to the setting signal terminal Vinit1, the second electrode is electrically connected to the fourth node Q4, and the control electrode is electrically connected to the setting control terminal.

[0147] Fig.11 Show Fig.10 The timing diagram of the key ports in the circuit schematic. The pixel driving process includes the reset phase t1, the compensation phase t2, the writing phase t3 and the light-emitting phase t4.

[0148] In the reset stage t1, the second light emitting control terminal EM2, the first reset control terminal Reset2, and the set control terminal Reset1 are at a high level, the tenth transistor M10, the eleventh transistor M11, and the thirteenth transistor M13 are all turned on, the signal of the first reset signal terminal Vinit2 is input to the sixth node Q6 and the seventh node Q7, and the signal of the set signal terminal Vinit1 is written into the fourth node Q4. At this time, the signal connected to the set signal Vinit1 is actually a reset signal.

[0149] In the compensation stage t2, the setting control terminal Reset1 is at a high level, the thirteenth transistor M13 is turned on, and the compensation signal of the setting signal terminal Vinit1 is directly written into the fourth node N4 to perform threshold compensation on the eighth transistor M8 as the driving transistor. Of course, in this process, the first light-emitting control terminal EM1 is also at a high level, and the eighth transistor M8 is turned on by turning on the ninth transistor M9 to cooperate with each other to achieve threshold compensation.

[0150] In the writing stage t3, the scanning signal output by the gate driving circuit reaches the writing control terminal Gate, the twelfth transistor M12 is turned on, and the data signal connected to the data signal terminal Vdata is input to the control electrode of the eighth transistor M8.

[0151] In the light emitting stage t4 , the first light emitting control terminal EM1 and the second light emitting control terminal EM2 are at high level, and the fourth node Q4 is kept turned on by the capacitor C, thereby forming a driving current path to output to the anode of the light emitting unit D.

[0152] The above arrangement utilizes separate data signal writing and threshold compensation to achieve the purpose of extending the threshold compensation time.

[0153] In particular, considering that the image display process includes refresh frames and hold frames, in the refresh frame stage, the pixel driving circuit writes data signals, and in the hold frame stage, the pixel driving circuit does not write data signals. The brightness of the display unit is different when the data signal is written and when the data signal is not written, which will produce visible flicker.

[0154] The inventors have found through research that the reason for the different brightness in the two stages is that when the eighth transistor M8 is turned on in one state for a long time during the frame holding stage, a characteristic shift in a certain direction will occur, that is, the shift degrees in the two stages are different, and a flash occurs at the switching moment.

[0155] In order to solve this problem, in the embodiment of the present disclosure, the signal connected to the first reset signal terminal is set to be a DC signal or an AC signal with a potential change. Preferably, the first reset signal terminal Vinit2 is connected to a signal with a first amplitude in the refresh frame and a signal with a second amplitude in the hold frame. The specific amplitude size relationship and value are determined according to the offset direction and amplitude of the driving transistor. The offset direction and amplitude are determined according to the detection mechanism in the display panel, which will not be repeated here.

[0156] Through the above settings, flickering when refreshing frames and maintaining frames during switching can be avoided, thereby improving the display effect.

[0157] It should be noted that the structure of the above pixel circuit is only schematic and is not intended to be limiting. Pixel driving circuits composed of other numbers of transistors are also applicable to the embodiments of the present disclosure, as long as the second electrode of the driving transistor is reset by the first reset sub-circuit.

[0158] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, comprising the display panel described in the above embodiment.

[0159] In this embodiment, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a car display, a digital photo frame or a navigator. By using a display panel with the above gate drive circuit, it is possible to ensure the normal display of the display image during the display process of the display device, especially at a high refresh rate. It has a strong driving capability and has broad application prospects.

[0160] In response to the existing problems, the present disclosure develops a shift register, a gate drive circuit and a driving method thereof, a display panel and a display device, and provides a shift register with a second control sub-circuit, and the effective level period of the signal connected to the third clock signal terminal as the control terminal in the control sub-circuit overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit for at least 1H, thereby being able to control the reset time of the first node, improve the regulation flexibility of the first node, increase the output drive capability, and improve the display effect, and has broad application prospects.

[0161] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A shift register, characterized in that: include: an input subcircuit, electrically connected to an input terminal, a first node and a first clock signal terminal, and configured to electrically connect the input terminal to the first node based on a signal at the first clock signal terminal; a first control subcircuit, electrically connected to a first power signal terminal, a second node, and the first clock signal terminal, and configured to electrically connect the first power signal terminal to the second node based on a signal at the first clock signal terminal; an output subcircuit, electrically connected to the third node, the second clock signal terminal and the output terminal, configured to output the signal of the second clock signal terminal to the output terminal based on the signal of the third node; an output control subcircuit, electrically connected to the second node, the second power signal terminal and the output terminal, configured to electrically connect the second power signal terminal to the output terminal based on a signal of the second node; a second control subcircuit, electrically connected to a third clock signal terminal, the second power signal terminal, the second node, and the first node, and configured to electrically connect the second power signal terminal to the second node based on a signal of the third clock signal terminal and the first node; There is an overlap period of at least 1H between the effective level period of the signal at the third clock signal end and the effective level period of the signal at the second power signal end, where H represents the time required for the shift register to scan a row of pixels.

2. The shift register according to claim 1, characterized in that: Also includes: A first voltage stabilizing subcircuit, wherein the first voltage stabilizing subcircuit comprises: a first transistor and a first capacitor, The first electrode of the first capacitor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the first electrode of the first transistor, the second electrode of the first transistor is electrically connected to the third node, and the control electrode is electrically connected to the second node.

3. The shift register according to claim 1, wherein: Also includes: The third control subcircuit is electrically connected to the first node, the second node and the first clock signal terminal, and is configured to electrically connect the first clock signal terminal to the second node based on a signal of the first node.

4. The shift register according to claim 1, wherein: Also includes: The second voltage stabilizing subcircuit is electrically connected to the first node, the third node and the first power signal terminal, and is configured to electrically connect the third node with the first node based on a signal at the first power signal terminal.

5. The shift register according to claim 1, characterized in that: The input subcircuit comprises a second transistor, a first electrode of the second transistor is electrically connected to the input terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the first clock signal terminal. The first control subcircuit includes a third transistor, a first electrode of the third transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the second node, and a control terminal is electrically connected to the first clock signal terminal. The output subcircuit includes a fourth transistor and a second capacitor, wherein a first electrode of the fourth transistor is electrically connected to the second clock signal terminal, a second electrode is electrically connected to the output terminal, and a control electrode is electrically connected to the third node; a first electrode of the second capacitor is electrically connected to the third node, and a second electrode is electrically connected to the output terminal. The output control subcircuit includes a fifth transistor and a third capacitor, wherein a first electrode of the fifth transistor is electrically connected to the output terminal, a second electrode is electrically connected to the second power signal terminal, and a control electrode is electrically connected to the second node, a first electrode of the third capacitor is electrically connected to the second node, and a second electrode is electrically connected to the second power signal terminal. The second control subcircuit includes a sixth transistor and a seventh transistor, The first electrode of the sixth transistor is electrically connected to the first node, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the third clock signal terminal. The second electrode of the seventh transistor is electrically connected to the second power supply signal terminal, and the control electrode is electrically connected to the second node.

6. The shift register according to claim 3, characterized in that: The third control subcircuit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node.

7. A gate drive circuit, characterized in that: A plurality of shift registers according to any one of claims 1 to 6 are cascaded, wherein an output terminal or a carry terminal of an n-th stage shift register is electrically connected to an input terminal of another stage shift register, wherein n is a positive integer greater than or equal to 1, The input end of the first stage shift register is electrically connected to the first initial signal line, and the input end of the second stage shift register is electrically connected to the second initial signal line. The effective level period of the signal connected to the first initial signal line and the effective level period of the signal connected to the second initial signal line overlap for at least 1H. The output end of the n-th shift register is electrically connected to the input end of the (n+2)-th shift register.

8. The gate driving circuit according to claim 7, characterized in that: The first clock signal terminal of the 4m-3 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line. The first clock signal terminal of the 4m-2 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 4m-1th stage shift register is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line. The first clock signal terminal of the 4m-stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. Wherein, m is a positive integer.

9. The gate driving circuit according to claim 8, characterized in that: in, There is an overlapping period of at least 1H between the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1-level shift register and the effective level signal period of the signal connected to the first clock signal terminal of the 2m-level shift register, there is an overlapping period of at least 1H between the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1-level shift register and the effective level signal period of the signal connected to the first clock signal terminal of the 2m-level shift register, there is an overlapping period of at least 1H between the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1-level shift register and the effective level signal period of the signal connected to the second clock signal terminal of the 2m-level shift register.

10. A display panel, characterized in that: Comprising a gate drive circuit as described in any one of claims 7-9.

11. The display panel according to claim 10, characterized in that: Also includes: at least one pixel circuit, the pixel circuit comprising: a driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a first resetting subcircuit and a light emitting unit, a driving subcircuit, electrically connected to the fourth node, the fifth node and the sixth node, and configured to generate a driving current based on a data signal inputted from the fourth node, a light emitting control subcircuit, electrically connected to the fourth power signal terminal, the fifth node, the sixth node, the first and second light emitting control terminals, and the anode of the light emitting unit, and configured to transmit the driving current to the anode based on the signals of the first and second light emitting control terminals, The write subcircuit is electrically connected to the fourth node, the data signal terminal and the write control terminal, and is configured to transmit the data signal connected to the data signal terminal to the fourth node based on the signal of the write control terminal. The first reset subcircuit is electrically connected to the first reset control terminal, the first reset signal terminal and the sixth node, and is configured to electrically connect the first reset signal terminal to the sixth node based on a signal of the first reset control terminal. The first reset signal terminal is connected to a DC signal or an AC signal with a potential change.

12. The display panel according to claim 11, characterized in that: The image display process of the light-emitting unit includes a refresh frame and a hold frame, the first reset signal terminal receives a signal with a first amplitude in the refresh frame and receives a signal with a second amplitude in the hold frame, The first amplitude is greater than the second amplitude.

13. The display panel according to claim 11, characterized in that: The output end of the shift register is electrically connected to the write control end of the pixel circuit of the corresponding row.

14. A driving method for a gate driving circuit as claimed in any one of claims 7 to 9, characterized in that: In the first stage of the n-stage shift register, based on the signal connected to the first clock signal terminal being at a valid level and the signal connected to the second clock signal terminal being at an invalid level, the input subcircuit and the output subcircuit of the n-stage shift register are turned on, and the first power signal terminal and the second node are turned on through the first control subcircuit of the n-stage shift register; In the second stage of the n-th stage shift register, the output sub-circuit of the n-th stage shift register is turned on to output a valid level signal, and based on the signal connected to the second clock signal terminal of another stage shift register cascaded with the n-th stage shift register becoming a valid level, the output sub-circuit of the other stage shift register is turned on to output a valid level signal.

15. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 10 to 13.

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