Display driving circuit, display driving chip, display module and electronic equipment

Abstract

The invention provides a display driving circuit, a display driving chip, a display module and electronic equipment. The display driving circuit comprises a first digital-to-analog converter (DAC), a second DAC, a driving enhancement circuit and a buffer, the first DAC is used for receiving the first digital signal and performing digital-to-analog conversion on the first digital signal; the input end of the second DAC is connected with the output end of the first DAC, and the second DAC is used for receiving the second digital signal and performing analog-to-digital conversion on the second digital signal; the buffer is used for outputting a voltage signal, and the input end of the buffer is connected with the output end of the second DAC; and the output end of the driving enhancement circuit is connected with the output end of the second DAC, and the driving enhancement circuit is used for charging the output end of the second DAC. According to the display panel, the situation of brightness inversion of pixel points on the display panel can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a display driving circuit, a display driving chip, a display module and an electronic device. Background Art

[0002] The source driver circuit is a circuit module integrated into the display driver chip, which can receive digital signals and convert them into analog signals, and charge the grayscale voltage corresponding to the analog signal to the pixel capacitor of the display panel, so that the pixel capacitor emits the brightness corresponding to the analog signal. In order to make the display panel display more delicate and accurate, the grayscale voltage can usually be divided into multiple gears.

[0003] The source driving circuit usually includes a digital-analog converter (DAC), which can convert digital signals into corresponding analog signals for output. When the grayscale voltage has more gears, the structure of the DAC becomes more complex and the volume becomes larger. Therefore, in order to save the area of ​​the display driver chip, interpolation technology is usually used to realize the conversion of digital signals to analog signals. That is, the voltage of multiple gears, some of which are non-interpolation voltages, and the voltage of other gears are interpolation voltages, and multiple interpolation voltages are evenly inserted between each two adjacent non-interpolation voltages.

[0004] However, in the related art, the non-interpolation step voltage is often smaller than the previous interpolation step voltage, which causes the brightness of the pixels on the display panel to be inverted, resulting in dark stripes on the display panel, making it impossible to achieve accurate display of the picture. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a display driving circuit, a display driving chip, a display module and an electronic device, which can reduce the brightness inversion of pixels on a display panel.

[0006] In a first aspect of the present application, a display driving circuit is provided, comprising: a first digital-to-analog converter DAC, a second DAC, a driving enhancement circuit and a buffer. The output end of the first DAC is connected to the input end of the second DAC, the output end of the second DAC is connected to the input end of the buffer, and the output end of the driving enhancement circuit is connected to the output end of the second DAC.

[0007] The display driver circuit of the present application can be applied to a display driver chip, and the display driver chip also includes a timing control circuit, and the timing control circuit can send a timing signal to the display driver circuit. The first DAC is used to receive a first digital signal, and the first digital signal can be a digital signal of the upper few bits in the timing signal. The first DAC performs analog-to-digital conversion on the first digital signal to obtain a first voltage signal. The second DAC is used to receive a second digital signal and a first voltage signal, and the second digital signal can be a digital signal of the lower few bits in the timing signal. The second DAC can perform analog-to-digital conversion on the second digital signal, and divide the first voltage signal into multiple second voltage signals according to the analog-to-digital conversion result and output them. The driving enhancement circuit is used to charge the output end of the second DAC, that is, to enhance the voltage of the multiple second voltage signals output by the second DAC. The buffer is used to receive multiple second voltage signals and output one voltage signal (hereinafter referred to as the third voltage signal for ease of distinction). In the specific charging process of the driving enhancement circuit, when the voltage corresponding to the timing signal is a first type of voltage (hereinafter referred to as a non-interpolation voltage for ease of description), the driving enhancement circuit may charge the output end of the second DAC; when the voltage corresponding to the timing signal is a second type of voltage (hereinafter referred to as an interpolation voltage for ease of description), the driving enhancement circuit may not charge the output end of the second DAC. Thus, when the voltage of the third voltage signal is a non-interpolation voltage, the voltage at the output end of the second DAC can be increased, thereby ensuring that the non-interpolation voltage currently output is always greater than the interpolation voltage of the previous gear, reducing the brightness inversion of the pixels on the display panel, and reducing the appearance of dark stripes on the display panel, thereby achieving accurate display of the picture.

[0008] In some embodiments of the present application, the driving enhancement circuit includes a first capacitor, the first end of the first capacitor is used to be connected to the first power supply, and the second end of the first capacitor is connected to the output end of the second DAC. The first power supply can charge the first capacitor, that is, the potential of the first end of the first capacitor is the same as the potential of the output end of the first power supply. Moreover, after the first power supply charges the first capacitor for a period of time, the potential of the second end of the first capacitor is the same as the potential of the first end of the first capacitor. Since the second end of the first capacitor is connected to the output end of the second DAC, the potential of the output end of the second DAC is the same as the potential of the second end of the first capacitor, thereby realizing the first capacitor charging the output end of the second DAC. The driving enhancement circuit is implemented by the first capacitor, which can make the structure of the scheme relatively simple and easy to implement. In addition, when the potential of the output end of the second DAC is the same as the potential of the second end of the first capacitor, and after the first power supply no longer charges the first capacitor, under the action of the first capacitor, the potential of the output end of the second DAC slowly decreases, and the voltage of the pixel capacitor will also slowly decrease to slightly higher than its previous interpolation stage voltage. Before the charging of the pixel capacitor is completed, the current non-interpolation stage voltage is always higher than the previous interpolation stage voltage, so that the brightness reversal of the pixel point on the display panel can be better avoided.

[0009] Based on this, the driving enhancement circuit also includes a second capacitor and a third capacitor, the first end of the second capacitor is used to connect to the second power supply, and the second end of the second capacitor is connected to the output end of the second DAC. The first end of the third capacitor is used to connect to the third power supply, and the second end of the third capacitor is connected to the output end of the second DAC. Since the voltage of the third voltage signal output by the buffer may be one of a plurality of non-interpolation step voltages, and the magnitudes of different non-interpolation step voltages are different. When the driving enhancement circuit also includes a second capacitor and a third capacitor, and the first end of the first capacitor is connected to the first power supply, the first end of the second capacitor is connected to the second power supply, and the first end of the third capacitor is connected to the third power supply, that is, the first ends of the first capacitor, the second capacitor and the third capacitor are respectively connected to different power supplies. Thus, the number of capacitors charged for the output end of the second DAC can be controlled by each power supply, thereby controlling the degree of charging for the output end of the second DAC, and then realizing different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal output from the buffer after charging is closer to the corresponding non-interpolation step voltage theoretical value, thereby improving the accuracy of brightness control of the pixel points of the display panel.

[0010] In some embodiments of the present application, the driving enhancement circuit further includes a first capacitor state control circuit, the input end of the first capacitor state control circuit is connected to the second end of the first capacitor, the output end of the first capacitor state control circuit is connected to the output end of the second DAC, and the first capacitor state control circuit is used to control whether the first capacitor is charged to the output end of the second DAC. In a specific implementation, when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first capacitor state control circuit controls the first capacitor to charge to the output end of the second DAC; when the voltage corresponding to the timing signal is an interpolation step voltage, the first capacitor state control circuit controls the first capacitor not to charge to the output end of the second DAC, thereby making the charging of the output end of the second DAC more accurate. In addition, when the voltage corresponding to the timing signal is an interpolation step voltage, the first power supply charges the first capacitor, and the first capacitor does not need to charge to the output end of the second DAC; when the voltage corresponding to the timing signal is an interpolation step voltage, the first power supply has completed charging the first capacitor, and the first capacitor can charge to the output end of the second DAC, thereby avoiding the extra occupation of the clock cycle, thereby increasing the charging speed of the pixel capacitor.

[0011] In a specific implementation, the first capacitor state control circuit can receive the lower digital signals in the timing signal, and determine whether the corresponding voltage is an interpolation step voltage or a non-interpolation step voltage based on the lower digital signals, so that when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first capacitor is controlled to charge the output end of the second DAC.

[0012] Further, the drive enhancement circuit also includes a second capacitor and a third capacitor, the first end of the second capacitor is used to be connected to the first power supply, and the first end of the third capacitor is used to be connected to the first power supply. The drive enhancement circuit also includes a second capacitor state control circuit and a third capacitor state control circuit, the input end of the second capacitor state control circuit is connected to the second end of the second capacitor, and the output end of the second capacitor state control circuit is connected to the output end of the second DAC. In this way, the second capacitor state control circuit can control whether the second capacitor is charged to the output end of the second DAC. The input end of the third capacitor state control circuit is connected to the second end of the third capacitor, and the output end of the third capacitor state control circuit is connected to the output end of the second DAC. In this way, the third capacitor state control circuit can control whether the third capacitor is charged to the output end of the second DAC. Therefore, in the present application, when a plurality of capacitors are included in the drive enhancement circuit, each capacitor state control circuit can control whether the corresponding capacitor is charged to the output end of the second DAC.

[0013] In some embodiments of the present application, the first capacitor state control circuit includes a first switch tube, the first electrode of the first switch tube is connected to the second end of the first capacitor, and the second electrode of the first switch tube is connected to the output end of the second DAC. The control electrode of the first switch tube can be used to receive a low-order digital signal in a timing signal. In one example, when the low-order digital signal is 0, the first switch tube is disconnected; when the low-order digital signal is 1, the first switch tube is closed. In another example, when the low-order digital signal is 1, the first switch tube is disconnected; when the low-order digital signal is 0, the first switch tube is closed. When the first switch tube is closed, the first switch tube can connect the second end of the first capacitor to the output end of the second DAC and charge the output end of the second DAC. This solution has a simple structure, is easy to implement, and is relatively reliable.

[0014] In some cases, the second DAC can receive a multi-bit digital signal in the timing signal, and each switch tube can receive a digital signal. Therefore, in order to realize receiving each digital signal in the multi-bit digital signal, in one embodiment, the capacitor state control circuit may also include a second switch tube and a third switch tube, the first pole of the second switch tube is connected to the second pole of the first switch tube, the first pole of the third switch tube is connected to the second pole of the second switch tube, and the second pole of the third switch tube is connected to the output end of the second DAC. In other words, the first switch tube, the second switch tube and the third switch tube are connected in series in sequence. The control pole of the first switch tube, the control pole of the second switch tube and the control pole of the third switch tube can respectively receive one of the digital signals in the multi-bit digital signal. When each digital signal is 1, the first switch tube, the second switch tube and the third switch tube are all closed, so that the first capacitor can charge the output end of the second DAC.

[0015] In another embodiment, the second DAC can receive a two-bit digital signal in the timing signal, and the first capacitor state control circuit may include two switches, namely a first switch and a second switch, and the first electrode of the second switch is connected to the second electrode of the first switch, and the second electrode of the second switch is connected to the output end of the second DAC. Thus, when the digital signals received by the control electrode of the first switch and the control electrode of the second switch are both 1, the first switch, the second switch and the third switch are all closed, so that the first capacitor can charge the output end of the second DAC.

[0016] It can be understood that in other embodiments, the second DAC can receive a four-bit digital signal in the timing signal, and the first capacitor state control circuit can include four switching tubes; the second DAC can receive a five-bit digital signal in the timing signal, and the first capacitor state control circuit can include five switching tubes; and so on.

[0017] In some embodiments of the present application, the driving enhancement circuit further includes a second capacitor and a third capacitor, the first end of the second capacitor is used to connect to the first power supply, and the second end of the third capacitor is used to connect to the first power supply. In this case, the driving enhancement circuit also includes a charging gear control circuit, the second ends of the first capacitor, the second capacitor and the third capacitor are all connected to the input end of the charging gear control circuit, the output end of the charging gear control circuit is connected to the output end of the second DAC, and the charging gear control circuit is used to control the number of capacitors charged to the output end of the second DAC. In other words, the charging gear control circuit can control whether the first capacitor is charged to the output end of the second DAC, control whether the second capacitor is charged to the output end of the second DAC, and control whether the third capacitor is charged to the output end of the second DAC. The first capacitor, the second capacitor and the third capacitor can form a capacitor array, and the more capacitors charged to the output end of the second DAC, the greater the capacitance value of the capacitor array, the faster the voltage establishment speed of the output end of the second DAC and the higher the voltage. This makes it easy to select different numbers of capacitors to charge the output end of the second DAC according to the size of the voltage corresponding to the timing signal, so as to control the degree of charging the output end of the second DAC, and then to achieve different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal output from the buffer after charging is closer to the corresponding non-interpolation step voltage theoretical value, thereby improving the accuracy of brightness control of the pixel points of the display panel.

[0018] In a specific implementation, the received signal of the driving enhancement circuit can be the same as the received signal of the first DAC, for example, both are high-order digital signals of the timing signal. The driving enhancement circuit can determine the number of capacitors to be charged to the output end of the second DAC based on the size relationship between the high-order digital signals.

[0019] Specifically, the charging gear control circuit includes a fourth switch tube, a fifth switch tube and a sixth switch tube, wherein the first electrode of the fourth switch tube is connected to the second end of the first capacitor, and the second electrode of the fourth switch tube is connected to the output end of the second DAC; the first electrode of the fifth switch tube is connected to the second end of the second capacitor, and the second electrode of the fifth switch tube is connected to the output end of the second DAC; the first electrode of the sixth switch tube is connected to the second end of the third capacitor, and the second electrode of the sixth switch tube is connected to the output end of the second DAC. In other words, the fourth switch tube controls whether the first capacitor is charged to the output end of the second DAC, the fifth switch tube controls whether the second capacitor is charged to the output end of the second DAC, and the sixth switch tube controls whether the third capacitor is charged to the output end of the second DAC. For example, when the fourth switch tube, the fifth switch tube and the sixth switch tube are all closed, the first capacitor, the second capacitor and the third capacitor can all be charged to the output end of the second DAC, that is, the number of capacitors charged to the output end of the second DAC is three; when two of the fourth switch tube, the fifth switch tube and the sixth switch tube are closed, the number of capacitors charged to the output end of the second DAC is two; when one of the fourth switch tube, the fifth switch tube and the sixth switch tube is closed, the number of capacitors charged to the output end of the second DAC is one.

[0020] In a specific implementation, the control electrodes of the fourth switch tube, the fifth switch tube, and the sixth switch tube can respectively receive three of the higher digital signals. When the digital signal received by the fourth switch tube is 1, it is closed; when the received digital signal is 0, it is disconnected, so that the first capacitor can charge the output end of the second DAC. Similarly, when the fifth switch tube is closed, the second capacitor can charge the output end of the second DAC. When the sixth switch tube is closed, the third capacitor can charge the output end of the second DAC.

[0021] It can be understood that the number of capacitors in the driving enhancement circuit can be the same as the number of bits of the upper digital signals in the timing signal received by the first DAC. For example, when the first DAC receives the upper 6-bit digital signal, the driving enhancement circuit can include 6 capacitors. Correspondingly, the number of switch tubes in the charging gear control circuit can also be the same as the number of bits of the upper digital signals in the timing signal received by the first DAC, that is, also 6. In this way, the charging degree of the output end of the second DAC by the driving enhancement circuit can be more accurately controlled.

[0022] In a second aspect of the present application, a display driver chip is provided, comprising a timing control circuit and the display driver circuit of any of the above embodiments, wherein the timing control circuit is electrically connected to the display driver circuit. The display driver chip can achieve all the effects of the display driver circuit.

[0023] In a third aspect of the present application, a display module is provided, comprising a display panel and the above-mentioned display driver chip, wherein the display panel is electrically connected to the display driver chip. The display module can achieve all the effects of the display driver chip.

[0024] In a fourth aspect of the present application, an electronic device is provided, comprising a controller and the above-mentioned display module, wherein the controller is electrically connected to the display module. The electronic device can display all effects of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 This is a schematic diagram of the structure of the display module in the embodiment of the present application;

[0027] Figure 2 A schematic diagram of the specific structure of a power supply, a display driver chip and a display panel in an embodiment of the present application;

[0028] Figure 3 The voltage variation curve in the process of charging the pixel capacitor by the non-interpolation step voltage 127 and the interpolation step voltage 126;

[0029] Figure 4 A schematic diagram of the structure of a display driving circuit in an embodiment of the present application;

[0030] Figure 5 for Figure 4 A specific structural schematic diagram of the display driving circuit shown;

[0031] Figure 6a for Figure 5 A schematic diagram of a specific structure of a driving enhancement circuit and a connection structure between the second DAC and the first power supply in the display driving circuit shown;

[0032] Figure 6b for Figure 5 Another specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC first power supply, the second power supply and the third power supply in the display driving circuit shown;

[0033] Figure 7 1 is a voltage variation curve of the non-interpolation step voltage 127 and the interpolation step voltage 126 in the present embodiment during the charging process of the pixel capacitor, and a voltage variation curve of the non-interpolation step voltage 127 during the charging process of the pixel capacitor C when the display driving circuit 50 does not include the driving enhancement circuit 54;

[0034] Figure 8a for Figure 5 A third specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC and the first power supply in the display driving circuit shown;

[0035] Figure 8b for Figure 5 A fourth specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC first power supply, the second power supply and the third power supply in the display driving circuit shown;

[0036] Fig. 9 for Figure 5 A fifth specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC first power supply, the second power supply and the third power supply in the display driving circuit shown;

[0037] Fig.10 for Figure 5 A sixth specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC first power supply, the second power supply and the third power supply in the display driving circuit shown;

[0038] Fig.11 for Figure 5 A seventh specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC first power supply, the second power supply and the third power supply in the display driving circuit shown;

[0039] Fig.12 for Figure 5 In the display driving circuit shown, an eighth specific structure of the driving enhancement circuit and a schematic diagram of the connection structure between the second DAC first power supply, the second power supply and the third power supply are shown.

[0040] Icons: 1000-display driver chip; 10-power conversion circuit; 11-first power supply; 12-second power supply; 13-third power supply; 20-reference voltage generation circuit; 30-timing control circuit; 40-gate drive circuit; 50-source drive circuit; 51-first DAC; 52-second DAC; 53-buffer; 531-differential circuit; 5311-differential pair; 532-power amplifier; 54-drive enhancement circuit; 541-first capacitor state control circuit; 542-second capacitor state control circuit; 543-third capacitor state control circuit; 544-charging gear control circuit; 200-power supply; 300-flexible cable; 400-display panel; 1000-display module. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] The term "and / or" herein is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, wherein A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following (items)" or similar expressions refers to any combination of these items, including any combination of single (items) or plural (items). For example, at least one (item) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or multiple.

[0043] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0044] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0045] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0046] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0047] An electronic device generally includes a display module and a controller. The display module is electrically connected to the controller. The controller can send a control signal to the display module to control the display module to display images, texts and other information.

[0048] Here, the electronic device may be, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the embodiments of the present application do not limit this. Indicatively, the above-mentioned consumer electronic products may be a mobile phone, a tablet computer, a laptop computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (e.g., a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. Home electronic products may be smart door locks, televisions, smart speakers, sweeping robots, etc. Vehicle-mounted electronic products may be vehicle-mounted navigators, vehicle-mounted displays, etc. Financial terminal products may be automated teller machines (ATMs), electronic devices for self-service transactions, etc.

[0049] like Figure 1 As shown, the display module 1000 may include a display panel 400 , a power supply 200 , a display driver chip 1000 and a flexible cable 300 , the display panel 400 and the display driver chip 1000 are connected via the flexible cable 300 , and the power supply 200 is connected to the display driver chip 1000 .

[0050] like Figure 2 As shown, the display panel 400 may include a plurality of pixel capacitors C arranged in a rectangular array, each pixel capacitor C corresponds to each pixel point on the display panel 400, and after the pixel capacitor C is charged, the corresponding pixel point will light up.

[0051] like Figure 2 As shown, the display driver chip 1000 may include a power conversion circuit 10, a reference voltage generating circuit 20, a timing control circuit 30, a gate driving circuit 40 and a source driving circuit 50. Among them, the input end of the power conversion circuit 10 may be connected to the external power supply 200, the output end of the power conversion circuit 10 may be connected to the input end of the reference voltage generating circuit 20, and the output end of the power conversion circuit 10 may also be respectively connected to the power supply end of the gate driving circuit 40, the power supply end of the timing control circuit 30 and the power supply end of the source driving circuit 50. The external power supply 200 may provide the original voltage to the power conversion circuit 10, and the power conversion circuit 10 may convert the received original voltage into voltages of different specifications and provide them to the reference voltage generating circuit 20, the timing control circuit 30, the gate driving circuit 40 and the source driving circuit 50 respectively.

[0052] like Figure 2 As shown, the output end of the timing control circuit 30 is also connected to the input end of the gate driving circuit 40, and the timing control circuit 30 is used to receive the display data signal, generate a first timing signal according to the display data signal, and send the first timing signal to the gate driving circuit 40. After receiving the first timing signal, the gate driving circuit 40 can generate a gate driving signal and send the gate driving signal to the display panel 400, so as to select a certain pixel capacitor C from the multiple pixel capacitors C of the display panel 400 as the pixel capacitor C that currently needs to be charged.

[0053] like Figure 2 As shown, the output end of the timing control circuit 30 is also connected to the input end of the source driving circuit 50. The timing control circuit 30 is used to receive the display data signal, generate a second timing signal according to the display data signal, and send the second timing signal to the source driving circuit 50. The second timing signal can be a digital signal. After receiving the second timing signal, the source driving circuit 50 can convert the second timing signal into a voltage signal and send the voltage signal to the display panel 400. The voltage signal can be charged to the pixel capacitor C selected by the gate driving signal, thereby charging the pixel capacitor C, and the pixel point corresponding to the C pixel capacitor is lit.

[0054] The larger the area of ​​the display panel 400, the longer the wiring length of the source driving circuit 50, and the larger the parasitic capacitance generated. In applications with high resolution (more pixels) and high refresh rate (each pixel switches brightness at a higher frequency), the charging time of the pixels is continuously compressed. In other words, the display driver chip 1000 is required to charge the pixel capacitor C in the display panel 400 faster.

[0055] against Figure 2The voltage of any pixel capacitor C shown in FIG. 1 determines the brightness of the corresponding pixel. In order to make the brightness control of the pixel more accurate and the display screen more delicate and accurate, the voltage is required to be divided into more gears. Here, an 8-bit binary digital signal is taken as an example, and correspondingly, the voltage is divided into 256 gears. In the display driver chip 1000, if the 8-bit digital-to-analog conversion is directly implemented, the design difficulty is large and the number of switches is large, which consumes chip area resources. Therefore, in the related art, interpolation technology is usually used. For example, a 6-bit DAC is first used to generate 64 non-interpolation step voltages, and then a 2-bit interpolation DAC is used to uniformly insert 3 interpolation step voltages between two adjacent non-interpolation step voltages, thereby realizing the conversion of 8-bit data through a 6-bit DAC and a 2-bit DAC. Moreover, the voltage of multiple gears, a part of which is a non-interpolation step voltage, and the other part of which is an interpolation step voltage, and a plurality of interpolation step voltages are uniformly inserted between each two adjacent non-interpolation step voltages. The structures of the 6-bit DAC and the 2-bit DAC are relatively simple and require fewer components, thus saving chip area.

[0056] Taking the voltages of the pixel capacitor C as 127 and 126 respectively as an example, the charging effect of the pixel capacitor C is analyzed. Among them, the voltage 127 is a non-interpolation step voltage, and the voltage 126 is an interpolation step voltage. In theory, the voltage 127 should be higher than the voltage 126. Figure 3 shows the non-interpolated step voltage 127 for Figure 2 The voltage variation curve (curve a) of the pixel capacitor C during the charging process and the interpolation step voltage 126 are shown in FIG. Figure 2 The voltage variation curve (curve b) of the pixel capacitor C during charging is shown. Figure 3 As can be seen from the figure, charging starts at the rising edge. If the charging result is pushed out to Figure 2 As shown in the pixel capacitor C, at this time, the pixel capacitor C corresponding to the voltage 127 has not been fully charged, and the voltage is lower than 126, which will cause brightness inversion and dark stripes will appear on the display panel 400.

[0057] Based on this, an embodiment of the present application provides a display driving circuit, which can be Figure 2 The source driving circuit 50 shown in FIG. Figure 4 As shown, the display driving circuit may include a first DAC51, a second DAC52, a buffer 53 and a driving enhancement circuit 54. The output end of the first DAC51 is connected to the input end of the second DAC52, the output end of the second DAC52 is connected to the input end of the buffer 53, and the output end of the driving enhancement circuit 54 is also connected to the output end of the second DAC52.

[0058] In this embodiment, the first DAC51 can be connected with Figure 2The timing control circuit 30 shown is connected to receive a first digital signal, which may be Figure 2 The high-order digits in the timing signal sent by the timing control circuit 30 shown, that is, the number of digits of the first digital signal is less than the number of digits of the timing signal. Exemplarily, when the number of digits of the timing signal is 8, the number of digits of the first digital signal can be 4, 5, 6 or 7, etc. Below, the number of digits of the first digital signal is 6. Then, the first digital signal can be the high 6-bit digital signal in the timing signal. Exemplarily, when the timing signal is 1111100 (the corresponding voltage is 124), the timing signal is 1111101 (the corresponding voltage is 125), the timing signal is 1111110 (the corresponding voltage is 126), and the timing signal is 1111111 (the corresponding voltage is 127), the first digital signal is 111111.

[0059] The first DAC51 performs digital-to-analog conversion on the first digital signal to obtain and output a first voltage signal, and the first voltage signal may include two sub-voltage signals. For ease of description, they are named as the first sub-voltage signal and the second sub-voltage signal respectively. The voltage of the first sub-voltage signal is obtained by subtracting 1 from the first digital signal and taking the high 6-bit digits, and determining the low 2-bit digits as 11; the voltage of the second sub-voltage signal can be obtained by taking the first digital signal as the high 6-bit digits and determining the low 2-bit digits as 11. Exemplarily, when the voltage corresponding to the timing signal is 124, 125, 126 and 127, the voltage of the first sub-voltage signal output by the first DAC51 is 123, and the voltage of the second sub-voltage signal is 127. The voltage of the first sub-voltage signal differs from that of the second sub-voltage signal by 4.

[0060] In the specific implementation, Figure 5 As shown, the first DAC51 may include a plurality of resistors R and a multiplexer Mux connected in series in sequence, and the first resistor R of the plurality of resistors R may be connected to Figure 2 In the power conversion circuit 10 shown, the last resistor R among the multiple resistors R can be grounded. The multiplexer Mux has multiple input terminals, which are respectively connected between every two resistors R. The multiplexers Mux connected to different positions can receive different voltages. The multiplexer Mux can be used to receive a first digital signal, and select the corresponding first sub-voltage signal and second sub-voltage signal according to the first digital signal, and output them from the output terminal of the multiplexer Mux.

[0061] like Figure 5 As shown, the second DAC52 can be used to receive a second digital signal, which can be Figure 2The lower digits of the timing signal sent by the timing control circuit 30 shown, and the sum of the number of digits of the second digital signal and the number of digits of the first digital signal can be the number of digits of the timing signal. For example, when the number of digits of the timing signal is 8 bits and the number of digits of the first digital signal is 5 bits, the number of digits of the second digital signal can be 3 bits; when the number of digits of the first digital signal is 6 bits, the number of digits of the second digital signal can be 2 bits; when the number of digits of the first digital signal is 7 bits, the number of digits of the second digital signal can be 1 bit. Below, the second digital signal is described as an example of 2 bits. Then, the second digital signal is the lower 2-bit digital signal in the timing signal output by the timing control circuit 30. For example, when the timing signal is 1111100, the second digital signal is 00.

[0062] When the timing signal is 1111100 (the corresponding voltage is 124), the voltage 124 can be calculated by 0.75×123+0.25×127, and 0.75 and 0.25 are weight coefficients. When the timing signal is 1111101 (the corresponding voltage is 125), the voltage 125 can be calculated by 0.5×123+0.5×127, and 0.5 and 0.5 are weight coefficients. When the timing signal is 1111110 (the corresponding voltage is 126), it can be calculated by 0.75×123+0.25×127, and 0.75 and 0.25 are weight coefficients. When the timing signal is 1111111 (the corresponding voltage is 127), it can be calculated by 0×123+1×127, and 0 and 1 are weight coefficients. It can be seen that when the lower 2 digits in the timing signal, that is, the second digital signal, are different, the corresponding weight coefficients are different. Therefore, the corresponding relationship between the second digital signal and the weight coefficient can be established in advance, and the second DAC52 can determine the weight coefficient according to the second digital signal after receiving the second digital signal. When the second digital signal is 00, the weight coefficient is determined to be 0.75 and 0.25. When the second digital signal is 01, the weight coefficient is determined to be 0.5 and 0.5. When the second digital signal is 10, the weight coefficient is determined to be 0.25 and 0.75. When the second digital signal is 11, the weight coefficient is determined to be 0 and 1.

[0063] The second DAC 52 can also receive the two first voltage signals sent by the first DAC 51, and divide the two first voltage signals into four second voltage signals according to the weight coefficient. Figure 1When the timing signal output by the timing control circuit 30 shown is 1111100 (the corresponding voltage is 124), the weight coefficients are 0.75 and 0.25, then among the four output second voltage signals, the voltages of three of the second voltage signals are the first sub-voltage, and the voltage of the other second voltage signal is the second sub-voltage. When the weight coefficients are 0.5 and 0.5, among the four output second voltage signals, the voltages of two of the second voltage signals are the first sub-voltage, and the voltages of the other two second voltage signals are the second sub-voltage; when the weight coefficients are 0.25 and 0.75, among the four output second voltage signals, the voltage of one of the second voltage signals is the first sub-voltage, and the voltages of the other three second voltage signals are the second sub-voltage; when the weight coefficients are 0 and 1, the voltages of the four output second voltage signals are all the first sub-voltage.

[0064] like Figure 4 As shown, the output end of the driving enhancement circuit 54 is connected to the output end of the second DAC 52, and the driving enhancement circuit 54 can be used to charge the output end of the second DAC 52. Since the output end of the second DAC 52 outputs multiple second voltage signals, the driving enhancement circuit 54 can perform voltage enhancement on each second voltage signal.

[0065] like Figure 5 As shown, the buffer 53 may include a differential circuit 531 and a power amplifier 532. The differential circuit 531 may include a plurality of differential pairs 5311. The number of the differential pairs 5311 is the same as the number of the second voltage signals output by the second DAC 52. Therefore, in this embodiment, Figure 4 As shown, the buffer 53 may include four differential pairs 5311. Each differential pair 5311 corresponds to one second voltage signal. When the voltage corresponding to the timing signal is 124, and the weight coefficients are 0.75 and 0.25, among the four second voltage signals, the voltages corresponding to three of the second voltage signals are the first sub-voltage, and the voltage corresponding to the other second voltage signal is the second sub-voltage, then three differential pairs 5311 are driven by the first sub-voltage, and one differential pair 5311 is driven by the second sub-voltage, that is, the four differential pairs 5311 are driven by the first sub-voltage and the second sub-voltage. Similarly, when the voltage corresponding to the timing signal is 125, the weight coefficients are 0.5 and 0.5, and when the voltage corresponding to the timing signal is 126, and the weight coefficients are 0.75 and 0.25, the four differential pairs 5311 are driven by the first sub-voltage and the second sub-voltage. When the voltage corresponding to the timing signal is 127 and the weight coefficient is 1 or 0, the voltages corresponding to the four output second voltage signals are all the first sub-voltage, and the four differential pairs 5311 are driven by the first sub-voltage. The four differential pairs 5311 can output a voltage signal to the power amplifier 532 for amplification and output a third voltage signal to Figure 1 The display panel 400 is shown.

[0066] The voltage of the third voltage signal corresponds to the timing signal, which can be the same as the second sub-voltage output by the first DAC51, or can be obtained by using the first sub-voltage and the second sub-voltage and their corresponding weight coefficients. Since the voltage corresponding to the timing signal is divided into 256 gears, the voltages of 64 gears are the same as the first sub-voltage or the second sub-voltage output by the first DAC51, and are not obtained by interpolation, these voltages can be called non-interpolation step voltages; the remaining voltages are obtained after interpolation, so they can also be called interpolation step voltages. Exemplarily, among the above four voltages 124, 125, 126 and 127, 124, 125 and 126 are all interpolation step voltages, and 127 is a non-interpolation step voltage.

[0067] For the non-interpolation voltage, four differential pairs 5311 need to be driven simultaneously, and for the interpolation voltage, it can be driven by two voltages together, so the interpolation voltage is charged faster than the non-interpolation voltage. Figure 3 As shown in the charging process diagram, the voltage 126 is charged faster than the voltage 127, so the voltage 126 is higher than the voltage 127, which causes Figure 2 Based on this, in this embodiment, the driving enhancement circuit 54 can charge the output terminal of the second DAC 52 when the voltage corresponding to the timing signal is a non-interpolation step voltage, thereby increasing the charging speed of the non-interpolation step voltage, thereby reducing the brightness inversion of the pixel capacitor, thereby reducing Figure 2 Dark stripes appear on the display panel 400, thereby achieving accurate display of the picture.

[0068] In this embodiment, if Figure 6a As shown, the driving enhancement circuit 54 includes a first capacitor C1, a first end of the first capacitor C1 is used to connect to the first power supply 11, and a second end of the first capacitor C1 is connected to the output end of the second DAC 52. The first power supply 11 can be Figure 1 The first capacitor C1 is charged under the control of the display module 1000 shown, that is, the potential of the first end of the first capacitor C1 is the same as the potential of the output end of the first power supply 11. Moreover, after the first power supply 11 charges the first capacitor C1 for a period of time, the potential of the second end of the first capacitor C1 is the same as the potential of the first end of the first capacitor C1. Since the second end of the first capacitor C1 is connected to the output end of the second DAC52, the potential of the output end of the second DAC52 is the same as the potential of the second end of the first capacitor C1, thereby realizing the first capacitor C1 charging the output end of the second DAC52. The drive enhancement circuit 54 is implemented by the first capacitor C1, which can make the structure of the solution simpler and easier to implement.

[0069] In addition, in this embodiment, the first capacitor C1 can be a common capacitor or a metal-oxide-semiconductor field-effect transistor (MOS) capacitor. When the first capacitor C1 is a MOS capacitor, it can save Figure 1 The area of ​​the display driver chip 1000 is shown.

[0070] In addition, when the potential of the output end of the second DAC 52 is the same as the potential of the second end of the first capacitor C1, and the first power supply 11 no longer charges the first capacitor C1, the potential of the output end of the second DAC 52 slowly decreases under the action of the first capacitor C1, and the voltage of the pixel capacitor C also slowly decreases. The specific change process is as follows: Figure 7 shown. Figure 7 The middle curve a1 represents the voltage variation curve during the process of charging the pixel capacitor C by the non-interpolation step voltage 127 in this embodiment, the curve a2 represents the voltage variation curve during the process of charging the pixel capacitor C by the non-interpolation step voltage 127 when the display driving circuit 50 does not include the driving enhancement circuit 54, and the curve b represents the voltage variation curve during the process of charging the pixel capacitor C by the interpolation step voltage 126 in this embodiment. Figure 7 It can be seen that the voltage of the pixel capacitor C also decreases slowly, and in this embodiment, the voltage of the pixel capacitor corresponding to the non-interpolation step voltage 127 is always higher than the voltage of the pixel capacitor corresponding to the interpolation step voltage 126. That is to say, in the process of charging the pixel capacitor, the current non-interpolation step voltage is always higher than the previous interpolation step voltage, so as to better avoid Figure 2 The brightness of the pixels on the display panel 400 is shown to be inverted.

[0071] In other embodiments of the present application, Figure 6b As shown, Figure 6a The difference between the embodiments shown is the number of capacitors. Specifically, the drive enhancement circuit 54 further includes a second capacitor C2 and a third capacitor C3, wherein the first end of the second capacitor C2 is connected to the second power supply 12, and the second end of the second capacitor C2 is connected to the output end of the second DAC 52. The first end of the third capacitor C3 is connected to the third power supply 13, and the second end of the third capacitor C3 is connected to the output end of the second DAC 52. Figure 4The voltage of the third voltage signal output by the buffer 53 shown may be one of a plurality of non-interpolation step voltages, and different non-interpolation step voltages have different magnitudes. In the present embodiment, the driving enhancement circuit 54 further includes a second capacitor C2 and a third capacitor C3, and the first end of the first capacitor C1 is connected to the first power supply 11, the first end of the second capacitor C2 is connected to the second power supply 12, and the first end of the third capacitor C3 is connected to the third power supply 13, that is, the first ends of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are respectively connected to different power supplies. Thus, the number of capacitors charged for the output end of the second DAC 52 can be controlled by each power supply, thereby controlling the degree of charging for the output end of the second DAC 52, and then achieving different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal output from the buffer 53 after charging is closer to the corresponding non-interpolation step voltage, thereby improving the control. Figure 2 The accuracy of brightness control of pixels of the display panel 400 is shown.

[0072] In specific implementation, Figure 1 The controller implementation in the display module 1000 shown is, for example, when one or several capacitors are required to charge the output end of the second DAC52, the corresponding one or more power supplies are controlled by the controller to start providing voltage to the corresponding capacitors. For example, when two capacitors are required to charge the output end of the second DAC52, the controller can send a control signal to the first power supply 11 and the second power supply 12, the first power supply 11 can receive the control signal, and start to provide voltage to the first capacitor C1, and the first capacitor C1 can charge the output end of the second DAC52. Similarly, the second power supply 12 can also receive the control signal and start to provide voltage to the second capacitor C2, and the second capacitor C2 can charge the output end of the second DAC52.

[0073] In other embodiments of the present application, Figure 8a As shown, Figure 6a The difference shown is that in Figure 6a A first capacitor state control circuit 541 is added on the basis of the embodiment shown. Specifically, the driving enhancement circuit 54 also includes a first capacitor state control circuit 541, an input end of the first capacitor state control circuit 541 is connected to the second end of the first capacitor C1, an output end of the first capacitor state control circuit 541 is connected to the output end of the second DAC52, and the first capacitor state control circuit 541 can be used to control whether the first capacitor C1 charges the output end of the second DAC52.

[0074] In a specific implementation, when the voltage corresponding to the timing signal is a non-interpolation voltage, the first capacitor state control circuit 541 controls the first capacitor C1 to charge the output end of the second DAC52; when the voltage corresponding to the timing signal is an interpolation voltage, the first capacitor state control circuit 541 controls the first capacitor C1 not to charge the output end of the second DAC52, thereby making the charging of the output end of the second DAC52 more accurate. Moreover, when the voltage corresponding to the timing signal is an interpolation voltage, the first power supply 11 can charge the first capacitor C1, and the first capacitor C1 does not need to charge the output end of the second DAC52; when the voltage corresponding to the timing signal is an interpolation voltage, the first power supply 11 has completed charging the first capacitor C1, and the first capacitor C1 can charge the output end of the second DAC52, thereby avoiding the extra occupation of clock cycles, thereby improving the control. Figure 2 The charging speed of the pixel capacitance C is shown.

[0075] Further, the first capacitor state control circuit 541 can receive the lower digital signals in the timing signal, and determine whether the corresponding voltage is an interpolation step voltage or a non-interpolation step voltage according to the lower digital signals, so that when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first capacitor C1 is controlled to charge to the output end of the second DAC52. When the voltage corresponding to the timing signal is an interpolation step voltage, the first capacitor C1 is controlled not to charge to the output end of the second DAC52, and the first power supply 11 can charge the first capacitor C1.

[0076] In other embodiments of the present application, Figure 8b As shown, Figure 8a The difference between the embodiments shown is that the drive enhancement circuit 54 is Figure 8a On the basis of the illustrated embodiment, a second capacitor C2, a third capacitor C3, a second capacitor state control circuit 542 and a third capacitor state control circuit 543 are added.

[0077] Specifically, Figure 8b As shown, the first end of the second capacitor C2 is used to be connected to the first power supply 11, the second end of the second capacitor C2 is connected to the input end of the second capacitor state control circuit 542, and the output end of the second capacitor state control circuit 542 is connected to the output end of the second DAC 52. In this way, the second capacitor state control circuit 542 can control whether the second capacitor C2 charges the output end of the second DAC 52.

[0078] like Figure 8bAs shown, the first end of the third capacitor C3 is used to be connected to the first power supply 11, the second end of the third capacitor C3 is connected to the input end of the third capacitor state control circuit 543, and the output end of the third capacitor state control circuit 543 is connected to the output end of the second DAC 52. In this way, the third capacitor state control circuit 543 can control whether the third capacitor C3 is charged to the output end of the second DAC 52. Therefore, in this embodiment, when the driving enhancement circuit 54 includes multiple capacitors, each capacitor state control circuit can control whether the corresponding capacitor is charged to the output end of the second DAC 52.

[0079] Based on this, Fig. 9 As shown, the first capacitor state control circuit 541 includes a first switch tube M1, a first electrode S1 of the first switch tube M1 is connected to the second end of the first capacitor C1, and a second electrode D1 of the first switch tube M1 is connected to the output end of the second DAC52. The control electrode G1 of the first switch tube M1 can be used to receive a low-bit digital signal in the timing signal. In one example, when the low-bit digital signal is 0, the first switch tube M1 is disconnected; when the low-bit digital signal is 1, the first switch tube M1 is closed. In another example, when the low-bit digital signal is 1, the first switch tube M1 is disconnected; when the low-bit digital signal is 0, the first switch tube M1 is closed. When the first switch tube M1 is closed, the first switch tube M1 can connect the second end of the first capacitor C1 to the output end of the second DAC52 and charge the output end of the second DAC52. This solution has a simple structure, is easy to implement, and is relatively reliable.

[0080] In some cases, the second DAC 52 may receive a multi-bit digital signal in the timing signal, and each switch tube may receive a single-bit digital signal. Therefore, in order to receive each digital signal in the multi-bit digital signal, in one embodiment, Fig. 9 As shown, the first capacitor state control circuit 541 may also include a second switch tube M2 and a third switch tube M3, the first electrode S2 of the second switch tube M2 is connected to the second electrode D1 of the first switch tube M1, the first electrode S3 of the third switch tube M3 is connected to the second electrode D2 of the second switch tube M2, and the second electrode D3 of the third switch tube M3 is connected to the output end of the second DAC52. In other words, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are connected in series in sequence. The control electrode G1 of the first switch tube M1, the control electrode G2 of the second switch tube M2 and the control electrode G3 of the third switch tube M3 can respectively receive one of the digital signals in the multi-bit digital signal, and when each digital signal is 1, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are all closed, thereby, the first capacitor C1 can charge the output end of the second DAC52.

[0081] In another embodiment, the second DAC52 can receive two digital signals in the timing signal, and the first capacitor state control circuit 541 may include two switches, namely the first switch M1 and the second switch M2, and the first electrode S2 of the second switch M2 is connected to the second electrode D1 of the first switch M1, and the second electrode D2 of the second switch M2 is connected to the output end of the second DAC52. Therefore, when the digital signals received by the control electrode G1 of the first switch M1 and the control electrode G2 of the second switch M2 are both 1, the first switch M1, the second switch M2 and the third switch M3 are all closed, so that the first capacitor C1 can charge the output end of the second DAC52.

[0082] It can be understood that in other embodiments, the second DAC52 can receive a four-bit digital signal in the timing signal, and the first capacitor state control circuit 541 can include four switching tubes; the second DAC52 can receive a five-bit digital signal in the timing signal, and the first capacitor state control circuit 541 can include five switching tubes; and so on.

[0083] In other embodiments of the present application, Fig.10 As shown, Figure 6b The difference between the illustrated embodiments is that the drive enhancement circuit 54 is Figure 6b A charging gear control circuit 544 is added on the basis of the illustrated embodiment. The second ends of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are all connected to the input end of the charging gear control circuit 544, and the output end of the charging gear control circuit 544 is connected to the output end of the second DAC52. The charging gear control circuit 544 is used to control the number of capacitors charged to the output end of the second DAC52. In other words, the charging gear control circuit 544 can control whether the first capacitor C1 charges the output end of the second DAC52, whether the second capacitor C2 charges the output end of the second DAC52, and whether the third capacitor C3 charges the output end of the second DAC52. The first capacitor C1, the second capacitor C2 and the third capacitor C3 can form a capacitor array. The more capacitors charged to the output end of the second DAC52, the greater the capacitance value of the capacitor array, the faster the voltage establishment speed of the output end of the second DAC52 and the higher the voltage. This makes it easy to select different numbers of capacitors to charge the output end of the second DAC 52 according to the size of the voltage corresponding to the timing signal, so as to control the degree of charging the output end of the second DAC 52, and then to achieve different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal output from the buffer 53 after charging is closer to the corresponding non-interpolation step voltage theoretical value, thereby improving the accuracy of brightness control of the pixel points of the display panel 400.

[0084] In a specific implementation, the received signal of the driving enhancement circuit 54 can be the same as the received signal of the first DAC51, for example, both are high-order digital signals of the timing signal. The driving enhancement circuit 54 can determine the number of capacitors charged to the output end of the second DAC52 based on the size relationship between the high-order digital signals.

[0085] like Fig.11 As shown, the charging gear control circuit 544 includes a fourth switch tube M4, a fifth switch tube M5 and a sixth switch tube M6. The first electrode S4 of the fourth switch tube M4 is connected to the second end of the first capacitor C1, and the second electrode D4 of the fourth switch tube M4 is connected to the output end of the second DAC52; the first electrode S5 of the fifth switch tube M5 is connected to the second end of the second capacitor C2, and the second electrode D5 of the fifth switch tube M5 is connected to the output end of the second DAC52; the first electrode S6 of the sixth switch tube M6 is connected to the second end of the third capacitor C3, and the second electrode D6 of the sixth switch tube M6 is connected to the output end of the second DAC52. That is, the fourth switch tube M4 controls whether the first capacitor C1 is charged to the output end of the second DAC52, the fifth switch tube M5 controls whether the second capacitor C2 is charged to the output end of the second DAC52, and the sixth switch tube M6 controls whether the third capacitor C3 is charged to the output end of the second DAC52. For example, when the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 are all closed, the first capacitor C1, the second capacitor C2 and the third capacitor C3 can all be charged to the output end of the second DAC52, that is, the number of capacitors charged to the output end of the second DAC52 is three; when two of the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 are closed, the number of capacitors charged to the output end of the second DAC52 is two; when one of the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 is closed, the number of capacitors charged to the output end of the second DAC52 is one.

[0086] In a specific implementation, the control electrodes of the fourth switch tube M4, the fifth switch tube M5, and the sixth switch tube M6 can respectively receive three of the higher digital signals. When the digital signal received by the fourth switch tube M4 is 1, it is closed; when the received digital signal is 0, it is disconnected, so that the first capacitor C1 can charge the output end of the second DAC52. Similarly, when the fifth switch tube M5 is closed, the second capacitor C2 can charge the output end of the second DAC52. When the sixth switch tube M6 is closed, the third capacitor C3 can charge the output end of the second DAC52.

[0087] It can be understood that the number of capacitors in the driving enhancement circuit 54 can be the same as the number of bits of the upper digital signals in the timing signal received by the first DAC51. For example, when the first DAC51 receives the upper 6-bit digital signal, the driving enhancement circuit 54 can include 6 capacitors. Correspondingly, the number of switch tubes in the charging gear control circuit 544 can also be the same as the number of bits of the upper digital signals in the timing signal received by the first DAC51, that is, also 6. In this way, the charging degree of the output end of the second DAC52 by the driving enhancement circuit 54 can be more accurately controlled.

[0088] It is understandable that in the embodiment of the present application, the first electrode of each switch tube may be a source electrode, and the second electrode of each switch tube may be a drain electrode. In other embodiments, the first electrode of each switch tube may be a drain electrode, and the second electrode of each switch tube may be a source electrode.

[0089] exist Figure 8b and Fig. 9 In the embodiment shown, the driving enhancement circuit 54 includes a first capacitance state control circuit 541, a second capacitance state control circuit 542 and a third capacitance state control circuit 543, but does not include a charging gear control circuit 544; Fig.10 and Fig.11 In the embodiment shown, the driving enhancement circuit 54 includes a charging gear control circuit 544, but does not include a first capacitor state control circuit 541, a second capacitor state control circuit 542, and a third capacitor state control circuit 543. In other embodiments of the present application, such as Fig.12 As shown, the driving enhancement circuit 54 may include a first capacitor state control circuit 541, a second capacitor state control circuit 542, a third capacitor state control circuit 543 and a charging gear control circuit 544. Among them, the first pole S4 of the fourth switch tube M4 in the charging gear control circuit 544 is connected to the second end of the first capacitor C1, the second pole D4 of the fourth switch tube M4 is connected to the first pole S1 of the first switch tube M1 in the first capacitor state control circuit 541, and the second pole D3 of the switch tube M3 is connected to the output end of the second DAC52. The first pole S5 of the fifth switch tube M5 in the charging gear control circuit 544 is connected to the second end of the second capacitor C2, the second pole D5 of the fifth switch tube M5 is connected to the first pole S1 of the first switch tube M1 in the second capacitor state control circuit 542, and the second pole D3 of the switch tube M3 in the second capacitor state control circuit 542 is connected to the output end of the second DAC52. The first electrode S6 of the sixth switch tube M6 in the charging gear control circuit 544 is connected to the second end of the first capacitor C1, the second electrode D6 of the sixth switch tube M6 is connected to the first electrode S1 of the first switch tube M1 in the third capacitor state control circuit 543, and the second electrode D3 of the switch tube M3 in the third capacitor state control circuit 543 is connected to the output end of the second DAC52.

[0090] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A display driving circuit, characterized in that: include: a first digital-to-analog converter DAC, a second DAC, a drive enhancement circuit, and a buffer; The first DAC is used to receive a first digital signal and perform digital-to-analog conversion on the first digital signal; The second DAC, whose input end is connected to the output end of the first DAC, is used to receive a second digital signal and perform analog-to-digital conversion on the second digital signal; The buffer is used to output a voltage signal, and the input end of the buffer is connected to the output end of the second DAC; The driving enhancement circuit has an output end connected to the output end of the second DAC and is used to charge the output end of the second DAC.

2. The display driving circuit according to claim 1, characterized in that: The driving enhancement circuit includes a first capacitor, a first end of the first capacitor is used to be connected to a first power supply, and a second end of the first capacitor is connected to an output end of the second DAC.

3. The display driving circuit according to claim 2, characterized in that: The driving enhancement circuit further includes a second capacitor and a third capacitor, wherein a first end of the second capacitor is used to be connected to a second power supply, and a second end of the second capacitor is connected to an output end of the second DAC; The first end of the third capacitor is used to be connected to a third power supply, and the second end of the third capacitor is connected to the output end of the second DAC.

4. The display driving circuit according to claim 2, characterized in that: The drive enhancement circuit also includes a first capacitor state control circuit, the input end of the first capacitor state control circuit is connected to the second end of the first capacitor, the output end of the first capacitor state control circuit is connected to the output end of the second DAC, and the first capacitor state control circuit is used to control whether the first capacitor charges the output end of the second DAC.

5. The display driving circuit according to claim 4, characterized in that: The driving enhancement circuit further includes a second capacitor and a third capacitor, wherein a first end of the second capacitor is used to be connected to the first power supply, and a first end of the third capacitor is used to be connected to the first power supply; The driving enhancement circuit further includes a second capacitance state control circuit and a third capacitance state control circuit, the input end of the second capacitance state control circuit is connected to the second end of the second capacitor, and the output end of the second capacitance state control circuit is connected to the output end of the second DAC; An input end of the third capacitor state control circuit is connected to the second end of the third capacitor, and an output end of the third capacitor state control circuit is connected to the output end of the second DAC.

6. The display driving circuit according to claim 4 or 5, characterized in that: The capacitor state control circuit includes a first switch tube, a first electrode of the first switch tube is connected to the second end of the capacitor, and a second electrode of the first switch tube is connected to the output end of the second DAC.

7. The display driving circuit according to claim 6, characterized in that: The capacitor state control circuit includes a second switch tube and a third switch tube, the first electrode of the second switch tube is connected to the second electrode of the first switch tube, the first electrode of the third switch tube is connected to the second electrode of the second switch tube, and the second electrode of the third switch tube is connected to the output end of the second DAC.

8. The display driving circuit according to any one of claims 2 or 4 to 7, characterized in that: The driving enhancement circuit further includes a second capacitor and a third capacitor, wherein a first end of the second capacitor is used to be connected to the first power supply, and a second end of the third capacitor is used to be connected to the first power supply; The drive enhancement circuit also includes a charging gear control circuit, the second ends of the first capacitor, the second capacitor and the third capacitor are all connected to the input end of the charging gear control circuit, the output end of the charging gear control circuit is connected to the output end of the second DAC, and the charging gear control circuit is used to control the number of the capacitors charged to the output end of the second DAC.

9. The display driving circuit according to claim 8, characterized in that: The charging gear control circuit includes a fourth switch tube, a fifth switch tube and a sixth switch tube, a first electrode of the fourth switch tube is connected to the second end of the first capacitor, and a second electrode of the fourth switch tube is connected to the output end of the second DAC; A first electrode of the fifth switch tube is connected to the second end of the second capacitor, and a second electrode of the fifth switch tube is connected to the output end of the second DAC; A first electrode of the sixth switch tube is connected to the second end of the third capacitor, and a second electrode of the sixth switch tube is connected to the output end of the second DAC.

10. A display driver chip, characterized in that: It comprises a timing control circuit and the display driving circuit according to any one of claims 1 to 9, wherein the timing control circuit is electrically connected to the display driving circuit.

11. A display module, characterized in that: It comprises a display panel and the display driver chip according to claim 10, wherein the display panel is electrically connected to the display driver chip.

12. An electronic device, characterized in that: The invention comprises a controller and the display module according to claim 11, wherein the controller is electrically connected to the display module.

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