Pixel driving circuit and display

Abstract

The invention provides a pixel driving circuit and a display. The pixel driving circuit comprises a multi-stage data driving circuit. The multi-stage data driving circuit is arranged in the non-display area. The nth-stage data driving circuit comprises a horizontal shift register and a multi-stage data processing circuit. The horizontal shift register is split into a plurality of horizontal shift register blocks based on a preset number. The multi-stage data processing circuit is split into a plurality of data processing circuit blocks based on a preset number. Each horizontal shift register block is coupled to a corresponding one of the plurality of data processing circuit blocks, and is disposed on each of a plurality of sides of the non-display area, so as to reduce the circuit area of the multi-stage data driving circuit in the non-display area.

Description

Technical Field

[0001] The invention relates to an electronic circuit, and in particular to a pixel driving circuit and a display. Background Art

[0002] The display can realize the display function by driving a plurality of pixel circuits in the display area through a pixel driving circuit. Generally speaking, each level of data driving circuit (or source driving circuit) in the pixel driving circuit is coupled to a plurality of pixel circuits in the same row to provide corresponding display data.

[0003] For a non-rectangular display area, the multi-level data driving circuits are arranged in sequence in the non-display area based on the outer frame of the display area. However, in the arrangement direction (e.g., the horizontal direction), the moving spacing between these data driving circuits is limited by the spacing between the multiple pixel circuits corresponding to the data driving circuits at each level. In this way, in the non-display area, the circuit area required for the multi-level data driving circuit increases, and the blank layout area between the multi-level data driving circuit and the display area also increases, and thus it cannot be applied to a display with a slim border. Summary of the invention

[0004] An embodiment of the present invention provides a pixel driving circuit suitable for a display and capable of reducing the circuit area of ​​a multi-level data driving circuit in a non-display area.

[0005] The pixel driving circuit of the embodiment of the present invention includes a multi-level data driving circuit. The multi-level data driving circuit is arranged in the non-display area of ​​the display. The n-th level data driving circuit in the multi-level data driving circuit includes a horizontal shift register and a multi-level data processing circuit. The horizontal shift register is divided into a plurality of horizontal shift register blocks based on a preset number. The multi-level data processing circuit is divided into a plurality of data processing circuit blocks based on a preset number. Each horizontal shift register block is coupled to a corresponding one of the plurality of data processing circuit blocks and is arranged on each of the plurality of sides of the non-display area. n is a positive integer.

[0006] Another embodiment of the present invention provides a display. The display includes a pixel array and the above-mentioned pixel driving circuit. The pixel array is arranged in a display area. The pixel driving circuit is coupled to the pixel array. The pixel driving circuit is arranged in a non-display area adjacent to the display area and is used to drive the pixel array.

[0007] Based on the above, the pixel driving circuit and the display of the embodiment of the present invention can arrange the data driving circuits in sequence based on the spacing between the multiple pixels corresponding to the aforementioned blocks by dividing the multiple circuit elements in the data driving circuits of each level into corresponding multiple blocks based on a preset number. In this way, the pixel driving circuit can reduce the arrangement spacing between the multi-level data driving circuits, thereby reducing the circuit area of ​​these data driving circuits in the non-display area, so as to be applied in a display with a narrow frame.

[0008] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a block diagram of a display according to an embodiment of the present invention.

[0010] Figure 1B According to the present invention Figure 1A A block diagram of a pixel driving circuit shown in an embodiment.

[0011] Figure 2 is a block diagram of a pixel driving circuit according to another embodiment of the present invention.

[0012] Figure 3 According to the present invention Figure 2 A circuit diagram of a horizontal shift register in an n-th stage data driving circuit shown in an embodiment.

[0013] Figure 4 According to the present invention Figure 2 A circuit diagram of a horizontal shift register in an n-th stage data driving circuit shown in an embodiment.

[0014] Figure 5 is a schematic diagram of a display according to an embodiment of the present invention.

[0015] Description of reference numerals:

[0016] 10, 50: Display

[0017] 10a, 20a, 50a: Pixel driving circuit

[0018] 10b: Pixel Array

[0019] 100_1~100_N1, 200: data drive circuit

[0020] 110, 210, 310, 410: Horizontal shift register

[0021] 110_R1~110_RN3, 210_R1~210_R4, 310_R1~310_R4, 410_R1~410_R8: horizontal shift register block

[0022] 120_1~120_N2, 220_1~220_8: data processing circuit

[0023] 120_R1~120_RN4, 220_R1~220_R4: Data processing circuit block

[0024] 230_1~230_4: Gate drive circuit

[0025] 311-314, 314a-314b, 411-415: Buffer

[0026] A1: Non-display area

[0027] AA: Display area

[0028] CK: clock signal

[0029] D1: First distance

[0030] D2: Second distance

[0031] DLH[n]: control signal

[0032] GL1~GL4: Gate lines

[0033] GLD[n]: gate control signal

[0034] HSR[n]: control signal

[0035] HSR[n+1]: post-stage control signal

[0036] HSR[n-1]: front stage control signal

[0037] HSR_R1~HSR_R4、HSR_R1~HSR_R8:Partial circuit

[0038] INV1~INV2: Buffer

[0039] LG1: NAND gate

[0040] LG2: Anti-OR gate

[0041] SB1~SB2, SB1~SB4: Side

[0042] SCS: reverse control signal

[0043] SW1~SW4:Switch

[0044] X: First direction

[0045] XCK: reverse clock signal

[0046] Y: Second direction DETAILED DESCRIPTION

[0047] Some embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples within the scope of the patent application of the present invention.

[0048] Figure 1A is a block diagram of a display according to an embodiment of the present invention. Figure 1A The display 10 may be, for example, a liquid crystal display (LCD), a light-emitting diode (LED), an organic light-emitting diode (OLED), or the like, which provides a display function. The display 10 includes a pixel driving circuit 10a and a pixel array 10b. The pixel driving circuit 10a is coupled to the pixel array 10b and is used to drive the pixel array 10b.

[0049] In the present embodiment, the pixel driving circuit 10a is disposed in the non-display area A1 of the display 10. The pixel array 10b is disposed in the display area AA of the display. The display area AA is a non-rectangular polygon, and may be, for example, a polygon close to a circle. The non-display area A1 is adjacent to the display area AA of the display 10. The non-display area A1 has a plurality of side edges (for example, the side edges SB1-SB2). These side edges are adjacent to (or overlap with) the plurality of side edges corresponding to the display area AA.

[0050] For reference Figure 1B , Figure 1B According to the present invention Figure 1A Block diagram of a pixel driving circuit shown in the embodiment. The pixel driving circuit 10a includes a multi-level data driving circuit 100_1 to 100_N1, where N1 is a positive integer greater than 1. These data driving circuits 100_1 to 100_N1 are arranged in the non-display area A1 and are used to drive the corresponding plurality of pixel circuits in the pixel array 10b. In this embodiment, the data driving circuit can also be referred to as a source driving circuit. The multi-level data driving circuits 100_1 to 100_N1 have the same circuit architecture.

[0051] In this embodiment, the n-th stage data driving circuit 100_1 among the multi-stage data driving circuits 100_1 ˜ 100_N1 includes a horizontal shift register (HSR) 110 and multi-stage data processing circuits 120_1 ˜ 120_N2 , wherein n is a positive integer, and N2 is a positive integer greater than 1.

[0052] In this embodiment, the horizontal shift register 110 is coupled to the multi-level data processing circuits 120_1 to 120_N2. The horizontal shift register 110 is used to temporarily store the corresponding display data in the pixel array 10b and provide the aforementioned display data to the corresponding multi-level data processing circuits 120_1 to 120_N2.

[0053] In this embodiment, the multi-stage data processing circuits 120_1-120_N2 are coupled to a plurality of pixel circuits in the pixel array 10b. These pixel circuits are arranged in a plurality of consecutive rows and a plurality of consecutive columns. Each data processing circuit 120_1-120_N2 is used to temporarily store the display data temporarily stored in the horizontal shift register 110. Each data processing circuit 120_1-120_N2 is coupled to a plurality of pixel circuits arranged in the corresponding same row, and is also used to provide display data to the corresponding plurality of pixel circuits.

[0054] In the present embodiment, the horizontal shift register 110 is divided into a plurality of horizontal shift register blocks 110_R1-110_RN3 based on a preset number, wherein RN3 is a positive integer greater than 1. In addition, the multi-stage data processing circuits 120_1-120_N2 are divided into a plurality of data processing circuit blocks 120_R1-120_RN4 based on a preset number, wherein RN4 is a positive integer greater than 1 and may be the same as RN3. Each horizontal shift register block 110_R1-110_RN3 is coupled to a corresponding one of the data processing circuit blocks 120_R1-120_RN4. Each horizontal shift register block 110_R1-110_RN3 is disposed on each of a plurality of side edges of the non-display area A1.

[0055] For example, the horizontal shift register block 110_R1 is coupled to the corresponding data processing circuit block 120_R1 and is disposed on the side SB1 of the non-display area A1. The horizontal shift register block 110_RN3 is coupled to the corresponding data processing circuit block 120_RN4 and is disposed on another side (not shown) of the non-display area A1.

[0056] In this embodiment, the preset number can be set to various numbers based on the design requirements of the display 10. For example, when the narrow frame applied to the display 10 is narrower, the preset number has a larger value.

[0057] That is, based on the preset number, the horizontal shift register 110 is divided into different circuit blocks 110_R1-10_RN3, and the multi-stage data processing circuits 120_1-120_N2 are re-divided into a plurality of circuit blocks 120_R1-120_RN4. These different circuit blocks 110_R1-10_RN3 and the coupled circuit blocks 120_R1-120_RN4 are respectively arranged on different sides of the non-display area A1 in sequence.

[0058] It is worth mentioning that, based on the preset number, the horizontal shift register 110 and the multi-stage data processing circuits 120_1 to 120_N2 are respectively divided into corresponding circuit blocks 110_R1 to 110_RN3 and 120_R1 to 120_RN4, so that the circuit blocks 110_R1 and 120_R2 can be arranged as a group of arrangement units on the corresponding single side SB1, and so on.

[0059] Therefore, the pixel driving circuit 10a can reduce the arrangement spacing between the multi-level data driving circuits 100_1 to 100_N1. The aforementioned arrangement spacing can be, for example, reduced to a multiple of the aforementioned arrangement unit (for example, the spacing between the circuit blocks 110_R1 and 120_R1 and the circuit blocks 110_R2 and 120_R2). In this way, the pixel driving circuit 10a can reduce the circuit area of ​​the multi-level data driving circuits 100 to 100_N1 in the non-display area A1, and at the same time reduce the blank layout area between the multi-level data driving circuits 100_1 to 100_N1 and the display area AA, thereby realizing the application of a narrow frame.

[0060] Figure 2 is a block diagram of a pixel driving circuit according to another embodiment of the present invention. Figure 2 , the pixel driving circuit 20a includes a multi-stage data driving circuit, wherein the n-th stage data driving circuit 200 includes a horizontal shift register 210 and a multi-stage data processing circuit 220_1-220_8. The number of these data processing circuits 220_1-220_8 is for example. The horizontal shift register 210 and the multi-stage data processing circuit 220_1-220_8 can refer to the relevant description of the n-th stage data driving circuit 100 and be analogous.

[0061] In this embodiment, the horizontal shift register 210 is used to output the multi-stage control signal HSR[n] to the multi-stage data processing circuits 220_1 ˜ 220_8 .

[0062] In the present embodiment, the multi-level data processing circuits 220_1 to 220_8 are controlled by the multi-level control signal HSR[n] to temporarily store the identification signal (SID signal) stage by stage according to the multi-level control signal HSR[n], and output the temporarily stored SID signal to the corresponding plurality of pixel circuits according to the multi-level control signal (including the control signal DLH[n]). In the present embodiment, the data processing circuits 220_1 to 220_8 of each level can be implemented by a data latch, for example.

[0063] exist Figure 2 In an embodiment, the pixel driving circuit 20a further includes a multi-stage gate driving circuit (e.g., a multi-stage gate driving circuit 230_1-230_4). The multi-stage gate driving circuit 230_1-230_4 is coupled to a multi-stage data driving circuit (including the n-th stage data driving circuit 200) in the pixel driving circuit 20a. Based on multiple sides (e.g., sides SB1-SB4) of the non-display area A1, these gate driving circuits 230_1-230_4 are arranged in sequence to be disposed in the non-display area A1. Each gate driving circuit 230_1-230_4 is used to control whether a plurality of gate lines GL1-GL4 are turned on or off according to a corresponding gate control signal GLD[n]. These gate lines GL1-GL4 are also coupled to corresponding multiple pixel circuits in the pixel array 10b.

[0064] In this embodiment, the preset number for splitting each level of data driving circuit is greater than 1. In addition, the preset number is the number (e.g., 4) of the multi-stage gate driving circuits 230_1 to 230_4 coupled to the n-th level data driving circuit 200. That is, based on design requirements, each level of data driving circuit (e.g., the n-th level data driving circuit 200) is configured to couple 4 multi-stage gate driving circuits 230_1 to 230_4.

[0065] Under this design requirement, based on a preset number (e.g., 4), the horizontal shift register 210 and the multi-stage data processing circuits 220_1-220_8 in the n-th stage data driving circuit 200 are respectively divided into corresponding multiple circuit blocks (i.e., "HSR_R1" to "HSR_R4") 210_R1-210_R4 and multiple circuit blocks (i.e., "DLH_R1" to "DLH_R4") 220_R1-220_R4. In this way, the multi-stage gate driving circuits 230_1-230_4 and the corresponding circuit blocks 210_R1-210_R4 and 220_R1-220_R4 are sequentially arranged on multiple side edges SB1-SB4 in the non-display area A1.

[0066] Specifically, based on a predetermined number (eg, 4), the horizontal shift register 210 is divided into a plurality of horizontal shift register blocks 210_R1 ˜ 210_R4 , and the multi-stage data processing circuits 220_1 ˜ 220_8 are divided into a plurality of data processing circuit blocks 220_R1 ˜ 220_R4 .

[0067] It should be noted that each data processing circuit block 220_R1-220_R4 has m of the multi-stage data processing circuits 220_1-220_8. m is a positive integer and is less than the total number of the multi-stage data processing circuits 220_1-220_8 (i.e., 8). In other words, the multi-stage data processing circuits 220_1-220_8 are evenly divided into a plurality of circuit blocks 220_R1-220_R4, wherein these circuit blocks 220_R1-220_R4 have the same circuit architecture (e.g., m parallel data processing circuits).

[0068] exist Figure 2 In the embodiment, m may be, for example, 2. Based on a preset number (e.g., 4), the multi-stage data processing circuits 220_1-220_8 are divided into 4 circuit blocks 220_R1-220_R4. That is, each circuit block 220_R1-220_R4 has 2 of the multi-stage data processing circuits 220_1-220_8. For example, the data processing circuit block 220_R1 has 2 data processing circuits 220_1-220_2, and the data processing circuit block 220_R2 has 2 data processing circuits 220_3-220_4, and so on.

[0069] That is, for the n-th stage data driving circuit 200, each quarter portion of the horizontal shift register 210 (e.g., circuit block 210_R1) is configured to connect corresponding m data processing circuits (e.g., 2-stage data processing circuits 220_1-220_2) in series and are disposed together on the same side (e.g., side SB1).

[0070] In addition, in the non-display block A1, in the first direction X, the multi-stage data driving circuit (including the n-th stage data driving circuit 200) is arranged in a staircase shape. In detail, the horizontal shift register block 210_R1 and the corresponding data processing circuit block 220_R1 can be used as a group of arrangement units, and are arranged on the side SB1 together with the corresponding gate driving circuit 230_1. The arrangement unit has a first distance D1 in the first direction X, and a second distance D2 in the second direction X.

[0071] In the present embodiment, the first distance D1 is the layout length required for the data processing circuit block 220_R1 in the first direction X. Since the data processing circuit block 220_R1 includes m (e.g., 2) data processing circuits 220_1-220_2, the aforementioned layout length is the pitch of a plurality of pixel circuits arranged in m (e.g., 2) rows. That is, the first distance D1 may be, for example, the pixel pitch between m (e.g., 2) pixel circuits.

[0072] In addition, the second distance D2 is the layout height required for the horizontal shift register block 210_R1 in the second direction X. The second distance D2 may be, for example, a pixel pitch between m (eg, 2) pixel circuits.

[0073] It should be noted that since the horizontal shift register 210 and the multi-stage data processing circuits 220_1 to 220_8 are respectively divided into a plurality of circuit blocks 210_R1 to 210_R4 and 220_R1 to 220_R4, compared with the conventional layout, the arrangement unit of the n-th stage data driving circuit 200 in the first direction X can be reduced from the multiple of 8 pixel pitches required for the 8 data processing circuits 220_1 to 220_8 to the multiple of m (e.g., 2) pixel pitches.

[0074] For example, the horizontal shift register block 210_R2 and the corresponding data processing circuit block 220_R2 are shifted by one arrangement unit relative to the circuit blocks 210_R1 and 220_R1, so as to be disposed on the adjacent side SB1 together with the corresponding gate driving circuit 230_2. That is, relative to the circuit blocks 210_R1 and 220_R1, the circuit blocks 210_R2 and 220_R2 are shifted by a first distance D1 in the first direction X, and by a second distance D2 in the second direction X, and so on.

[0075] Figure 3 According to the present invention Figure 2 The circuit diagram of the horizontal shift register in the n-th stage data driving circuit shown in the embodiment. Figure 3 , the horizontal shift register 310 can be used in Figure 2 In the n-th stage data driving circuit 200. Based on a preset number (eg, 4), the horizontal shift register 310 is divided into a plurality of horizontal shift register blocks 310_R1 ˜ 310_R4.

[0076] exist Figure 3In the embodiment, the horizontal shift register 310 includes a first partial circuit HSR_R1, a second partial circuit HSR_R2, a third partial circuit HSR_R3 and a fourth partial circuit HSR_R4. The partial circuits HSR_R1-HSR_R4 belong to different horizontal shift register blocks 310_R1-310_R4.

[0077] In detail, the first partial circuit HSR_R1 includes a first buffer 311, a second buffer 312, a third buffer 313, a first switch SW1, a second switch SW2 and a third switch SW3. The input end of the first buffer 311 receives the previous stage control signal HSR[n-1]. The output end of the first buffer 311 is coupled to the input end of the second buffer 312. The second buffer 312 is also coupled to the first switch SW1 to be controlled by the first switch SW1 to operate. The first switch SW1 is implemented, for example, by an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The control end of the first switch SW1 receives the subsequent stage control signal HSR[n+1] to perform a switching operation according to the subsequent stage control signal HSR[n+1].

[0078] Continuing with the above description, the input end of the third buffer 313 is coupled to the output end of the second buffer 312. The third buffer 313 is also coupled to the second switch SW2 and the third switch SW3 to be controlled by these switches SW2-SW3 to operate. The second switch SW2 is implemented, for example, by a p-type Metal-Oxide-SemiconductorField-Effect Transistor (NMOSFET). The third switch SW3 is implemented, for example, by an NMOSFET. The control end of the second switch SW2 receives the subsequent control signal HSR[n+1] to perform a switching operation according to the subsequent control signal HSR[n+1]. The control end of the third switch SW3 is coupled to the output end of the first buffer 311 to perform a switching operation according to the output signal of the first buffer 311.

[0079] In this embodiment, the second partial circuit HSR_R2 includes a plurality of fourth buffers 314 and a fourth switch SW4. The fourth buffers 314 are connected in series. The fourth buffers 314 are coupled to the fourth switch SW4, the output end of the second buffer 312 and the output end of the third buffer 313 to be controlled by the fourth switch SW4 to operate.

[0080] Specifically, the plurality of fourth buffers 314 include buffers 314a and 314b. The input end of the buffer 314a is coupled to the output end of the second buffer 312, the input end of the third buffer 313, and the fourth switch SW4. The fourth switch SW4 is implemented, for example, by NMOSFET. The control end of the fourth switch SW4 receives the reverse control signal SCS to perform a switching operation according to the reverse control signal SCS. The input end of the buffer 314b is coupled to the output end of the buffer 314a and the output end of the third buffer 313.

[0081] In this embodiment, the third circuit HSR_R2 includes a plurality of logic gates LG1 ˜ LG2 . The logic gates LG1 ˜ LG2 are connected in series and are coupled to output terminals of the fourth buffers 314 .

[0082] Specifically, the plurality of logic gates LG1-LG2 include a NAND gate (NAND) LG1 and a NOR gate (NOR) LG2. A first input terminal of the NAND gate LG1 receives a clock signal CK. A second input terminal of the NAND gate LG1 is coupled to output terminals of the plurality of fourth buffers 314. A first input terminal of the NOR gate LG2 receives an inverted clock signal XCK. A second input terminal of the NOR gate LG2 is coupled to an output terminal of the NAND gate LG1. An output terminal of the NOR gate LG2 is coupled to an input terminal of the fourth partial circuit HSR_R2.

[0083] In this embodiment, the fourth circuit HSR_R2 includes a plurality of fifth buffers INV1 ˜ INV2 . The fifth buffers INV1 ˜ INV2 are implemented by inverters, for example. The fifth buffers INV1 ˜ INV2 are connected in series. The fifth buffers INV1 ˜ INV2 are coupled to output ends of the plurality of logic gates LG1 ˜ LG2 .

[0084] Specifically, the plurality of fifth buffers INV1-INV2 include buffers INV1 and INV2. The input of buffer INV1 is coupled to the output of NOR gate LG2. The output of buffer INV1 is coupled to the input of buffer INV2. The output of buffer INV2 provides control signal HSR[n] to multi-stage data processing circuits 220_1-220_8.

[0085] Figure 4 According to the present invention Figure 2 The circuit diagram of the horizontal shift register in the n-th stage data driving circuit shown in the embodiment. Figure 4 , the horizontal shift register 410 can be used in Figure 2In the n-th stage data driving circuit 200. Based on a preset number (e.g., 8), the horizontal shift register 410 is divided into a plurality of horizontal shift register blocks 410_R1-410_R8. Correspondingly, based on a preset number (e.g., 8), the multi-stage data processing circuits 220_1-220_8 in the n-th stage data driving circuit 200 are divided into 8 data processing circuit blocks. That is, each data processing circuit block has m (e.g., 1) of the multi-stage data processing circuits 220_1-220_8.

[0086] It should be noted that since the horizontal shift register 210 and the multi-stage data processing circuits 220_1 to 220_8 are respectively divided into eight horizontal shift register blocks 210_R1 to 210_R8 and eight data processing circuit blocks, compared with the conventional layout, the arrangement unit of the n-th stage data driving circuit 200 in the first direction X can be reduced from eight pixel pitches required by the eight data processing circuits 220_1 to 220_8 to m (e.g., one) pixel pitches.

[0087] exist Figure 4 In the embodiment, the horizontal shift register 410 includes a first circuit HSR_R1, a second circuit HSR_R2, a third circuit HSR_R3, a fourth circuit HSR_R4, a fifth circuit HSR_R5, a sixth circuit HSR_R6, a seventh circuit HSR_R7 and an eighth circuit HSR_R8. The circuits HSR_R1 to HSR_R8 belong to different horizontal shift register blocks 410_R1 to 410_R8. Figure 3 The horizontal shift register 310 has the same circuit structure.

[0088] In detail, the first partial circuit HSR_R1 includes a first buffer 411, a second buffer 412 and a first switch SW1. The input end of the first buffer 411 receives the previous stage control signal HSR[n-1]. The output end of the first buffer 411 is coupled to the input end of the second buffer 312. The second buffer 412 is also coupled to the first switch SW1. The control end of the first switch SW1 receives the next stage control signal HSR[n+1].

[0089] In this embodiment, the second partial circuit HSR_R2 includes a third buffer 413, a second switch SW2, and a third switch SW3. The input end of the third buffer 413 is coupled to the output end of the second buffer 412. The third buffer 413 is also coupled to the second switch SW2 and the third switch SW3. The control end of the second switch SW2 receives the subsequent control signal HSR[n+1]. The control end of the third switch SW3 is coupled to the output end of the first buffer 411.

[0090] In this embodiment, the third circuit HSR_R3 includes a fourth buffer 414 and a fourth switch SW4. The input terminal of the fourth buffer 414 is coupled to the output terminal of the second buffer 412, the input terminal of the third buffer 413 and the fourth switch SW4. The control terminal of the fourth switch SW4 receives the reverse control signal SCS.

[0091] In this embodiment, the fourth partial circuit HSR_R4 includes a fifth buffer 415 . An input terminal of the fifth buffer 415 is coupled to an output terminal of the fourth buffer 414 and an output terminal of the third buffer 413 .

[0092] In this embodiment, the fifth circuit HSR_R5 includes a first logic gate LG1 (eg, a NAND gate). A first input terminal of the first logic gate LG1 receives the clock signal CK. A second input terminal of the first logic gate LG1 is coupled to the output terminal of the fifth buffer 415 .

[0093] In this embodiment, the sixth circuit HSR_R6 includes a second logic gate LG2 (eg, a negative OR gate (NOR)). A first input terminal of the second logic gate LG2 receives the inverted clock signal XCK. A second input terminal of the second logic gate LG2 is coupled to the output terminal of the first logic gate LG1.

[0094] In this embodiment, the seventh partial circuit HSR_R7 includes a sixth buffer INV1. An input terminal of the sixth buffer INV1 is coupled to an output terminal of the second logic gate LG2.

[0095] In this embodiment, the eighth partial circuit HSR_R8 includes a seventh buffer INV2. The input terminal of the seventh buffer INV2 is coupled to the output terminal of the sixth buffer INV1. The output terminal of the seventh buffer INV2 provides a control signal HSR[n] to the multi-stage data processing circuits 220_1 to 220_8.

[0096] Figure 5 is a schematic diagram of a display according to an embodiment of the present invention. Figure 5 The display 50 includes a pixel driving circuit 50a and a pixel array (not shown). The pixel driving circuit 50a and the pixel array can refer to the relevant description of the display 10 and be deduced by analogy.

[0097] In this embodiment, the display area AA is a non-rectangular polygon, and may be, for example, a polygon close to a circle. The non-display area A1 is adjacent to the display area AA. The non-display area A1 has a plurality of side edges adjacent to (or overlapping with) the display area AA.

[0098] In this embodiment, based on the split multiple circuit blocks, the multi-level data driving circuits in the pixel driving circuit 50a are sequentially arranged in the non-display area A1 with a reduced arrangement pitch. In this way, the display 50 can be implemented as a narrow-frame and circular display.

[0099] In summary, the pixel driving circuit and display of the embodiment of the present invention are suitable for narrow-frame and circular displays, and can reduce the arrangement spacing between the horizontal shift registers in each level of data driving circuit and the multi-level data processing circuit based on the preset number, thereby reducing the arrangement spacing between the multi-level data driving circuits. In this way, the pixel driving circuit can reduce the circuit area of ​​the multi-level data driving circuit in the non-display area, and at the same time reduce the blank layout area between the multi-level data driving circuit and the display area.

[0100] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A pixel driving circuit, suitable for a display, comprising: A multi-level data driving circuit is arranged in a non-display area of ​​the display, wherein the n-th level data driving circuit among the data driving circuits comprises: a horizontal shift register, divided into a plurality of horizontal shift register blocks based on a predetermined number; and The multi-stage data processing circuit is divided into a plurality of data processing circuit blocks based on the preset number, Each of the horizontal shift register blocks is coupled to a corresponding one of the data processing circuit blocks and is disposed on each of a plurality of sides of the non-display area, wherein n is a positive integer.

2. The pixel driving circuit as claimed in claim 1, wherein each of the data processing circuit blocks has m of the multi-stage data processing circuits, wherein m is a positive integer.

3. The pixel driving circuit according to claim 1, further comprising: The multi-stage gate driving circuit is coupled to the data driving circuits and is arranged in sequence based on the side edges to be disposed in the non-display area. 4 . The pixel driving circuit as claimed in claim 3 , wherein the preset number is the number of the gate driving circuits coupled to the n-th stage data driving circuit, and the preset number is greater than 1. 5 . 5 . The pixel driving circuit as claimed in claim 1 , wherein in the non-display area, in a first direction, the data driving circuits are arranged in a staircase shape.

6. The pixel driving circuit as claimed in claim 1, wherein the horizontal shift register comprises: A first partial circuit includes a first buffer, a second buffer, a third buffer, a first switch, a second switch and a third switch, wherein the first switch is coupled to the second buffer, the second switch and the third switch are coupled to the third buffer, the output end of the first buffer is coupled to the input end of the second buffer and the control end of the third switch, and the output end of the second buffer is coupled to the input end of the third buffer; A second circuit section includes a plurality of fourth buffers and a fourth switch, wherein the fourth buffers are connected in series and coupled to the fourth switch, an output end of the second buffer, and an output end of the third buffer; A third circuit section includes a plurality of logic gates, wherein the logic gates are connected in series and coupled to the output terminals of the fourth buffers; as well as a fourth circuit section, comprising a plurality of fifth buffers, wherein the fifth buffers are connected in series and coupled to the output ends of the logic gates, The first circuit section, the second circuit section, the third circuit section and the fourth circuit section belong to different horizontal shift register blocks respectively.

7. The pixel driving circuit as claimed in claim 1, wherein the logic gates include an NAND gate and an NOR gate. The multiple input terminals of the NAND gate receive a clock signal and are coupled to the output terminals of the fourth buffers, the multiple input terminals of the NOR gate receive a reverse clock signal and are coupled to the output terminals of the NAND gate, and the output terminals of the NOR gate are coupled to the input terminals of the fifth buffers.

8. The pixel driving circuit as claimed in claim 1, wherein the horizontal shift register comprises: A first partial circuit includes a first buffer, a second buffer and a first switch, wherein the first switch is coupled to the second buffer, and an output terminal of the first buffer is coupled to an input terminal of the second buffer; a second circuit section, comprising a third buffer, a second switch and a third switch, wherein the second switch and the third switch are coupled to the third buffer, a control end of the third switch is coupled to the output end of the first buffer, and an input end of the third buffer is coupled to the output end of the second buffer; a third circuit section, comprising a fourth buffer and a fourth switch, wherein the fourth switch is coupled to the fourth buffer, and an input end of the fourth buffer is coupled to an output end of the second buffer; a fourth circuit section, comprising a fifth buffer, wherein an input terminal of the fifth buffer is coupled to an output terminal of the fourth buffer and an output terminal of the third buffer; a fifth circuit section, comprising a first logic gate, wherein a plurality of input terminals of the first logic gate receive a clock signal and are coupled to the output terminal of the fifth buffer; a sixth circuit section, comprising a second logic gate, wherein a plurality of input terminals of the second logic gate receive an inverted clock signal and are coupled to the output terminal of the first logic gate; a seventh circuit section, comprising a sixth buffer, wherein an input terminal of the sixth buffer is coupled to an output terminal of the second logic gate; as well as an eighth circuit section, comprising a seventh buffer, wherein an input terminal of the seventh buffer is coupled to an output terminal of the sixth buffer, The first circuit section, the second circuit section, the third circuit section, the fourth circuit section, the fifth circuit section, the sixth circuit section, the seventh circuit section and the eighth circuit section belong to different horizontal shift register blocks respectively.

9. A display comprising: A pixel array is disposed in a display area; as well as The pixel driving circuit as claimed in claim 1 is coupled to the pixel array, disposed in a non-display area adjacent to the display area, and used to drive the pixel array. 10 . The pixel driving circuit as claimed in claim 9 , wherein the display area is a non-rectangular polygon.

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