Pixel circuit, display device and electronic device

Abstract

The invention relates to a pixel circuit, a display device and an electronic device. The pixel circuit comprises a public storage circuit and m pixel driving circuits sharing the public storage circuit, the pixel driving circuit comprises a driving switch, and the driving switch is configured as follows: a first end is connected with a power supply, and a second end is grounded through a light-emitting module; the public storage circuit comprises n storage units and mn control switches; the storage unit is connected with the control end of the corresponding driving switch through the corresponding control switch; wherein in m non-overlapped time periods, data are read through the public storage circuit in sequence, n control switches control the connected light emitting modules to emit light, m is larger than or equal to 2, and m is an integer; n > = 1, and n is an integer. According to the embodiment of the invention, the storage efficiency of image data in the pixel circuit is improved, the power consumption of data processing is reduced, and the size of a product is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a pixel circuit, a display device and an electronic device. Background Art

[0002] Silicon-based microdisplay is a display based on silicon semiconductor technology, which usually includes a driving circuit and a light-emitting device. For the display drive of Micro Light Emitting Diode Display (Micro LED) or Mini Light Emitting Diode Display (Mini LED), a digital subfield scanning method is commonly used, that is, one frame (1H) of display data includes multiple subframes, each subframe has a different weight value, and one frame of display data is a grayscale superposition of each subframe, thereby achieving 256 grayscale display. Therefore, in order to achieve 256 grayscales, each pixel of the digital drive needs to store at least 8 bits of binary data.

[0003] In the related art, the memory is set inside the pixel. When the video source data is input, it needs to be processed in a certain way before the data is transferred to the memory. However, under the current demand for high pixel density of micro-display devices, if multiple storage units and functional modules are integrated into each pixel circuit, the manufacturer's process precision is very high, resulting in high manufacturing costs. In addition, the memory needs to occupy a certain area, which makes the frame of the display screen larger, affecting the size and weight of the overall module of the micro-display device. Summary of the invention

[0004] Based on this, it is necessary to provide a pixel circuit, a display device and an electronic device to address the problems in the above-mentioned background technology, so as to improve the storage efficiency of image data in the pixel circuit, reduce the power consumption of data processing and reduce the size of the product, thereby improving the integration of the display device.

[0005] To achieve the above-mentioned purpose and other related purposes, one aspect of the present application provides a pixel circuit, comprising: a common storage circuit and m pixel driving circuits sharing the common storage circuit; the pixel driving circuit comprises a driving switch, and the driving switch is configured as follows: a first end is used to connect to a power supply, and a second end is used to connect to a ground via a light-emitting module; the common storage circuit comprises n storage units and mn control switches; the storage unit is connected to the control end of the corresponding driving switch via the corresponding control switch; wherein, data is read out sequentially via the common storage circuit in m non-overlapping time periods and the connected light-emitting modules are controlled to emit light via the n control switches; m≥2, m is an integer; n≥1, n is an integer.

[0006] In the pixel circuit in the above embodiment, the pixel circuit includes a common storage circuit and m pixel driving circuits sharing the common storage circuit. By reading out data in sequence through the common storage circuit in m non-overlapping time periods and controlling the connected light-emitting modules to emit light through n control switches, the light-emitting modules of the m pixel driving circuits are driven to emit light in m non-overlapping time periods, so as to achieve time-sharing driving of the m pixel driving circuits sharing the common storage circuit, where m≥2, m is an integer; n≥1, n is an integer. Since the common storage circuit can be used to write, read and store video source data, it is not necessary to store the data in the peripheral circuit, which simplifies the data flow, does not require data writing and reading processing through the frame buffer, can improve the storage efficiency of image data in the pixel circuit and reduce the power consumption of data processing. Since the m pixel driving circuits share the common storage circuit, the impact of the introduction of the storage circuit on the volume is reduced, which is conducive to the miniaturization of the product size and the improvement of the integration, and can achieve a higher pixel density (Pixels Per Inch, PPI) on the basis of a low degree of advancement of the wafer factory process node.

[0007] In some of the embodiments, the i-th storage unit among the n storage units is configured as follows: the first input terminal is connected to the common word line, the second input terminal is connected to the i-th bit line, the third input terminal is connected to the i-th complementary bit line, the first output terminal is connected to the input terminal of the 1_i-th control switch, and the j-th output terminal is connected to the input terminal of the j_i-th control switch; the 1_i-th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the 1st pixel driving circuit via the 1st common adder, and the control terminal is used to receive the 1_i-th timing control signal; the j_i-th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the j-th pixel driving circuit via the j-th common adder, and the control terminal is used to receive the j_i-th timing control signal; i∈[1,n], i is an integer, j∈[2,m], j is an integer.

[0008] In some of the embodiments, the i-th storage unit among the n storage units is configured as follows: the first input terminal is connected to the i-th word line, the second input terminal is connected to the common bit line, the third input terminal is connected to the complementary common bit line, the first output terminal is connected to the input terminal of the 1_i-th control switch, and the j-th output terminal is connected to the input terminal of the j_i-th control switch; the 1_i-th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the 1st pixel driving circuit via the 1st common adder, and the control terminal is used to receive the 1_i-th timing control signal; the j_i-th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the j-th pixel driving circuit via the j-th common adder, and the control terminal is used to receive the j_i-th timing control signal; i∈[1,n], i is an integer, j∈[2,m], j is an integer.

[0009] In some of the embodiments, the storage unit is a single pixel storage unit, and n=256.

[0010] In some of these embodiments, the power source is a voltage source or a current source.

[0011] In some of the embodiments, the pixel circuit includes 8 pixel driving circuits and 4 common storage circuits, the 4 common storage circuits are arranged sequentially along a first direction, and every 2 different pixel driving circuits among the 8 pixel driving circuits share different common storage circuits.

[0012] In some of the embodiments, the pixel circuit includes 8 pixel driving circuits and 2 common storage circuits, the 2 common storage circuits are arranged sequentially along a first direction, and every 4 different pixel driving circuits among the 8 pixel driving circuits share a different common storage circuit.

[0013] In some of the embodiments, the pixel circuit includes 12 pixel driving circuits and 4 common storage circuits, and every three different pixel driving circuits among the 12 pixel driving circuits share a different common storage circuit.

[0014] In some of the embodiments, the pixel circuit includes two pixel driving circuits and one common storage circuit; the common storage circuit includes n storage units and 2n control switches; wherein data is read out sequentially through the common storage circuit in two consecutive non-overlapping half-frame times, and the connected light-emitting modules are controlled to emit light through the n control switches.

[0015] Another aspect of the present application provides a display device, including any pixel circuit described in the embodiments of the present application, which can save a frame buffer module for storing image data in the display peripheral circuit, reduce the area of ​​the peripheral circuit of the display area, and improve the chip integration. It can also save power consumption of data stream processing and increase pixel density, thereby improving the overall performance of the display device.

[0016] Another aspect of the present application provides an electronic device, comprising the display device described in any one of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to better describe and illustrate the embodiments and / or examples of those applications disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, and the best modes of these applications currently understood.

[0018] Figure 1 Shown is a schematic diagram of sub-field segmentation corresponding to 256 gray levels in the related art provided in an embodiment of the present application;

[0019] Figure 2 Shown is a schematic top view of a display backplane provided in one embodiment of the present application;

[0020] Figure 3 Shown is a circuit schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0021] Figure 4 Shown is a principle schematic diagram of a pixel circuit provided in another embodiment of the present application;

[0022] Figure 5 Shown is a circuit schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0023] Figure 6 Shown is a circuit schematic diagram of a pixel circuit provided in another embodiment of the present application;

[0024] Figure 7 Shown is a schematic diagram of the working timing of a pixel circuit provided in an embodiment of the present application;

[0025] Figure 8-Figure 11 Schematic diagram of pixel distribution of pixel circuits provided in different embodiments of the present application.

[0026] Description of reference numerals:

[0027] 100, common storage circuit; 300 / 300', pixel driving circuit; 20, pixel module; 200, pixel array; 201, signal receiving unit; 202, signal storage unit; 203, current regulating module; 204, switch module; 205, light emitting unit; 21, current source module; 22, power generation module; 23, gate driving module; 24, source driving module; 25, timing control module; 26, storage module. DETAILED DESCRIPTION

[0028] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0031] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing, and the zones shown in the figures are schematic in nature, and their shapes are not intended to display the actual shapes of the zones of the device and are not intended to limit the scope of the application.

[0034] See also Figure 1-Figure 10 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0035] Silicon-based microdisplay is a special display that forms a large field of view through optical magnification based on silicon semiconductor technology. It generally includes a driving circuit and a light-emitting device. Its grayscale generation methods mainly include analog amplitude modulation and digital pulse width modulation. Among them, analog amplitude modulation is to convert digital signals into analog signals through a digital to analog converter (DAC), and obtain different brightness values ​​by adjusting the voltage value at both ends of the light-emitting device or the current value flowing through the light-emitting device. However, analog amplitude modulation is limited by factors such as DAC accuracy, speed and cost, and is rarely used in high grayscale and high-resolution microdisplays. Digital pulse width modulation refers to controlling the light-emitting time of the light-emitting chip through pulse width modulation (PWM) to produce different grayscale levels.

[0036] Digital pulse width modulation can be achieved through a PWM generator composed of a comparator and a counter. Specifically, the PWM signal is generated by controlling the PWM generator to control the on-time of the light-emitting chip to obtain different degrees of luminous brightness; the on-time of the light-emitting chip can also be controlled by directly generating a PWM signal. However, since the volt-ampere characteristic of micro LED is similar to that of a pn junction, when it is in the forward working area, the slope of the current brightness curve is very large. If the current is accurately adjusted by adjusting the voltage amplitude or the current amplitude is directly adjusted to obtain different brightness, low grayscale cannot be stably displayed and the brightness adjustment range is small.

[0037] See also Figure 1In the related art, the display driver for micro LED or mini LED is generally implemented by digital subfield scanning method. The principle is that one frame (1H) of display data includes multiple subframes, each subframe has a different weight value, and each subframe includes a data writing stage T1 and a light-emitting stage T2. The different weight values ​​of each subframe mean that the duration of the light-emitting stage T2 in each subframe is different, that is, the lighting duration of the light-emitting chip is different. Specifically, the weight value can be set in a standard binary weight value increment or a non-standard binary weight value increment. For example, Figure 1 The display data of the digital display device includes 8 subframes, namely subframe F1, subframe F2, subframe F3, subframe F4, subframe F5, subframe F6, subframe F7 and subframe F8. The standard binary weight value increment method is adopted. The weight value ratio of each subframe is 1(20):2(21):4(22):8(23):16(24):32(25):64(26):128(27). One frame of display data is the grayscale superposition of each subframe, so as to realize 256 grayscale display. Therefore, in order to realize 256 grayscale display in digital driving, each pixel needs to store at least 8 bits of binary data, and the storage function takes up a lot of time and power consumption.

[0038] Figure 2 It is a pixel and related circuits around the display area commonly used in the related art, including a driving backplane and a light-emitting unit stacked from bottom to top, and the driving backplane includes a pixel array 200, a power generation module 22, a gate driving module 23, a source driving module 24, a timing control module 25 and a storage module 26. In order to improve the luminous brightness of the grayscale of the display unit L255, when the scanning signal scans each row of display units, the display units of each row can emit light immediately after the addressing scanning time, and each display unit can continue to emit light within the driving time of the entire frame display picture, and the storage module 26 around the display area can be used for frame buffering.

[0039] Figure 3It is a schematic diagram of a structure of a pixel circuit commonly used in the related art, and the pixel circuit includes a signal receiving unit 201, a signal storage unit 202, a current regulating module 203, a switch module 204 and a light emitting unit 205. Specifically, the 1-bit SRAM structure includes 6 MOS transistors of two signal receiving units 201 and one signal storage unit 202, wherein two adders composed of MOS transistors T7, MOS transistors T8, MOS transistors T9 and MOS transistors T10 in the signal storage unit 202 are cross-coupled to form a bistable trigger circuit, and the MOS transistors T2 and MOS transistors T2' in the two signal receiving units 201 store the column data of the data driver on the bistable trigger when the Scan scanning pixel module in the row scanning circuit addresses the pixel module 20 of the row row by row. The MOS transistor T1 in the switch module 204 controls the switch of the anode of the light-emitting unit 205 to the drain electrode of the MOS transistor T3 in the current regulating module 203 according to the data level on the bistable trigger, and the cathode of multiple light-emitting units 205 is connected to the driving power ground VSS, thereby controlling the light-emitting and extinguishing of the light-emitting unit 205. The column driving signal Data is combined with the adjustment signal of the MOS transistor T3 in the current regulating module 203 and the Iref signal of the gate electrode to jointly control the state of the light-emitting unit 205. The larger the voltage of the adjustment signal Iref, that is, the voltage from VDD to the Iref signal line, the larger the current flowing through the light-emitting unit 205, and the greater the brightness of the LED, so the brightness of the LED chip can be adjusted by changing the adjustment signal Iref.

[0040] As an example, see Figure 3 However, in the related art, after the video source data is input, it needs to be processed such as image scaling and gamma correction, and then the data is transmitted to the storage module outside the display area. The frame buffer module is used to store image data. Its size is at least the product of the number of pixels and the color depth, and it uses a bit plane to store image data. In addition, it must be divided into at least 8 subfields to read data from the memory and write it to each pixel module in the display area. Its data flow processing process is complicated, and the power consumption of data reading and writing is high; and the frame buffer circuit needs to occupy a large area, which increases the border of the display screen.

[0041] Moreover, in the existing digital driving technology, if at least 8 bits of data for realizing 256 grayscales are integrated inside the pixel unit, a large number of MOS tubes will be required to realize it, and the pixel area will be larger, making it difficult to achieve the high PPI specification requirements of micro display devices (such as AR / VR); or it is necessary to use very high-precision process preparation in the wafer fab to achieve high PPI, in which case the process difficulty will be relatively high and the preparation cost will also be very high.

[0042] Based on the problems in the above-mentioned background technology, the present application provides a pixel circuit, a display device and an electronic device to improve the storage efficiency of image data in the pixel circuit, reduce the power consumption of data processing and reduce the size of the product, thereby improving the integration of the display device.

[0043] See also Figure 4 According to one aspect of the present application, a pixel circuit is provided, comprising: a common storage circuit 100 and m pixel driving circuits sharing the common storage circuit 100, the m pixel driving circuits comprising pixel driving circuits 1, ..., pixel driving circuit m, the pixel driving circuit comprising a driving switch, the driving switch being configured as follows: a first end is used to connect to a power supply, and a second end is used to connect to ground via a light-emitting module; the common storage circuit 100 comprises n storage units and mn control switches; the storage units are connected to the control ends of the corresponding driving switches in sequence via a PWM generation module and corresponding control switches; wherein, data is read out in sequence via the common storage circuit 100 in m non-overlapping time periods and the connected light-emitting modules are controlled to emit light via the n control switches; m≥2, m is an integer; n≥1, n is an integer.

[0044] Please continue reading Figure 4 , by reading out data in sequence through the common storage circuit 100 in m non-overlapping time periods and controlling the connected light-emitting modules to emit light through n control switches respectively, so that the light-emitting modules of m pixel driving circuits are driven to emit light respectively in m non-overlapping time periods, and the m pixel driving circuits sharing the common storage circuit 100 are driven to emit light in a time-sharing manner, m≥2, m is an integer; n≥1, n is an integer. Since the common storage circuit 100 can be used to write, read and store video source data, it is not necessary to store the data in the peripheral circuit, which simplifies the data flow, does not require data writing and reading processing through the frame buffer, can improve the storage efficiency of image data in the pixel circuit and reduce the power consumption of data processing. Since the m pixel driving circuits share the common storage circuit 100, the impact of the introduction of the storage circuit on the volume is reduced, which is conducive to the miniaturization of the product size and the improvement of the integration, and can achieve a higher pixel density (Pixels Per Inch, PPI) based on the low degree of advancement of the existing process node of the wafer factory.

[0045] In some embodiments, the i-th memory cell (memory cell i) among the n memory cells is configured as follows: a first input terminal is connected to a common word line WL, a second input terminal is connected to an i-th bit line BLi, and a third input terminal is connected to a common word line WL.

[0046] —is connected to the i-th complementary bit line BLi, the first output terminal is connected to the input terminal of the 1_i-th control switch, and the j-th output terminal is connected to the input terminal of the j_i-th control switch; the 1_i-th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the 1st pixel driving circuit via the 1st common adder 101, and the control terminal is used to receive the 1_i-th timing control signal Ck1_i; the j_i-th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the j-th pixel driving circuit via the j-th common adder 10j, and the control terminal is used to receive the j_i-th timing control signal Ckj_i; i∈[1,n], i is an integer, j∈[2,m], j is an integer.

[0047] In some embodiments, the i-th memory cell (memory cell i) among the n memory cells is configured as follows: a first input terminal is connected to the i-th word line WLi, a second input terminal is connected to the common bit line BL, and a third input terminal is connected to the common bit line BL.

[0048] —is connected to the complementary common bit line BL, the first output terminal is connected to the input terminal of the 1_i th control switch, and the j th output terminal is connected to the input terminal of the j_i th control switch; the 1_i th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the 1st pixel driving circuit via the 1st common adder 101, and the control terminal is used to receive the 1_i th timing control signal Ck1_i; the j_i th control switch is configured as follows: the output terminal is connected to the control terminal of the driving switch of the jth pixel driving circuit via the j th common adder 10j, and the control terminal is used to receive the j_i th timing control signal Ckj_i; i∈[1,n], i is an integer, j∈[2,m], j is an integer.

[0049] In some embodiments, the storage unit is a single pixel storage unit, and n=256.

[0050] In some embodiments, please refer to Figure 5 and Figure 7 The pixel circuit includes a pixel driving circuit 300 and a pixel driving circuit 300', and the pixel driving circuit 300 and the pixel driving circuit 300' share a common storage circuit 100; the common storage circuit 100 includes n storage units and 2n control switches; wherein, data is read out sequentially through the common storage circuit 100 in two consecutive half frame times (1 frame is 1 Frame) that do not overlap each other, and the connected light-emitting modules are controlled to emit light through the n control switches. wherein, the two consecutive half frame times include the clock signal CK in the first half frame time and the clock signal CK' in the second half frame time.

[0051] Please continue reading Figure 5 and Figure 7The storage unit can be a single pixel storage unit such as a bit SRAM. n bit SRAMs use the same word line WL for addressing, that is, they are selected at the same time, and use N groups of BL and complementary bit lines BL to write data signals; the data writing method can be flexibly selected according to the product specifications and writing speed requirements. In addition, each bit of SRAM will be connected to the source of a MOS tube that controls the light-emitting duration of each bit, and the gate of this MOS tube is connected to the clock signal corresponding to each bit. The timing of each clock signal can be referred to Figure 7 As shown, the 1H period is the time to write each bit of SRAM data, T*2 1 Time period and T*2 2 The time period is the light-emitting time of a pixel, and the light-emitting time is determined by the PWM signal generated by each bit of SRAM data and the corresponding clock signal.

[0052] In some embodiments, see Figure 6 and Figure 7 , the storage unit can be a single pixel storage unit such as

[0053] —bit SRAM, n bit SRAM uses the same set of bit lines BL and complementary bit lines BL for address selection, that is, they are selected at the same time, and use word lines WL1, WL2, ..., WLn to write data signals to the connected storage cells; the data writing method can be flexibly selected according to the product specifications and writing speed requirements. In addition, each bit of SRAM will be connected to the source of a MOS tube that controls the light-emitting duration of each bit, and the gate of this MOS tube is connected to the clock signal corresponding to each bit. The timing of each clock signal can be referred to Figure 7 As shown, the 1H period is the time to write each bit of SRAM data, T*2 1 Time period and T*2 2 The time period is the light-emitting time of a pixel, and the light-emitting time is determined by the PWM signal generated by each bit of SRAM data and the corresponding clock signal.

[0054] In some embodiments, the power source is a voltage source or a current source.

[0055] In some embodiments, see Fig. 9, 4 common storage circuits are arranged in sequence along a first direction (e.g., ox direction), and every 2 different pixel driving circuits in the 8 pixel driving circuits share different common storage circuits. For example, the pixel driving circuit of pixel 1 and the pixel driving circuit of pixel 5 share a common storage circuit 115, the pixel driving circuit of pixel 2 and the pixel driving circuit of pixel 6 share a common storage circuit 126, the pixel driving circuit of pixel 3 and the pixel driving circuit of pixel 7 share a common storage circuit 137, and the pixel driving circuit of pixel 4 and the pixel driving circuit of pixel 8 share a common storage circuit 148. Figure 8 The pixel driving circuit and the storage circuit are arranged one-to-one. This embodiment effectively reduces the impact of introducing the storage circuit on the product volume, which is beneficial to miniaturization of the product size and improvement of integration.

[0056] In some embodiments, see Fig.10 , the pixel circuit includes 12 pixel driving circuits and 4 common storage circuits, and every 3 different pixel driving circuits in the 12 pixel driving circuits share different common storage circuits. For example, the pixel driving circuit of pixel 1, the pixel driving circuit of pixel 2 and the pixel driving circuit of pixel 3 share a common storage circuit 1123, the pixel driving circuit of pixel 4, the pixel driving circuit of pixel 5 and the pixel driving circuit of pixel 6 share a common storage circuit 1456, the pixel driving circuit of pixel 7, the pixel driving circuit of pixel 8 and the pixel driving circuit of pixel 9 share a common storage circuit 1789, the pixel driving circuit of pixel 10, the pixel driving circuit of pixel 11 and the pixel driving circuit of pixel 12 share a common storage circuit 1012, relative to Figure 8 The pixel driving circuit and the storage circuit are arranged one-to-one. This embodiment effectively reduces the impact of introducing the storage circuit on the product volume.

[0057] In some embodiments, see Fig.11 The pixel circuit includes 8 pixel driving circuits and 2 common storage circuits. The 2 common storage circuits are arranged in sequence along the first direction. Every 4 different pixel driving circuits in the 8 pixel driving circuits share different common storage circuits. For example, the pixel driving circuit of pixel 1, the pixel driving circuit of pixel 2, the pixel driving circuit of pixel 5 and the pixel driving circuit of pixel 6 share common storage circuit 1526, and the pixel driving circuit of pixel 3, the pixel driving circuit of pixel 4, the pixel driving circuit of pixel 7 and the pixel driving circuit of pixel 8 share common storage circuit 3748.

[0058] In some embodiments, a display device is provided, including any pixel circuit described in the embodiments of the present application, which can save a frame buffer module for storing image data in the display peripheral circuit, reduce the area of ​​the peripheral circuit of the display area, and improve the chip integration. It can also save power consumption of data stream processing and increase pixel density, thereby improving the overall performance of the display device.

[0059] In some embodiments, an electronic device is provided, comprising the display device described in any one of the embodiments of the present application.

[0060] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0061] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0062] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A pixel circuit, characterized in that: include: A common storage circuit and m pixel driving circuits sharing the common storage circuit; The pixel driving circuit includes a driving switch, wherein the driving switch is configured as follows: a first end is used to connect to a power source, and a second end is used to connect to a ground via a light emitting module; The common storage circuit includes n storage units and mn control switches; The storage unit is connected to the control end of the corresponding driving switch via the corresponding control switch; Wherein, data is read out in sequence through the common storage circuit in m non-overlapping time periods and the connected m light-emitting modules are controlled to emit light through n control switches; m≥2, m is an integer; n≥1, n is an integer.

2. The pixel circuit according to claim 1, characterized in that: The i-th memory cell among the n memory cells is configured as follows: a first input terminal is connected to a common word line, a second input terminal is connected to an i-th bit line, a third input terminal is connected to an i-th complementary bit line, a first output terminal is connected to an input terminal of a 1_i-th control switch, and a j-th output terminal is connected to an input terminal of a j_i-th control switch; The 1_i th control switch is configured as follows: an output end is connected to a control end of a driving switch of a first pixel driving circuit via a first common adder, and the control end is used to receive a 1_i th timing control signal; The j_i-th control switch is configured as follows: an output end is connected to a control end of a driving switch of a j-th pixel driving circuit via a j-th common adder, and the control end is used to receive a j_i-th timing control signal; i∈[1,n], i is an integer, j∈[2,m], j is an integer.

3. The pixel circuit according to claim 1, characterized in that: The i-th memory cell among the n memory cells is configured as follows: a first input terminal is connected to an i-th word line, a second input terminal is connected to a common bit line, a third input terminal is connected to a complementary common bit line, a first output terminal is connected to an input terminal of a 1_i-th control switch, and a j-th output terminal is connected to an input terminal of a j_i-th control switch; The 1_i th control switch is configured as follows: an output end is connected to a control end of a driving switch of a first pixel driving circuit via a first common adder, and the control end is used to receive a 1_i th timing control signal; The j_i-th control switch is configured as follows: an output end is connected to a control end of a driving switch of a j-th pixel driving circuit via a j-th common adder, and the control end is used to receive a j_i-th timing control signal; i∈[1,n], i is an integer, j∈[2,m], j is an integer.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that: The storage unit is a single-pixel storage unit, and n=256.

5. The pixel circuit according to any one of claims 1 to 3, characterized in that: The power source is a voltage source or a current source.

6. The pixel circuit according to any one of claims 1 to 3, characterized in that: include: 8 pixel driving circuits and 4 common storage circuits, the 4 common storage circuits are arranged in sequence along a first direction, and every 2 different pixel driving circuits in the 8 pixel driving circuits share a different common storage circuit; or There are 8 pixel driving circuits and 2 common storage circuits, the 2 common storage circuits are arranged in sequence along a first direction, and every 4 different pixel driving circuits in the 8 pixel driving circuits share a different common storage circuit.

7. The pixel circuit according to any one of claims 1 to 3, characterized in that: include: There are 12 pixel driving circuits and 4 common storage circuits, and every 3 different pixel driving circuits in the 12 pixel driving circuits share a different common storage circuit.

8. The pixel circuit according to any one of claims 1 to 3, characterized in that: include: 2 pixel driving circuits and 1 common storage circuit; The common storage circuit includes n storage units and 2n control switches; The data are read out in sequence through different common storage circuits in two consecutive non-overlapping half frame times, and the connected light-emitting modules are controlled to emit light through n control switches.

9. A display device, characterized in that: include: The pixel circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The display device according to claim 9.

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