Gate driving module and display panel

Abstract

The invention provides a gate driving module and a display panel, and the module comprises a plurality of cascaded gate driving circuits. The gate drive circuit comprises a level transmission unit (a level transmission receiving unit used for receiving a level transmission signal generated by an upper-level gate drive circuit and outputting the level transmission signal of the level to a lower-level gate drive circuit according to a signal of a first node and a signal of a second node), and an output unit used for outputting the level transmission signal of the level to the lower-level gate drive circuit according to the first node and the second node. A grid control signal is output from the signal of one of the first node, the signal of one of the second nodes and the signal of the third node), a stage transmission frequency division control unit and an output frequency division control unit; the stage transmission frequency division control unit is used for controlling the stage transmission output unit to output a stage transmission signal of the stage according to signals of one of the first node, the second node and the third node, and the output frequency division control unit is used for controlling a signal of the third node according to a frequency division control signal so as to control the output unit to output a grid control signal of the stage; therefore, differential setting of the refresh rates of different display areas is realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving module and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used due to their flexibility and other characteristics.

[0003] Among them, the gate driving circuit in the OLED display panel generally outputs effective pulses step by step to turn on multiple rows of sub-pixels in sequence. The refresh rate of the entire display area is the same, and it is impossible to use different refresh rates to drive different areas, resulting in limited usage scenarios.

[0004] Therefore, the existing OLED display panels have the defect that different areas cannot achieve different refresh rates, which urgently needs to be improved. Summary of the invention

[0005] The present invention provides a gate driving module and a display panel to achieve driving of different areas with different refresh rates.

[0006] An embodiment of the present invention provides a gate driving module, comprising a frequency division signal line and a plurality of cascaded gate driving circuits, wherein the frequency division signal line is used to transmit a frequency division control signal to the plurality of gate driving circuits, and the gate driving circuit comprises:

[0007] A level transmission unit, comprising a level transmission receiving unit and a level transmission output unit, wherein the level transmission receiving unit is used to receive a level transmission signal generated by the upper-level gate driving circuit, and the level transmission output unit is electrically connected to the level transmission receiving unit through a first node and a second node, and is used to output the level transmission signal of the current level to the lower-level gate driving circuit according to the signal of the first node and the signal of the second node;

[0008] an output unit, electrically connected to the stage transmission output unit through the first node, one of the second nodes, and a third node, and configured to output a gate control signal according to a signal of the first node, one of the second nodes, and a signal of the third node; and

[0009] a stage transmission frequency division control unit, electrically connected to the stage transmission receiving unit through the first node or the second node, and electrically connected to the stage transmission output unit through a fourth node, and configured to control a signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output unit to output the stage transmission signal of the current stage;

[0010] An output frequency division control unit is connected between the first node, one of the second nodes and the third node, and is used to control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of this stage.

[0011] In one embodiment, the frequency division control signal includes a first frequency division control signal and a second frequency division control signal, and the frequency division signal line includes a first frequency division signal line for transmitting the first frequency division control signal and a second frequency division control signal line for transmitting the second frequency division control signal;

[0012] Wherein, the first frequency division signal line is electrically connected to the output frequency division control unit to control the signal of the third node;

[0013] The second frequency division signal line is electrically connected to the stage transmission frequency division control unit to control a signal of one of the first node and the second node.

[0014] In one embodiment, the output frequency division control unit includes:

[0015] a first frequency-dividing transistor, wherein a gate of the first frequency-dividing transistor is connected to the first frequency-dividing signal line, a source of the first frequency-dividing transistor is electrically connected to the first node or the second node, and a drain of the control transistor is electrically connected to the third node;

[0016] The first frequency division control signal is used to control whether the third node is electrically connected to or disconnected from the first node or the second node.

[0017] In one embodiment, the output frequency division control unit further includes:

[0018] a second frequency-dividing transistor, wherein a gate of the second frequency-dividing transistor is electrically connected to the fifth node of the stage transmission unit, a source of the second frequency-dividing transistor is electrically connected to the first frequency-dividing signal line, and a drain of the second frequency-dividing transistor is electrically connected to the gate of the first frequency-dividing transistor;

[0019] The first frequency division control signal and the signal of the fifth node are used to control the third node to be electrically connected or disconnected with the first node or the second node;

[0020] The signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate driving circuit of this stage.

[0021] In one embodiment, the stage transmission and frequency division control unit includes:

[0022] a third frequency-dividing transistor, wherein the gate of the third frequency-dividing transistor is electrically connected to the second frequency-dividing signal line, the source of the first frequency-dividing transistor is electrically connected to the stage transmission receiving unit through the fourth node, and the drain of the third frequency-dividing transistor is electrically connected to the first node or the second node;

[0023] The second frequency division control signal is used to control whether the fourth node is electrically connected to or disconnected from the first node or the second node.

[0024] In one embodiment, the level transmission output unit includes:

[0025] a first-stage transmission output transistor, wherein a gate of the first-stage transmission output transistor is electrically connected to the first node, a source of the first-stage transmission output transistor is electrically connected to the first voltage line to load a first voltage, and a drain of the first-stage transmission output transistor is electrically connected to a stage transmission output terminal in the gate driving circuit for outputting the stage transmission signal;

[0026] A second-stage transmission output transistor, wherein the gate of the second-stage transmission output transistor is electrically connected to the second node, the source of the second-stage transmission output transistor is electrically connected to the second voltage line to load a second voltage, and the drain of the second-stage transmission output transistor is electrically connected to the stage transmission output end.

[0027] In one embodiment, the output unit includes:

[0028] a first output transistor, wherein a gate of the first output transistor is electrically connected to the third node, a source of the first output transistor is electrically connected to the first voltage line, and a drain of the first output transistor is electrically connected to a gate output terminal of the gate driving circuit for outputting the gate control signal;

[0029] A second output transistor, wherein the gate of the second output transistor is electrically connected to the first node or the second node, the source of the second output transistor is electrically connected to the second voltage line, and the drain of the second output transistor is electrically connected to the gate output terminal.

[0030] In one embodiment, the gate driving circuit is electrically connected to a corresponding at least one pixel driving circuit, the gate output terminal is electrically connected to a corresponding pixel transistor in each of the pixel driving circuits, and the first voltage is greater than the second voltage;

[0031] The pixel transistor is an N-type transistor, and the drain of the third frequency-dividing transistor and the source of the first frequency-dividing control transistor are both electrically connected to the first node;

[0032] Alternatively, the pixel transistor is a P-type transistor, and the drain of the third frequency-dividing transistor and the source of the first frequency-dividing control transistor are both electrically connected to the second node.

[0033] In one embodiment, the level transmission receiving unit includes:

[0034] a fourth node control unit, electrically connected to the clock signal line and the fourth node, and configured to control a signal of the fourth node according to a clock signal transmitted by the clock signal line;

[0035] a second node control unit, electrically connected to the clock signal line and the second node, and configured to control a signal of the second node according to the clock signal;

[0036] An input unit, wherein the input end of the input unit is electrically connected to the gate driving circuit of the upper level to load the level transmission signal generated by the gate driving circuit of the upper level, and the input end of the input unit is electrically connected to the fourth node control unit and the second node control unit, or is electrically connected to the fourth node control unit and the first node control unit.

[0037] In one embodiment, the stage transmission frequency division control unit and the output frequency division control unit are both electrically connected to the first node;

[0038] The input unit comprises an input transistor, a gate of the input transistor is loaded with the clock signal, a source of the input transistor is configured as an input terminal of the input unit, and a drain of the input transistor is configured as an output terminal of the input unit;

[0039] The fourth node control unit includes a first transistor, a seventh transistor, a second transistor and a third transistor connected in series, the gate of the seventh transistor is electrically connected to the drain of the input transistor, the source of the seventh transistor is loaded with the clock signal, the gate of the first transistor is loaded with the clock signal, the source of the first transistor is loaded with the second voltage, the drain of the first transistor is electrically connected to the gate of the second transistor and the drain of the seventh transistor, the drain of the second transistor is electrically connected to the source of the third transistor, the source of the second transistor and the gate of the third transistor are both loaded with the clock signal, and the drain of the third transistor is electrically connected to the fourth node;

[0040] The second node control unit includes a fourth transistor, a first capacitor, a fifth transistor and a sixth transistor arranged in series, the gate of the fourth transistor is loaded with a control signal, the source of the fourth transistor is loaded with the first voltage, the drain of the fourth transistor is electrically connected to the second node, the gate of the fifth transistor is electrically connected to the drain of the first transistor, the source of the fifth transistor is loaded with the first voltage, the drain of the fifth transistor is electrically connected to the source of the sixth transistor, the drain of the sixth transistor is loaded with the clock signal, the gate of the sixth transistor is also loaded with the level transmission signal generated by the upper gate drive circuit, and the first capacitor is electrically connected between the gate and the drain of the sixth transistor.

[0041] In one embodiment, the second node control unit further includes:

[0042] a tenth transistor, wherein a source of the tenth transistor is loaded with the level transmission signal generated by the upper gate driving circuit, a gate of the tenth transistor is loaded with the clock signal, and a drain of the tenth transistor is electrically connected to the gate of the sixth transistor;

[0043] an eleventh transistor, wherein a gate and a source of the eleventh transistor are both electrically connected to the gate of the sixth transistor, and a drain of the eleventh transistor is electrically connected to the second node.

[0044] An embodiment of the present invention also provides a display panel, including:

[0045] A gate drive module as described in any one of the above;

[0046] A panel body, comprising a plurality of sub-pixels and a plurality of scanning lines, wherein the plurality of sub-pixels comprise light-emitting devices and a pixel driving circuit for driving the light-emitting devices to emit light, wherein the pixel driving circuit comprises at least one transistor;

[0047] The gate control signal output by the gate driving circuit is transmitted to the gates of the plurality of transistors in the corresponding plurality of pixel driving circuits via the corresponding scanning lines.

[0048] In one embodiment, the display panel is in a frequency reduction mode and a frequency increase mode in a time-sharing manner, and the plurality of gate driving circuits include a plurality of first gate driving circuits cascaded together, and a plurality of second gate driving circuits cascaded together after the plurality of first gate driving circuits;

[0049] The plurality of sub-pixels include a plurality of first sub-pixels electrically connected to a plurality of the first gate driving circuits, and a plurality of second sub-pixels electrically connected to a plurality of the second gate driving circuits, the plurality of the first sub-pixels constitute a first display area, and the plurality of the second sub-pixels constitute a second display area;

[0050] In the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area;

[0051] In the frequency-upgrading mode, the refresh rate of the first display area is lower than the refresh rate of the second display area.

[0052] In one embodiment, in the frequency reduction mode, the first frequency division control signal is used to control the third node in each stage of the gate driving circuit to be electrically connected to the first node or the second node;

[0053] In the first type of frame, the second frequency-divided control signal is used to control the first node or the second node in the first gate driving circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device;

[0054] In the first type of frame, the second frequency division control signal is also used to control the first node or the second node and the fourth node in the second gate drive circuit to open the circuit, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

[0055] In one embodiment, in the frequency reduction mode, the second frequency division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node;

[0056] In the second type of frame, the first frequency division control signal is used to control the third node in the first gate driving circuit to be electrically connected to the first node or the second node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light emitting device;

[0057] In the second type of frame, the first frequency division control signal is also used to control the circuit between the third node and the first node or the second node in the second gate drive circuit to be disconnected, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

[0058] In one embodiment, in the frequency-up mode, the second frequency-division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node;

[0059] In the third type of frame, the first frequency division control signal is used to control the third node in the first gate drive circuit and the first node or the second node (for Figure 3(in terms of) a circuit is disconnected between the gate control signals to control the output gate control signal to not have the gate effective pulse to not turn on the corresponding light emitting device;

[0060] In the third type of frame, the first frequency-division control signal is used to control the first node or the second node in the second gate drive circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have the gate effective pulse to turn on the corresponding light-emitting device.

[0061] In one embodiment, the gate driving module includes n-stage gate driving circuits cascaded in sequence, where n is a positive integer greater than or equal to 2, and the n-stage gate driving circuits are all loaded with the same clock signal;

[0062] In one frame, the clock signal is alternately equal to the first clock voltage and the second clock voltage during the period of time when it effectively acts on the gate driving circuit of the i-th level to the (i+k)-th level, and i and k are both positive integers greater than or equal to 1;

[0063] Among them, when the gate control signals output by the gate driving circuits of the (i+k+1)th to nth levels do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period when it effectively acts on the gate driving circuits of the (i+k+1)th to nth levels.

[0064] The present invention provides a gate driving module and a display panel, comprising the above-mentioned frequency division signal line and a plurality of cascaded gate driving circuits, wherein the gate driving circuit comprises the above-mentioned level transmission unit and output unit. Among them, a level transmission frequency division control unit electrically connected to the level transmission receiving unit through the first node or the second node (also electrically connected to the level transmission output unit through the fourth node), and an output frequency division control unit connected between the first node, one of the second node and the third node are also provided, and the two are respectively used to control the signal of one of the first node and the second node according to the frequency division control signal to control the level transmission output unit to output the level transmission signal of the current level, and control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of the current level, so that the invalidity of the gate control signal will not affect the invalidity of the level transmission signal, and the sequential frequency reduction mode of multiple regions of the display panel can be realized by setting whether the level transmission signal has a level transmission valid pulse, and the arbitrary frequency conversion mode of multiple regions of the display panel can be realized by setting whether the gate control signal has a gate valid pulse (because the level transmission valid pulse can always exist). BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0066] Figure 1 A schematic structural diagram of a gate driving module provided in an embodiment of the present invention.

[0067] Figure 2 and Figure 3 They are circuit diagrams of two gate driving circuits provided in embodiments of the present invention.

[0068] Figure 4 and Figure 5 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention.

[0069] Figure 6 and Figure 7 A circuit diagram of a pixel driving circuit provided by an embodiment of the present invention.

[0070] Figure 8 and Fig. 9 They are Figure 6 and Figure 7 Waveform diagram of part of the signal.

[0071] Fig.10 Waveform diagram of some signals in a single-stage gate drive circuit provided by an embodiment of the present invention.

[0072] Figures 11 to 16 The waveform diagram of some signals in the multi-stage gate driving circuit provided by the embodiment of the present invention.

[0073] Fig.17 The waveform diagram is a data signal transmitted on the same data line and two frequency division control signals corresponding to two gate driving circuits. DETAILED DESCRIPTION

[0074] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0075] In the description of the present invention, the terms "first", "second" and the like are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In this article, no distinction is made between the source and the drain of the transistor, and the two can be interchangeably set. The terms "low voltage" and "high voltage" represent two voltages with a relatively smaller voltage value and a relatively larger voltage value, and can represent two voltage values ​​of the same signal at different times, or two voltage values ​​of different signals at the same time or at different times. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings so that the invention points are clear at a glance, rather than to indicate that the actual device is the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0076] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0077] The present invention provides a gate driving module, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0078] In one embodiment, if Figure 1 As shown, the gate driving module 10 includes a frequency division signal line FDL and a plurality of cascaded gate driving circuits 20, wherein the frequency division signal line FDL is used to transmit the frequency division control signal FD to the plurality of gate driving circuits 20. Figure 2 and Figure 3As shown, the gate driving circuit 20 includes: a level transmission unit 201, including a level transmission receiving unit 2011 and a level transmission output unit 2012, wherein the level transmission receiving unit 2011 is used to receive the level transmission signal generated by the upper gate driving circuit 20, and the level transmission output unit 2012 is electrically connected to the level transmission receiving unit 2011 through a first node P and a second node Q, and is used to output the level transmission signal of this level to the lower gate driving circuit 20 according to the signal of the first node P and the signal of the second node Q; an output unit 202 is electrically connected to the level transmission output unit 2012 through the first node P, one of the second nodes Q, and a third node S, and is used to output the level transmission signal of this level to the lower gate driving circuit 20 according to the signal of the first node P and the signal of the second node Q. The signal of the third node S outputs the gate control signal of this stage; and a stage transmission frequency division control unit 203, which is electrically connected to the stage transmission receiving unit 2011 through the first node P or the second node Q, and is electrically connected to the stage transmission output unit 2012 through a fourth node R, and is used to control the signal of one of the first node P and the second node Q according to the frequency division control signal FD, so as to control the stage transmission output unit 2012 to output the stage transmission signal of this stage; an output frequency division control unit 204, which is connected between the first node P, the second node Q and the third node S, and is used to control the signal of the third node S according to the frequency division control signal FD, so as to control the output unit 202 to output the gate control signal of this stage.

[0079] Specifically, Figure 1 In the figure, n (n≥2) cascaded gate driving circuits 20 are taken as an example for explanation, and the first-level gate driving circuit 2010 can use the first start signal STV1 or the second start signal STV2 (the two have opposite phases) as its corresponding "upper-level gate control signal", and the gate control signal Scan(1) of this level output is transmitted to the lower-level (second-level) gate driving circuit 20. Similarly, the n-th-level gate driving circuit 20 can generate and output the gate control signal Scan(n) of this level (n-level) according to the gate control signal Scan(n-1) of the (n-1)-th level. Figure 2 and Figure 3 The i-th level gate driving circuit 20 is taken as an example for explanation. The i-th level gate driving circuit 20 can generate and output the gate control signal Scan(i) of the current level (i-th level) according to the gate control signal Scan(i-1) of the (i-1)-th level.

[0080] It can be understood that, on the basis that the signal of one of the first node P and the second node Q electrically connected to the stage transmission output unit 2012 remains unchanged, on the one hand, in this embodiment, a stage transmission frequency division control unit 203 connected between the stage transmission receiving unit 2011 and the stage transmission output unit 2012 is provided, so that the signal of the other of the first node P and the second node Q (whether it can be acted upon by the fourth node R) can be controlled according to the frequency division control signal FD, so that the signal transmitted to the stage transmission output unit 2012 can be controlled, and then the specific situation of the stage transmission signal output by the stage transmission output unit 2012 of the current stage (whether it has a stage transmission valid pulse) is determined to determine whether to drive the next stage gate driving circuit 20. If the stage transmission signal has a stage transmission valid pulse, it can be considered that the stage transmission receiving unit 2011 in the next stage gate driving circuit 20 is not in the stage transmission receiving unit 2011. 011 can work normally. Similarly, it is combined with the level transmission frequency division control unit 203 of this level to determine the specific situation of the level transmission signal output by the level transmission output unit 2012 of this level. On the other hand, this embodiment also provides an output frequency division control unit 204 connected between the first node P, one of the second node Q and the third node S to control the signal of the third node S according to the frequency division control signal FD, so as to control the specific situation (whether there is a gate effective pulse) of the gate control signal of this level output by the output unit 202 (that is, the signal transmitted to the corresponding multiple sub-pixels Pi in the display panel to control whether the sub-pixel Pi is turned on), so as to decide whether to turn on the corresponding multiple sub-pixels Pi. If the gate control signal has a gate effective pulse, it can be considered that the corresponding multiple sub-pixels Pi can be refreshed for later light emission.

[0081] It should be understood that, for multiple gate driving circuits 20 cascaded in sequence, if the multiple gate control signals output by the multiple gate driving circuits 20 of the first part all output a gate effective pulse once in one frame in every n1 frames, the multiple gate control signals output by the multiple gate driving circuits 20 of the second part all output a gate effective pulse once in one frame in every n2 frames, and the multiple gate control signals output by the multiple gate driving circuits 20 of the third part all output a gate effective pulse once in one frame in every n3 frames, then it can be considered that the three display areas respectively constituted by the three parts of sub-pixels Pi corresponding to the three parts of the gate driving circuits 20 have three corresponding refresh rates, respectively (1 / n1)*m, (1 / n2)*m, and (1 / n3)*m, where m is the least common multiple of n1, n1, and n1.

[0082] To summarize, in the present embodiment, the gate control signal for determining the refresh rate of any display area of ​​the display panel is directly determined by the corresponding output frequency division unit and the frequency division control signal FD at this time. One input end of the output frequency division unit is connected to one of the first node P and the second node Q, and the other input end is connected to the third node S, wherein the third node S is connected to the first node P or the second node Q through the stage transmission frequency division unit, that is, it can be considered that the signal of the third node S is jointly determined by the stage transmission frequency division unit and the frequency division control signal FD loaded to the stage transmission frequency division unit, so the gate control signal is jointly determined by the stage transmission frequency division unit, the output frequency division unit, and the frequency division control signal FD loaded to the stage transmission frequency division unit and the output frequency division unit. The refresh rate of the corresponding display area can be determined by reasonably setting these three elements. Furthermore, the above three elements in the different multiple gate driving circuits 20 corresponding to different display areas of the display panel can be reasonably set to respectively achieve different refresh rates.

[0083] Among them, in this embodiment, there is no limitation on whether the stage transmission frequency division units in different gate driving circuits 20 are set differently, whether the output frequency division units are set differently, and whether the time periods during which the frequency division control signal FD is effectively effective are set differently. For the convenience of circuit design, the stage transmission frequency division units and the output frequency division units in the multi-stage gate driving circuit 20 can be set to be the same. Correspondingly, the time periods during which the frequency division control signal FD is effectively effective on different gate driving circuits 20 can be set differently to achieve differentiated settings of the refresh rates of different display areas.

[0084] In one embodiment, if Figures 1 to 3 As shown, the frequency division control signal FD includes a first frequency division control signal FD1 and a second frequency division control signal FD2, and the frequency division signal line FDL includes a first frequency division signal line FDL1 for transmitting the first frequency division control signal FD1, and a second frequency division signal line FDL2 for transmitting the second frequency division control signal FD2; wherein, the first frequency division signal line FDL is electrically connected to the output frequency division control unit 204 to control the signal of the third node S; wherein, the second frequency division signal line FDL is electrically connected to the stage transmission frequency division control unit 203 to control the signal of one of the first node P and the second node Q.

[0085] It can be understood that in this embodiment, by specifically setting the frequency division signal line FDL as an independent first frequency division signal line FDL and a first frequency division signal line FDL, independent first frequency division control signals FD1 and second frequency division control signals FD2 (which may not necessarily be the same) can be transmitted respectively, so as to independently control the working states of the output frequency division control unit 204 and the stage transmission frequency division control unit 203, thereby respectively controlling the specific conditions of the stage transmission signal and the gate signal generated by the gate drive circuit 20 of this stage.

[0086] Specifically, the effective action period of the first frequency division control signal FD1 corresponding to each level of the gate driving circuit 20 and the effective action period of the second frequency division control signal FD2 corresponding to each level of the gate driving circuit 20 can be reasonably set to meet different situations. For each level of the gate driving circuit 20, it can include but is not limited to the following situations:

[0087] Case 1: the second frequency division control signal FD2 is reasonably set so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 has a level transmission effective pulse, thereby controlling the level transmission receiving unit 2011 in the next-stage gate driving circuit 20 to work normally;

[0088] Based on situation 1, it may include but is not limited to the following situations:

[0089] Case 1.1, the first frequency division control signal FD1 is reasonably set so that the gate control signal generated and output by the output frequency division unit has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for later light emission;

[0090] Case 1.2, the first frequency division control signal FD1 is reasonably set so that the gate control signal generated and output by the output frequency division unit does not have a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi not to turn on, that is, not refreshing the corresponding multiple sub-pixels Pi for later light emission.

[0091] Furthermore, in case 1, if the time period of the effective action of the second frequency-division control signal FD2 corresponding to each stage of the gate driving circuit 20 is set so that each stage transmission signal has a stage transmission effective pulse, that is, each stage transmission signal is uninterrupted, then at this time, the first frequency-division control signal FD1 can be set to control whether each stage of the gate control signal has a gate effective pulse. Combined with the above discussion, arbitrary frequency division of multiple display areas can be achieved (the refresh rate of the latter display area can be increased or decreased compared with the former display area), that is, by controlling the relatively first and last stages of the gate control signals to have or not have gate effective pulses, or to have or not have gate effective pulses, respectively, in one frame.

[0092] Case 2: The second frequency division control signal FD2 is reasonably set so that the signal of the fourth node R cannot act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 does not have a level transmission effective pulse (determined by the signal of the first node P or the signal of the second node Q), thereby controlling the level transmission receiving unit 2011 in the next-level gate driving circuit 20 to be unable to work normally. At the same time, since the signal of the third node S connected to the source of the output unit 202 is also determined by the signal of the first node P or the signal of the second node Q, it can be considered here that the signal of the third node S will also cause the gate control signal of this level to have no gate effective pulse. Therefore, it can be considered that the gate control signal from the current level to the last level does not have a gate effective pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. Combined with the above discussion, only frequency reduction of multiple display areas can be achieved.

[0093] Case 3: The first frequency division control signal FD1 is reasonably set so that the output frequency division control unit 204 can control the third node S to be acted upon by the first node P or the second node Q, thereby enabling the output unit 202 to be acted upon by the first node P or the second node Q;

[0094] Based on situation 3, it may include but is not limited to the following situations:

[0095] Case 3.1, the second frequency division control signal FD2 is reasonably set so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 has a level transmission effective pulse, thereby controlling the level transmission receiving unit 2011 in the next-level gate driving circuit 20 to work normally. Since the signal of the first node P or the signal of the second node Q can also act on the third node S to act on the output unit 202, the gate control signal generated and output by the output frequency division unit at this time also has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for later light emission;

[0096] In case 3.2, the second frequency division control signal FD2 is reasonably set so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 does not have a level transmission effective pulse. Similarly, in "case 2", it can be seen that the signal of the first node P or the signal of the second node Q cannot invalidate the signal of the third node S, that is, it will also cause the gate control signal of this stage to have no gate effective pulse. Therefore, it can be considered that the gate control signal from the current stage to the last stage has no gate effective pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission;

[0097] Furthermore, in Case 3, if the first frequency-division control signal FD1 is set to correspond to the effective action period of each stage of the gate driving circuit 20, so that the third node S of each stage is acted upon by the first node P or the second node Q, then at this time, the second frequency-division control signal FD2 can be set to control whether the signal of the fourth node R acts on the signal of the first node P or the signal of the second node Q, so as to control whether the stage transfer signal generated and output by each stage transfer frequency-division control unit 203 has a stage transfer effective pulse. Combined with the above discussion, frequency reduction of multiple display areas can be achieved.

[0098] Case 4: The first frequency division control signal FD1 is reasonably set so that the output frequency division control unit 204 cannot control the third node S to be affected by the first node P or the second node Q, thereby preventing the output unit 202 from being affected by the first node P or the second node Q. That is, no matter what the signal of the first node P and the signal of the second node Q are, the first frequency division control signal FD1 will act on the output frequency division control unit 204, so that the signal of the third node S will cause the gate control signal of this stage to have no gate effective pulse. Therefore, it can be considered that the gate control signal from the current stage to the last stage has no gate effective pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. Combined with the above discussion, only frequency reduction of multiple display areas can be achieved.

[0099] In one embodiment, if Figures 1 to 3 As shown, the output frequency division control unit 204 includes: a first frequency division transistor T18, the gate of the first frequency division transistor T18 is connected to the first frequency division signal line FDL, the source of the first frequency division transistor T18 is electrically connected to the first node P or the second node Q, and the drain of the control transistor is electrically connected to the third node S; wherein, the first frequency division control signal FD1 is used to control the third node S to be electrically connected or disconnected with the first node P or the second node Q.

[0100] Among them, combined with the above discussion, it can be known that the first frequency division control signal FD1 can act on the output frequency division control unit 204 to control whether the third node S is affected by the first node P or the second node Q. Furthermore, this embodiment describes that the first frequency division control signal FD1 can act on the gate of the first frequency division transistor T18 in the output frequency division control unit 204 to control the third node S to be electrically connected or disconnected with the first node P or the second node Q.

[0101] Specifically, if electrically connected, it can be considered that the third node S can be affected by the first node P or the second node Q, which is equivalent to that the signal of the first node P or the signal of the second node Q can control whether the gate control signal generated and output by the output unit 202 has a gate effective pulse (i.e., the above-mentioned situation 3); if disconnected, it can be considered that the third node S cannot be affected by the first node P or the second node Q. Since the first node P or the second node Q used to control the generation of the level transfer signal cannot act on the output unit 202, it can be considered that the gate control signal generated and output by the output unit 202 does not have a gate effective pulse (i.e., the above-mentioned situation 4).

[0102] In one embodiment, if Figures 1 to 3 As shown, the output frequency division control unit 204 also includes: a second frequency division transistor T20, the gate of the second frequency division transistor T20 is electrically connected to the fifth node of the stage transmission unit 201, the source of the second frequency division transistor T20 is electrically connected to the first frequency division signal line FDL, and the drain of the second frequency division transistor T20 is electrically connected to the gate of the first frequency division transistor T18; wherein, the first frequency division control signal FD1 and the signal of the fifth node are used to control the electrical connection or disconnection of the third node S with the first node P or the second node Q; wherein, the signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of this stage.

[0103] It can be understood that in the present embodiment, a second frequency-dividing transistor T20 electrically connected to the gate of the first frequency-dividing transistor T18 is further provided, and the opening state of the second frequency-dividing transistor T20 is determined by the signal of the fifth node, and the signal of the fifth node is also used to control the level transmission signal and the gate control signal output by this stage, that is, it can be considered that the state of the signal of the fifth node can feedback the state of both the level transmission signal and the gate control signal of this stage, so as to ensure that the opening of the second frequency-dividing transistor T20 is controlled only when the state of both the level transmission signal and the gate control signal generated by this stage is appropriate, thereby making the first frequency-dividing control signal FD1 transmitted to the gate of the first frequency-dividing transistor T18 of this stage to control the opening state of the first frequency-dividing transistor T18, and taking into account the premise that the level transmission signal and the gate control signal output of each stage are correct waveforms, so as to realize the differentiated setting of the refresh rate of different display areas.

[0104] It should be noted that, in this embodiment, the specific connection relationship between the fifth node and the above-mentioned module is not limited, and it is only necessary to satisfy the above-mentioned limitation that "the signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of this stage". For example, the fifth node can be electrically connected to the first node P or the second node Q, and even the fifth node can be the first node P or the second node Q. In the present invention, the fifth node is taken as the node D for explanation (based on Figure 2 , Figure 3 The second frequency dividing transistors T20 in the embodiment are respectively a P-type transistor and an N-type transistor, both of which can be referred to in the following text about Fig.10 analysis).

[0105] Specifically, in conjunction with the following Figure 2 and Fig.10 It can be seen from the analysis that the level transfer signal generated by this stage has a level transfer effective pulse (that is, the signal of the first node P and the signal of the second node Q are both effective signals). If the gate control signal of this stage needs to output a gate effective pulse, it can be considered that the signal of the fifth node can ensure that the gate effective pulse of this stage is completely output at the time node (for example, Fig.10 The voltage after the fifth node (the end point of the fifth stage t5) can be used to control the first frequency-division control signal FD1 to be transmitted to the gate of the first frequency-division transistor T18 of this stage. For example, the second frequency-division transistor T20 is a P-type transistor, then it can be considered that the voltage of the fifth node is respectively a higher voltage and a lower voltage before and after the time node when the gate effective pulse of this stage is completely output, so as to ensure that the second frequency-division transistor T20 will not be turned on until the gate effective pulse of this stage is completely output.

[0106] In particular, if the gate control signal of this stage does not need to output a gate effective pulse, it can be seen from the above discussion that the starting point (voltage jump) of the first frequency division control signal FD1 corresponding to the effective action period of this stage can be set at the time when the voltage corresponding to the gate effective pulse of this stage starts to be output in the signal of the fifth node (for example, Fig.10 Before the starting time of the third stage t3 in the process, it is ensured that the electrical connection between the third node S and the first node P or the second node Q is cut off before the gate effective pulse of this stage is output.

[0107] In one embodiment, if Figures 1 to 3As shown, the stage transmission frequency division control unit 203 includes: a third frequency division transistor T17, the gate of the third frequency division transistor T17 is electrically connected to the second frequency division signal line FDL, the source of the first frequency division transistor T18 is electrically connected to the stage transmission receiving unit 2011 through the fourth node R, and the drain of the third frequency division transistor T17 is electrically connected to the first node P or the second node Q; wherein, the second frequency division control signal FD2 is used to control the fourth node R to be electrically connected or disconnected with the first node P or the second node Q.

[0108] Among them, combined with the above discussion, it can be known that the second frequency division control signal FD2 can act on the stage transmission frequency division control unit 203 to control whether the first node P or the second node Q is affected by the fourth node R. Furthermore, this embodiment describes that the second frequency division control signal FD2 can act on the gate of the third frequency division transistor T17 in the stage transmission frequency division control unit 203 to control the fourth node R to be electrically connected or disconnected with the first node P or the second node Q.

[0109] Specifically, if they are electrically connected, it can be considered that the first node P or the second node Q can be affected by the fourth node R, which is equivalent to that the signal of the fourth node R can control whether the level transmission signal generated and output by the level transmission output unit 2012 has a level transmission valid pulse (i.e., the above-mentioned situation 1); if they are disconnected, it can be considered that the first node P or the second node Q cannot be affected by the fourth node R, because the fourth node R used to control the level transmission signal generated by this level cannot act on the level transmission output unit 2012, it can be considered that the level transmission signal generated and output by the level transmission output unit 2012 does not have a level transmission valid pulse (i.e., the above-mentioned situation 2).

[0110] In one embodiment, if Figure 2 and Figure 3 As shown, the stage transmission output unit 2012 includes: a first-stage transmission output transistor T10, the gate of the first-stage transmission output transistor T10 is electrically connected to the first node P, the source of the first-stage transmission output transistor T10 is electrically connected to the first voltage line to load the first voltage VGH, and the drain of the first-stage transmission output transistor T10 is electrically connected to the stage transmission output terminal OUT in the gate driving circuit 20 for outputting the stage transmission signal; a second-stage transmission output transistor T9, the gate of the second-stage transmission output transistor T9 is electrically connected to the second node Q, the source of the second-stage transmission output transistor T9 is electrically connected to the second voltage line to load the second voltage VGL, and the drain of the second-stage transmission output transistor T9 is electrically connected to the stage transmission output terminal OUT.

[0111] Specifically, the first node P can control the opening of the first-stage transmission output transistor T10 to control whether the first voltage can be transmitted to the stage transmission output terminal OUT, and the second node Q can control the opening of the second-stage transmission output transistor T9 to control whether the second voltage can be transmitted to the stage transmission output terminal OUT. In combination with the above discussion, it can be seen that in the present invention, by setting a third frequency-dividing transistor T17 connected between the fourth node R and the first node P or the second node Q to control whether the first node P or the second node Q can receive the signal of the fourth node R, the opening of the first output transistor T22 or the opening of the second output transistor T21 is controlled, thereby controlling the specific situation of the stage transmission signal generated and output by the stage transmission output terminal OUT.

[0112] For example, when the first-level transmission output transistor T10 is turned on and the second-level transmission output transistor T9 is turned off, the gate control signal can be equal to the first voltage; for another example, when the first-level transmission output transistor T10 is turned off and the second-level transmission output transistor T9 is turned on, the generated level transmission signal can be equal to the second voltage; for another example, when both are turned off, the generated level transmission signal can be equal to the previous voltage; for another example, when both are turned on, the generated level transmission signal can be between the first voltage and the second voltage.

[0113] In one embodiment, if Figure 2 and Figure 3 As shown, the output unit 202 includes: a first output transistor T22, the gate of the first output transistor T22 is electrically connected to the third node S, the source of the first output transistor T22 is electrically connected to the first voltage line, and the drain of the first output transistor T22 is electrically connected to the gate output terminal OUTA in the gate driving circuit 20 for outputting the gate control signal; a second output transistor T21, the gate of the second output transistor T21 is electrically connected to the first node P or the second node Q, the source of the second output transistor T21 is electrically connected to the second voltage line, and the drain of the second output transistor T21 is electrically connected to the gate output terminal OUTA.

[0114] Similarly, as discussed above, the third node S can control the opening of the first output transistor T22 to control whether the first voltage can be transmitted to the gate output terminal OUTA, and the first node P or the second node Q can control the opening of the second output transistor T21 to control whether the second voltage can be transmitted to the gate output terminal OUTA. In combination with the above discussion, it can be seen that in the present invention, by setting a first frequency dividing transistor T18 connected between the third node S and the first node P or the second node Q to control whether the third node S can receive the signal of the first node P or the second node Q, the opening of the first output transistor T22 or the opening of the second output transistor T21 is controlled, thereby controlling the specific situation of the gate control signal generated and output by the gate output terminal OUTA.

[0115] In one embodiment, the gate driving circuit 20 is electrically connected to at least one corresponding pixel driving circuit 302, the gate output terminal OUTA is electrically connected to a corresponding pixel transistor in each of the pixel driving circuits 302, and the first voltage is greater than the second voltage; wherein, Figure 2 As shown, the pixel transistor is an N-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are both electrically connected to the first node P (at this time, the gate driving circuit 20 can be considered to be the i-th stage NScan circuit, the gate control signal generated is the NScano(i) signal, the stage transmission signal is the NScan(i) signal, and the stage transmission signal of the previous stage is the NScan(i-1) signal); or Figure 3 As shown, the pixel transistor is a P-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are electrically connected to the second node Q (at this time, the gate drive circuit 20 can be considered to be the i-th level PScan circuit, the gate control signal generated is the PScano(i) signal, the level transmission signal is the PScan(i) signal, and the level transmission signal of the previous level is the PScan(i-1) signal).

[0116] In this embodiment, the structure of the pixel driving circuit 302 is not limited. It can be considered that the pixel transistor K can control the opening state of the corresponding sub-pixel Pi under the control of the gate control signal output by the gate driving circuit 20. Specifically, in this embodiment, based on the fact that the first voltage is greater than the second voltage, when the pixel transistor is an N-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are electrically connected to the first node P, so that the opening status of both the first-stage transmission transistor T10 and the first output transistor T22 can be controlled to control whether the larger first voltage (which can be the effective voltage of the N-type transistor) can be transmitted to the gate of the N-type pixel transistor, thereby controlling whether the corresponding sub-pixel Pi is turned on; when the pixel transistor is a P-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are electrically connected to the second node Q, so that the opening status of the second-stage transmission transistor T9 and the second output transistor T21 can be controlled to control whether the smaller second voltage (which can be the effective voltage of the P-type transistor) can be transmitted to the gate of the P-type pixel transistor, thereby controlling whether the corresponding sub-pixel Pi is turned on.

[0117] According to the above discussion, if the duration of the effective voltage required to turn on the N-type or P-type pixel transistor is equal, it can be considered that in the NScano signal and PSScano signal output by the NScan circuit and the PScan circuit respectively, the voltage value of the gate effective pulse of the former (for example but not limited to being equal to the first voltage) is greater than the voltage value of the gate effective pulse of the latter (for example but not limited to being equal to the second voltage), and the pulse width of the gate effective pulses of the two can be equal.

[0118] Furthermore, since the level transmission receiving unit 2011 can receive the level transmission signal generated by the upper level, according to the level transmission function of the level transmission signal, the first start signal STV1 and the second start signal STV2 respectively loaded to the NScan circuit of the first level and the PScan circuit of the first level can also be obtained by translating the level transmission signals (NScan(1), PScan(1)) generated by the respective first-level gate driving circuits 20 along the negative direction of the time axis by the same distance, that is, the voltage values ​​of the level transmission effective pulses of the two can be equal to the first voltage and the second voltage respectively. Among them, the first start signal STV1, the second start signal STV2, the NScano signal, the PScano signal, the NScan signal and the PScan signal can all be periodic signals.

[0119] In one embodiment, if Figure 2 and Figure 3As shown, the stage transmission receiving unit 2011 includes: a fourth node control unit 20111, which is electrically connected to the clock signal line (including but not limited to the first clock signal line CKL1 and the second clock signal line CKL2, the first clock signal XCK and the second clock signal line CKL2CK loaded respectively on the two can be symmetrical about the time axis, and the voltage value of the intersection of the time axis and the voltage axis is not limited here, and both can include two different voltage values) and the fourth node R, and is used to control the signal of the fourth node R according to the clock signal transmitted by the clock signal line; a second node control unit 20112 (such as Figure 2 As shown) or the first node control unit 20113 (as shown Figure 3 As shown), the second node control unit 20112 is electrically connected to the clock signal line and the second node Q, and is used to control the signal of the second node Q according to the clock signal, the first node control unit 20113 is electrically connected to the clock signal line and the first node P, and is used to control the signal of the one node according to the clock signal; an input unit 20114, the input end of the input unit 20114 is electrically connected to the gate drive circuit 20 of the upper level to load the level transmission signal generated by the gate drive circuit 20 of the upper level, and the output end of the input unit 20114 is electrically connected to the fourth node control unit 20111 and the second node control unit 20112, or is electrically connected to the fourth node control unit 20111 and the first node control unit 20113.

[0120] It should be noted that, for the sake of convenience in description, the schematic diagram of the present invention only takes the second-stage transmission transistor T9 as an example of being located below the first-stage transmission transistor T10 (that is, the second node Q is located below the first node P for illustration, and similarly, the second output transistor T21 is located below the first output transistor T22 as an example. In fact, the present invention protects the connection relationship of multiple electronic devices and is not limited to the position relationship. Based on the input unit 20114 loading the stage transmission signal generated by the upper gate drive circuit 20, such as Figure 2 As shown, for the NScan circuit, since the stage transmission and frequency division control unit 203 is connected to the first node P located at the top, it can be considered that the fourth node R is also set at the top. At this time, it can be considered that the fourth node control unit 20111 needs to be set near the top to control the voltage of the fourth node R (further combined with the stage transmission and frequency division control unit 203 to control the voltage of the first node P), and the voltage of the second node Q needs to be set near the bottom The second node control unit 20112 is controlled; Figure 3As shown, for the PScan circuit, since the stage transmission and frequency division control unit 203 is connected to the second node Q located at the bottom, it can be considered that the fourth node R is also set at the bottom. At this time, it can be considered that the fourth node control unit 20111 is also needed to be set near the bottom to control the voltage of the fourth node R (further combined with the stage transmission and frequency division control unit 203 to control the voltage of the second node Q), and the voltage of the first node P needs to be controlled by the first node control unit 20113 set near the top.

[0121] In one embodiment, if Figure 2As shown, the stage transmission frequency division control unit 203 and the output frequency division control unit 204 are both electrically connected to the first node P (that is, the gate driving circuit 20 is taken as an NScan circuit for example); the input unit 20114 includes an input transistor T3, the gate of the input transistor T3 is loaded with the clock signal (for example, the first clock signal line CKL1 is connected to load the first clock signal), the source of the input transistor T3 is configured as the input end of the input unit 20114, and the drain of the input transistor T3 is configured as the output end of the input unit 20114. The fourth node control unit 20111 includes a first transistor T4, a seventh transistor T5, a second transistor T6 and a third transistor T7 which are arranged in series, the gate of the seventh transistor T5 is electrically connected to the drain of the input transistor T3, the source of the seventh transistor T5 is loaded with the clock signal (for example, the first clock signal), the gate of the first transistor T4 is loaded with the clock signal (for example, the first clock signal), the source of the first transistor T4 is loaded with the second voltage, the drain of the first transistor T4 is electrically connected to the gate of the second transistor T6 and the drain of the seventh transistor T7. The drain of the second transistor T5, the drain of the second transistor T6 is electrically connected to the source of the third transistor T7, the source of the second transistor T6 and the gate of the third transistor T7 are both loaded with the clock signal, and the drain of the third transistor T7 is electrically connected to the fourth node R; the second node control unit 20112 includes a fourth transistor T13, a first capacitor C1, a fifth transistor T1 and a sixth transistor T2 arranged in series, the gate of the fourth transistor T13 (electrically connected to the control line CL) is loaded with the control signal, and the source of the fourth transistor T13 is loaded with the clock signal. The first voltage is applied to the drain of the fourth transistor T13, the drain of the fourth transistor T13 is electrically connected to the second node Q, the gate of the fifth transistor T1 is electrically connected to the drain of the first transistor T4, the source of the fifth transistor T1 is loaded with the first voltage, the drain of the fifth transistor T1 is electrically connected to the source of the sixth transistor T2, the drain of the sixth transistor T2 is loaded with the clock signal, the gate of the sixth transistor T2 is also loaded with the stage transmission signal generated by the upper gate driving circuit 20, and the first capacitor C1 is electrically connected between the gate and the drain of the sixth transistor T2.

[0122] Among them, in the present invention, the transistors in the gate drive circuit 20 are all P-type transistors as an example, and the operation of some signals in some states is explained: when the power is turned on, the control signal transmitted by CL can control the fourth transistor T13 to turn on to transmit the first voltage to the second node Q; later, when the voltage is low in the first clock signal and the voltage is low in the (i-1)th level gate control signal NScano(i-1), the gate control signal NScano(i-1) controls both the seventh transistor T5 and the second output transistor T21 to turn on, and the second voltage is transmitted to the level transmission output terminal OUT through the second output transistor T21, and the first clock signal controls the first transistor T4 to turn on, and the second voltage is transmitted to the gate of the second transistor T6 to control it to turn on, at this time, the high voltage in the second clock signal controls the third transistor T7 to turn off; later, when the voltage is high in the first clock signal, the input transistor T3, the second transistor T6 and the first transistor T4 are turned off, at this time, it can be considered that the second output transistor T21 remains turned on, the low voltage in the second clock signal controls the third transistor T7 to turn on, the fourth node R is still not loaded with voltage, and the level transmission output terminal OUT still outputs the second voltage.

[0123] It should be noted that the present invention does not limit the type of each transistor in the gate drive circuit 20. For example, they can all be P-type transistors, or some can be N-type transistors and the other can be P-type transistors. The corresponding signals can also be matched and set according to the type of transistor. For details, please refer to the full text for the principle explanation of "all transistors in the gate drive circuit 20 are P-type transistors".

[0124] Furthermore, the fourth node control unit 20111 may also include an eighth transistor T11 and a second capacitor C2, the second node control unit 20112 may also include a ninth transistor T12, the stage transmission output unit 2012 may also include a third capacitor C3 electrically connected between the gate and the source of the first output transistor T22, the gate of the eighth transistor T11 and the gate of the ninth transistor T12 may both be loaded with a second voltage to maintain opening, the source and the drain of the eighth transistor T11 are respectively electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6, the second capacitor C2 is electrically connected between the gate and the drain of the second transistor T6, and the source and the drain of the ninth transistor T12 are respectively electrically connected to the drain of the input transistor T3 and the second node Q.

[0125] Among them, the first capacitor C1, the second capacitor C2 and the third capacitor C3 can be used to maintain the voltage of the corresponding nodes and play a coupling role. The eighth transistor T11 and the ninth transistor T12 can respectively ensure that they are turned on only when the source voltage of the two is low enough to maintain the drain of the two to have a lower voltage, which is beneficial to the turning on of the first output transistor T22 and the second output transistor T21.

[0126] In one embodiment, if Figure 2 As shown, the second node control unit 20112 also includes: a tenth transistor T14, the source of which is loaded with the stage transmission signal generated by the upper gate driving circuit 20, the gate of which is loaded with the clock signal (first clock signal), and the drain of which is electrically connected to the gate of the sixth transistor T2; an eleventh transistor T16, the gate and source of which are both electrically connected to the gate of the sixth transistor T2, and the drain of which is electrically connected to the second node Q. Similarly, a twelfth transistor T15 for maintaining the gate of the sixth transistor T2 with a lower voltage may also be provided, the gate of which may be loaded with the second voltage, and the source and drain of which may be electrically connected to the drain of the tenth transistor T14 and the gate of the sixth transistor T2, respectively.

[0127] It can be understood that in this embodiment, the second node control unit 20112 is also provided with the above-mentioned tenth transistor T14 and eleventh transistor T16. The tenth transistor T14 can be used to control the voltage of the gate of the sixth transistor T2. At the same time, by further providing the eleventh transistor T16 connected between the second node Q and the gate of the sixth transistor T2, the second node Q is not directly electrically connected to the first capacitor C1 to avoid being coupled by the first capacitor C1, and the second node Q can be maintained at a lower voltage.

[0128] It should be noted that, compared Figure 3 and Figure 2It can be seen that the PScan circuit is different from the NScan circuit in that one difference is the difference between the second start signal STV2 and the first start signal STV1 as discussed above, and the specific structures of the input unit 20114 and the output unit 202 of the two circuits can be the same, and another difference is that the NScan circuit needs to include a fourth node control unit 20111 and a second node control unit 20112, while the PScan circuit needs to include a fourth node control unit 20111 and a first node control unit 20113. Among them, the specific structure of the fourth node control unit 20111 in the NScan circuit can be the same as the specific structure of the first node control unit 20113 in the PScan circuit, the difference is that the output end of the former is connected to the first node P through the stage transmission and frequency division control unit 203, and the output end of the latter is directly connected to the first node P; similarly, the specific structure of the second node control unit 20112 in the NScan circuit can be the same as the specific structure of the third node S control unit in the PScan circuit, the difference is that the output end of the former is directly connected to the second node Q, and the output end of the latter is connected to the second node Q through the stage transmission and frequency division control unit 203.

[0129] Furthermore, the gate drive circuit 20 in the present invention can also be but not limited to an EM circuit. The difference between the EM circuit and the NScan circuit is that the first start signal STV1 is replaced by the third start signal STV3. The third start signal STV3 can be understood as the first start signal STV1 being shifted a certain distance along the negative or positive direction of the time axis, and the waveforms of the two do not overlap. Similarly, the third start signal STV3 can also be a periodic signal.

[0130] The present invention provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0131] In one embodiment, in combination Figures 4 to 7 As shown, the display panel 100 includes: a gate driving module 10 as described in any one of the above; a panel body 30, including a plurality of sub-pixels Pi and a plurality of scanning lines SL, the plurality of sub-pixels Pi including a light-emitting device 301 and a pixel driving circuit 302 for driving the light-emitting device 301 to emit light, the pixel driving circuit 302 including at least one transistor (i.e., the pixel transistor discussed above); wherein the gate control signal output by the gate driving circuit 20 is transmitted to the gates of the plurality of transistors in the corresponding plurality of pixel driving circuits 302 via the corresponding scanning lines.

[0132] in, Figure 4In the figure, a display panel 100 including six gate driving modules 10 (GOA1, GOA2, two GOA3, GOA4, GOA5, electrically connected to the corresponding sub-pixels Pi through the first scan line EML1, the second scan line NSL1, the third scan line PSL, the fourth scan line NSL2, and the fifth scan line EML2) is used as an example for explanation: for example, the two GOA3s may be but are not limited to the same PScan circuit, that is, the signals loaded by the two (the second start signal STV2) and the output signals may be the same, so as to improve the reliability of the PScan signals output by the two; for example, GOA1 and GOA5 may be two different EM circuits, for example, the two third start signals STV3 corresponding to the two may be different (for example, but not limited to, the pulse width and / or starting time of the effective pulses of the two may be different); for example, GOA2 and GOA4 may be two different NScan circuits, for example, the two first start signals STV1 corresponding to the two may be different (for example, but not limited to, the pulse width and / or starting time of the effective pulses of the two may be different).

[0133] Figure 5 and Figure 4 The difference is that the six gate driving modules 10 include two GOA1', GOA2', two GOA3', and GOA4', which are electrically connected to the corresponding sub-pixels Pi through the sixth scan line EML', the seventh scan line NSL1', the eighth scan line PSL1', and the ninth scan line NSL2' respectively. Similarly, the two GOA1's can be but not limited to the same EM circuit, GOA2' and GOA4' can be two different NScan circuits respectively, for example, the two first start signals STV1 corresponding to the two can be different, and the two GOA3s can be but not limited to the same PScan circuit.

[0134] It should be noted that Figure 4 and Figure 5 Only the connection relationship between the multiple gate driving circuits 20 in the same gate module and the connection relationship between each of them and the multiple sub-pixels Pi are shown. As for the signal lines connected to each gate driving circuit 20, please refer to Figures 1 to 3 And the relevant text description above.

[0135] Specific, combined Figure 4 and Figure 6 As shown, Figure 6 include Figure 4The pixel driving circuit 302 corresponding to the setting method of the gate driving module 10 in the figure may include a data transistor M2, the source of the data transistor M2 is loaded with a data signal Vdata, the drain of the data transistor is electrically connected to the source of the driving transistor M1, and the gate of the data transistor M2 (for example, a P-type transistor) can be electrically connected to the third scan line PSL to load a PScan signal.

[0136] Among them, the pixel driving circuit 302 can also include a reset transistor M4 and a compensation transistor M3, the gate of the reset transistor M4 (for example, an N-type transistor) can be electrically connected to the scan line NSL1 to load the NScan1 signal, the reset transistor M4 is configured to transmit the reset signal VI1 to the gate of the driving transistor M1 for resetting, the gate of the compensation transistor M3 (for example, an N-type transistor) can be electrically connected to the fourth scan line NSL2 to load the NScan2 signal, and the source and drain of the compensation transistor M3 are respectively electrically connected to the drain and gate of the driving transistor M1.

[0137] Among them, the pixel driving circuit 302 may also include an initialization transistor M7, the gate of the initialization transistor M7 (for example, a P-type transistor) is electrically connected to the fifth scan line EML2 to load the EM2 signal, the drain of the initialization transistor M7 is electrically connected to one end of the light-emitting device 301 (the other end of the light-emitting device 301 can be loaded with a low voltage signal VSS), and the initialization transistor M7 is configured to transmit the initialization signal VI2 to one end of the light-emitting device 301 for initialization.

[0138] Among them, the pixel driving circuit 302 also includes a reset transistor M8, the gate of the reset transistor M8 (for example, a P-type transistor) can be electrically connected to the fifth scan line EML2 to load the EM2 signal, the drain of the reset transistor M8 is electrically connected to the source of the driving transistor M1, and the reset transistor M8 is configured to transmit the reset signal VI3 to the source of the driving transistor M1 to reset its voltage.

[0139] Among them, the pixel driving circuit 302 may also include a first light-emitting control transistor M5 and a second light-emitting control transistor M6, the source of the first light-emitting control transistor M5 is loaded with a first high voltage VDD, the drain of the first light-emitting control transistor M5 is electrically connected to the source of the driving transistor M1, the source and drain of the second light-emitting control transistor M6 are electrically connected to the drain of the driving transistor M1 and one end of the light-emitting device 301, respectively, and the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 (for example, both are P-type transistors) are electrically connected to the first scanning line EML1 to load the EM1 signal, and are both configured to control the light-emitting moment of the light-emitting device 301 according to the EM1 signal.

[0140] The pixel driving circuit 302 further includes a storage capacitor Cst, and the storage capacitor Cst is connected in series between the source of the first light emitting control transistor M5 and the gate of the driving transistor M1.

[0141] The pixel driving circuit 302 further includes a boost capacitor Cboost, and the boost capacitor Cboost is connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.

[0142] Based on the above discussion, if Figure 8 As shown, Figure 8 for Figure 7 According to the timing diagram corresponding to the pixel driving circuit 302 in FIG. 1 , the writing frame WF of the display panel may include a first reset phase tim1, a second reset phase tim2, a data writing phase tim3 and a light emitting phase tim4. The specific working process is as follows:

[0143] In the first reset stage tim1, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2, and the input end, output end and control end source, drain and gate of the driving transistor M1 can be reset according to the reset signal VI3;

[0144] In the second reset phase tim2, the reset transistor M4 is turned on according to the corresponding NScano1 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate and drain of the driving transistor M1 are reset according to the initialization signal VI2;

[0145] In the data writing phase tim3, the data transistor M2 is turned on according to the corresponding PScano signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate of the driving transistor M1 can be written with the data signal Vdata;

[0146] In the light emitting stage tim4, the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on according to the EMo1 signal, so that the driving transistor M1 generates a driving current to drive the corresponding light emitting device 301 to emit light;

[0147] Furthermore, a third reset stage tin may be included between the light-emitting stage tim4 and the data writing stage tim3. In the third reset stage tin, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2, and the source and drain of the driving transistor M1 can be reset according to the reset signal VI3.

[0148] It should be noted that Figure 5 and Figure 4 The difference in the gate drive module 10 settings can be seen, combined with Figure 5 and Figure 7 As shown, Figure 7 include Figure 5 The pixel driving circuit 302 corresponding to the gate driving module 10 configuration mode in FIG. Figure 7 can only be driven by the same EM circuit, so it can only be electrically connected to the same sixth scan line EML' and loaded with the same signal (and cannot be like Figure 6 The first scan line EML1 and the fifth scan line EML2 may be electrically connected to the first scan line EML1 and the fifth scan line EML2 to be loaded with two different signals).

[0149] Specifically, Figure 7 As shown, compared Figure 6 The difference is that the reset transistor M8 is removed, the first scan line EML1 is replaced by the sixth scan line EML', the second scan line NSL1 is replaced by the seventh scan line NSL1', the third scan line PSL is replaced by the eighth scan line PSL1', the fourth scan line NSL2 is replaced by the ninth scan line NSL2', and the fifth scan line EML2 is also replaced by the eighth scan line PSL1' of the previous level.

[0150] Based on the above discussion, if Fig. 9 As shown, Fig. 9 for Figure 7 The timing diagram corresponding to the pixel driving circuit 302 in FIG. 1 , the writing frame WF of the display panel may include a first reset phase tim1 ', a second reset phase tim2 ', a data writing phase tim3 ' and a light emitting phase tim4 '. Taking the i-th level gate driving circuit 20 as an example, the specific working process is as follows:

[0151] In the first reset phase tim1′, the reset transistor M4 is turned on according to the corresponding NScano1′(i) signal, so that the gate of the driving transistor M1 is reset according to the initialization signal VI1;

[0152] In the second reset phase tim2', the initial transistor M7 is turned on according to the corresponding PScano1'(i-1) signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the compensation transistor M3 is turned on according to the corresponding NScano1'(2) signal;

[0153] In the data writing phase tim3', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal, and the compensation transistor M3 is turned on according to the corresponding NScano2'(i) signal, so that the gate of the driving transistor M1 can be written with the data signal Vdata;

[0154] In the third reset stage tim4', the initial transistor M7 is turned on according to the corresponding PScano1'(i-1) signal, so that the anode of the light emitting device 301 is reset again according to the initialization signal VI2;

[0155] In the coupling stage tim5', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal. At this time, no matter what the data signal Vdata is, since the compensation transistor M3 is turned off, it will not affect the gate voltage of the driving transistor M1. However, since the gate voltage of the data transistor M2 is reduced, the gate voltage of the driving transistor M1 will also increase.

[0156] In the light-emitting stage tim6', the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on according to the EMo'(i) signal, so that the driving transistor M1 generates a driving current to drive the corresponding light-emitting device 301 to emit light. Since the gate voltage of the driving transistor M1 in the coupling stage tim5' rises to a value greater than the data voltage given by the data signal Vdata in the data writing stage tim3', the light-emitting device 301 will have a greater brightness, and it can also be considered that the upper limit of the data voltage can be effectively reduced, thereby saving power consumption.

[0157] According to the above analysis, in the writing frame WF, in order to realize the normal light emission of each row of sub-pixels Pi, that is, each level of gate driving circuit 20 (each of GOA1 to GOA5, each of GOA1' to GOA4') needs to output the corresponding gate effective pulse in the corresponding time period to control the corresponding transistor in the pixel driving circuit 302 to turn on, so as to realize the corresponding function to turn on the sub-pixel Pi. It can also be considered that if the gate driving circuit 20 cannot output the corresponding gate effective pulse in the corresponding time period, the sub-pixel Pi of the corresponding row will not be able to emit light.

[0158] like Figure 6 and Figure 7As shown, if the PScano signal and the PScano1'(i) signal do not have a gate effective (low voltage) pulse, the data transistor M2 cannot be turned on, which will cause the data signal to be unable to be written into the source of the driving transistor M1 and the sub-pixel Pi will be unable to be turned on; if the EM1 signal and the EMo'(i) signal do not have a gate effective (low voltage) pulse, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 cannot be turned on, which will cause the driving current to be unable to be formed and the sub-pixel Pi will be unable to be turned on; if the NScano2 signal and the NScano2'(i) signal do not have a gate effective (high voltage) pulse, the compensation transistor M3 cannot be turned on, which will cause the data signal to be unable to be written into the gate of the driving transistor M1 and the sub-pixel Pi will be unable to be turned on. Of course, if the EMo2 signal, the NScano1 signal, and the NScano1'(i) signal do not have a valid pulse, it will also have a certain impact on the luminescence of the sub-pixel Pi.

[0159] Specifically, based on Figure 6 The pixel driving circuit 302 shown in the figure, at least one of the three gate driving circuits 20 for generating the PScano signal, the EMo1 signal, and the NScano2 signal in the present invention, can be provided with the stage transmission frequency division control unit 203 and the output frequency division control unit 204 discussed above, based on Figure 7 The pixel driving circuit 302 shown in the present invention, at least one of the three gate driving circuits 20 for generating the PScano1'(i) signal, the EMo'(i) signal, and the NScano2'(i) signal, respectively, can be provided with the stage transmission frequency division control unit 203 and the output frequency division control unit 204 discussed above; thus, based on the premise that the start signal (for example, the first start signal STV1, the second start signal STV2, and the third start signal STV3) in the first stage gate driving circuit 20 has been set, in each frame, and in combination with the setting of the frequency division control signal FD (refer to the discussion of the above cases 1 to 4), the first node P (for Figure 2 for the second node Q (for Figure 3 whether the third node S is electrically connected to the first node P (for Figure 2 for the second node Q (for Figure 3 For example, the output gate control signal may have or not have a gate effective pulse to control whether the sub-pixel Pi of the corresponding row is turned on (refreshed).

[0160] In one embodiment, if Figure 4 and Figure 5As shown, the display panel is in a frequency reduction mode and a frequency increase mode in a time-sharing manner, and the plurality of gate driving circuits 20 include a plurality of cascaded first gate driving circuits 2001 and a plurality of cascaded second gate driving circuits 2002 cascaded after the plurality of first gate driving circuits 2001; wherein, the plurality of sub-pixels Pi include a plurality of first sub-pixels Pi1 electrically connected to the plurality of first gate driving circuits 2001 and a plurality of second sub-pixels Pi2 electrically connected to the plurality of second gate driving circuits 2002, the plurality of first sub-pixels Pi constitute a first display area, and the plurality of second sub-pixels Pi constitute a second display area; in the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area; in the frequency increase mode, the refresh rate of the first display area is less than the refresh rate of the second display area.

[0161] In combination with the above discussion, it can be seen that the present invention can control whether the level transmission signal generated by this stage has a level transmission valid pulse and whether the gate control signal has a gate valid pulse by setting the above-mentioned level transmission frequency division control unit 203 and output frequency division control unit 204 in the gate driving unit.

[0162] Specifically, here Figure 2 As an example, the i-th level NScan circuit shown here is based on Figure 2 The transistors in are all P-type transistors (i.e., low voltage is effective), the third frequency-dividing transistor T17 is turned on (i.e., the second frequency-dividing control signal FD2 is at its lower voltage), the first clock signal line CKL1 and the second clock signal line CKL2 transmit the first clock signal and the second clock signal respectively, and the combination Fig. 9 The working timing of the NScan circuit shown is described, which may include but is not limited to the following 6 working stages t1 to t6.

[0163] In the first stage t1, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transfer signal NScan(i-1) generated in the previous stage is set low: the third transistor T7 is in a closed state according to the second clock signal line CK; the first transistor T4, the input transistor T3 and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low stage transfer signal NScan(i-1) is transmitted to the node D, the second node Q and the node F, so that the seventh transistor T5, the thirteenth transistor T8, the second stage transmission transistor T9, the sixth transistor T2 and the eleventh transistor T16 are turned on according to NScan(i-1), the second voltage VGL is transmitted to the node C and the node B, and the high second clock signal line CK is transmitted to the node E, The first voltage VGH is transmitted to the node P (the fourth node R), so that the second transistor T6 and the fifth transistor T1 are turned on according to the second voltage VGL, and the high second clock signal line CK is transmitted to the node A to charge the second capacitor C2 to a voltage difference between the node A and the node B. The first voltage VGH is transmitted to the node E (the voltage of the node E may be between the first voltage VGH and the high voltage of the second clock signal line CK to charge the first capacitor C1 to a voltage difference between the node E and the node F, so that the voltage of the node F is coupled and increased. Since the first-stage transmission output transistor T10 is turned off and the second-stage transmission output transistor T9 is turned on, the generated gate control signal NScano(i) is a low voltage.

[0164] In the second stage t2, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transfer signal NScan(i-1) generated in the previous stage is set low: the first transistor T4, the input transistor T3 and the tenth transistor T14 are in a closed state according to the first clock signal XCK, and the gate of the seventh transistor T5, the node D, the second node Q, and the node F are maintained at the previous voltage; the sixth transistor T2 is maintained to be turned on, and the low-set second clock signal line CK is transmitted to the node E, and the voltage of the node F is further pulled down by the first capacitor C1 due to the decrease of the second clock signal CK, so that the eleventh transistor T16 is maintained to be turned on, and the voltage of the node F is transmitted to the node D, but the voltage of the node D is also increased by the coupling effect of the rise of the first clock signal XCK transmitted by the first clock signal line CKL1 in the circuit layout; the eleventh transistor T16 is turned off, due to The effect of the ninth transistor T12 is to prevent the voltage of the second node Q from changing with the voltage of the node D, and the second-stage transmission transistor T9 is still turned on; the seventh transistor T5 is still turned on, and the high first clock signal XCK is transmitted to the node C and the node B, and the fifth transistor T1 and the second transistor T6 are turned off; the thirteenth transistor T8 is turned on according to the voltage of the node D, and the first voltage VGH is transmitted to the first node P (the fourth node R) so that the first-stage transmission transistor T10 is turned off, and at the same time, the low second clock signal line CK turns on the third transistor T7, and the first voltage VGH is further transmitted to the node A to charge the second capacitor C2 to a voltage difference equal to the voltage difference between the nodes A and B; since the first-stage transmission transistor T10 is turned off and the second-stage transmission transistor T9 is turned on, the generated gate control signal NScano(i) is a low voltage;

[0165] In the third stage t3, the first clock signal XCK is set low, the second clock signal line CK is set high, and the level transfer signal NScan(i-1) generated in the previous stage is set high: the third transistor T7 is in a closed state according to the second clock signal line CK; the first transistor T4, the input transistor T3 and the tenth transistor T14 are turned on according to the first clock signal XCK, and the high level transfer signal NScan(i-1) is transmitted to the node D, the node Q, the node F, and the gate of the seventh transistor T5, and the second voltage VGL is transmitted to the node C and the node B; the second-stage transmission transistor T9 is turned off, and the seventh transistor T5 is turned off according to the high level transfer signal NScan(i-1); the fifth transistor T1 and the second transistor T6 are turned on according to The first voltage VGH is transmitted to the node E to charge the first capacitor C1 to a voltage difference between the node E and the node F, and the high second clock signal line CK is transmitted to the node A to charge the second capacitor C2 to a voltage difference between the node A and the node B; the thirteenth transistor T8 is turned off according to the high level transmission signal NScan(i-1), and the first node P (the fourth node R) maintains the previous (high) voltage through the third capacitor C3, so that the first-level transmission output transistor T10 is turned off. Since the first-level transmission output transistor T10 is turned off and the second-level transmission output transistor T9 is turned off, that is, the level transmission output terminal OUT is suspended, the generated gate control signal NScano(i) is maintained at a low voltage;

[0166] In the fourth stage t4, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transfer signal NScan(i-1) generated in the previous stage is set high: the input transistor T3, the first transistor T4 and the tenth transistor T14 are in a closed state according to the first clock signal XCK, and the gate of the seventh transistor T5, the node D, the second node Q, and the node C are maintained at the previous voltage; the seventh transistor T5 is turned off according to the previous high voltage, the second-stage transmission transistor T9 is turned off according to the previous high voltage of the second node Q, the thirteenth transistor T8 is turned off according to the high voltage of the node D, the fifth transistor T1 and the second transistor T6 are turned on according to the previous low voltage of the node C, and the sixth transistor T2 is turned on according to the previous high voltage of the node F. The first voltage VGH is transmitted to the node E through the fifth transistor T1, that is, the voltage of the node E is basically unchanged. Combined with the coupling effect of the first capacitor C1, the voltage of the node F can also be basically unchanged. The low second clock signal CK is transmitted to the node A through the second transistor T6. Combined with the coupling effect of the second capacitor C2, the voltage of the node B is also reduced. The third transistor T7 is turned on according to the second clock signal CK, and the low voltage at point A is transmitted to the node P (the fourth node R) through the third transistor T7, thereby turning on the first-stage transmission output transistor T10. Since the first-stage transmission output transistor T10 is turned on and the second-stage transmission output transistor T9 is turned off, the generated gate control signal NScano(i) is a high voltage.

[0167] In the fifth stage t5, the first clock signal XCK is set low, the second clock signal line CK is set high, and the level transfer signal NScan(i-1) generated in the previous stage is set low: the third transistor T7 is in a closed state according to the second clock signal line CK; the first transistor T4, the input transistor T3 and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low level transfer signal NScan(i-1) is transmitted to the node D, the second node Q, and the gate of the seventh transistor T5 through the input transistor T3; the second-stage transmission transistor T9 is turned on according to the low voltage of the second node Q, and the sixth transistor T2 is turned on according to the voltage of the node F so that the high second clock signal line CK is transmitted to the node E, so as to charge the first capacitor C1 to a voltage difference equal to the voltage between the nodes E and F; the seventh transistor T5 is turned on so that the low first clock signal XCK is transmitted to the nodes C and B, and the fifth transistor T1 is turned on according to the low first clock signal XCK and the second voltage VGL. The voltage VGH is transmitted to the node E through the fifth transistor T1 (the voltage of the node E can be between the first voltage VGH and the high voltage of the second clock signal line CK). Based on the fact that the first voltage VGH and the high voltage of the second clock signal line CK are equal, the voltage of the node E is almost unchanged, and the voltage of the node F is almost unchanged, while the eleventh transistor T16 is turned off, so that the first capacitor C1 can be prevented from affecting the falling speed of the voltage of the second node Q; the second transistor T6 is turned on according to the low voltage of the node B, so that the high second clock signal line CK is transmitted to the node A, so as to charge the second capacitor C2 to a voltage difference equal to the voltage between the nodes A and B; the thirteenth transistor T8 is turned on according to the low voltage of the node D, so that the first voltage VGH is transmitted to the first node P (the fourth node R), thereby turning off the first-stage transmission output transistor T10. Since the first-stage transmission output transistor T10 is turned off and the second-stage transmission output transistor T9 is turned on, the generated gate control signal NScano(i) is a low voltage;

[0168] In the sixth stage t6, the stage transfer signal NScan(i-1) generated by the previous stage is set low, and the first clock signal XCK and the second clock signal line CK are alternately set low and high, driving the voltage of node F to couple downward. Each time the voltage of node F is coupled downward, the voltage will gradually decrease, approaching -16V, and the voltage of the corresponding second node Q will gradually decrease, approaching -20V. In the first few cycles after the seventh transistor T5 in the fifth stage, the voltage of node F is coupled downward more obviously, and the voltage of the second node Q is greatly affected by the voltage of node F. Later, the eleventh transistor T16 is turned off, and the voltage of the second node Q tends to be stable and will not be affected by the voltage of node F.

[0169] It should be noted that the gate drive circuit provided in the present invention may be, but is not limited to, a 16T3C structure or a 13T3C structure ( Figure 2 and Figure 3 In the figure, only the former is taken as an example. Compared with the 13T3C structure, the 16T3C structure is additionally provided with the above-mentioned tenth transistor T14, twelfth transistor T15, and eleventh transistor T16. On the one hand, when the stage transmission signal NScan(i-1) of the previous stage writes a low voltage to the second node Q and the node F, the voltage of the second node Q can flow out from the eleventh transistor T16 and the ninth transistor T12 at the same time, and the second node Q is not directly connected to the first capacitor C1 (blocked by the eleventh transistor T16) to maintain the voltage, so the voltage of the second node Q can drop faster, which is conducive to the opening of the second-stage transmission transistor T9; on the other hand, the second node Q is not directly connected to the first capacitor C1 (blocked by the eleventh transistor T16), so the fluctuation of the node E voltage will not drive the change of the second node Q voltage, and the eleventh transistor T16 plays a role similar to a diode, and the second node Q voltage will not be pulled up by the node F.

[0170] Combined with the above discussion, we can see that Figure 2 and Fig.10 It can be seen that if the level transfer signal NScan(i-1) generated by the upper stage is always set to low (excluding valid high voltage pulses), it can be considered that the second node and node D are always maintained at a low voltage, so as to always turn on the second-stage transmission output transistor T9 and the thirteenth transistor T8, and to always turn off the first-stage transmission output transistor T10, so that the level transfer signal NScan(i) output by this stage is always a low voltage (excluding valid high voltage pulses).

[0171] Combined with the above discussion, we can see that Figure 2 and Fig.10 It can be seen that if the third frequency-dividing transistor T17 is turned off (that is, the second frequency-dividing control signal FD2 is at its higher voltage), that is, the first node P and the fourth node R are disconnected, then the voltage of the first node P can only be determined by the on state of the thirteenth transistor T8 and the coupling effect of the third capacitor C3.

[0172] Specifically, in the first stage t1, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-level transmission output transistor T10 is turned off; in the second stage t2, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-level transmission output transistor T10 is turned off; in the third stage t3, the thirteenth transistor T8 is turned off, the first node P is maintained at the first voltage VGH, and the first-level transmission output transistor T10 is turned off; in the fourth stage t4, the thirteenth transistor T8 is turned off, the first node P is maintained at the first voltage VGH, and the first-level transmission output transistor T10 is turned off; in the fifth stage t5, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-level transmission output transistor T10 is turned off; in the sixth stage t6, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-level transmission output transistor T10 is turned off. Therefore, it can be considered that the first-level transmission output transistor T10 is turned off in each stage, and the gate control signal is related to the turn-on state of the second-level transmission output transistor T9, as follows:

[0173] In the first stage t1, the second stage transmission output transistor T9 is turned on, so the stage transmission signal NScan(i) generated by this stage is a low voltage;

[0174] In the second stage t2, the second stage transmission output transistor T9 is turned on, so the stage transmission signal NScan(i) generated by this stage is a low voltage;

[0175] In the third stage t3, the second-stage transmission output transistor T9 is turned off, that is, the stage transmission output terminal OUT is suspended, so the stage transmission signal NScano(i) generated by this stage is maintained at a low voltage;

[0176] In the fourth stage t4, the second-stage transmission output transistor T9 is turned off, that is, the stage transmission output terminal OUT is suspended, so the stage transmission signal NScano(i) generated by this stage is maintained at a low voltage;

[0177] In the fifth stage t5, the second stage transmission output transistor T9 is turned on, so the stage transmission signal NScano(i) generated by this stage is a low voltage;

[0178] In the sixth phase t6 , the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScano(i) generated by this stage is a low voltage.

[0179] In summary, if the third frequency-dividing transistor T17 is turned off (i.e., the second frequency-dividing control signal FD2 is at its higher voltage), the level-transmitting signal NScan(i) generated by this stage is all at a low voltage; if the third frequency-dividing transistor T17 is turned on (i.e., the second frequency-dividing control signal FD2 is at its lower voltage), under the alternating high and low voltages of the level-transmitting signal NScan(i-1) generated by the previous stage, the first clock signal XCK, and the second clock signal CK, the level-transmitting signal NScan(i) generated by this stage can be at a corresponding time period (e.g., Fig.10 The effective pulse (eg, high voltage pulse) is formed between the starting point of the fourth stage t4 and the end point of the fifth stage in the pixel driving circuit 302 of the corresponding row, thereby acting on the corresponding transistor (eg, Figure 6 and Figure 7 The compensation transistor M3 in the corresponding row is used to turn on (refresh) the light emitting device 301 in the corresponding row.

[0180] It can be understood that in the present invention, the level transmission signal generated by the gate driving circuit 20 of this level is only transmitted to the gate driving circuit 20 of the next level, and the generated gate control signal is only loaded to the sub-pixel Pi of the corresponding row of this level; combined with the above analysis, it can be known that in one frame, if the first node P (for Figure 2 for the second node Q (for Figure 3 For example, the third node S is not electrically connected to the fourth node R. Regardless of whether the third node S is electrically connected to the first node P or the second node Q, the gate control signal of this stage does not have a valid pulse, which causes the sub-pixel Pi of the corresponding row of this stage to be unable to be turned on. At the same time, the level transmission signal of this stage does not have a level transmission valid pulse, so it is also unable to control the operation of the gate driving circuit 20 of the lower stage, resulting in the level transmission signal and the gate control signal of the lower stage also not having a level transmission valid pulse and a gate valid pulse respectively (that is, the sub-pixel Pi of the corresponding row of the lower stage cannot be turned on either). By analogy, the sub-pixel Pi of the subsequent rows cannot be turned on; that is, only at the first node P (for the gate driving circuit 20 of each stage) in the gate driving circuit 20 of each stage Figure 2 for the second node Q (for Figure 3 For example, when the third node S is electrically connected to the fourth node R, whether the sub-pixels Pi in each row are turned on can be further controlled by controlling whether the third node S is electrically connected to the first node P or the second node Q.

[0181] It should be understood that if the first sub-pixels Pi are turned on for more frames in a plurality of consecutive frames than the second sub-pixels Pi, it means that the first display area has a higher refresh rate than the second display area, and vice versa.

[0182] If you want to implement the frequency reduction mode (the refresh rate from the first display area to the second display area decreases), you can use the following method: in the continuous multiple frames, in at least one of the previous frames (for example Fig.11 Frame1 in the figure) can control the level transmission signals and gate control signals generated by all stages (e.g. Fig.11 NScano(1) to NScano(6) in each of the above-mentioned frames have a level transfer effective pulse and a gate effective pulse pl; in at least one subsequent frame (e.g. Fig.11 Frame 4 in the figure) to control the level transmission signal and gate control signal (eg Fig.11 NScano(1) to NScano(2)) in the embodiment respectively have a level transfer valid pulse and a gate valid pulse pl, and control the level transfer signal generated by each second gate driving circuit 2002 to have no level transfer valid pulse so that the corresponding gate control signal (e.g. Fig.11 NScano(3) to NScano(6) in FIG. 10 also do not have gate valid pulses, or only generate gate control signals (such as Fig.11 NScano(3) to NScano(6)) in do not have gate valid pulses.

[0183] Specifically, here we combine Figure 2 and Figure 3 As can be seen from the related discussion, in the frequency reduction mode, taking the first frequency dividing transistor T18 as a P-type transistor as an example, there are two implementation methods as follows:

[0184] Method 1, please refer to but not limited to Fig.11 , the first frequency division control signal FD1 (ie, its voltage is equal to the low voltage) is used to control the third node S in each stage of the gate driving circuit 20 to be electrically connected to the first node P (for Figure 2 for) or the second node Q (for Figure 3 In one frame, the second frequency-division control signal FD2 is used to control the first node P or the second node Q in the first gate drive circuit 2001 to be electrically connected to the fourth node R, so as to control the output gate control signal to have a gate effective pulse pl, so as to turn on the corresponding light-emitting device 301; in the frame, the second frequency-division control signal FD2 is also used to control the first node P or the second node Q in the second gate drive circuit 2002 to be disconnected from the fourth node R, so as to control the output gate control signal to not have the gate effective pulse pl, so as not to turn on the corresponding light-emitting device 301.

[0185] Mode 2 is different from Mode 1 in that the second frequency division control signal FD2 (i.e., its voltage is equal to the low voltage) is used to control the fourth node R in each stage of the gate drive circuit 20 to be electrically connected to the first node P (for Figure 2 for) or the second node Q (for Figure 3 In one frame, the first frequency-division control signal FD1 is used to control the third node S in the first gate driving circuit 2001 to be electrically connected to the first node P or the second node Q, so as to control the output gate control signal to have a gate effective pulse pl, so as to turn on the corresponding light-emitting device 301; in the frame, the first frequency-division control signal FD1 is also used to control the third node S in the second gate driving circuit 2002 to be disconnected from the first node P or the second node Q, so as to control the output gate control signal to not have the gate effective pulse pl, so as not to turn on the corresponding light-emitting device 301.

[0186] Regardless of whether method 1 or 2 is adopted, for the first-level gate driving circuit 20 to the sixth-level gate driving circuit 20, assuming that the refresh rates of the first two levels (level 1 to level 2) gate driving circuit 20, the middle two levels (level 3 to level 4) gate driving circuit 20, and the last two levels (level 5 to level 6) gate driving circuit 20 are 120HZ, 60HZ, and 30HZ respectively, then according to the above content, in the four consecutively arranged frames (Frame 1 to Frame 4), it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 to Frame 4, the gate control signals NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 and Frame 3, and the gate control signals NScano(5) to NScano(6) have gate effective pulses pl only in Frame 1;

[0187] That is, the frequency division control signal FD needs to be set as follows (the following is an example of method 1):

[0188] The first frequency division control signal FD1 is a low voltage in Frame 1 to Frame 4 to turn on the six first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first to sixth stages, so that the gate control signal generated by each can be the same as the corresponding stage transmission signal;

[0189] The second frequency division control signal FD2 is a low voltage corresponding to each stage in Frame 1 so that the six third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to sixth stages are turned on, so that the six stage transmission signals NScan(1) to NScan(6) and the six gate control signals NScano(1) to NScano(6) all have gate effective pulses pl in Frame 1;

[0190] The second frequency division control signal FD2 is a low voltage before tf1 in Frame 2 to turn on the two third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first stage to the second stage, so that NScano(1) to NScano(2) have gate effective pulses pl in Frame 2, and a high voltage after tf1 to turn off the four third frequency division transistors T17 corresponding to the gate driving circuits 20 of the third stage to the sixth stage, so that NScano(3) to NScano(6) do not have gate effective pulses pl in Frame 2;

[0191] The second frequency division control signal FD2 is a low voltage before tf2 in Frame 3 to turn on the four third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to fourth stages, so that NScan(1) to NScan(4) have gate effective pulses pl in Frame 3, and a high voltage after tf2 to turn off the two third frequency division transistors T17 corresponding to the gate driving circuits 20 of the fifth to sixth stages, so that NScan(5) to NScan(6) do not have gate effective pulses pl in Frame 3;

[0192] The analysis of the second frequency division control signal FD2 in Frame 4 may refer to the analysis in Frame 2 .

[0193] Of course, as analyzed above, Fig.11 For example, the second frequency division control signal FD2 can also be set to a low voltage in Frame 1 to Frame 4 to turn on the six third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to sixth stages, so that the level transfer signals generated by each of them have level transfer effective pulses.

[0194] Furthermore, the corresponding frequency division setting is achieved by controlling the first frequency division control signal FD1 in each frame to have or not have a gate effective pulse during the period when the first frequency division control signal FD1 effectively acts on the gate driving circuit of the corresponding stage.

[0195] To summarize, the display panel can be divided into at least a first area, a second area and a third area. The first area (corresponding to being acted upon by the 1st to 2nd level gate driving circuit 20) is loaded with a valid pulse pl in Frame 1 to Frame 4 to perform data writing (i.e., data refreshing is performed 4 times). The second area (corresponding to being acted upon by the 3rd to 4th level gate driving circuit 20) is loaded with a gate valid pulse pl in Frame 1 and Frame 3 to perform data writing (i.e., data refreshing is performed 2 times), that is, its refresh rate is half of that of the first area. Similarly, the second area (corresponding to being acted upon by the 5th to 6th level gate driving circuit 20) is loaded with a valid pulse pl only in Frame 1 to perform data writing (i.e., data refreshing is performed 1 time), and its refresh rate is 1 / 4 of that of the first area. In the above example, the refresh rates of the first area, the second area and the third area can be a, (1 / 2)*a, (1 / 4)*a respectively. If a is an integer multiple of 4, it needs to be divided into 4 frames, for example, 120HZ, 60HZ, and 30HZ respectively.

[0196] For the sake of convenience, the following example is used to illustrate that the display panel is divided into three areas, and each area is affected by a two-level gate control signal, and the refresh rates of the three areas can be a, (1 / 2)*a, and (1 / 4)*a, respectively. Those skilled in the art should understand that the number of areas of the display panel and the number of rows of sub-pixels Pi contained in each area can be changed, and the corresponding refresh rate can also be adjusted. The only difference here is the degree of refresh rate difference of the multiple areas illustrated, and the frame number setting requirements. If the refresh rate of each of the three areas is 1 / 3 of the refresh rate of the former, 9 frames need to be illustrated so that the refresh times of the three areas are 3 times, that is, the three areas are refreshed 9 times, 3 times and 1 time, respectively, in 9 frames.

[0197] Specifically, if you want to implement the frequency up-conversion mode (the frequency from the first display area to the second display area increases), you can use the following method: in the continuous multiple frames, in at least one of the preceding frames (for example Figures 12 to 16 In Frame 1), the level transmission signals and gate control signals generated by all levels can be controlled to have level transmission effective pulses and gate effective pulses respectively; in at least one subsequent frame (e.g. Figure 12 to Figure 13 Frame4 in Figure 14 to Figure 15 Frame 3 in Fig.16 Frame 4 in the figure), the level transmission signal generated by each first gate driving circuit 2001 is controlled to have a level transmission effective pulse (level transmission is continuously applied to the second gate driving circuit 2002), and the generated gate control signal does not have a gate effective pulse (for example Figure 12 to Figure 13 NScan(1) to NScan(2) in Figure 14 to Figure 15NScan(3) to NScan(4) in Fig.16 NScan(1) to NScan(4)), each level transmission signal and gate control signal generated by the second gate drive circuit 2002 respectively has a level transmission effective pulse and a gate effective pulse (for example Figure 12 to Figure 13 NScan(3) to NScan(4) in Figure 14 to Figure 15 NScan(5) to NScan(6) in Fig.16 NScan(5) to NScan(6) in the example above).

[0198] Specifically, here we combine Figure 2 and Figure 3 As can be seen from the related discussion, in the frequency-up mode, please refer to but not limited to Figures 12 to 16 Here, the third frequency-dividing transistor T17 is a P-type transistor as an example, that is, the second frequency-dividing control signal FD2 (for example, its voltage is equal to a low voltage) is used to control the fourth node R in each stage of the gate driving circuit 20 to be electrically connected to the first node P (for Figure 2 for) or the second node Q (for Figure 3 In one frame, the first frequency division control signal FD1 is used to control the third node S and the first node P in the first gate drive circuit 2001 (for Figure 2 for) or the second node Q (for Figure 3 ) is disconnected to control the output gate control signal to have no gate effective pulse so as not to turn on the corresponding light emitting device 301; within the frame, the first frequency division control signal FD1 is used to control the first node P (for the second gate driving circuit 2002) in Figure 2 for) or the second node Q (for Figure 3 For example, the gate control signal 301 is electrically connected to the fourth node R to control the output gate control signal to have the gate effective pulse to turn on the corresponding light emitting device 301.

[0199] For example Fig.12As shown, the refresh rates of the first two-stage gate driving circuit 20, the middle two-stage gate driving circuit 20, and the last two-stage gate driving circuit 20 are 30HZ, 120HZ, and 60HZ respectively. According to the above content, in Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have a gate effective pulse pl in Frame 1, NScano(3) to NScano(4) have a gate effective pulse pl in Frame 1 to Frame 4, and the gate control signal NScano(5) to NScano(6) have a gate effective pulse pl in Frame 1 and Frame 3;

[0200] That is, the frequency division control signal FD needs to be set as follows:

[0201] The second frequency division control signal FD2 is a low voltage in Frame 1 to Frame 4 so that the six third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to sixth stages are all turned on, so that the level transfer signal generated by each has a level transfer effective pulse;

[0202] The first frequency division control signal FD1 is a low voltage corresponding to each stage in Frame 1, so that the six first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first stage to the sixth stage are turned on, so that the third node S can be electrically connected to the first node P or the second node Q, so that the six gate control signals NScano(1) to NScano(6) also have gate valid pulses pl in Frame 1;

[0203] The first frequency division control signal FD1 is a high voltage before tf1 and after ft2 in Frame 2 to turn off the two first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first, second, fifth and sixth stages, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have the gate effective pulse pl in Frame 2, and is a low voltage between tf1 and ft2 to turn on the two first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first and third stages, so that NScano(1) to NScano(3) do not have the gate effective pulse pl in Frame 2;

[0204] The first frequency division control signal FD1 is a high voltage before tf3 in Frame 3 to turn off the two first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first and second stages, so that NScano(1) to NScano(2) do not have a gate effective pulse pl in Frame 3, and is a low voltage after tf3 to turn on the four first frequency division transistors T18 corresponding to the gate driving circuits 20 of the third to sixth stages, so that NScano(3) to NScano(6) have a gate effective pulse pl in Frame 3;

[0205] The analysis of the first frequency division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0206] Similarly, for example Fig.13 As shown, the refresh rates of the first two-stage gate driving circuit 20, the middle two-stage gate driving circuit 20, and the last two-stage gate driving circuit 20 are 60HZ, 120HZ, and 30HZ respectively. According to the above content, in Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 to Frame 4, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl only in Frame 1;

[0207] That is, the frequency division control signal FD needs to be set as follows:

[0208] The second frequency division control signal FD2 is Fig.12 The same arrangement is used in the embodiment so that the level transmission signal generated by each level gate driving circuit 20 has a level transmission effective pulse;

[0209] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate effective pulses pl in Frame 1.

[0210] The first frequency division control signal FD1 is a high voltage before tf1 and after ft2 in Frame 2. Similarly, NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have a gate effective pulse pl in Frame 2. The first frequency division control signal FD1 is a low voltage between tf1 and ft2. Similarly, NScano(3) to NScano(4) have a gate effective pulse pl in Frame 2.

[0211] The first frequency division control signal FD1 is a low voltage before tf3 in Frame 3, so that NScano(1) to NScano(4) have gate valid pulses pl in Frame 3, and is a high voltage after tf3, so that NScano(5) to NScano(6) do not have gate valid pulses pl in Frame 3;

[0212] The analysis of the first frequency division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0213] Similarly, for example Fig.14 As shown, the refresh rates of the first two-stage gate driving circuit 20, the middle two-stage gate driving circuit 20, and the last two-stage gate driving circuit 20 are 120HZ, 30HZ, and 60HZ respectively. According to the above content, in Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 to Frame 4, NScano(3) to NScano(4) have gate effective pulses pl only in Frame 1, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 and Frame 3;

[0214] That is, the frequency division control signal FD needs to be set as follows:

[0215] The second frequency division control signal FD2 is Fig.12 The same arrangement is used in the embodiment so that the level transmission signal generated by each level gate driving circuit 20 has a level transmission effective pulse;

[0216] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate effective pulses pl in Frame 1.

[0217] The first frequency division control signal FD1 is a low voltage before tf1 in Frame 2, so that NScano(1) to NScano(2) have gate valid pulses pl in Frame 2, and is a high voltage after tf1, so that NScano(3) to NScano(6) do not have gate valid pulses pl in Frame 2;

[0218] The first frequency division control signal FD1 is a low voltage before tf2 and after ft3 in Frame 3, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) have gate effective pulses pl in Frame 3, and is a high voltage between tf2 and ft3, so that NScano(3) to NScano(4) do not have gate effective pulses pl in Frame 3;

[0219] The analysis of the first frequency division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0220] Similarly, for example Fig.15 As shown, the refresh rates of the first two-stage gate driving circuit 20, the middle two-stage gate driving circuit 20, and the last two-stage gate driving circuit 20 are 60HZ, 30HZ, and 120HZ respectively. According to the above content, in Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate effective pulses pl only in Frame 1, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 to Frame 4;

[0221] That is, the frequency division control signal FD needs to be set as follows:

[0222] The second frequency division control signal FD2 is Fig.12 The same arrangement is used in the embodiment so that the level transmission signal generated by each level gate driving circuit 20 has a level transmission effective pulse;

[0223] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate effective pulses pl in Frame 1.

[0224] The first frequency division control signal FD1 is a high voltage before tf1 in Frame 2, so that NScano(1) to NScano(4) do not have a gate effective pulse pl in Frame 2, and is a low voltage after tf1, so that NScano(5) to NScano(6) have a gate effective pulse pl in Frame 2;

[0225] The first frequency division control signal FD1 is a low voltage before tf2 and after ft3 in Frame 3, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) have gate effective pulses pl in Frame 3, and is a high voltage between tf2 and ft3, so that NScano(3) to NScano(4) do not have gate effective pulses pl in Frame 3;

[0226] The analysis of the first frequency division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0227] Similarly, for example Fig.16 As shown, the refresh rates of the first two-stage gate driving circuit 20, the middle two-stage gate driving circuit 20, and the last two-stage gate driving circuit 20 are 30HZ, 60HZ, and 120HZ respectively. According to the above content, in Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl only in Frame 1, NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 and Frame 3, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 to Frame 4;

[0228] That is, the frequency division control signal FD needs to be set as follows:

[0229] The second frequency division control signal FD2 is Fig.12 The same arrangement is used in the embodiment so that the level transmission signal generated by each level gate driving circuit 20 has a level transmission effective pulse;

[0230] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate effective pulses pl in Frame 1.

[0231] The first frequency division control signal FD1 is a high voltage before tf1 in Frame 2, so that NScano(1) to NScano(4) do not have a gate effective pulse pl in Frame 2, and is a low voltage after tf1, so that NScano(5) to NScano(6) have a gate effective pulse pl in Frame 2;

[0232] The first frequency division control signal FD1 is a high voltage before tf2 in Frame 3, so that NScano(1) to NScano(2) do not have a gate effective pulse pl in Frame 3, and is a low voltage after tf2, so that NScano(3) to NScano(6) have a gate effective pulse pl in Frame 3;

[0233] The analysis of the first frequency division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0234] Combination Figures 11 to 16 The display panel can be further divided into m regions corresponding to the m gate drive circuits 20 cascaded in sequence, and the corresponding m refresh rates can be expressed as a / (j1), a / (j2) to a / (jm), j1 to jm are all positive integers, and the m refresh rates are all positive integers, then the number of frames should be set to the least common multiple of the m numbers j1 to jm, for example, including the two refresh rates of 120Hz and 1Hz, then there should be 120 frames as a cycle. Similarly, the above description of "m is the least common multiple of n1, n1, n1" can be referred to.

[0235] In summary, the first frequency division control signal FD1 and the second frequency division control signal FD2 can be reasonably controlled according to the refresh rate relationship among the first area, the second area A2 and the third area. For example, the first area A1, the second area A2 and the third area A3 are respectively used for video playback, the comment area screen (which can be scrolled according to needs), and the keyboard screen, that is, the refresh rates of the three are reduced in sequence. At this time, the first frequency division control signal FD1 can be kept at a low voltage in multiple frames, and the second frequency division control signal FD2 can be relied on to jump from a valid (low) voltage to an invalid (high) voltage to achieve this. The second frequency division control signal FD2 can also be kept at a low voltage in multiple frames. The low voltage is continuously maintained, and it is achieved by relying on the jump of the first frequency-dividing control signal FD1 from the valid (low) voltage to the invalid (high) voltage; for another example, the first area A1, the second area A2 and the third area A3 are respectively used for date display, video playback, and comment area screen (which can be scrolled according to needs), that is, the refresh rates of the three show a trend of first increasing and then decreasing. At this time, it can only be achieved by maintaining the low voltage of the above-mentioned second frequency-dividing control signal FD2 in multiple frames to maintain that each stage can output a valid stage transfer pulse, and relying on the first frequency-dividing control signal FD1 to jump from the invalid (high) voltage to the valid (low) voltage, and then from the valid (low) voltage to the invalid (high) voltage.

[0236] The frame in which the gate of the multi-level gate control signal corresponding to any region has a gate effect pulse is called the write frame of the region, which is used to turn on the sub-pixel Pi so that the corresponding at least one data string can be loaded to the corresponding at least one row of sub-pixels Pi respectively, and the frame without a gate effect pulse is called the hold frame of the region, so that the corresponding at least one row of sub-pixels Pi respectively maintains the corresponding at least one data string. For example Figures 11 to 16 Frame 1 in the figure is also a writing frame for the three regions corresponding to the front 2-stage, middle 2-stage, and rear 2-stage gate driving circuits 20; Figure 12 to Figure 13 Frame 2 and Frame 4 in the figure are both writing frames of a region corresponding to the middle two-stage gate driving circuit 20, and are also holding frames of a region corresponding to the front two-stage and rear two-stage gate driving circuit 20; Figure 14 to Figure 15 Frame 3 in FIG. 1 is a holding frame for a region corresponding to the middle two-stage gate driving circuit 20 and is also a writing frame for a region corresponding to the front two-stage and rear two-stage gate driving circuit 20; Figure 15 to Figure 16 Frame 2 and Frame 4 in the figure are both holding frames for a region corresponding to the first two stages and the middle two stages of the gate driving circuit 20 , and are also writing frames for a region corresponding to the last two stages of the gate driving circuit 20 .

[0237] In accordance with the above discussion, it can be considered that in the write frame, the gate effective pulse in the gate control signal turns on the corresponding row of sub-pixels Pi, so that the multiple sub-data in the corresponding data string are respectively transmitted to the corresponding multiple sub-pixels Pi. Therefore, it is possible to determine whether the frame is a write frame for the next row of sub-pixels Pi or a hold frame for the previous row of sub-pixels Pi based on whether the two data strings corresponding to the two adjacent rows of sub-pixels Pi have changed (that is, whether the two voltage values ​​corresponding to the two adjacent sub-data transmitted by the data line electrically connected to any column of sub-pixels Pi are the same, that is, whether the data signal transmitted by the data line has jumped).

[0238] like Fig.17 As shown, if the data signal source transmitted by the data line jumps, due to the row-by-row scanning, that is, the data signal transmitted by each data line will simultaneously undergo an effective jump hop1 (that is, the gate control signal of the corresponding level needs to have a gate effective pulse to turn on the sub-pixel Pi of the corresponding row to load the multiple sub-data after the jump), the frequency division control signal FD can be set to control the corresponding gate effective pulse to be generated before the corresponding data string appears, so as to ensure the turning on of the sub-pixel Pi of the corresponding row, based on the fact that the first frequency division transistor T18 and the second frequency division transistor T20 are both P-row transistors, that is, the first frequency division control signal FD1 and the first frequency division control signal FD1 are both set to a low voltage to turn on the above two.

[0239] Specifically, Figure 6 For example, Figure 8 The NScano2 and NScano1 signals in the Figure 6 The signals on the gates of M3 and M4 (both P-type transistors) in Fig.17 The con(M3) signal and the con(M4) signal can respectively represent the total frequency division control signal FD in the two NScan circuits used to generate the NScano2 signal and the NScano1 signal. The "total frequency division control signal FD" can be understood as the signal after the first frequency division control signal FD1 and the second frequency division control signal FD2 in the NScan circuit are summed, that is, only when both are at a valid (low) voltage, the "total frequency division control signal FD" will be at a valid (low) voltage, otherwise they are both at an invalid (high) voltage.

[0240] See above about Figure 6 and Figure 8 The NScano2 signal needs to be a valid (high) voltage in advance of the NScano1 signal, so that the compensation transistor M3 is turned on in the first reset stage tim1 so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2, and then the reset transistor M4 is turned on in the second reset stage tim2 so that the gate of the driving transistor M1 is reset according to the initialization signal VI2. Fig.17 As shown, for example, the con (M3) signal and the con (M4) signal corresponding to the two NScan circuits can be respectively changed from an invalid (high) voltage to a valid (low) voltage 32 line cycles and 16 line cycles before the "sub-data valid jump hop1" to sequentially turn on the compensation transistor and the reset transistor. Figure 2 and Figure 3 It can be seen from the relevant discussion that the first reset phase tim1 and the second reset phase tim2 of the corresponding row of sub-pixels Pi are completed in sequence;

[0241] Further, still based on Figure 6 As shown, the frequency division control signal FD (also referred to as con(M2) signal) in the PScan circuit for generating the PScano signal can be controlled to jump from an invalid (high) voltage to a valid (low) voltage before the "sub-data valid jump hop1" (less than 16 line cycles), or when it is equal to the "sub-data valid jump hop1". Fig.17 (not shown) to turn on the data transistor and continue the period from the valid transition hop1 to the invalid transition hop2 of the data signal transmitted by the data line to perform the data writing phase tim3;

[0242] Furthermore, still based on Figure 6As shown, after the "sub-data invalid jump hop2", the frequency division control signal FD (also referred to as con(M5 / 6) signal) in the EM circuit used to generate the EMo1 signal can be controlled to jump from an invalid (high) voltage to a valid (low) voltage ( Fig.17 (not shown) to turn on the first light-emitting control transistor and the second light-emitting control transistor, and continue the period from the effective transition hop1 to the invalid transition hop2 of the data signal transmitted by the data line to perform the light-emitting stage tim4;

[0243] Among them, it is still based on Figure 6 As shown, between the light-emitting stage tim4 and the data writing stage tim3, the frequency division control signal FD (also referred to as con(M7 / 8) signal) in the EM circuit for generating the EMo2 signal can also be controlled to jump from an invalid (high) voltage to a valid (low) voltage ( Fig.17 (not shown) to turn on the initial transistor and reset the transistor to perform the third reset stage tin.

[0244] The above “row period” can be understood as the sum of the turn-on time of each row of sub-pixels Pi and the row blanking time. Fig.17 In only one frame, the first 878 rows of sub-pixels Pi are in a holding frame (i.e., the corresponding con(M3) signal and con(M4) signal are in an invalid (high) voltage for a period of 878 row cycles), and the con(M3) signal and con(M4) signal jump from a valid (low) voltage to an invalid (high) voltage 30 row cycles and 14 row cycles before the "sub-data invalid jump hop2", respectively, and the subsequent 878 rows of sub-pixels Pi are also in a holding frame (i.e., the corresponding con(M3) signal and con(M4) signal are in an invalid (high) voltage for a period of 878 row cycles).

[0245] In summary, in this embodiment, the waveform of the "total frequency division control signal FD" in at least one corresponding gate driving circuit 20 can be set according to the "sub-data valid transition hop1" and "sub-data valid transition hop1" of the data signal transmitted by the data line. For example, in the low-frequency region, the Source signal is in a constant voltage signal in the holding frame. At this time, the "total frequency division control signal FD" can be equal to an invalid (high) voltage, so that the effective gate pulse cannot be output. For example, in the high-frequency region, when the Source signal has a "sub-data valid transition hop1", it can trigger the "total frequency division control signal FD" to jump to a valid (low) voltage, so that the effective gate pulse is output normally. And combined with the above analysis, it can be known that the transition moment of the "total frequency division control signal FD" in different gate driving circuits 20 for different transistors in the pixel driving circuit 302 can be at the "sub-data valid transition hop1" or before or after it, so as to realize different working stages respectively.

[0246] It should be noted that, combined with the above Figure 2 , Figure 3 and Fig.10 As discussed in the foregoing, in any level of the gate driving circuit 20, if at least one of the first clock signal and the second clock signal is equal to the constant voltage, the corresponding level transfer signal and the gate control signal will not have a level transfer effective pulse and a gate effective pulse respectively, thereby failing to refresh (i.e., failing to turn on) the sub-pixel Pi of the corresponding row.

[0247] Furthermore, the gate driving module 10 includes n-stage gate driving circuits 20 cascaded in sequence, where n is a positive integer greater than or equal to 2, and the n-stage gate driving circuits 20 are all loaded with the same clock signal (for example Figures 11 to 16 The six-level gate driving circuits 20 are all loaded with the first clock signal and the second clock signal, and it can be considered that the positions where the first clock signal and the second clock signal are loaded in two adjacent levels are opposite); within one frame, the clock signal is alternately equal to the first clock voltage and the second clock voltage (which can be the high voltage and the low voltage in the first clock signal and the second clock signal, respectively, that is, it can control the opening of multiple rows of sub-pixels Pi corresponding to the gate control signals of the i-th to (i+k)-th levels), and i and k are both positive integers greater than or equal to 1; wherein, when the gate control signals output by the gate driving circuits 20 of the (i+k+1)-th to n-th levels do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period of effective action on the gate driving circuits 20 of the (i+k+1)-th to n-th levels (which just satisfies the corresponding multiple sub-pixels Pi not to be turned on).

[0248] It can be understood that since the gate control signals from the i-th to the (i+k)-th levels all have gate effective pulses, and the gate control signals from the (i+k+1)-th to the n-th levels all do not have gate effective pulses, based on this, in this embodiment, the clock signal is set to be equal to a constant voltage during the period when it effectively acts on the gate drive circuits 20 from the (i+k+1)-th to the n-th levels, which not only meets the requirement of "the gate control signals from the (i+k+1)-th to the n-th levels all do not have gate effective pulses", but also saves power consumption.

[0249] Furthermore, to ensure that the gate effective pulse of the (i+k)th level gate control signal is completely generated (to avoid interruption due to the clock signal becoming a constant voltage signal), the clock signal can be set equal to the constant voltage signal after the gate effective pulse is completely generated.

[0250] It should be noted that it must be satisfied that the last few levels of gate control signals do not have gate effective pulses respectively. If there is at least one last level of gate control signal with a gate effective pulse, the voltage of the gate drive circuits 20 corresponding to the previous few levels of gate control signals without gate effective pulses cannot be set to a constant voltage because this will also result in the inability to generate a level transfer signal acting on the next level, and it will be impossible to achieve at least one subsequent level of gate control signal with a gate effective pulse.

[0251] Specific, for example Fig.11 As shown, in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal (the two may be equal or unequal) may be set to be equal to at least one of the high voltage and the low voltage after the end time of the gate effective pulse in NScano(2); in Frame 3, at least one of the first clock signal and the second clock signal may be set to be equal to at least one of the high voltage and the low voltage after the end time of the gate effective pulse in NScano(4).

[0252] Similarly, for example Fig.12 As shown, in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano (4).

[0253] Similarly, for example Fig.13 As shown, in Frame 2 to Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano (4).

[0254] Similarly, for example Fig.14 As shown, in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano(2).

[0255] As discussed above, for example Fig.15 and Fig.16As shown, in Frame 1 and Frame 4, since NScano(5) and NScano(6) (i.e. corresponding to the last two stages of gate driving circuits 20) both have gate effective pulses, the first clock signal and the second clock signal need to be maintained alternately set to the first clock voltage and the second clock voltage in each frame to ensure that the stage transfer signal of each stage can be generated until the generation of the sixth stage, i.e., the gate control signal, is controlled.

[0256] The present invention provides a gate driving module and a display panel, comprising the above-mentioned frequency division signal line and a plurality of cascaded gate driving circuits, wherein the gate driving circuit comprises the above-mentioned level transmission unit and output unit. Among them, a level transmission frequency division control unit electrically connected to the level transmission receiving unit through the first node or the second node (also electrically connected to the level transmission output unit through the fourth node), and an output frequency division control unit connected between the first node, one of the second node and the third node are also provided, and the two are respectively used to control the signal of one of the first node and the second node according to the frequency division control signal to control the level transmission output unit to output the level transmission signal of the current level, and control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of the current level, so that the invalidity of the gate control signal will not affect the invalidity of the level transmission signal, and the sequential frequency reduction mode of multiple regions of the display panel can be realized by setting whether the level transmission signal has a level transmission valid pulse, and the arbitrary frequency conversion mode of multiple regions of the display panel can be realized by setting whether the gate control signal has a gate valid pulse (because the level transmission valid pulse can always exist).

[0257] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A gate drive module, characterized in that: It includes a frequency division signal line and a plurality of cascaded gate drive circuits, wherein the frequency division signal line is used to transmit a frequency division control signal to the plurality of gate drive circuits, and the gate drive circuit includes: A level transmission unit, comprising a level transmission receiving unit and a level transmission output unit, wherein the level transmission receiving unit is used to receive a level transmission signal generated by the upper-level gate driving circuit, and the level transmission output unit is electrically connected to the level transmission receiving unit through a first node and a second node, and is used to output the level transmission signal of the current level to the lower-level gate driving circuit according to the signal of the first node and the signal of the second node; an output unit, electrically connected to the stage transmission output unit through the first node, one of the second nodes, and a third node, and configured to output a gate control signal according to a signal of the first node, one of the second nodes, and a signal of the third node; and a stage transmission frequency division control unit, electrically connected to the stage transmission receiving unit through the first node or the second node, and electrically connected to the stage transmission output unit through a fourth node, and configured to control a signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output unit to output the stage transmission signal of the current stage; An output frequency division control unit is connected between the first node, one of the second nodes and the third node, and is used to control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of this stage.

2. The gate driving module according to claim 1, characterized in that: The frequency division control signal includes a first frequency division control signal and a second frequency division control signal, and the frequency division signal line includes a first frequency division signal line for transmitting the first frequency division control signal and a second frequency division control signal line for transmitting the second frequency division control signal; Wherein, the first frequency division signal line is electrically connected to the output frequency division control unit to control the signal of the third node; The second frequency division signal line is electrically connected to the stage transmission frequency division control unit to control a signal of one of the first node and the second node.

3. The gate driving module according to claim 2, characterized in that: The output frequency division control unit comprises: a first frequency-dividing transistor, wherein a gate of the first frequency-dividing transistor is connected to the first frequency-dividing signal line, a source of the first frequency-dividing transistor is electrically connected to the first node or the second node, and a drain of the control transistor is electrically connected to the third node; The first frequency division control signal is used to control whether the third node is electrically connected to or disconnected from the first node or the second node.

4. The gate driving module according to claim 3, characterized in that: The output frequency division control unit also includes: a second frequency-dividing transistor, wherein a gate of the second frequency-dividing transistor is electrically connected to the fifth node of the stage transmission unit, a source of the second frequency-dividing transistor is electrically connected to the first frequency-dividing signal line, and a drain of the second frequency-dividing transistor is electrically connected to the gate of the first frequency-dividing transistor; The first frequency division control signal and the signal of the fifth node are used to control the third node to be electrically connected or disconnected with the first node or the second node; The signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate driving circuit of this stage.

5. The gate driving module according to any one of claims 2 to 4, characterized in that: The level transmission and frequency division control unit comprises: a third frequency-dividing transistor, wherein the gate of the third frequency-dividing transistor is electrically connected to the second frequency-dividing signal line, the source of the first frequency-dividing transistor is electrically connected to the stage transmission receiving unit through the fourth node, and the drain of the third frequency-dividing transistor is electrically connected to the first node or the second node; The second frequency division control signal is used to control whether the fourth node is electrically connected to or disconnected from the first node or the second node.

6. The gate driving module according to claim 5, characterized in that: The level transmission output unit comprises: a first-stage transmission output transistor, wherein a gate of the first-stage transmission output transistor is electrically connected to the first node, a source of the first-stage transmission output transistor is electrically connected to the first voltage line to load a first voltage, and a drain of the first-stage transmission output transistor is electrically connected to a stage transmission output terminal in the gate driving circuit for outputting the stage transmission signal; A second-stage transmission output transistor, wherein the gate of the second-stage transmission output transistor is electrically connected to the second node, the source of the second-stage transmission output transistor is electrically connected to the second voltage line to load a second voltage, and the drain of the second-stage transmission output transistor is electrically connected to the stage transmission output end.

7. The gate driving module according to claim 6, characterized in that: The output unit comprises: a first output transistor, wherein a gate of the first output transistor is electrically connected to the third node, a source of the first output transistor is electrically connected to the first voltage line, and a drain of the first output transistor is electrically connected to a gate output terminal of the gate driving circuit for outputting the gate control signal; A second output transistor, wherein the gate of the second output transistor is electrically connected to the first node or the second node, the source of the second output transistor is electrically connected to the second voltage line, and the drain of the second output transistor is electrically connected to the gate output terminal.

8. The gate driving module according to claim 7, characterized in that: The gate driving circuit is electrically connected to at least one corresponding pixel driving circuit, the gate output terminal is electrically connected to a corresponding pixel transistor in each of the pixel driving circuits, and the first voltage is greater than the second voltage; The pixel transistor is an N-type transistor, and the drain of the third frequency-dividing transistor and the source of the first frequency-dividing control transistor are both electrically connected to the first node; Alternatively, the pixel transistor is a P-type transistor, and the drain of the third frequency-dividing transistor and the source of the first frequency-dividing control transistor are both electrically connected to the second node.

9. The gate driving module according to claim 5, characterized in that: The level transmission receiving unit comprises: a fourth node control unit, electrically connected to the clock signal line and the fourth node, and configured to control a signal of the fourth node according to a clock signal transmitted by the clock signal line; a second node control unit, electrically connected to the clock signal line and the second node, and configured to control a signal of the second node according to the clock signal; An input unit, wherein the input end of the input unit is electrically connected to the gate driving circuit of the upper level to load the level transmission signal generated by the gate driving circuit of the upper level, and the input end of the input unit is electrically connected to the fourth node control unit and the second node control unit, or is electrically connected to the fourth node control unit and the first node control unit.

10. The gate driving module according to claim 9, characterized in that: The stage transmission frequency division control unit and the output frequency division control unit are both electrically connected to the first node; The input unit comprises an input transistor, a gate of the input transistor is loaded with the clock signal, a source of the input transistor is configured as an input terminal of the input unit, and a drain of the input transistor is configured as an output terminal of the input unit; The fourth node control unit includes a first transistor, a seventh transistor, a second transistor and a third transistor connected in series, the gate of the seventh transistor is electrically connected to the drain of the input transistor, the source of the seventh transistor is loaded with the clock signal, the gate of the first transistor is loaded with the clock signal, the source of the first transistor is loaded with the second voltage, the drain of the first transistor is electrically connected to the gate of the second transistor and the drain of the seventh transistor, the drain of the second transistor is electrically connected to the source of the third transistor, the source of the second transistor and the gate of the third transistor are both loaded with the clock signal, and the drain of the third transistor is electrically connected to the fourth node; The second node control unit includes a fourth transistor, a first capacitor, a fifth transistor and a sixth transistor arranged in series, the gate of the fourth transistor is loaded with a control signal, the source of the fourth transistor is loaded with the first voltage, the drain of the fourth transistor is electrically connected to the second node, the gate of the fifth transistor is electrically connected to the drain of the first transistor, the source of the fifth transistor is loaded with the first voltage, the drain of the fifth transistor is electrically connected to the source of the sixth transistor, the drain of the sixth transistor is loaded with the clock signal, the gate of the sixth transistor is also loaded with the level transmission signal generated by the upper gate drive circuit, and the first capacitor is electrically connected between the gate and the drain of the sixth transistor.

11. The gate driving module according to claim 10, characterized in that: The second node control unit also includes: a tenth transistor, wherein a source of the tenth transistor is loaded with the level transmission signal generated by the upper gate driving circuit, a gate of the tenth transistor is loaded with the clock signal, and a drain of the tenth transistor is electrically connected to the gate of the sixth transistor; an eleventh transistor, wherein a gate and a source of the eleventh transistor are both electrically connected to the gate of the sixth transistor, and a drain of the eleventh transistor is electrically connected to the second node.

12. A display panel, characterized in that: include: The gate drive module according to any one of claims 2 to 11; A panel body, comprising a plurality of sub-pixels and a plurality of scanning lines, wherein the plurality of sub-pixels comprise light-emitting devices and a pixel driving circuit for driving the light-emitting devices to emit light, wherein the pixel driving circuit comprises at least one transistor; The gate control signal output by the gate driving circuit is transmitted to the gates of the plurality of transistors in the corresponding plurality of pixel driving circuits via the corresponding scanning lines.

13. The display panel according to claim 12, characterized in that: The display panel is in a frequency reduction mode and a frequency increase mode in a time-sharing manner, and the plurality of gate driving circuits include a plurality of first gate driving circuits cascaded together and a plurality of second gate driving circuits cascaded together after the plurality of first gate driving circuits; The plurality of sub-pixels include a plurality of first sub-pixels electrically connected to a plurality of the first gate driving circuits, and a plurality of second sub-pixels electrically connected to a plurality of the second gate driving circuits, the plurality of the first sub-pixels constitute a first display area, and the plurality of the second sub-pixels constitute a second display area; In the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area; In the frequency-upgrading mode, the refresh rate of the first display area is lower than the refresh rate of the second display area.

14. The display panel according to claim 13, characterized in that: In the frequency reduction mode, the first frequency division control signal is used to control the third node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the first type of frame, the second frequency-divided control signal is used to control the first node or the second node in the first gate driving circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device; In the first type of frame, the second frequency division control signal is also used to control the first node or the second node and the fourth node in the second gate drive circuit to open the circuit, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

15. The display panel according to claim 13, characterized in that: In the frequency reduction mode, the second frequency division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the second type of frame, the first frequency division control signal is used to control the third node in the first gate driving circuit to be electrically connected to the first node or the second node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light emitting device; In the second type of frame, the first frequency division control signal is also used to control the circuit between the third node and the first node or the second node in the second gate drive circuit to be disconnected, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

16. The display panel according to any one of claims 13 to 15, characterized in that: In the frequency-up mode, the second frequency-division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the third type of frame, the first frequency division control signal is used to control the disconnection between the third node and the first node or the second node (for FIG. 3 ) in the first gate driving circuit, so as to control the output gate control signal to have no gate effective pulse, so as not to turn on the corresponding light emitting device; In the third type of frame, the first frequency-division control signal is used to control the first node or the second node in the second gate drive circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have the gate effective pulse to turn on the corresponding light-emitting device.

17. The display panel according to claim 12, characterized in that: The gate driving module comprises n-stage gate driving circuits cascaded in sequence, where n is a positive integer greater than or equal to 2, and the n-stage gate driving circuits are all loaded with the same clock signal; In one frame, the clock signal is alternately equal to the first clock voltage and the second clock voltage during the period of time when it effectively acts on the gate driving circuit of the i-th level to the (i+k)-th level, and i and k are both positive integers greater than or equal to 1; Among them, when the gate control signals output by the gate driving circuits of the (i+k+1)th to nth levels do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period when it effectively acts on the gate driving circuits of the (i+k+1)th to nth levels.

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