Display device and display panel

Abstract

The invention relates to a display device and a display panel. A display device according to one or more examples may include: a substrate; the display area is provided with a first display area and a second display area; a non-display area; a base circuit layer on the substrate and including an in-panel gate circuit and a sub-pixel circuit array disposed in the display area; and a light emitting device layer on the base circuit layer and including two or more first light emitting devices disposed in the first display area and two or more second light emitting devices disposed in the second display area. The sub-pixel circuit array may include: one first sub-pixel circuit configured to simultaneously drive two or more first light emitting devices and disposed in the second display area; and two or more second sub-pixel circuits configured to respectively drive the two or more second light emitting devices and disposed in the second display area.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device, and more particularly, for example but not limited to, to a display device and a display panel. Background Art

[0002] The display device may include: a display panel on which a plurality of data lines and a plurality of gate lines are arranged; a data driving circuit for driving the plurality of data lines; and a gate driving circuit for driving the plurality of gate lines. Here, the display panel may include a display area for displaying an image and a non-display area for not displaying an image.

[0003] In the case of a general display device, the gate drive circuit can be connected to or arranged in the non-display area (also called the frame) of the display panel. Therefore, the non-display area (i.e., the frame) of the display panel needs to have a specific size sufficient to connect or place the gate drive circuit.

[0004] The description of related art should not be assumed to be prior art merely because it is mentioned in or associated with this section. The description of related art may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the invention

[0005] The inventors of the present disclosure have recognized the problems and disadvantages of the related art and have conducted extensive research and experiments. Therefore, the inventors of the present disclosure have invented a new display device and display panel that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0006] One or more example embodiments of the present disclosure may provide a display panel and a display device having an extremely narrow bezel structure.

[0007] One or more example embodiments of the present disclosure may provide a display panel and a display device in which an intra-panel gate circuit as a gate driving circuit of an intra-panel gate type is provided in a display region.

[0008] One or more example embodiments of the present disclosure may provide a display panel and a display apparatus in which an in-panel gate circuit is disposed to overlap a light emitting device layer in a vertical direction.

[0009] One or more example embodiments of the present disclosure may provide a display panel and a display apparatus having a structure capable of shielding an electric field between a gate circuit and a light emitting device layer within a panel.

[0010] One or more example embodiments of the present disclosure may provide a display panel and a display device in which a connection structure of a cathode and a base voltage line is disposed within a display area.

[0011] A display device according to one or more example embodiments of the present disclosure may include: a substrate; a display area having a first display area and a second display area; a non-display area located outside the display area; a basic circuit layer located on the substrate and including an intra-panel gate circuit and a sub-pixel circuit array arranged in the display area; and a light-emitting device layer located on the basic circuit layer and including two or more first light-emitting devices arranged in the first display area and two or more second light-emitting devices arranged in the second display area.

[0012] The sub-pixel circuit array may include: a first sub-pixel circuit, which is configured to simultaneously drive two or more first light-emitting devices and is arranged in a second display area; and two or more second sub-pixel circuits, which are configured to respectively drive two or more second light-emitting devices and are arranged in the second display area.

[0013] The in-panel gate circuit may be disposed in the first display area, and the sub-pixel circuit array may be disposed in the second display area.

[0014] At least some of the two or more first light emitting devices may overlap at least a portion of a gate circuit within a panel, and at least some of the two or more second light emitting devices may overlap at least a portion of a sub-pixel circuit array.

[0015] A display device according to one or more example embodiments of the present disclosure may further include an extension link (if the pixel electrode is an anode, it may also be referred to as an anode extension link) connecting a first sub-pixel circuit disposed in the second display area to two or more first light-emitting devices disposed in the first display area.

[0016] The extended link may include metal between the base circuit layer and the light emitting device layer.

[0017] The first display area may be located between the non-display area and the second display area.

[0018] The display device according to one or more example embodiments of the present disclosure may further include a shielding layer between the gate circuit and the light emitting device layer within the panel.

[0019] In the case where the display device according to one or more example embodiments of the present disclosure further includes an extended link connecting one first sub-pixel circuit to two or more pixel electrodes included in two or more first light-emitting devices, the shielding layer may be located between the extended link and the in-panel gate circuit, and at least a portion of the shielding layer may overlap the extended link and the in-panel gate circuit. The shielding layer may be disposed in the first display area.

[0020] The display device according to one or more example embodiments of the present disclosure may further include a base voltage line applying a base voltage, and a cathode connection pattern electrically connecting the cathode and the base voltage line.

[0021] The display device according to one or more example embodiments of the present disclosure may further include an anode extension link connecting one first sub-pixel circuit to the two or more first light emitting devices.

[0022] The cathode connection pattern may include a first cathode connection pattern disposed on the same metal layer as the anode extension link.

[0023] The base voltage line and the cathode connection pattern may be located in the non-display area.

[0024] The base voltage line may be disposed outside the gate circuit within the panel.

[0025] The display device according to one or more example embodiments of the present disclosure may further include a shielding layer disposed in the first display region and between the in-panel gate circuit included in the base circuit layer and the light emitting device layer. In this case, the shielding layer may be electrically connected to the cathode connection pattern.

[0026] The base voltage line and the cathode connection pattern may be located in the display area.

[0027] The cathode may be electrically connected to at least one of a cathode connection pattern and a base voltage line located below the bank through a hole in the bank between the two or more second anodes.

[0028] A display panel according to one or more example embodiments of the present disclosure may include: a substrate; a display area having a first display area and a second display area; a non-display area located outside the display area; two or more first light-emitting devices, the two or more first light-emitting devices being arranged in the first display area; a plurality of second light-emitting devices, the plurality of second light-emitting devices being arranged in the second display area; a first sub-pixel circuit, the first sub-pixel circuit being commonly connected to the two or more first light-emitting devices; and two or more second sub-pixel circuits. Each of the two or more second sub-pixel circuits may be connected to a second light-emitting device among the plurality of second light-emitting devices.

[0029] The display panel according to one or more example embodiments of the present disclosure may further include an intra-panel gate circuit disposed in the first display area.

[0030] The display panel according to one or more example embodiments of the present disclosure may further include an extension link commonly connecting a pixel electrode of each of the two or more first light emitting devices to one first sub-pixel circuit.

[0031] The display panel according to one or more example embodiments of the present disclosure may further include a shielding layer disposed between the in-panel gate circuit and the extension link.

[0032] A display device according to one or more example embodiments of the present disclosure may include: a substrate; a display area; a light-emitting device layer, which is disposed above the substrate and includes a plurality of light-emitting devices disposed in the display area; and a basic circuit layer, which is disposed between the light-emitting device layer and the substrate and includes a gate drive circuit and a sub-pixel circuit.

[0033] The gate drive circuit and the sub-pixel circuit can be arranged in the display area, and at least a portion of the gate drive circuit can overlap with one or more first light-emitting devices among the multiple light-emitting devices; and at least a portion of the sub-pixel circuit can overlap with one or more second light-emitting devices among the multiple light-emitting devices.

[0034] The cathode may be disposed on the light emitting layers of the plurality of light emitting devices. The cathode may overlap at least a portion of the gate driving circuit and at least a portion of the sub-pixel circuit.

[0035] The gate driving circuit may send a scan signal to a scan line of the sub-pixel circuit or send a light emission control signal to a light emission control line of the sub-pixel circuit. One or more sub-pixel circuits in the sub-pixel circuit may drive one or more second light emitting devices.

[0036] According to one or more example embodiments of the present disclosure, a display panel and a display device having an extremely narrow bezel structure may be provided.

[0037] According to one or more example embodiments of the present disclosure, an intra-panel gate circuit as an intra-panel gate type gate driving circuit may be provided in a display area, thereby reducing the size of a non-display area.

[0038] According to one or more example embodiments of the present disclosure, the in-panel gate circuit is arranged to overlap with the light emitting device layer in a vertical direction, thereby reducing the size of the non-display area.

[0039] According to one or more example embodiments of the present disclosure, a structure capable of shielding an electric field between a gate circuit in a panel and a light emitting device layer may be provided, thereby eliminating unnecessary electrical effects between the gate circuit in the panel and the light emitting device layer.

[0040] According to one or more example embodiments of the present disclosure, a connection structure between a cathode and a base voltage line is provided in a display area, thereby further reducing the size of a non-display area.

[0041] According to one or more exemplary embodiments of the present disclosure, the gate drive circuit and the cathode connection structure are arranged in the display area, so that the length of the path through which the gate signal output from the gate drive circuit is provided to the sub-pixel circuit can be shortened, and the length of the cathode connection structure can also be shortened. The hanger on the structure can also be shortened. Therefore, the metal used in the path can be reduced, thereby enabling the display panel and the display device to be lightened.

[0042] After reviewing the drawings and detailed description herein, other devices, apparatus, panels, methods, features and advantages will be or will become apparent to those skilled in the art. All such devices, apparatus, panels, methods, features and advantages are intended to be included in this specification, within the scope of the present disclosure and protected by the appended claims. Nothing in this section should be construed as limiting the claims. Other aspects and advantages are discussed below in conjunction with the embodiments of the present disclosure.

[0043] It is to be understood that both the foregoing description and the following description of the present disclosure are examples and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and constitute a part of the disclosure, illustrate aspects and embodiments of the disclosure, and together with the description serve to explain principles and examples of the disclosure.

[0045] Figure 1 is a system configuration diagram of a display device according to one or more example embodiments of the present disclosure.

[0046] Figure 2 A display panel according to one or more example embodiments of the present disclosure is illustrated.

[0047] Figure 3 and Figure 4 A vertical structure and a planar structure of a display area of ​​a display panel according to one or more example embodiments of the present disclosure are illustrated.

[0048] Figure 5 and Figure 6 yes Figure 4An example of a plan view of a partial area of ​​a display panel.

[0049] Figure 7 The corresponding relationship between the sub-pixel circuits and the light emitting devices in the display panel according to one or more example embodiments of the present disclosure is illustrated.

[0050] Figure 8 Only the corresponding relationship between the first sub-pixel circuit and the first light emitting device in the display panel according to one or more example embodiments of the present disclosure is illustrated.

[0051] Fig. 9 is an equivalent circuit of a sub-pixel disposed on or in a display panel according to one or more example embodiments of the present disclosure.

[0052] Fig. 10A and Fig. 10B An in-panel gate circuit provided on or in a display panel according to one or more example embodiments of the present disclosure is illustrated.

[0053] Fig.11 is an equivalent circuit of a sub-pixel disposed on or in a display panel according to one or more example embodiments of the present disclosure.

[0054] Fig.12 An in-panel gate circuit provided on or in a display panel according to one or more example embodiments of the present disclosure is illustrated.

[0055] Fig.13 An in-panel gate circuit provided on or in a display panel according to one or more example embodiments of the present disclosure is illustrated.

[0056] Fig.14 A vertical structure of a display panel according to one or more example embodiments of the present disclosure is illustrated.

[0057] Fig.15 is a cross-sectional view illustrating a vertical structure of a display panel according to one or more example embodiments of the present disclosure.

[0058] Fig.16 is another plan view of a partial area of ​​a display panel according to one or more example embodiments of the present disclosure.

[0059] Fig.17 is another cross-sectional view illustrating a vertical structure of a display panel according to one or more example embodiments of the present disclosure.

[0060] Fig.18is another cross-sectional view illustrating a vertical structure of a display panel according to one or more example embodiments of the present disclosure.

[0061] Fig.19 is another cross-sectional view illustrating a vertical structure of a display panel according to one or more example embodiments of the present disclosure.

[0062] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures.The size, length, thickness, and depiction of layers, regions, and elements may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0063] Reference is now made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known methods, functions, structures, or configurations may be omitted for the sake of brevity when such detailed descriptions may unnecessarily obscure aspects of the present disclosure. Furthermore, repeated descriptions may be omitted for the sake of brevity. The described progression of processing steps and / or operations are non-limiting examples.

[0064] The order of steps and / or operations is not limited to the order set forth herein, and except for steps and / or operations that must occur in a particular order, they may be changed to occur in a different order than that described herein. In one or more examples, two operations in succession may be performed substantially simultaneously, or two operations may be performed in reverse order or in a different order, depending on the functions or operations involved.

[0065] Unless otherwise noted, the same reference numerals may always refer to the same elements even if shown in different figures. Unless otherwise noted, the same reference numerals may be used to refer to the same or substantially the same elements throughout the specification and drawings. In one or more aspects, the same elements (or elements with the same names) in different figures may have the same or substantially the same functions and characteristics unless otherwise noted. The names of the corresponding elements used in the following explanations are selected for convenience only and therefore may be different from the names used in the actual product.

[0066] The advantages and features of the present disclosure and their implementation methods are explained by referring to the embodiments described in the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are examples and are provided so that the present disclosure can be thorough and complete, to help those skilled in the art understand the inventive concept without limiting the scope of protection of the present disclosure.

[0067] The shapes, dimensions (e.g., size, length, width, height, thickness, position, radius, diameter, and area), proportions, ratios, angles, quantities, number of elements, etc. disclosed herein (including those shown in the drawings) are merely examples, and thus, the present disclosure is not limited to the details shown. However, it should be noted that the relative dimensions of the components shown in the drawings are part of the present disclosure.

[0068] When the terms "including", "having", "containing", "comprising", "made of", "formed of", "composed of", "composed of", etc. are used with respect to one or more elements (e.g., layers, films, regions, components, sections, members, parts, regions, areas, parts, steps, operations, etc.), unless terms such as "only" are used, one or more other elements may be added. The terms used in the present disclosure are only used to describe specific example embodiments and are not intended to limit the scope of the present disclosure. Unless the context clearly indicates otherwise, terms in the singular may include plural forms. The word "exemplary" is used to indicate use as an example or illustration. An embodiment is an example embodiment. An aspect is an example aspect. "An embodiment", "an example", "an aspect", etc. should not be interpreted as being better than or superior to other implementations. Unless otherwise specified, an embodiment, an example, an example embodiment, an aspect, etc. may refer to one or more embodiments, one or more examples, one or more example embodiments, one or more aspects, etc. In addition, the term "may" covers all meanings of the term "can".

[0069] In one or more aspects, unless explicitly stated otherwise, elements, features, or corresponding information (e.g., levels, ranges, dimensions, sizes, etc.) are interpreted as including an error or tolerance range even if no explicit description of such an error or tolerance range is provided. The error or tolerance range may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). When interpreting a numerical value, unless explicitly stated otherwise, the value is interpreted as including an error range.

[0070] When any of the terms indicating position or location such as "on", "on top of", "over", "on top of", "above", "below", "above", "upper", "lower", "below", "beneath", "near", "near", "adjacent", "adjacent to", "beside", "at or on one side" and the like are used to describe the positional relationship between two elements (e.g., layers, films, regions, components, sections, members, parts, areas, zones, parts, etc.), one or more other elements may be located between the two elements unless more restrictive terms such as "immediately adjacent", "directly", or "closely" are used. For example, when any of the aforementioned terms are used to describe an element and another element, the description should be interpreted as including the case where the elements are in direct contact with each other and the case where one or more additional elements are disposed or inserted therebetween. In addition, spatially relative terms such as the aforementioned terms and other terms such as "front", "back", "rear", "left", "right", "top", "bottom", "downward", "upward", "up", "down", "column", "row", "vertical", "horizontal", "diagonal", etc. refer to an arbitrary reference system. For example, these terms can be used to illustrate the relative relationship between elements, including any correlation shown in the drawings. However, the embodiments of the present disclosure are not limited or not limited thereto. Spatially relative terms should be understood as terms that include different orientations of elements in use or operation in addition to the orientations depicted in the drawings or described herein. For example, in the case where a lower element or an element located below another element is flipped, the element can be referred to as an upper element or an element located above another element. Therefore, for example, the term "below" or "below" can encompass the term "above" or "above" in meaning. Example terms "below" etc. can include all directions including "below", "above" and diagonal directions. Similarly, example terms "above", "on" etc. can include all directions, including "above", "on", "below" and diagonal directions.

[0071] When describing a temporal relationship, when the temporal order is described as, for example, "after", "subsequently", "next", "before", "precedes", "in front of", etc., unless more restrictive terms such as "just", "immediately" or "directly" are used, discontinuous or non-sequential situations may also be included, and therefore one or more other events may occur in between.

[0072] It should be understood that although the terms "first", "second", etc. can be used to describe various elements (e.g., layers, films, regions, components, sections, members, parts, zones, parts, steps, operations, etc.) in this article, these elements should not be limited by these terms (e.g., limited to any particular order, priority, or number of elements). These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can represent the second element, and similarly, the second element can represent the first element. In addition, without departing from the scope of the present disclosure, the first element, the second element, etc. can be arbitrarily named according to the convenience of those skilled in the art. For the sake of clarity, the function or structure of these elements (e.g., the first element, the second element, etc.) is not limited by the ordinal number or name in front of the element. In addition, the first element can include one or more first elements. Similarly, the second element, etc. can include one or more second elements, etc.

[0073] When describing elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", "(b)", etc. may be used. These terms are intended to identify corresponding elements from other elements, and these terms are not used to define the nature, basis, order or number of the elements.

[0074] When an element (for example, a layer, a film, a region, a component, a section, a member, a part, a section, a portion, etc.) is “connected”, “coupled”, “attached”, “bonded”, “linked”, etc. to another element, unless otherwise specified, the element may not only be directly connected, coupled, attached, bonded, linked, etc. to the other element, but may also be indirectly connected, coupled, attached, bonded, linked, etc. to the other element with one or more intermediate elements disposed or interposed between the elements.

[0075] Regarding the expression that an element (for example, a layer, film, region, component, section, member, part, zone, portion, etc.) is "contacting", "overlapping", etc. with another element, unless otherwise specified, the element may not only directly contact, overlap, etc. with the other element but also may indirectly contact, overlap, etc. with the other element with one or more intermediate elements disposed or interposed between the elements.

[0076] Phrases where an element (e.g., a layer, a film, a region, a component, a section, a member, a component, a zone, a portion, etc.) is "equipped with," "set," "connected," "coupled," etc. in another element, "equipped with," "set," "connected," "coupled," etc. on another element, "equipped with," "set," "connected," "coupled," etc. with another element, or "equipped with," "set," "connected," "coupled," etc. to another element may be understood, for example, that at least a portion of the element is equipped, set, connected, coupled, etc. in at least a portion of another element, equipped, set, connected, coupled, etc. on at least a portion of another element, equipped, set, connected, coupled, etc. with at least a portion of another element, or equipped, set, connected, coupled, etc. to at least a portion of another element. The phrase "through" may be understood, for example, at least partially through or completely through. Phrases where an element (e.g., a layer, a film, a region, a component, a section, a member, a component, a zone, a portion, etc.) is "in contact with," "overlaps," etc. with another element may be understood, for example, that at least a portion of the element is in contact with, overlaps, etc. with at least a portion of another element.

[0077] Terms such as "line" or "direction" should not be interpreted solely based on the geometric relationship of the corresponding lines or directions being parallel, perpendicular, diagonal or inclined relative to each other, and may mean lines or directions having a wider direction within the range in which the components of the present disclosure can functionally operate.

[0078] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, each of the phrases "at least one of the first, second, or third items" and "at least one of the first, second, and third items" can mean (i) a combination of items provided by two or more of the first, second, and third items, or (ii) only one of the first, second, or third items.

[0079] The expression of a first element, a second element “and / or” a third element should be understood as one of the first element, the second element, and the third element or any or all combinations of the first element, the second element, and the third element. By way of example, A, B, and / or C may refer to only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. In addition, the expression “A / B” may be understood as A and / or B. For example, the expression “A / B” may refer to only A; only B; A or B; or A and B.

[0080] In one or more aspects, unless otherwise specified, the terms "between" and "among" may be simply used interchangeably. For example, the expression "between a plurality of elements" may be understood as among a plurality of elements. In another example, the expression "among a plurality of elements" may be understood as between a plurality of elements. In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. In addition, when an element (e.g., a layer, a film, a region, a component, a section, a member, a part, a zone, a portion, etc.) is referred to as being "between" at least two elements, the element may be the only element between the at least two elements, or one or more intermediate elements may also be present.

[0081] In one or more aspects, unless otherwise specified, the phrases "each other" and "mutually" may be used interchangeably for convenience. For example, the expression "different from each other" may be understood as different from each other. In another example, the expression "different from each other" may be understood as different from each other. In one or more examples, the number of elements involved in the foregoing statements may be two. In one or more examples, the number of elements involved in the foregoing statements may exceed two.

[0082] In one or more aspects, unless otherwise indicated, the phrases "one or more of" and "one or more of" may be used interchangeably simply for convenience.

[0083] The term "or" means an inclusive or, not an exclusive or. That is, unless otherwise specified or clear from the context, the statement "x employs a or b" means any of the natural inclusive permutations. For example, "a or b" can mean "a", "b", or "a and b". For example, "a, b or c" can mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0084] The features of the various embodiments of the present disclosure may be partially or completely connected or combined with each other, may be technically associated with each other, and may be operated, linked or driven together in various ways. The embodiments of the present disclosure may be implemented or executed independently of each other, or may be implemented or executed together in a mutually dependent or related relationship. In one or more aspects, the components of each device and apparatus according to the various embodiments of the present disclosure may be operationally connected and configured.

[0085] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as those generally understood by a person of ordinary skill in the art to which the example embodiments belong. It should also be understood that, unless otherwise explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense. For example, the term "component" may apply to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function as would be understood by a person of ordinary skill in the art.

[0086] The terms used herein have been selected as general terms in the relevant technical field; however, other terms may exist according to the development and / or change of technology, convention, preference of technicians, etc. Therefore, the terms used herein should not be understood as limiting the technical ideas, but should be understood as examples of terms used to describe example embodiments.

[0087] In addition, in certain cases, the terms may be arbitrarily selected by the applicant, and in this case, the detailed meanings thereof are described herein. Therefore, the terms used herein should be understood not only based on the names of the terms but also based on the meanings of the terms and their contents.

[0088] In the following description, various example embodiments of the present disclosure are described in detail with reference to the accompanying drawings. With respect to the reference numerals of the elements of each of the accompanying drawings, the same elements may be illustrated in other drawings, and unless otherwise specified, the same reference numerals may refer to the same elements. Even if they are depicted in different drawings, the same or similar elements may be represented by the same reference numerals. In addition, for ease of description, the scale, size, size and thickness of each of the elements shown in the accompanying drawings may be different from the actual scale, size, size and thickness, and therefore, the embodiments of the present disclosure are not limited to the scale, size, size and thickness shown in the accompanying drawings.

[0089] Figure 1 is a system configuration diagram of a display device 100 according to one or more example embodiments of the present disclosure.

[0090] Reference Figure 1 The display device 100 according to one or more exemplary embodiments of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit is a circuit for driving the display panel 110, and may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0091] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0092] The substrate 111 of the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA located outside the display area DA.

[0093] In the display panel 110 according to one or more example embodiments of the present disclosure, the non-display area NDA may be very small.

[0094] For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction intersecting the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. One or both of the first to fourth non-display areas may include a pad area connected or joined to the data driving circuit 120. Among the first to fourth non-display areas, the size of two or three non-display areas not including the pad area may be very small.

[0095] As another example, the boundary area between the display area DA and the non-display area NDA may be curved so that the non-display area NDA may be located below the display area. In this case, when the user views the display device 100 from the front, little or no non-display area NDA may be visible to the user.

[0096] Various types of signal lines for driving the plurality of sub-pixels SP may be disposed on the substrate 111 of the display panel 110 .

[0097] The display device 100 according to one or more example embodiments of the present disclosure may be a liquid crystal display device, etc., or may be a self-luminous display device in which the display panel 110 emits light itself. When the display device 100 according to one or more example embodiments of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0098] For example, the display device 100 according to one or more example embodiments of the present disclosure may be an organic light-emitting display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to one or more example embodiments of the present disclosure may be an inorganic light-emitting display device in which the light-emitting device is implemented as an inorganic-based light-emitting diode. As another example, the display device 100 according to one or more example embodiments of the present disclosure may be a quantum dot display device in which the light-emitting device is implemented using quantum dots, which are semiconductor crystals that emit light by themselves.

[0099] The structure of each of the plurality of subpixels SP may vary according to the type of the display device 100. For example, if the display device 100 is a self-luminous display device having self-luminous subpixels SP, each subpixel SP may include a self-luminous light emitting device, one or more transistors, and one or more capacitors.

[0100] For example, the various types of signal lines may include a plurality of data lines DL for supplying data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL for transmitting gate signals (also referred to as scan signals).

[0101] For example, a plurality of data lines DL and a plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for ease of explanation, an example will be given of a case where each of the plurality of data lines DL is arranged in a column direction and each of the plurality of gate lines GL is arranged in a row direction.

[0102] The data driving circuit 120 is a circuit for driving the plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0103] The data driving circuit 120 may receive image data in a digital form from the display controller 140 and convert the received image data into analog data signals to output to the plurality of data lines DL.

[0104] For example, the data driving circuit 120 can be connected to the display panel 110 using a tape automated bonding (TAB) method, or can be connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or can be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0105] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. The data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110 according to a driving method, a panel design method, etc.

[0106] The data driving circuit 120 may be connected to the outside of the display area DA of the display panel 110 , but alternatively, the data driving circuit 120 may be provided in the display area DA of the display panel 110 .

[0107] The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL, and may output a gate signal to the plurality of gate lines GL.

[0108] The gate driving circuit 130 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage and various gate driving control signals GCS, and may generate a gate signal and provide the generated gate signal to a plurality of gate lines GL.

[0109] In the display device 100 according to one or more example embodiments of the present disclosure, the gate driving circuit 130 may be built into the display panel 110 as a gate-in-panel (GIP) type. If the gate driving circuit 130 is a gate-in-panel type, the gate driving circuit 130 may be formed on a substrate of the display panel 110 during a manufacturing process of the display panel 110.

[0110] In the display device 100 according to one or more example embodiments of the present disclosure, the gate drive circuit 130 may be disposed in the display area DA of the display panel 110. For example, the gate drive circuit 130 may be disposed in a first partial area (e.g., a left area or a right area) within the display area DA. As another example, the gate drive circuit 130 may be disposed in a first partial area (e.g., a left area or a right area within the display area DA) and a second partial area (e.g., a right area or a left area within the display area DA) within the display area DA.

[0111] In the present disclosure, the gate driving circuit 130 built in the display panel 110 as an in-panel gate type may be referred to as an “in-panel gate circuit”.

[0112] The display controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130 , and may control driving timings of the plurality of data lines DL and driving timings of the plurality of gate lines GL.

[0113] The display controller 140 may provide a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and may provide a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 130 .

[0114] The display controller 140 may receive input image data from the host system 150 and provide image data DATA to the data driving circuit 120 based on the input image data.

[0115] The display controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0116] The display controller 140 may be a timing controller used in typical display technologies, or may be a control device including a timing controller capable of further performing other control functions, or may be a control device different from the timing controller, or may be a control device other than the timing controller, or may be a circuit within the control device. The display controller 140 may be implemented with various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0117] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or another component, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit.

[0118] The display controller 140 may transmit and receive data with the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock dot-dot interface (EPI) interface, or a serial peripheral interface (SPI).

[0119] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to one or more example embodiments of the present disclosure may include a touch sensor and a touch sensing circuit for detecting occurrence of a touch of a touch object such as a finger or a pen or detecting a touch position by sensing the touch sensor.

[0120] The touch sensing circuit may include: a touch driving circuit for driving and sensing the touch sensor to generate and output touch sensing data; and a touch controller for detecting occurrence of a touch or detecting a touch position using the touch sensing data.

[0121] The touch sensor may include a plurality of touch electrodes and may further include a plurality of touch lines to electrically connect the plurality of touch electrodes with a touch driving circuit.

[0122] The touch sensor may exist outside the display panel 110 in the form of a touch panel, or may exist inside the display panel 110. If the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. If the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately and combined during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes located on the touch panel substrate.

[0123] If the touch sensor exists inside the display panel 110 , the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0124] The touch driving circuit may provide a touch driving signal to at least one of the plurality of touch electrodes, and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0125] The touch sensing circuit may perform touch sensing using a self-capacitance sensing method or a mutual capacitance sensing method.

[0126] If the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, or another object). According to the self-capacitance sensing method, each of the plurality of touch electrodes may be used as a driving touch electrode and a sensing touch electrode. The touch drive circuit 260 may drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0127] If the touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing method, the plurality of touch electrodes may be divided into a driving touch electrode and a sensing touch electrode. The touch driving circuit may drive the driving touch electrode and sense the sensing touch electrode.

[0128] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as one device. In addition, the touch driving circuit 260 and the data driving circuit 120 may be implemented as separate devices or as one device.

[0129] The display device 100 may further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0130] The display device 100 according to one or more example embodiments of the present disclosure may be a mobile terminal such as a smart phone or a tablet, or monitors or televisions of various sizes, but is not limited thereto, and may be displays of various types and sizes capable of displaying information or images.

[0131] The display device 100 according to one or more exemplary embodiments of the present disclosure may further include an electronic device such as a camera (e.g., an image sensor) and a detection sensor. For example, the detection sensor may be a sensor for detecting an object or a human body by receiving light such as infrared, ultrasonic, or ultraviolet rays.

[0132] Figure 2 The display panel 110 according to one or more example embodiments of the present disclosure is illustrated.

[0133] Reference Figure 2 , the display panel 110 may include a substrate 111 disposed in a plurality of sub-pixels SP and an encapsulation layer 220 located on the substrate 111. Here, the encapsulation layer 220 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0134] Reference Figure 2 , when the display device 100 according to one or more example embodiments of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting device ED and a sub-pixel circuit SPC for driving the light emitting device ED.

[0135] Reference Figure 2 , the sub-pixel circuit SPC may include at least one capacitor and a plurality of pixel driving transistors for driving the light emitting device ED. In the present disclosure, the sub-pixel circuit SPC may drive the light emitting device ED by providing a driving current to the light emitting device ED at a predetermined timing. The light emitting device ED may be driven by the driving current and emit light.

[0136] The plurality of pixel driving transistors may include a driving transistor DT for driving the light emitting device ED and a scanning transistor ST turned on or off according to a scanning signal SC. The scanning transistor ST may be configured to control an electrical state of a corresponding node in the sub-pixel circuit SPC or to control a state or operation of the driving transistor DT.

[0137] The at least one capacitor may include a storage capacitor Cst to maintain a constant voltage during a frame.

[0138] To drive the subpixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the subpixel SP. In addition, a common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS may be applied to the subpixel SP to drive the subpixel SP.

[0139] The light emitting device ED may include an anode AND, a device intermediate layer EL, and a cathode CAT. The device intermediate layer EL may be a layer disposed between the anode AND and the cathode CAT, and may include a light emitting layer EML.

[0140] In the case where the light emitting device ED is an organic light emitting device, the device intermediate layer EL may include a light emitting layer EML, a first common layer COM1 between the anode AND and the light emitting layer EML, and a second common layer COM2 between the light emitting layer EML and the cathode. The light emitting layer EML may be disposed in each sub-pixel SP. In contrast, the first common layer COM1 and the second common layer COM2 may be commonly disposed across a plurality of sub-pixels SP. The light emitting layer EML may be disposed in each light emitting region, and the first common layer COM1 and the second common layer COM2 may be commonly disposed across a plurality of light emitting regions and non-light emitting regions.

[0141] For example, the first common layer COM1 may include a hole injection layer HIL and a hole transport layer HTL, and the second common layer COM2 may include an electron transport layer ETL and an electron injection layer EIL. The hole injection layer may inject holes from the anode AND into the hole transport layer, the hole transport layer may transport holes to the light emitting layer EML, the electron injection layer may inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer may transport electrons to the light emitting layer EML.

[0142] For example, the cathode CAT may be electrically connected to a second driving voltage line VSSL. A second driving voltage VSS as a common pixel driving voltage may be applied to the cathode CAT through the second driving voltage line VSSL. The anode AND may be electrically connected to a first node N1 of a driving transistor DT of each sub-pixel SP. In the present disclosure, the second driving voltage VSS may also be referred to as a base voltage VSS, and the second driving voltage line VSSL may also be referred to as a base voltage line VSSL.

[0143] For example, the anode AND may be a pixel electrode provided in each sub-pixel SP, and the cathode CAT may be a common electrode provided in common in the plurality of sub-pixels SP. As another example, the cathode CAT may be a pixel electrode provided in each sub-pixel SP, and the anode AND may be a common electrode provided in common in the plurality of sub-pixels SP. Hereinafter, for ease of explanation, it is assumed that the anode AND is a pixel electrode, and the cathode CAT is a common electrode.

[0144] Each light emitting device ED may be composed of an overlapping portion of an anode AND, a device intermediate layer EL, and a cathode CAT. A predetermined light emitting region may be formed by each light emitting device ED. For example, the light emitting region of each light emitting device ED may include an overlapping region of an anode AND, a device intermediate layer EL, and a cathode CAT.

[0145] For example, the light emitting device ED may be an organic light emitting diode (OLED), an inorganic light emitting diode or a quantum dot light emitting device. For example, in the case where the light emitting device ED is an organic light emitting diode OLED, the device intermediate layer EL in the light emitting device ED may include an organic device intermediate layer EL including an organic material.

[0146] The driving transistor DT may be a driving transistor for providing a driving current to the light emitting device ED. The driving transistor DT may be connected between the first driving voltage line VDDL and the light emitting device ED.

[0147] The driving transistor DT may include a first node N1 electrically connected to the light emitting device ED, a second node N2 to which the data signal VDATA is applied, and a third node N3 to which the driving voltage VDD is applied from the driving voltage line DVL.

[0148] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, a case in which the second node N2 is a gate node, the first node N1 is a source node, and the third node N3 is a drain node in the driving transistor DT will be described.

[0149] Included in Figure 2 The scan transistor ST in the illustrated sub-pixel circuit SPC may be a switching transistor for transmitting the data signal VDATA, which is an image signal, to the second node N2, which is a gate node of the driving transistor DT.

[0150] The scanning transistor ST may be controlled to be turned on or off by a scanning signal SC which is a gate signal applied by a scanning line SCL as a kind of gate line GL, and the scanning transistor ST may control the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain electrode or the source electrode of the scanning transistor ST may be electrically connected to the data line DL, and the source electrode or the drain electrode of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate electrode of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0151] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0152] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (eg, Cgs, Cgd) that is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0153] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0154] At least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light emitting device ED in the vertical direction. Alternatively, the sub-pixel circuit SPC may not overlap with the light emitting device ED in the vertical direction.

[0155] like Figure 2 As shown, the sub-pixel circuit SPC may have a 2T-1C structure including two transistors T1 and T2 and one capacitor Cst. In some cases, depending on this, the sub-pixel circuit SPC may also include one or more transistors or one or more capacitors.

[0156] For example, the sub-pixel circuit SPC may have an 8T-1C structure including eight transistors and a single capacitor. As another example, the sub-pixel circuit SPC may have a 6T-2C structure including six transistors and two capacitors. As another example, the sub-pixel circuit SPC may have a 7T-1C structure including seven transistors and one capacitor.

[0157] According to the structure of the sub-pixel circuit SPC, the type and number of gate signals and / or gate lines provided to the sub-pixels SP may be changed.

[0158] In addition, according to the structure of the sub-pixel circuit SPC, the type and amount of the common pixel driving voltage supplied to the sub-pixel SP may be changed.

[0159] Since the circuit elements within each sub-pixel SP (specifically, the light emitting device ED implemented using an organic light emitting diode (OLED) including an organic material) are easily affected by external moisture or oxygen, an encapsulation layer 220 may be provided on the display panel 110 to prevent oxygen from penetrating into the circuit elements (specifically, the light emitting device ED). The encapsulation layer 220 may be configured in various shapes to prevent the light emitting device ED from contacting moisture or oxygen.

[0160] The display panel 110 according to one or more example embodiments of the present disclosure may have a top emission structure or a bottom emission structure.

[0161] The display device 100 according to one or more example embodiments of the present disclosure may have an extremely narrow frame structure in which the non-display area NDA of the display panel 110 is extremely small or almost non-existent. Hereinafter, the extremely narrow frame structure of the display panel 110 of the display device 100 is described according to one or more example embodiments of the present disclosure.

[0162] Figure 3 and Figure 4 A vertical structure and a planar structure of the display area DA of the display panel 110 according to one or more example embodiments of the present disclosure are illustrated.

[0163] Reference Figure 3 , the display panel 110 according to one or more example embodiments of the present disclosure may include a substrate 111 , a base circuit layer 310 , a light emitting device layer 330 , and an encapsulation layer 220 .

[0164] Reference Figure 3 and Figure 4 , the display area DA may include a first display area DA1 and a second display area DA2.

[0165] like Figure 3 and Figure 4 As shown, the first display area DA1 may be disposed on both one side and the other side of the second display area DA2. Alternatively, the first display area DA1 may be disposed only on one side or the other side of the second display area DA2.

[0166] Reference Figure 3 and Figure 4 The basic circuit layer 310 may be located on the substrate 111 and may include an intra-panel gate circuit GIPC and a sub-pixel circuit array SPCA disposed in the display area DA.

[0167] Reference Figure 3 and Figure 4 The light emitting device layer 330 may be located on the base circuit layer 310. A plurality of light emitting devices ED may be disposed in the light emitting device layer 330. The plurality of light emitting devices ED disposed in the light emitting device layer 330 may include a plurality of light emitting devices ED disposed in the first display area DA1 and a plurality of light emitting devices ED disposed in the second display area DA2.

[0168] Reference Figure 3 and Figure 4 , the sub-pixel circuit array SPCA may include a plurality of sub-pixel circuits SPC. Figure 3 , Figure 4 and Figure 7The plurality of sub-pixel circuits SPC may include a first sub-pixel circuit SPC1 configured to simultaneously drive two or more light-emitting devices ED disposed in the first display area DA1 and two or more second sub-pixel circuits SPC2 configured to respectively drive two or more light-emitting devices ED disposed in the second display area DA2.

[0169] Reference Figure 3 and Figure 4 , one first sub-pixel circuit SPC1 may be placed in the second display area DA2 among the first display area DA1 and the second display area DA2 included in the display area DA.

[0170] Two or more second sub-pixel circuits SPC2 may be disposed in the second display area DA2 among the first display area DA1 and the second display area DA2 included in the display area DA.

[0171] Reference Figure 3 and Figure 4 The in-panel gate circuit GIPC may be disposed in the first display area DA1 and the sub-pixel circuit array SPCA may be disposed in the second display area DA2.

[0172] At least some of the two or more light emitting devices ED disposed in the first display area DA1 may overlap at least a portion of the intra-panel gate circuit GIPC.

[0173] At least some of the two or more second light emitting devices ED2 disposed in the second display area DA2 may overlap at least a portion of the sub-pixel circuit array SPCA.

[0174] A first sub-pixel circuit SPC1 may include a first driving transistor DT for providing driving current to two or more light emitting devices ED arranged in the first display area DA1, and a first scanning transistor ST connected between one of the gate node, source node and drain node of the first driving transistor DT and the first data line DL.

[0175] Each of the two or more second sub-pixel circuits SPC2 may include a second driving transistor DT for providing a driving current to a corresponding light-emitting device ED among two or more light-emitting devices ED arranged in the second display area DA2, and a second scanning transistor ST connected between one of the gate node, source node and drain node of the second driving transistor DT and the second data line DL.

[0176] Reference Figure 3The display panel 110 according to one or more example embodiments of the present disclosure may further include an anode extension link layer 320 between the base circuit layer 310 and the light emitting device layer 330 .

[0177] At least one anode extension link (which may also be referred to as an extension link or Figure 7 A connection pattern (shown as AEL in FIG. 1 ) may be disposed in the anode extension link layer 320. At least one anode extension link may electrically connect at least one first sub-pixel circuit SPC1 disposed in the second display area DA2 and a plurality of light emitting devices ED disposed in the first display area DA1.

[0178] As described above, in the display panel 110 according to one or more example embodiments of the present disclosure, the in-panel gate circuit GIPC may be provided in the first display area DA1 included in the display area DA, thereby reducing a bezel corresponding to the non-display area NDA.

[0179] Figure 5 and Figure 6 yes Figure 4 FIG. 4 is a plan view of a partial area 400 of the display panel 110 .

[0180] Reference Figure 5 and Figure 6 , the display panel 110 may include a display area DA and a non-display area NDA1, and the display area DA may include a first display area DA1 and a second display area DA2. The non-display area NDA may also be referred to as a bezel.

[0181] Reference Figure 5 and Figure 6 , the first display area DA1 may be located between the non-display area NDA and the second display area DA2.

[0182] Reference Figure 5 and Figure 6 The display area DA may include a plurality of light emitting devices ED. For example, the plurality of light emitting devices ED may include a red light emitting device ED_R for emitting red light, a green light emitting device ED_G for emitting green light, and a blue light emitting device ED_B for emitting blue light.

[0183] Reference Figure 5 and Figure 6 , the plurality of light emitting devices ED disposed in the display area DA may include a plurality of first light emitting devices ED1 disposed in the first display area DA1 and a plurality of light emitting devices ED2 disposed in the second display area DA2.

[0184] Reference Figure 5 and Figure 6, the sub-pixel circuit array SPCA may be disposed in the second display area DA2. The sub-pixel circuit array SPCA may include a plurality of sub-pixel circuits SPC.

[0185] The plurality of sub-pixel circuits SPC may include at least one first sub-pixel circuit SPC for driving a plurality of first light emitting devices ED1 disposed in the first display area DA1, and a plurality of second sub-pixel circuits SPC for driving a plurality of second light emitting devices ED2 disposed in the second display area DA2.

[0186] Reference Figure 5 and Figure 6 , all or part of the intra-panel gate circuit GIPC may be disposed in the first display area DA1.

[0187] Reference Figure 5 and Figure 6 The display panel 110 according to one or more example embodiments of the present disclosure may include a link area LKA in which a plurality of links are provided to transmit various gating signals output from the in-panel gate circuit GIPC to the sub-pixel circuit array SPCA.

[0188] For example, the link set in the link area LKA can electrically connect the output point of the intra-panel gate circuit GIPC and the gate line GL. In the case where the output point of the intra-panel gate circuit GIPC is a first metal layer and the gate line GL is a second metal layer different from the first metal layer, the link may include a transition metal connecting the first metal layer and the second metal layer to each other.

[0189] Reference Figure 5 and Figure 6 , the link area LKA may be located between the in-panel gate circuit GIPC and the sub-pixel circuit array SPCA.

[0190] The link area LKA may be included in the first display area DA1.

[0191] Reference Figure 5 and Figure 6 , the display panel 110 according to one or more example embodiments of the present disclosure may further include a base voltage line area VSSA in which the base voltage line VSSL is disposed.

[0192] Reference Figure 5 and Figure 6 , the base voltage line area VSSA may also be placed outside the in-panel gate circuit GIPC. That is, the base voltage line area VSSA may be closer to the trimming line TRL than the in-panel gate circuit GIPC. Here, the trimming line TRL may be an end cutting point of the substrate 111 of the display panel 110.

[0193] For example, Figure 5 As shown, the base voltage line area VSSA may also be located outside the intra-panel gate circuit GIPC and may be included in the non-display area NDA. In this case, the base voltage line VSSL may not overlap the first light emitting device ED1 disposed in the first display area DA1.

[0194] As another example, Figure 6 As shown, the base voltage line area VSSA may also be located further outside the in-panel gate circuit GIPC, but may be included in the first display area DA1. In this case, the base voltage line VSSL may overlap the first light emitting device ED1 disposed in the first display area DA1.

[0195] Reference Figure 5 and Figure 6 , the display panel 110 according to one or more example embodiments of the present disclosure may include a crack management area CRA in which a crack detection line and / or a crack prevention pattern is disposed.

[0196] For example, Figure 5 As shown, the crack management area CRA may be included in the non-display area NDA. In this case, the crack detection line and / or the crack prevention pattern may not overlap with the first light emitting device ED1 disposed in the first display area DA1.

[0197] As another example, Figure 6 As shown, the crack management area CRA may be included in the first display area DA1. In this case, the crack detection line and / or the crack prevention pattern may overlap with the first light emitting device ED1 disposed in the first display area DA1.

[0198] Figure 7 The corresponding relationship between the sub-pixel circuits SPC1 , SPC2_TRANS, and SPC2 and the light emitting devices ED1 and ED2 in the display panel 110 according to one or more example embodiments of the present disclosure is illustrated. Figure 8 Only the corresponding relationship between the first sub-pixel circuit SPC1 and the first light emitting device ED1 in the display panel 110 according to one or more example embodiments of the present disclosure is illustrated. Figure 5 The floor plan structure illustrates Figure 7 .

[0199] Reference Figure 7 Based on the planar structure, the display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include a first display area DA1 and a second display area DA2.

[0200] Reference Figure 7 , based on the vertical structure, the display panel 110 may include a basic circuit layer 310 and a light emitting device layer 330 .

[0201] Reference Figure 7 In the basic circuit layer 310, all or most of the intra-panel gate circuit GIPC may be disposed in the first display area DA1. In the basic circuit layer 310, a sub-pixel circuit array SPCA including sub-pixel circuits SPC1, SPC2_TRANS, and SPC2 may be disposed in the second display area DA2.

[0202] Reference Figure 7 , in the basic circuit layer 310 , the link area LKA may be disposed in the first display area DA1 or the second display area DA2 , or may be disposed across the first display area DA1 and the second display area DA2 .

[0203] Reference Figure 7 , a plurality of light emitting devices ED disposed on or in the light emitting device layer 330 may be disposed in the display area DA. The plurality of light emitting devices ED disposed in the light emitting device layer 330 may include a plurality of first light emitting devices ED1 disposed in the first display area DA1 and a plurality of second light emitting devices ED2 disposed in the second display area DA2.

[0204] Reference Figure 7 The multiple sub-pixel circuits SPC included in the sub-pixel circuit array SPCA may include at least one first sub-pixel circuit SPC1 configured to drive a plurality of first light-emitting devices ED1 set in the first display area DA1 and a plurality of second sub-pixel circuits SPC2 configured to drive a plurality of second light-emitting devices ED2 set in the second display area DA2.

[0205] Reference Figure 7 , a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA may be classified into a first group GR1 [1:n], a transition group GR_TRANS [1:n], and a second group GR2 [1:1].

[0206] Reference Figure 7 , the second group GR2[1:1] may include a plurality of second sub-pixel circuits SPC2. The second group GR2[1:1] may drive one second light emitting device ED2 disposed in the second display area DA2 in a "one-to-one (ie, 1:1) driving method".

[0207] Each of the plurality of second sub-pixel circuits SPC2 included in the second group GR2[1:1] may drive one second light emitting device ED2 disposed in the second display area DA2. That is, one second sub-pixel circuit SPC2 included in the second group GR2[1:1] may drive one second light emitting device ED2 disposed in the second display area DA2. Therefore, the second anode AND2 of one second light emitting device ED2 may be connected one-to-one to one second sub-pixel circuit SPC2.

[0208] Reference Figure 7 and Figure 8 , the first group GR1[1:n] may include a plurality of first sub-pixel circuits SPC1. The first group GR1[1:n] may drive two or more first light emitting devices ED1 disposed in the first display area DA1 in a "one-to-many driving method or a common driving method".

[0209] Each of the plurality of first sub-pixel circuits SPC1 included in the first group GR1[1:n] can simultaneously drive two or more first light-emitting devices ED1 disposed in the first display area DA1. That is, one first sub-pixel circuit SPC1 included in the first group GR1[1:n] can drive two or more first light-emitting devices ED1 disposed in the first display area DA1 together.

[0210] For example, Figure 7 and Figure 8 As shown, one first sub-pixel circuit SPC1 included in the first group GR1 [1:n] may drive two first light emitting devices ED1 disposed in the first display area DA1.

[0211] Reference Figure 7 and Figure 8 In order to enable a first sub-pixel circuit SPC1 set in the second display area DA2 to drive two or more first light-emitting devices ED1 set in the first display area DA1 together, the display panel 110 according to one or more example embodiments of the present disclosure may further include an anode extension link AEL connecting a first sub-pixel circuit SPC1 set in the second display area DA2 with two or more first light-emitting devices ED1 set in the first display area DA1.

[0212] The anode extension link AEL may be disposed on or in the anode extension link layer 320 between the base circuit layer 310 and the light emitting device layer 330. Therefore, the anode extension link AEL may include a metal between the base circuit layer 310 and the light emitting device layer 330 (ie, an anode extension link layer metal).

[0213] Reference Figure 7 and Figure 8 , some of the plurality of first sub-pixel circuits SPC1 included in the first group GR1 [1:n] may be connected to one scan line SCL and may receive the scan signal SC from the one scan line SCL.

[0214] Reference Figure 7 and Figure 8 , two or more first light emitting devices ED1 driven together by one first sub-pixel circuit SPC1 included in the first group GR1 [1:n] may emit light of the same color.

[0215] Reference Figure 7 and Figure 8 , one first sub-pixel circuit SPC1 included in the first group GR1 [1:n] may receive the scan signal SC and the data signal VDATA, and drive two or more first light emitting devices ED1 together based on the scan signal SC and the data signal VDATA.

[0216] Reference Figure 7 , the transition group GR_TRANS[1:n] may include a plurality of transition sub-pixel circuits SPC2_TRANS. The transition group GR_TRANS[1:n] may also drive two or more second light emitting devices ED2 disposed in the second display area DA2 in a "one-to-many driving method or a common driving method".

[0217] Each of the plurality of transition sub-pixel circuits SPC2_TRANS included in the transition group GR_TRANS[1:n] can drive two or more second light-emitting devices ED2 disposed in the second display area DA2. That is, one transition sub-pixel circuit SPC2_TRANS included in the transition group GR_TRANS[1:n] can drive two or more second light-emitting devices ED2 disposed in the second display area DA2.

[0218] Reference Figure 7 , two or more second light emitting devices ED2 driven together by one transition sub-pixel circuit SPC2_TRANS according to the one-to-many driving method may be adjacent light emitting devices ED emitting light of the same color.

[0219] Since the two or more second light-emitting devices ED2 driven together by one transition sub-pixel circuit SPC2_TRANS according to the one-to-many driving method are composed of light-emitting devices ED that emit light of the same color and are arranged adjacently, the two or more second light-emitting devices ED2 can have similar light-emitting characteristics. Therefore, the image quality through the one-to-many driving can be at the same level as the image quality through the one-to-one driving.

[0220] Reference Figure 7In order to enable a transition sub-pixel circuit SPC2_TRANS set in the second display area DA2 to drive two or more second light-emitting devices ED2 set in the second display area DA2 together, the display panel 110 according to one or more example embodiments of the present disclosure may also include a transition anode extension link AEL connecting a transition sub-pixel circuit SPC2_TRANS set in the second display area DA2 and two or more second light-emitting devices ED2 set in the second display area DA2.

[0221] Reference Figure 7 , the second light emitting device ED2 driven by the transition sub-pixel circuit SPC2_TRANS included in the transition group GR_TRANS[1:n] may be disposed adjacent to the first light emitting device ED1 driven by the first sub-pixel circuit SPC1 included in the first group GR1[1:n].

[0222] Reference Figure 7 , the second light emitting device ED2 driven by the transition sub-pixel circuit SPC2_TRANS included in the transition group GR_TRANS[1:n] can be set between the first light emitting device ED1 driven by the first sub-pixel circuit SPC1 included in the first group GR1[1:n] and the second light emitting device ED2 driven by the second sub-pixel circuit SPC2 included in the second group GR2[1:1].

[0223] Reference Figure 7 , the transition group GR_TRANS[1:n] may be disposed between the first group GR1[1:n] and the second group GR2[1:1].

[0224] Fig. 9 is an equivalent circuit of a sub-pixel SP provided on or in the display panel 110 according to one or more example embodiments of the present disclosure.

[0225] Reference Fig. 9 A subpixel SP disposed on or in the display panel 110 according to one or more example embodiments of the present disclosure may include a light emitting device ED and a subpixel circuit SPC, and the subpixel circuit SPC may include a driving transistor DT, first to seventh transistors T1 to T7, and a storage capacitor Cst.

[0226] The sub-pixel circuit SPC of the sub-pixel SP may include a first node N1, a second node N2, a third node N3, and a fourth node N4.

[0227] The light emitting device ED may include an anode AND, a device intermediate layer EL, and a cathode CAT. The device intermediate layer EL may include a first common layer COM1, a light emitting layer EML, and a second common layer COM2.

[0228] The anode electrode AND of the light emitting device ED may correspond to the fourth node N4.

[0229] The cathode CAT of the light emitting device ED may be electrically connected to a base voltage line VSSL. A base voltage VSS may be applied to the base voltage line VSSL. The base voltage line VSSL may also be referred to as a second driving voltage line, and the base voltage VSS may also be referred to as a second driving voltage.

[0230] The driving transistor DT may include a source node, a drain node, and a gate node. The first node N1 may be a drain node or a source node of the driving transistor DT, the second node N2 may be a gate node of the driving transistor DT, and the third node N3 may be a source node or a drain node of the driving transistor DT.

[0231] The first transistor T1 may be connected between the first node N1 and the second node N2. The first transistor T1 may be turned on or off by a first scan signal SC1 provided from the first scan line SCL1, thereby controlling the connection between the first node N1 and the second node N2.

[0232] The second transistor T2 may be connected between the third node N3 and the data line DL. The second transistor T2 may be turned on or off by a second scan signal SC2 provided from the second scan line SCL2 and may control connection between the third node N3 of the driving transistor DT and the data line DL.

[0233] The third transistor T3 may be connected between the third node N3 and the first driving voltage line VDDL to which the first driving voltage VDD is applied. The third transistor T3 may be turned on or off by the emission control signal EM provided from the emission control line EMCL and may control the connection between the third node N3 and the first driving voltage line VDDL.

[0234] The fourth transistor T4 may be connected between a fourth node N4 corresponding to the anode AND of the light emitting device ED and the first node N1. The fourth transistor T4 may be turned on or off by a light emitting control signal EM provided from the light emitting control line EMCL and may control connection between the first node N1 and the fourth node N4.

[0235] The fifth transistor T5 may be connected between the second node N2 and the initialization voltage line VINIL to which the initialization voltage VINI is applied. The fifth transistor T5 may be turned on or off by the fourth scan signal SC4 provided from the fourth scan line SCL4 and may control the connection between the second node N2 and the initialization voltage line VINIL.

[0236] The sixth transistor T6 may be connected between a fourth node N4 corresponding to the anode AND of the light emitting device ED and an anode reset voltage line VARL to which the anode reset voltage VAR is applied. The sixth transistor T6 may be turned on or off by a third scan signal SC3 provided from the third scan line SCL3, and may control the connection between the fourth node N4 and the anode reset voltage line VARL to which the anode reset voltage VAR is applied.

[0237] The seventh transistor T7 may be connected between the third node N3 and the bias voltage line VOBSL to which the bias voltage VOBS is applied. The seventh transistor T7 may be turned on or off by the third scan signal SC3 provided from the third scan line SCL3, and may control the connection between the third node N3 and the bias voltage line VOBSL to which the bias voltage VOBS is applied.

[0238] Each of the driving transistor DT and the first to seventh transistors T1 to T7 may be an n-type transistor or a p-type transistor.

[0239] For example, Fig. 9 As shown, the first transistor T1 and the fifth transistor T5 may be n-type transistors, and the driving transistor DT, the second transistor T2 and the third transistor T3 , the fourth transistor T4 , the sixth transistor T6 and the seventh transistor T7 may be p-type transistors.

[0240] Fig. 10A and Fig. 10B The in-panel gate circuit GIPC provided on or in the display panel 110 according to one or more example embodiments of the present disclosure is illustrated. However, Fig. 10A and Fig. 10B 1. The following example illustrates that each sub-pixel SP disposed on or in the display panel 110 according to one or more exemplary embodiments of the present disclosure is Fig. 9 The gate circuit GIPC in the panel as shown.

[0241] Reference Fig. 10A, the intra-panel gate circuit GIPC arranged in the first display area DA1 located on the side of the second display area DA2 may include: a first scan drive circuit SCD1, which is configured to generate a first scan signal SC1 and output it to the first scan line SCL1; a second scan drive circuit SCD2_O, which is configured to generate a second scan signal SC2 and output it to the odd-numbered second scan line SCL2; a second scan drive circuit SCD2_E, which is configured to generate a second scan signal SC2 and output it to the even-numbered second scan line SCL2; and a third scan drive circuit SCD3, which is configured to generate a third scan signal SC3 and output it to the third scan line SCL3.

[0242] Reference Fig. 10A Among the first scan driving circuit SCD1, the second scan driving circuit SCD2_O and SCD2_E, and the third scan driving circuit SCD3, the second scan driving circuit SCD2_O and SCD2_E may be disposed closest to the second display area DA2, and the third scan driving circuit SCD3 may be disposed closest to the non-display area NDA.

[0243] Reference Fig. 10B , the intra-panel gate circuit GIPC arranged in the first display area DA1 located on the other side of the second display area DA2 may include: a second scan drive circuit SCD2_O, which is configured to generate a second scan signal SC2 and output it to the odd-numbered second scan line SCL2; a second scan drive circuit SCD2_E, which is configured to generate a second scan signal SC2 and output it to the even-numbered second scan line SCL2; a fourth scan drive circuit SCD4, which is configured to generate a fourth scan signal SC4 and output it to the fourth scan line SCL4; and a light emitting control circuit EMD, which is configured to generate a light emitting control signal EM and output it to the light emitting control line EMCL.

[0244] Reference Fig. 10B Among the second scan driving circuits SCD2_O and SCD2_E, the light emitting control circuit EMD and the fourth scan driving circuit SCD4, the second scan driving circuits SCD2_O and SCD2_E may be placed closest to the second display area DA2, and the fourth scan driving circuit SCD4 may be placed closest to the non-display area NDA.

[0245] Fig.11 is an equivalent circuit of a sub-pixel SP provided on or in the display panel 110 according to one or more example embodiments of the present disclosure.

[0246] Reference Fig.11A subpixel SP disposed on or in the display panel 110 according to one or more example embodiments of the present disclosure may include a light emitting device ED and a subpixel circuit SPC, and the subpixel circuit SPC may include a driving transistor DT, first to fifth transistors T1 to T5, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0247] The sub-pixel circuit SPC of the sub-pixel SP may include a first node N1, a second node N2, a third node N3, and a fourth node N4.

[0248] The light emitting device ED may include an anode AND, a device intermediate layer EL, and a cathode CAT. The device intermediate layer EL may include a first common layer COM1, a light emitting layer EML, and a second common layer COM2.

[0249] The anode electrode AND of the light emitting device ED may correspond to the first node N1.

[0250] The cathode CAT of the light emitting device ED may be electrically connected to a base voltage line VSSL. A base voltage VSS may be applied to the base voltage line VSSL. The base voltage line VSSL may also be referred to as a second driving voltage line, and the base voltage VSS may be referred to as a second driving voltage.

[0251] The driving transistor DT may include a source node, a drain node, and a gate node. The first node N1 may be a drain node or a source node of the driving transistor DT, the second node N2 may be a gate node of the driving transistor DT, and the third node N3 may be a source node or a drain node of the driving transistor DT.

[0252] The first transistor T1 may be connected between the third node N3 and the fourth node N4. The first transistor T1 may be turned on or off by a first scan signal SC1(n-2) of a previous stage provided from a first scan line SCL1(n-2) of a previous stage, and may control the connection between the third node N3 and the fourth node N4.

[0253] The second transistor T2 may be connected between the fourth node N4 and the data line DL. The second transistor T2 may be turned on or off by the first scan signal SC1(n) provided from the first scan line SCL1(n), and may control the connection between the fourth node N4 and the data line DL.

[0254] The third transistor T3 may be connected between the second node N2 and the initialization voltage line VINIL to which the initialization voltage VINI is applied. The third transistor T3 may be turned on or off by the first scan signal SC1(n-2) of the previous stage provided from the first scan line SCL1(n-2) of the previous stage, and may control the connection between the second node N2 and the initialization voltage line VINIL to which the initialization voltage VINI is applied.

[0255] The fourth transistor T4 may be connected between the third node N3 and the first driving voltage line VDDL to which the first driving voltage VDD is applied. The fourth transistor T4 may be turned on or off by the emission control signal EM provided from the emission control line EMCL and may control the connection between the third node N3 and the first driving voltage line VDDL.

[0256] The fifth transistor T5 may be connected between the first node N1 and the power line VPL. The fifth transistor T5 may be turned on or off by the second scan signal SC2(n-2) provided from the second scan line SCL2(n-2), and may control the connection between the first node N1 and the power line VPL. Here, the initialization voltage VINI or the parking voltage Vp may be applied to the power line VPL.

[0257] Each of the driving transistor DT and the first to fifth transistors T1 to T5 may be an n-type transistor or a p-type transistor. For example, the driving transistor DT, the fourth transistor T4 and the fifth transistor T5 may be p-type transistors, and the first transistor T1, the second transistor T2 and the third transistor T3 may be n-type transistors.

[0258] The first storage capacitor Cst1 may be connected between the second node N2 and the fourth node N4. The second storage capacitor Cst2 may be connected between the fourth node N4 and the first driving voltage line VDDL.

[0259] Fig.12 The in-panel gate circuit GIPC provided on or in the display panel 110 according to one or more example embodiments of the present disclosure is illustrated.

[0260] Reference Fig.12 , the intra-panel gate circuit GIPC arranged in the first display area DA1 may include: a first scan driving circuit SCD1, which is configured to generate a first scan signal SC1 and output it to the first scan line SCL1; a second scan driving circuit SCD2, which is configured to generate a second scan signal SC2 and output it to the second scan line SCL2; and a light emitting control circuit EMD, which is configured to generate a light emitting control signal EM and output it to the light emitting control line EMCL.

[0261] Reference Fig.12 Among the first scan driving circuit SCD1, the second scan driving circuit SCD2 and the light emitting control circuit EMD, the second scan driving circuit SCD2 may be disposed closest to the second display area DA2, and the light emitting control circuit EMD may be disposed closest to the non-display area NDA.

[0262] Fig.13 The in-panel gate circuit GIPC provided on or in the display panel 110 according to one or more example embodiments of the present disclosure is illustrated.

[0263] Reference Fig.13 , the in-panel gate circuit GIPC provided on or in the display panel 110 according to one or more example embodiments of the present disclosure may include an output buffer 1310 and a control circuit 1320 .

[0264] The output buffer 1310 may include a pull-up transistor Tu connected between a clock node Nclk of an input clock signal CLK and an output node Nout of an output enable signal Vout, and a pull-down transistor Td connected between the output node Nout of the output enable signal Vout and a low voltage node Nvgl of an input second gate voltage VGL.

[0265] In the sub-pixel SP Fig. 9 In the case shown, the selection signal Vout may be one of the first scan signal SC1, the second scan signal SC2, the third scan signal SC3, the fourth scan signal SC4 and the light emitting control signal EM. In this case, the output node Nout may be one of the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the fourth scan line SCL4 and the light emitting control line EMCL.

[0266] When the sub-pixel SP is Fig.11 As shown, the selection signal Vout may be one of the first scan signal SC1(n), the second scan signal SC2(n-2) and the light emitting control signal EM. In this case, the output node Nout may be one of the first scan line SCL1(n), the second scan line SCL2(n-2) and the light emitting control line EMCL.

[0267] A gate node of the pull-up transistor Tu may correspond to the Q node. According to a voltage level of the Q node, the pull-up transistor Tu may be turned on or off.

[0268] A gate node of the pull-down transistor Td may correspond to the QB node. The pull-down transistor Td may be turned on or off according to a voltage level of the QB node.

[0269] The voltage level of the Q node and the voltage level of the QB node may be opposite to each other. That is, when the voltage level of the Q node is high, the voltage level of the QB node may be low. When the voltage level of the Q node is low, the voltage level of the QB node may be high.

[0270] Since the voltage level of the Q node and the voltage level of the QB node are opposite to each other, the on-off state of the pull-up transistor Tu and the on-off state of the pull-down transistor Td may be different. That is, when the pull-up transistor Tu is turned on, the pull-down transistor Td may be turned off. When the pull-up transistor Tu is turned off, the pull-down transistor Td may be turned on.

[0271] The control circuit 1320 may receive control signals such as a start signal STR and a reset signal RST, and control a voltage level of the Q node and a voltage level of the QB node.

[0272] The control circuit 1320 may include a plurality of transistors.

[0273] When the voltage level of the Q node becomes high and the voltage level of the QB node becomes low by the control circuit 1320 , the pull-up transistor Tu may be turned on and the gate signal Vout of the clock signal CLK having a high level voltage may be output to the output node Nout.

[0274] When the voltage level of the Q node becomes low and the voltage level of the QB node becomes high by the control circuit 1320 , the pull-down transistor Td may be turned on and the gate signal Vout having the second gate voltage VGL corresponding to the low level voltage may be output to the output node Nout.

[0275] The transistors Tu and Td included in the output buffer 1310 and the plurality of transistors included in the control circuit 1320 may be referred to as gate drive transistors.

[0276] Fig.14 A vertical structure of the display panel 110 according to one or more example embodiments of the present disclosure is illustrated.

[0277] Reference Fig.14 , the display panel 110 according to one or more example embodiments of the present disclosure may include a shielding layer 1400 disposed between the in-panel gate circuit GIPC included in the base circuit layer 310 and the light emitting device layer 330 .

[0278] Reference Fig.14The display panel 110 according to one or more example embodiments of the present disclosure may further include an anode extension link AEL connecting one first sub-pixel circuit SPC1 to two or more anodes AND, where the two or more anodes AND are two or more pixel electrodes included in the two or more first light emitting devices ED1.

[0279] Reference Fig.14 The shielding layer 1400 may be disposed in the first display area DA1 and may be disposed between the intra-panel gate circuit GIPC and the anode extension link layer 320 provided with the anode extension link AEL.

[0280] At least a portion of the shielding layer 1400 may overlap the anode extension link AEL and the in-panel gate circuit GIPC. Therefore, the in-panel gate circuit GIPC and the anode extension link AEL electrically connected to the anode AND may not have unnecessary electrical effects on each other, thereby improving image quality.

[0281] Fig.15 is a cross-sectional view illustrating a vertical structure of a display panel 110 according to one or more example embodiments of the present disclosure.

[0282] Reference Fig.15 , the display panel 110 according to one or more example embodiments of the present disclosure may include a display area DA and a non-display area NDA. The display area DA may include a first display area DA1 and a second display area DA2. The first display area DA1 may be located between the second display area DA2 and the non-display area NDA.

[0283] Reference Fig.15 The display panel 110 according to one or more example embodiments of the present disclosure may include a substrate 111 , a base circuit layer 310 on the substrate 111 , and a light emitting device layer 330 on the base circuit layer 310 .

[0284] The display panel 110 according to one or more example embodiments of the present disclosure may further include at least one insulating layer disposed between the base circuit layer 310 and the light emitting device layer 330 .

[0285] For example, Fig.15 As shown, the first to third insulating layers INS1, INS2, and INS3 may be disposed between the base circuit layer 310 and the light emitting device layer 330. For example, the first insulating layer INS1 may be an inorganic layer or an organic layer. The second insulating layer INS2 and the third insulating layer INS3 may serve as a planarization layer and may be an organic layer.

[0286] Reference Fig.15, the sub-pixel circuit array SPCA, the link area LKA, the in-panel gate circuit GIPC and the base voltage line area VSSA may be disposed in the basic circuit layer 310 .

[0287] The sub-pixel circuit array SPCA may be disposed in the second display area DA2, the link area LKA may be disposed in the first display area DA1, the intra-panel gate circuit GIPC may be placed in the first display area DA1, and the base voltage line area VSSA may be placed in the non-display area NDA.

[0288] Reference Fig.15 , a plurality of light emitting devices ED may be provided in the light emitting device layer 330. The plurality of light emitting devices ED provided in the light emitting device layer 330 may include a plurality of first light emitting devices ED1 provided in the first display area DA1 and a plurality of second light emitting devices ED2 provided in the second display area DA2.

[0289] Two or more first light emitting devices ED1 disposed in the first display area DA1 may be driven in a one-to-many driving method (ie, a common driving method) by at least one first sub-pixel circuit SPC1 among a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA.

[0290] Most of the plurality of second light emitting devices ED2 disposed in the second display area DA2 may be driven in a one-to-one driving manner by a second sub-pixel circuit SPC2 among a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA.

[0291] Some of the plurality of second light emitting devices ED2 disposed in the second display area DA2 may be driven in a common driving manner by a transition sub-pixel circuit SPC2_TRANS among a plurality of sub-pixel circuits SPC included in the sub-pixel circuit array SPCA (see Figure 7 ).

[0292] Reference Fig.15 , the light emitting device layer 330 may include two or more first anodes AND1 disposed in the first display area DA1 and two or more first light emitting layers EML1 disposed in the first display area DA1 and each on the two or more first anodes AND1.

[0293] Reference Fig.15 The light emitting device layer 330 may include two or more second anodes AND2 disposed in the second display area DA2 and two or more second light emitting layers EML2 disposed in the second display area DA2 and each located on the two or more second anodes AND2.

[0294] Reference Fig.15, the light emitting device layer 330 may include a cathode CAT disposed across the first display area DA1 and the second display area DA2 and disposed on the two or more first light emitting layers EML1 and the two or more second light emitting layers EML2.

[0295] Reference Fig.15 , two or more first light emitting devices ED1 may be formed in the first display area DA1 by two or more first anodes AND1 , two or more first light emitting layers EML1 , and cathodes CAT.

[0296] Reference Fig.15 , two or more second light emitting devices ED2 may be formed in the second display area DA2 by two or more second anodes AND2 , two or more second light emitting layers EML2 , and cathodes CAT.

[0297] Reference Fig.15 , the first common layer COM1 and the second common layer COM2 may be disposed over the entire display area DA. The first common layer COM1 may be disposed between the anodes AND1 and AND2 and the light emitting layers EML1 and EML2, and may be disposed over the entire display area DA. The second common layer COM2 may be disposed between the light emitting layers EML1 and EML2 and the cathode CAT, and may be disposed in the entire display area DA.

[0298] Reference Fig.15 In the display area DA, the light emitting regions of the light emitting devices ED1 and ED2 may be defined by the opening of the bank BK. The bank BK may be located on the anodes AND1 and AND2 and may have an opening exposing a portion of the anodes AND1 and AND2. The opening of the bank BK may be a light emitting region. The bank BK may also be referred to as a light emitting unit defining layer.

[0299] Reference Fig.15 , the display panel 110 according to one or more example embodiments of the present disclosure may include a connection metal structure for connection between the base circuit layer 310 and the light emitting device layer 330 .

[0300] Reference Fig.15 The connection metal structure of the display panel 110 according to one or more example embodiments of the present disclosure may include a first metal layer disposed between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer disposed between the second insulating layer INS2 and the third insulating layer INS3, and a third metal layer disposed between the third insulating layer INS3 and the light emitting device layer 330.

[0301] Reference Fig.15The display panel 110 according to one or more example embodiments of the present disclosure may include a second anode connection structure that electrically connects a second anode AND2 disposed in the light emitting device layer 330 and a second sub-pixel circuit SPC2 disposed in the base circuit layer 310 one-to-one.

[0302] Reference Fig.15 The second anode connection structure of the display panel 110 according to one or more example embodiments of the present disclosure may include a second anode connection pattern CP_AND2. Each of the two or more second anodes AND2 may be electrically connected to a second sub-pixel circuit SPC2 disposed in the base circuit layer 310 through the second anode connection pattern CP_AND2.

[0303] Reference Fig.15 , the second anode connection pattern CP_AND2 may include a second metal connection pattern CP2_AND2 and a first metal connection pattern CP1_AND2.

[0304] Reference Fig.15 , two or more second anodes AND2 may be disposed in the third metal layer. One second anode AND2 may be electrically connected to a second metal connection pattern CP2_AND2 disposed in the second metal layer through a hole in the third insulating layer INS3, the second metal connection pattern CP2_AND2 may be electrically connected to a first metal connection pattern CP1_AND2 disposed in the first metal layer through a hole in the second insulating layer INS2, and the first metal connection pattern CP1_AND2 may be electrically connected to a second sub-pixel circuit SPC2 disposed in the base circuit layer 310 through a hole in the first insulating layer INS1.

[0305] Reference Fig.15 , the two or more first anodes AND1 may be electrically connected to the first sub-pixel circuit SPC1 disposed in the base circuit layer 310 through the anode extension link AEL disposed in the anode extension link layer 320 .

[0306] Reference Fig.15 The display panel 110 according to one or more example embodiments of the present disclosure may include a first anode connection structure electrically connecting two or more first anodes AND1 disposed in the light emitting device layer 330 and a first sub-pixel circuit SPC1 disposed in the base circuit layer 310 .

[0307] Reference Fig.15 , the first anode connection structure of the display panel 110 according to one or more example embodiments of the present disclosure may include an anode extension link AEL and an anode connection pattern CP_AND1 .

[0308] Reference Fig.15 , two or more first anodes AND1 may be disposed in the third metal layer. The anode extension link layer 320 may be a second metal layer on the second insulating layer INS2. The anode connection pattern CP_AND1 may include a first metal connection pattern CP1_AND1 in a first metal layer on the first insulating layer INS1.

[0309] Reference Fig.15 In the first display area DA1 , each of the two or more first anodes AND1 may be electrically connected to one anode extension link AEL located in the second metal layer through a hole in the third insulating layer INS3 . Here, the second metal layer may be the anode extension link layer 320 .

[0310] Reference Fig.15 The anode extension link AEL can be electrically connected to the first metal connection pattern CP1_AND1 located in the first metal layer through the hole in the second insulating layer INS2, and the first metal connection pattern CP1_AND1 can be electrically connected to the first sub-pixel circuit SPC1 set in the base circuit layer 310 through the hole in the first insulating layer INS1.

[0311] Reference Fig.15 , the anode extension link AEL may include a first portion electrically connected to two or more first anodes AND1 in the light emitting device layer 330 located in the first display area DA1, and a second portion connected to the first sub-pixel circuit SPC1 in the base circuit layer 310 located in the second display area DA2. Here, the first portion may be located in the first display area DA1, and the second portion may be located in the second display area DA2.

[0312] Reference Fig.15 , the anode extension link AEL may be arranged to extend from the first display area DA1 to the second display area DA2 in a planar manner. The first anode connection structure including the anode extension link AEL may be positioned from the base circuit layer 310 to the light emitting device layer 330 in a vertical direction.

[0313] Reference Fig.15 , in the basic circuit layer 310 , the link area LKA may be located between the sub-pixel circuit array SPCA and the intra-panel gate circuit GIPC.

[0314] Reference Fig.15 , a base voltage line area VSSA may exist outside the intra-panel gate circuit GIPC in the basic circuit layer 310. A base voltage line VSSL to which a base voltage VSS is applied may be provided in the base voltage line area VSSA.

[0315] Reference Fig.15, the display panel 110 according to one or more example embodiments of the present disclosure may include a cathode connection structure to electrically connect the cathode CAT and the base voltage line VSSL.

[0316] Reference Fig.15 The cathode connection structure of the display panel 110 according to one or more example embodiments of the present disclosure may include a cathode connection pattern CP_VSS. The cathode connection pattern CP_VSS may include a first cathode connection pattern CP1_VSS, a second cathode connection pattern CP2_VSS, and a third cathode connection pattern CP3_VSS.

[0317] Reference Fig.15 , the first cathode connection pattern CP1_VSS may be located in the first metal layer on the first insulating layer INS1.

[0318] The second cathode connection pattern CP2_VSS may be located in a second metal layer on the second insulating layer INS2. Here, the second metal layer may be an anode extension link layer 320 provided with an anode extension link AEL.

[0319] The third cathode connection pattern CP3_VSS may be located in a third metal layer on the third insulating layer INS3. Here, the third metal layer may be a metal layer provided with the anodes AND1 and AND2.

[0320] Reference Fig.15 The cathode CAT may be electrically connected to the third cathode connection pattern CP3_VSS through a hole in the embankment BK, the third cathode connection pattern CP3_VSS may be electrically connected to the second cathode connection pattern CP2_VSS through a hole in the third insulating layer INS3, the second cathode connection pattern CP2_VSS may be electrically connected to the first cathode connection pattern CP1_VSS through a hole in the second insulating layer INS2, and the first cathode connection pattern CP1_VSS may be electrically connected to the base voltage line VSSL through a hole in the first insulating layer INS1.

[0321] Reference Fig.15 , the first cathode connection pattern CP1_VSS may be disposed in the same first metal layer as the shielding layer 1400 , and may be electrically connected to the shielding layer 1400 or may be integrally configured with the shielding layer 1400 .

[0322] Reference Fig.15 The base voltage line VSSL and the cathode connection pattern CP_VSS may be located in the non-display area NDA. The base voltage line VSSL may be disposed in a base voltage line area VSSA located outside the in-panel gate circuit GIPC.

[0323] Reference Fig.15, the shielding layer 1400 may be located between the in-panel gate circuit GIPC included in the base circuit layer 310 and the light emitting device layer 330 .

[0324] The shielding layer 1400 may be disposed in the first display area DA1.

[0325] The shielding layer 1400 may be electrically connected to the cathode connection pattern CP_VSS. Therefore, the base voltage VSS applied to the cathodes CAT of the light emitting devices ED1 and ED2 may be applied to the shielding layer 1400.

[0326] The shielding layer 1400 may be disposed in the first display area DA1 and may be located between the intra-panel gate circuit GIPC and the anode extension link AEL. The shielding layer 1400 may overlap the intra-panel gate circuit GIPC and the anode extension link AEL.

[0327] Therefore, the anode extension link AEL may not be affected by the gate circuit GIPC in the panel. The gate circuit GIPC in the panel may not be affected by the anode extension link AEL.

[0328] Reference Fig.15 According to one or more example embodiments of the present disclosure, the display panel 110 may include a substrate 111, which includes: a display area DA having a first display area DA1 and a second display area DA2, and a non-display area NDA located outside the display area DA; two or more first light-emitting devices ED1 arranged in the first display area DA1; two or more second light-emitting devices ED2 arranged in the second display area DA2; a first sub-pixel circuit SPC1 commonly connected to the two or more first light-emitting devices ED1; and two or more second sub-pixel circuits SPC2 respectively connected to the two or more second light-emitting devices ED2.

[0329] Reference Fig.15 , the display panel 110 according to one or more example embodiments of the present disclosure may further include an in-panel gate circuit GIPC disposed in the first display area DA1.

[0330] Reference Fig.15 , the display panel 110 according to one or more example embodiments of the present disclosure may further include an anode extension link AEL electrically connecting the two or more first light emitting devices ED1 and the one first sub-pixel circuit SPC1.

[0331] Reference Fig.15 , the display panel 110 according to one or more example embodiments of the present disclosure may further include a shielding layer 1400 disposed between the intra-panel gate circuit GIPC and the anode extension link AEL.

[0332] Fig.16 is another plan view of a partial region of the display panel 110 according to one or more example embodiments of the present disclosure.

[0333] Reference Fig.16 , the display panel 110 may include a display area DA and a non-display area NDA1, and the display area DA may include a first display area DA1 and a second display area DA2. The non-display area NDA may also be referred to as a bezel.

[0334] Reference Fig.16 , the first display area DA1 may be located between the non-display area NDA and the second display area DA2.

[0335] Reference Fig.16 The display area DA may include a plurality of light emitting devices ED. For example, the plurality of light emitting devices ED may include a red light emitting device ED_R for emitting red light, a green light emitting device ED_G for emitting green light, and a blue light emitting device ED_B for emitting blue light.

[0336] Reference Fig.16 , the plurality of light emitting devices ED1 disposed in the display area DA may include a plurality of first light emitting devices ED1 disposed in the first display area DA1 and a plurality of second light emitting devices ED2 disposed in the second display area DA2.

[0337] Reference Fig.16 , the sub-pixel circuit array SPCA may be disposed in the second display area DA2. The sub-pixel circuit array SPCA may include a plurality of sub-pixel circuits SPC.

[0338] The plurality of sub-pixel circuits SPC may include at least one first sub-pixel circuit SPC for driving a plurality of first light emitting devices ED1 disposed in the first display area DA1 and a plurality of second sub-pixel circuits SPC for driving a plurality of second light emitting devices ED2 disposed in the second display area DA2.

[0339] Reference Fig.16 , all or part of the intra-panel gate circuit GIPC may be disposed in the first display area DA1.

[0340] Reference Fig.16 , the display panel 110 according to one or more example embodiments of the present disclosure may include a link area LKA, wherein a link is configured to transmit various gate signals output from the in-panel gate circuit GIPC to the sub-pixel circuit array SPCA.

[0341] For example, the link set in the link area LKA can electrically connect the gate line GL and the output point of the intra-panel gate circuit GIPC. In the case where the output point of the intra-panel gate circuit GIPC is a first metal layer and the gate line GL is a second metal layer different from the first metal layer, the link may include a transition metal connecting the first metal layer and the second metal layer to each other.

[0342] Reference Fig.16 , the link area LKA may be located between the in-panel gate circuit GIPC and the sub-pixel circuit array SPCA.

[0343] The link area LKA may be included in the first display area DA1.

[0344] Reference Fig.16 , the display panel 110 according to one or more example embodiments of the present disclosure may include a crack management area CRA in which a crack detection line and / or a crack prevention pattern is disposed.

[0345] For example, the crack management area CRA may be included in the non-display area NDA. In this case, the crack detection line and / or the crack prevention pattern may not overlap with the first light emitting device ED1 disposed in the first display area DA1.

[0346] As another example, the crack management area CRA may be included in the first display area DA1. In this case, the crack detection line and / or the crack prevention pattern may overlap with the first light emitting device ED1 disposed in the first display area DA1.

[0347] Reference Fig.16 In the display panel 110 according to one or more example embodiments of the present disclosure, the base voltage line VSSL may be provided in the display area DA. For example, the base voltage line VSSL may be provided in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Therefore, the cathode CAT may be electrically connected to the base voltage line VSSL provided on at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0348] Therefore, the base voltage line area VSSA may not exist in the non-display area NDA. Therefore, a frame as the non-display area NDA may become smaller.

[0349] Fig.17 is another cross-sectional view illustrating a vertical structure of a display panel 110 according to one or more exemplary embodiments of the present disclosure. Fig.15 The differences are discussed above, and repeated descriptions may be omitted for the sake of brevity.

[0350] Reference Fig.17 In the display panel 110 according to one or more example embodiments of the present disclosure, the base voltage line VSSL may be located in the display area DA. The display panel 110 according to one or more example embodiments of the present disclosure may include a cathode connection structure electrically connecting the cathode CAT and the base voltage line VSSL, and the cathode connection structure may be located in the display area DA.

[0351] For example, the base voltage line VSSL may be provided in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Therefore, the cathode CAT may be electrically connected to the base voltage line VSSL through a cathode connection structure located in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0352] Reference Fig.17 , a cathode connection pattern CP_VSS as a cathode connection structure connecting the cathode CAT and the base voltage line VSSL may be located in the display area DA. That is, the cathode connection pattern CP_VSS may be located in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0353] Reference Fig.17 , the cathode CAT may be electrically connected to the cathode connection pattern CP_VSS located under the bank BK through a hole in the bank BK between the two or more second anodes.

[0354] Reference Fig.17 , the base voltage line VSSL may be located in a first metal layer on the first insulating layer INS1. The cathode connection pattern CP_VSS may include a first cathode connection pattern CP2_VSS located in a second metal layer on the second insulating layer INS2.

[0355] The cathode electrode CAT may be electrically connected to the first cathode connection pattern CP2_VSS through a via hole in the second common layer COM2 , the first common layer COM1 , the bank BK, and the third insulating layer INS3 .

[0356] The first cathode connection pattern CP2_VSS may be electrically connected to the base voltage line VSSL on the first insulating layer INS1 through a hole in the second insulating layer INS2 .

[0357] Reference Fig.17 , through holes in the second common layer COM2 , the first common layer COM1 , the bank BK, and the third insulating layer INS3 may be formed by a laser drilling process.

[0358] According to the above, the cathode connection pattern CP_VSS and the base voltage line VSSL as the cathode connection structure do not need to be provided in the non-display area NDA. Therefore, the frame can be further reduced to the extreme.

[0359] exist Figures 15 to 17 , the display panel 110 according to one or more example embodiments of the present disclosure may include three metal layers between the base circuit layer 310 and the light emitting device layer 330 and three insulating layers INS1 to INS3 as a connection metal structure for connection between the base circuit layer 310 and the light emitting device layer 330. Here, the three metal layers may include a first metal layer disposed between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer disposed between the second insulating layer INS2 and the third insulating layer INS3, and a third metal layer disposed between the third insulating layer INS3 and the light emitting device layer 330. Here, the third metal layer may be a metal layer provided with anodes AND1 and AND2.

[0360] The display panel 110 according to one or more example embodiments of the present disclosure may include Figures 15 to 17 The connection metal structure between the base circuit layer 310 and the light emitting device layer 330 (ie, three insulating layers and three metal layers) is different from the connection metal structure.

[0361] In the following, reference will be made to Fig.18 and Fig.19 Other connection metal structures of the display panel 110 according to one or more example embodiments of the present disclosure are described. In the following description, the following will mainly explain Fig.15 The differences are discussed above, and repeated descriptions may be omitted for the sake of brevity.

[0362] Fig.18 is another cross-sectional view illustrating a vertical structure of the display panel 110 according to one or more example embodiments of the present disclosure.

[0363] Reference Fig.18 The display panel 110 according to one or more example embodiments of the present disclosure may include four insulating layers INS1 to INS4 between the base circuit layer 310 and the light emitting device layer 330 and four metal layers as a connection metal structure for connection between the base circuit layer 310 and the light emitting device layer 330 .

[0364] Reference Fig.18, the four metal layers may include a first metal layer disposed between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer disposed between the second insulating layer INS2 and the third insulating layer INS3, a third metal layer disposed between the third insulating layer INS3 and the fourth insulating layer INS4, and a fourth metal layer disposed between the fourth insulating layer INS4 and the light emitting device layer 330. Here, the fourth metal layer may be a metal layer provided with the anodes AND1 and AND2.

[0365] Reference Fig.18 In the light emitting device layer 330 , a second anode AND2 for configuring the second light emitting device ED2 provided in the second display area DA2 may be provided in a fourth metal layer on the fourth insulating layer INS4 .

[0366] Reference Fig.18 The display panel 110 according to one or more example embodiments of the present disclosure may include a second anode connection pattern CP_AND2 as a second anode connection structure to electrically connect the second anode AND2 to a second sub-pixel circuit SPC2 disposed on or in the base circuit layer 310 .

[0367] Reference Fig.18 , the second anode connection pattern CP_AND2 may include a first metal connection pattern CP1_AND2, a second metal connection pattern CP2_AND2, and a third metal connection pattern CP3_AND2.

[0368] Reference Fig.18 The second anode AND2 can be electrically connected to the third metal connection pattern CP3_AND2 through the hole in the fourth insulating layer INS4, the third metal connection pattern CP3_AND2 can be electrically connected to the second metal connection pattern CP2_AND2 through the hole in the third insulating layer INS3, the second metal connection pattern CP2_AND2 can be electrically connected to the first metal connection pattern CP1_AND2 through the hole in the second insulating layer INS2, and the first metal connection pattern CP1_AND2 can be electrically connected to the second sub-pixel circuit SPC2 through the hole in the first insulating layer INS1.

[0369] Reference Fig.18 The display panel 110 according to one or more example embodiments of the present disclosure may include a first anode connection structure electrically connecting two or more first anodes AND1 disposed in the light emitting device layer 330 and a first sub-pixel circuit SPC1 disposed in the base circuit layer 310 .

[0370] Reference Fig.18, two or more first anodes AND1 may be electrically connected to one first sub-pixel circuit SPC1 disposed in the base circuit layer 310 through the first anode connection structure. Fig.18 In the example of FIG. 3 , the three first anodes AND1 may be electrically connected to one first sub-pixel circuit SPC1 disposed in the base circuit layer 310 through the first anode connection structure.

[0371] Reference Fig.18 , the first anode connection structure of the display panel 110 according to one or more example embodiments of the present disclosure may include an anode extension link AEL and a first anode connection pattern CP_AND1 .

[0372] Reference Fig.18 , in the first display area DA1, two or more first anodes AND1 may be disposed in the fourth metal layer. The anode extension link layer 320 may be a third metal layer on the third insulating layer INS2.

[0373] Reference Fig.18 , the first anode connection pattern CP_AND1 may include a first metal connection pattern CP1_AND1 in a first metal layer on the first insulating layer INS1 and a second metal connection pattern CP2_AND1 in a second metal layer on the second insulating layer INS2.

[0374] Reference Fig.18 Each of the two or more first anodes AND1 may be electrically connected to an anode extension link AEL located in the third metal layer through a hole in the fourth insulating layer INS4. Here, the third metal layer on the third insulating layer INS3 may be an anode extension link layer 320.

[0375] The anode extension link AEL may be electrically connected to the second metal connection pattern CP2_AND1 located in the second metal layer through a hole in the third insulating layer INS3 .

[0376] The second metal connection pattern CP2_AND1 may be electrically connected to the first metal connection pattern CP1_AND1 located in the first metal layer through a hole in the second insulating layer INS2 .

[0377] The first metal connection pattern CP1_AND1 may be electrically connected to the first sub-pixel circuit SPC1 disposed in the base circuit layer 310 through a hole in the first insulating layer INS1.

[0378] Reference Fig.18, the anode extension link AEL may include a first portion electrically connected to two or more first anodes AND1 in the light emitting device layer 330 located in the first display area DA1, and a second portion connected to the first sub-pixel circuit SPC1 in the base circuit layer 310 located in the second display area DA2. Here, the first portion may be located in the first display area DA1, and the second portion may be located in the second display area DA2.

[0379] Reference Fig.18 , the anode extension link AEL may be arranged to extend from the first display area DA1 to the second display area DA2 in a plane. The first anode connection structure including the anode extension link AEL may be positioned from the base circuit layer 310 to the light emitting device layer 330 in a vertical direction.

[0380] Reference Fig.18 , the shielding layer 1400 may be disposed on the first insulating layer INS1, and may be disposed in a first metal layer between the first insulating layer INS1 and the second insulating layer (INS2).

[0381] Alternatively, the shielding layer 1400 may be disposed on the second insulating layer INS2, and may be disposed in a third metal layer between the second insulating layer INS2 and the third insulating layer INS3.

[0382] Reference Fig.18 , in the basic circuit layer 310, a base voltage line area VSSA may exist outside the intra-panel gate circuit GIPC. A base voltage line VSSL to which a base voltage VSS is applied may be provided in the base voltage line area VSSA.

[0383] Reference Fig.18 , the display panel 110 according to one or more example embodiments of the present disclosure may include a cathode connection structure to electrically connect the cathode CAT and the base voltage line VSSL.

[0384] Reference Fig.18 The cathode connection structure of the display panel 110 according to one or more example embodiments of the present disclosure may include a cathode connection pattern CP_VSS. The cathode connection pattern CP_VSS may include a first cathode connection pattern, a second cathode connection pattern, a third cathode connection pattern, and a fourth cathode connection pattern.

[0385] Reference Fig.18, the first cathode connection pattern may be a first cathode connection pattern CP1_VSS in a first metal layer disposed on the first insulating layer INS1. The second cathode connection pattern may be a second cathode connection pattern CP2_VSS in a second metal layer disposed on the second insulating layer INS2. The third cathode connection pattern may be a third cathode connection pattern CP3_VSS in a third metal layer disposed on the third insulating layer INS3. Here, the third metal layer may be an anode extension link layer 320 provided with an anode extension link AEL. The fourth cathode connection pattern may be a fourth metal connection pattern CP4_VSS in a fourth metal layer located on the fourth insulating layer INS4. Here, the fourth metal layer may be a metal layer provided with anodes AND1 and AND2.

[0386] Reference Fig.18 The cathode CAT may be electrically connected to the fourth metal connection pattern CP4_VSS through a hole in the embankment BK, the fourth metal connection pattern CP4_VSS may be electrically connected to the third cathode connection pattern CP3_VSS through a hole in the fourth insulating layer INS4, the third cathode connection pattern CP3_VSS may be electrically connected to the second cathode connection pattern CP2_VSS through a hole in the third insulating layer INS3, the second cathode connection pattern CP2_VSS may be electrically connected to the first cathode connection pattern CP1_VSS through a hole in the second insulating layer INS2, and the first cathode connection pattern CP1_VSS may be electrically connected to the base voltage line VSSL through a hole in the first insulating layer INS1.

[0387] Reference Fig.18 , the first cathode connection pattern CP1_VSS may be disposed in the same first metal layer as the shielding layer 1400 , and may be electrically connected to the shielding layer 1400 or may be integrally configured with the shielding layer 1400 .

[0388] Reference Fig.18 The base voltage line VSSL and the cathode connection pattern CP_VSS may be located in the non-display area NDA. The base voltage line VSSL may be disposed in a base voltage line area VSSA located outside the in-panel gate circuit GIPC.

[0389] Fig.19 is another cross-sectional view illustrating a vertical structure of the display panel 110 according to one or more example embodiments of the present disclosure.

[0390] Reference Fig.19 The light emitting device layer 330 may further include two or more third anodes AND′ disposed in the first display area DA1 and two or more third light emitting layers EML1′ each located on the two or more third anodes AND′.

[0391] Two or more third light emitting devices ED1 ′ may be formed in the first display area DA1 by two or more third anodes AND′, two or more third light emitting layers EML1 ′, and a cathode CAT.

[0392] The sub-pixel circuit array SPCA may be configured to simultaneously drive two or more third light emitting devices ED1 ′, and may further include one third sub-pixel circuit SPC1 ′ disposed in the first display area DA1 .

[0393] In the display panel 110 according to one or more example embodiments of the present disclosure, the anode extension links AEL may all be disposed in the same metal layer. That is, the number of the anode extension link layer 320 as a metal layer disposed with the anode extension link AEL may be one.

[0394] Alternatively, in the display panel 110 according to one or more example embodiments of the present disclosure, the anode extension link AEL may be provided in different metal layers. That is, the number of the anode extension link layers 320 as the metal layer provided with the anode extension link AEL may be two or more.

[0395] according to Fig.19 For example, the display panel 110 according to one or more example embodiments of the present disclosure may include a first anode extension link AEL1 located in the first anode extension link layer 320b and a second anode extension link AEL2 located in the second anode extension link layer 320a.

[0396] The first anode extension link AEL1 may connect one first sub-pixel circuit SPC1 disposed in the second display area DA2 to two or more first light emitting devices ED1 disposed in the first display area DA1.

[0397] The second anode extension link AEL2 may connect one third sub-pixel circuit SPC1 ′ provided in the second display area DA2 to two or more third light emitting devices ED1 ′ provided in the first display area DA1 .

[0398] Reference Fig.19 , the first anode extension link AEL1 and the second anode extension link AEL2 may be located between the base circuit layer 310 and the light emitting device layer 330 , and may be provided in different metal layers.

[0399] Reference Fig.19 , the first anode extension link AEL1 may be located in the third metal layer between the third insulating layer INS3 and the fourth insulating layer INS4. In this case, two or more first anodes AND1 may be electrically connected to the first anode extension link AEL1 through holes in the fourth insulating layer INS4.

[0400] Reference Fig.19 , the second anode extension link AEL1' may be located in the second metal layer between the second insulating layer INS2 and the third insulating layer INS3. In this case, two or more third anodes AND1' may be electrically connected to the second anode extension link AEL1' through holes in the fourth insulating layer INS4 and the third insulating layer INS3.

[0401] Reference Fig.19 The cathode connection pattern CP_VSS may include a first cathode connection pattern CP1_VSS disposed on a first metal layer, a second cathode connection pattern CP2_VSS disposed on the same second metal layer as the second anode extension link AEL2, and a third cathode connection pattern CP3_VSS disposed on the same third metal layer as the first anode extension link AEL1.

[0402] like Fig.19 As shown, the anode extension links AEL (i.e., AEL1 and AEL2) are formed using a plurality of metal layers so that the anode extension links AEL (i.e., AEL1 and AEL2) can be arranged at a high density. Therefore, even if more light-emitting devices ED are arranged in the region without the sub-pixel circuit array SPCA (i.e., the first display area DA1), the light-emitting devices ED arranged in the region without the sub-pixel circuit array SPCA can be driven normally.

[0403] like Fig.19 As shown, the anode extension links AEL (ie, AEL1 and AEL2) are formed using a plurality of metal layers, and the anode extension links AEL (ie, AEL1 and AEL2) may be arranged at a high density so that the first display area DA1 may be enlarged, and the first display area DA1 may be extended to the same Figure 6 The area adjacent to the trim line TRL is shown. Therefore, the border can be greatly reduced.

[0404] Various examples and aspects of the present disclosure are described below. These examples and aspects are provided as examples and do not limit the scope of the present disclosure.

[0405] A display device according to one or more example embodiments of the present disclosure may include: a substrate; a display area having a first display area and a second display area; a non-display area located outside the display area; a basic circuit layer located on the substrate and including an intra-panel gate circuit and a sub-pixel circuit array arranged in the display area; and a light-emitting device layer located on the basic circuit layer and including two or more first light-emitting devices arranged in the first display area and two or more second light-emitting devices arranged in the second display area.

[0406] The sub-pixel circuit array may include: a first sub-pixel circuit, which is configured to simultaneously drive two or more first light-emitting devices and is arranged in a second display area; and two or more second sub-pixel circuits, which are configured to respectively drive two or more second light-emitting devices and are arranged in the second display area.

[0407] The in-panel gate circuit may be disposed in the first display area, and the sub-pixel circuit array may be disposed in the second display area.

[0408] At least some of the two or more first light emitting devices may overlap at least a portion of a gate circuit within the panel. At least some of the two or more second light emitting devices may overlap at least a portion of a sub-pixel circuit array.

[0409] The display device according to one or more example embodiments of the present disclosure may also include an extension link (if the pixel electrode is an anode, it may also be called an anode extension link) connecting a first sub-pixel circuit arranged in the second display area to two or more first light-emitting devices arranged in the first display area.

[0410] The extended link may include a metal between the base circuit layer and the light emitting device layer. At least a portion of the extended link may overlap at least a portion of the gate circuit within the panel.

[0411] The first display area may be located between the non-display area and the second display area.

[0412] The display device according to one or more example embodiments of the present disclosure may further include a shielding layer between the gate circuit and the light emitting device layer within the panel.

[0413] In the case where the display device according to one or more example embodiments of the present disclosure may also include an extended link connecting a first sub-pixel circuit to two or more pixel electrodes included in two or more first light-emitting devices, the shielding layer is disposed in the first display area and may be located between the extended link and the gate circuit within the panel.

[0414] At least a portion of the shielding layer may overlap the extended link and the in-panel gate circuit. The shielding layer may be disposed in the first display area.

[0415] The light-emitting device layer may include: two or more first anodes, which are arranged in a first display area; two or more first light-emitting layers, which are respectively located on the two or more first anodes; two or more second anodes, which are arranged in a second display area; two or more second light-emitting layers, which are respectively located on the two or more second anodes; and a cathode, which is arranged across the first display area and the second display area and is located on the two or more first light-emitting layers and the two or more second light-emitting layers.

[0416] Two or more first light emitting devices may be configured in the first display region through two or more first anodes, two or more first light emitting layers, and a cathode.

[0417] Two or more second light emitting devices may be configured in the second display region through two or more second anodes, two or more second light emitting layers, and a cathode.

[0418] A base voltage may be applied to the cathode.

[0419] The display device according to one or more example embodiments of the present disclosure may further include a base voltage line to which a base voltage is applied, and a cathode connection pattern electrically connecting the cathode and the base voltage line.

[0420] The display device according to one or more example embodiments of the present disclosure may further include an anode extension link connecting one first sub-pixel circuit to the two or more first light emitting devices.

[0421] The cathode connection pattern may include a first cathode connection pattern disposed on the same metal layer as the anode extension link.

[0422] The base voltage line and the cathode connection pattern may be located in the non-display area.

[0423] The base voltage line may be disposed outside the gate circuit within the panel.

[0424] The display device according to one or more example embodiments of the present disclosure may further include a shielding layer located between the gate circuit and the light emitting device layer in the panel and disposed in the first display area. In this case, the shielding layer may be electrically connected to the cathode connection pattern.

[0425] The base voltage line and the cathode connection pattern may be located in the display area.

[0426] The cathode may be electrically connected to at least one of a base voltage line and a cathode connection pattern through a hole in the bank between the two or more second anodes. The base voltage line and the cathode connection pattern may be located below the bank.

[0427] The light emitting device layer may further include two or more third anodes disposed in the first display region, and two or more third light emitting layers respectively located on the two or more third anodes.

[0428] Two or more third light emitting devices may be configured in the first display region through two or more third anodes, two or more third light emitting layers, and a cathode.

[0429] The sub-pixel circuit array may also be configured to simultaneously drive two or more third light emitting devices, and may further include one third sub-pixel circuit disposed in the second display area.

[0430] The display device according to one or more example embodiments of the present disclosure may also include: a first anode extension link, which connects a first sub-pixel circuit set in the second display area with two or more first light-emitting devices set in the first display area; and a second anode extension link, which connects a third sub-pixel circuit set in the second display area with two or more third light-emitting devices set in the first display area.

[0431] The first anode extension link and the second anode extension link may be located between the base circuit layer and the light emitting device layer, and may be disposed on different metal layers.

[0432] The cathode connection pattern may include a first cathode connection pattern disposed on the same metal layer as the first anode extension link and a second cathode connection pattern disposed on the same metal layer as the second anode extension link.

[0433] A display panel according to one or more example embodiments of the present disclosure may include a substrate, a display area having a first display area and a second display area, a non-display area outside the display area, two or more first light-emitting devices disposed in the first display area, a plurality of second light-emitting devices disposed in the second display area, a first sub-pixel circuit commonly connected to the two or more first light-emitting devices, and two or more second sub-pixel circuits. Each of the two or more second sub-pixel circuits may be connected to a second light-emitting device among the plurality of second light-emitting devices.

[0434] The display panel according to one or more example embodiments of the present disclosure may further include an in-panel gate circuit disposed in the first display area.

[0435] In a display panel according to one or more example embodiments of the present disclosure, an intra-panel gate circuit may be disposed in a first display region, and one first sub-pixel circuit and two or more second sub-pixel circuits may be disposed in a second display region.

[0436] The display panel according to one or more example embodiments of the present disclosure may further include an extended link that commonly connects the pixel electrode of each of the two or more first light-emitting devices to a first sub-pixel circuit. That is, the extended link may commonly connect the pixel electrodes (e.g., the first anode) of the two or more first light-emitting devices to a first sub-pixel circuit. In a first sub-pixel circuit, the point at which the pixel electrode (e.g., the first anode) of each of the two or more first light-emitting devices is connected may be a node (e.g., Figure 2 The first node N1 in Fig. 9 The fourth node N4 in Fig.11 The second node N2 in the block diagram).

[0437] The display panel according to one or more example embodiments of the present disclosure may further include a metal layer disposed between the gate circuit and the extension link within the panel. A signal having a constant voltage level may be applied to the metal layer.

[0438] The display panel according to one or more example embodiments of the present disclosure may further include a shielding layer disposed between the gate circuit and the extension link within the panel. The shielding layer may be included in the metal layer.

[0439] A driving voltage applied to a common electrode for configuring the two or more first light emitting devices and the plurality of second light emitting devices may be applied to the shielding layer. The driving voltage may be a signal having a constant voltage level.

[0440] For example, the common electrode may be a cathode, and the driving voltage applied to the common electrode may be a cathode voltage and a base voltage. In this case, the shielding layer may be electrically connected to at least one of a base voltage line, a cathode, and a cathode connection pattern. Here, the cathode connection pattern may be a pattern connecting a cathode and a base voltage line.

[0441] A display device according to one or more example embodiments of the present disclosure may include a substrate, a display area for displaying an image, a light emitting device layer disposed above the substrate and including a plurality of light emitting devices disposed in the display area, and a basic circuit layer disposed between the light emitting device layer and the substrate and including a gate driving circuit and a sub-pixel circuit.

[0442] The gate drive circuit and the sub-pixel circuit can be arranged in the display area, at least a portion of the gate drive circuit can overlap with one or more first light-emitting devices among the multiple light-emitting devices, and at least a portion of the sub-pixel circuit can overlap with one or more second light-emitting devices among the multiple light-emitting devices.

[0443] The cathode may be disposed on the light emitting layers of the plurality of light emitting devices. The cathode may overlap at least a portion of the gate driving circuit and at least a portion of the sub-pixel circuit.

[0444] Gate drive circuit (for example, Fig.15 and Figures 17 to 19 The GIPC) can send a scan signal to a sub-pixel circuit (eg, Fig.15 and Figures 17 to 19 The strobe driving circuit (eg, SPC1, SPC2 and / or SPC1') may be configured to control a scanning line of the sub-pixel circuit or to send a light emitting control signal to a light emitting control line of the sub-pixel circuit. Fig.15 and Figures 17 to 19 GIPC) can control or drive sub-pixel circuits (e.g., Fig.15 and Figures 17 to 19 The gate of one or more of SPC1, SPC2 and / or SPC1').

[0445] One or more of the sub-pixel circuits may drive one or more second light emitting devices.

[0446] In one or more examples, the display device may include or may be a display device. In one or more examples, the display device may include or may be a display panel. In one or more examples, the display device may include or may be a device having electronic components and optical components.

[0447] In one or more examples, the gate drive circuit may include an intra-panel gate circuit. In one or more examples, the sub-pixel circuit may include a sub-pixel circuit array.

[0448] According to one or more example embodiments of the present disclosure, a display panel and a display device having an extremely narrow bezel structure may be provided.

[0449] According to one or more example embodiments of the present disclosure, an intra-panel gate circuit as an intra-panel gate type gate driving circuit may be provided in a display area, thereby reducing the size of a non-display area.

[0450] According to one or more example embodiments of the present disclosure, the in-panel gate circuit is arranged to overlap with the light emitting device layer in a vertical direction, thereby reducing the size of the non-display area.

[0451] According to one or more example embodiments of the present disclosure, a structure capable of shielding an electric field between a gate circuit in a panel and a light emitting device layer may be provided, thereby eliminating unnecessary electrical effects between the gate circuit in the panel and the light emitting device layer.

[0452] According to one or more example embodiments of the present disclosure, a connection structure between a cathode and a base voltage line is provided in the display area, thereby further reducing the size of the non-display area.

[0453] According to one or more exemplary embodiments of the present disclosure, the gate drive circuit and the cathode connection structure are arranged in the display area so that the length of the path through which the gate signal output from the gate drive circuit is provided to the sub-pixel circuit can be shortened, and the length of the cathode connection structure can also be shortened. The hanger on the structure can also be shortened. Therefore, the metal used in the path can be reduced, thereby enabling the display panel and the display device to be lightened.

[0454] The above description and accompanying drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments.

[0455] CROSS-REFERENCE TO RELATED APPLICATIONS

[0456] This application claims the benefit of and priority to Korean Patent Application No. 10-2023-0082777, filed on Jun. 27, 2023, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: substrate; A display area, the display area having a first display area and a second display area; a non-display area, the non-display area being located outside the display area; A basic circuit layer, the basic circuit layer is located on the substrate and includes an in-panel gate circuit and a sub-pixel circuit array arranged in the display area; as well as a light emitting device layer, the light emitting device layer being located on the base circuit layer and comprising two or more first light emitting devices disposed in the first display area and two or more second light emitting devices disposed in the second display area, Wherein, the sub-pixel circuit array comprises: a first sub-pixel circuit configured to simultaneously drive the two or more first light-emitting devices and disposed in the second display area; and Two or more second sub-pixel circuits are configured to drive the two or more second light emitting devices, respectively, and are disposed in the second display area.

2. The display device according to claim 1, wherein: The in-panel gate circuit is disposed in the first display area, and the sub-pixel circuit array is disposed in the second display area.

3. The display device according to claim 1, wherein: At least some of the two or more first light emitting devices overlap at least a portion of the in-panel gate circuit, and Wherein, at least some of the two or more second light emitting devices overlap with at least a portion of the sub-pixel circuit array.

4. The display device according to claim 1, further comprising an extension link connecting the one first sub-pixel circuit disposed in the second display area to the two or more first light-emitting devices disposed in the first display area, in, At least a portion of the extended link overlaps at least a portion of the in-panel gate circuit.

5. The display device according to claim 1, wherein: The first display area is located between the non-display area and the second display area. 6 . The display device according to claim 1 , further comprising a shielding layer, wherein the shielding layer is located between the in-panel gate circuit and the light emitting device layer.

7. The display device according to claim 6, further comprising an extension link connecting the one first sub-pixel circuit to two or more pixel electrodes included in the two or more first light emitting devices, in, The shielding layer is disposed in the first display area and between the extended link and the in-panel gate circuit, and Wherein, at least a portion of the shielding layer overlaps with the extended link and the in-panel gate circuit.

8. The display device according to claim 1, wherein: The light emitting device layer comprises: two or more first anodes, the two or more first anodes being arranged in the first display area; Two or more first light-emitting layers, wherein the two or more first light-emitting layers are respectively located on the two or more first anodes; two or more second anodes, the two or more second anodes being disposed in the second display area; two or more second light-emitting layers, the two or more second light-emitting layers being respectively located on the two or more second anodes; and a cathode, the cathode being arranged across the first display area and the second display area and being located on the two or more first light-emitting layers and the two or more second light-emitting layers, wherein a base voltage is applied to the cathode, The two or more first light emitting devices are configured in the first display area through the two or more first anodes, the two or more first light emitting layers and the cathode. wherein the two or more second light emitting devices are arranged in the second display area through the two or more second anodes, the two or more second light emitting layers and the cathode, and The display device further includes a base voltage line to which the base voltage is to be applied and a cathode connection pattern electrically connecting the cathode and the base voltage line.

9. The display device according to claim 8, further comprising an anode extension link connecting the one first sub-pixel circuit to the two or more first light emitting devices, in, The cathode connection pattern includes a first cathode connection pattern disposed on the same metal layer as the anode extension link.

10. The display device according to claim 8, wherein: The base voltage line and the cathode connection pattern are located in the non-display area, and Wherein, the base voltage line is arranged outside the gate circuit in the panel.

11. The display device according to claim 10, further comprising a shielding layer, the shielding layer being located between the gate circuit in the panel and the light emitting device layer and being disposed in the first display area, in, The shielding layer is electrically connected to at least one of the cathode, the base voltage line, and the cathode connection pattern.

12. The display device according to claim 8, wherein: The base voltage line and the cathode connection pattern are located in the display area, and The cathode is electrically connected to at least one of the cathode connection pattern and the base voltage line located below the bank through a hole in the bank between the two or more second anodes.

13. The display device according to claim 8, wherein: The light emitting device layer further includes two or more third anodes disposed in the first display area and two or more third light emitting layers respectively located on the two or more third anodes. wherein two or more third light emitting devices are arranged in the first display area through the two or more third anodes, the two or more third light emitting layers and the cathode, The sub-pixel circuit array further includes a third sub-pixel circuit, which is disposed in the second display area and configured to simultaneously drive the two or more third light-emitting devices, and Wherein, the display device further includes: a first anode extension link connecting the one first sub-pixel circuit disposed in the second display area with the two or more first light emitting devices disposed in the first display area; and A second anode extension link connects the one third sub-pixel circuit disposed in the second display area with the two or more third light emitting devices disposed in the first display area.

14. The display device according to claim 13, wherein: The first anode extension link and the second anode extension link are located between the basic circuit layer and the light emitting device layer, and are disposed on different metal layers.

15. A display panel, comprising: substrate; A display area, the display area having a first display area and a second display area; a non-display area, the non-display area being located outside the display area; Two or more first light emitting devices, wherein the two or more first light emitting devices are arranged in the first display area; a plurality of second light emitting devices, wherein the plurality of second light emitting devices are arranged in the second display area; a first sub-pixel circuit, the first sub-pixel circuit being commonly connected to the two or more first light-emitting devices; and two or more second sub-pixel circuits, Each of the two or more second sub-pixel circuits is connected to a second light-emitting device among the plurality of second light-emitting devices.

16. The display panel according to claim 15, further comprising an intra-panel gate circuit, wherein the intra-panel gate circuit is disposed in the first display area. in, The one first sub-pixel circuit and the two or more second sub-pixel circuits are disposed in the second display area. 17 . The display panel according to claim 16 , further comprising an extension link commonly connecting a pixel electrode of each of the two or more first light emitting devices to the one first sub-pixel circuit.

18. The display panel according to claim 17, further comprising a metal layer disposed between the gate circuit in the panel and the extended link, in, A signal having a constant voltage level is applied to the metal layer.

19. A display device, comprising: substrate; Display area; a light emitting device layer disposed above the substrate and including a plurality of light emitting devices disposed in the display area; as well as a basic circuit layer, which is disposed between the light emitting device layer and the substrate and includes a gate drive circuit and a sub-pixel circuit, in, The gate driving circuit and the sub-pixel circuit are arranged in the display area; At least a portion of the gate drive circuit overlaps with one or more first light emitting devices among the plurality of light emitting devices; and At least a portion of the sub-pixel circuit overlaps with one or more second light emitting devices among the plurality of light emitting devices.

20. The display device according to claim 19, wherein: The cathode is arranged on the light-emitting layers of the plurality of light-emitting devices; The cathode overlaps the at least a portion of the gate drive circuit and the at least a portion of the sub-pixel circuit; The gate drive circuit is configured to send a scan signal to a scan line of the sub-pixel circuit or send a light emission control signal to a light emission control line of the sub-pixel circuit; and One or more of the sub-pixel circuits are configured to drive the one or more second light emitting devices.

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