Control method and memory for a sensitive amplifier

Abstract

The present disclosure provides a control method of a sense amplifier and a memory. The sense amplifier includes a pre-charge phase, an offset cancellation phase, a charge sharing phase and a sense amplification phase. In the offset cancellation phase, a first power terminal is controlled to be connected to a power voltage, a second power terminal is controlled to be connected to a ground voltage, and the sense amplifier is controlled to form a compensation voltage on a bit line and a complementary bit line; a duration of the offset cancellation phase is an optimal offset cancellation duration, and a sensing margin of the sense amplifier is a maximum value at the optimal offset cancellation duration. In the sense amplification phase, the first power terminal is controlled to be connected to the power voltage, the second power terminal is controlled to be connected to the ground voltage, and a time when the first power terminal is connected to the power voltage is later than a time when the second power terminal is connected to the ground voltage, and the sense amplifier is controlled to amplify a voltage difference on the bit line and the complementary bit line.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a control method for a sense amplifier and a memory. Background Art

[0002] With the development of memory technology, memory is widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] The sense amplifier (SA) is a crucial component of semiconductor memory. Its primary function is to sense and amplify small signals on the bit line, enabling read or write operations. Improvements to the sense amplifier can help improve data read and write performance. Summary of the Invention

[0004] The present disclosure provides a control method for a sense amplifier, wherein the sense amplifier is connected to a bit line and a complementary bit line, the bit line is connected to a memory cell, and the sense amplifier includes a first power supply terminal and a second power supply terminal. The method includes:

[0005] In the pre-charging stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the pre-charging voltage, and the sense amplifier is controlled to drive the voltage on the bit line and the complementary bit line to the pre-charging voltage;

[0006] During the offset cancellation phase, the first power supply terminal is controlled to be connected to a power supply voltage, the second power supply terminal is controlled to be connected to a ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line. The duration of the offset cancellation phase is an optimal offset cancellation duration, and the sensing margin of the sense amplifier is maximized under the optimal offset cancellation duration.

[0007] In the charge sharing stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the precharge voltage, the memory cell and the bit line share charge, and a charge sharing voltage is formed on the bit line and the complementary bit line;

[0008] During the sensing and amplification phase, the first power supply terminal is controlled to be connected to the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage. The first power supply terminal is connected to the power supply voltage later than the second power supply terminal is connected to the ground voltage. The sense amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

[0009] In some embodiments, the control method further includes:

[0010] generating a plurality of first control scenarios, wherein each first control scenario includes a duration parameter of an offset elimination phase, and the duration parameters of the offset elimination phase in any two first control scenarios are different;

[0011] The first sensing margin of the sense amplifier in the first control scenario is obtained; and a time length parameter of the offset cancellation stage corresponding to the maximum sensing margin in the plurality of first sensing margins is taken as the optimal offset cancellation time length.

[0012] In some embodiments, the first sensing margin of the sense amplifier in the first control scenario is obtained, specifically comprising:

[0013] The second sensing margin of the sense amplifier in the first control scenario in the target storage area when the condition disadvantageous to reading out the first data is set is obtained.

[0014] The third sensing margin of the sense amplifier in the first control scenario in the target storage area when the condition disadvantageous to reading out the second data is set is obtained.

[0015] The sum of the second sensing margin and the third sensing margin is calculated as the first sensing margin.

[0016] In some embodiments, the second sensing margin of the sense amplifier in the first control scenario in the target storage area when the condition disadvantageous to reading out the first data is set is obtained, specifically comprising:

[0017] A plurality of first scan voltages greater than the lower plate reference voltage of the storage cell are generated.

[0018] For each first scan voltage, the voltage in the storage cell in the target storage area is adjusted according to the first scan voltage, and the time length of the offset cancellation stage of the sense amplifier is controlled to be the time length parameter, the data read error rate of the storage cell in the target storage area is counted, and a first mapping relationship between the plurality of first scan voltages and the read error rate under each first scan voltage is obtained.

[0019] The second sensing margin is calculated and obtained according to the first mapping relationship.

[0020] In some embodiments, the third sensing margin of the sense amplifier in the first control scenario in the target storage area when the condition disadvantageous to reading out the second data is set is obtained, specifically comprising:

[0021] A plurality of second scan voltages less than the lower plate reference voltage of the storage cell are generated.

[0022] For each second scan voltage, the voltage in the storage cell in the target storage area is adjusted according to the second scan voltage, and the time length of the offset cancellation stage of the sense amplifier is controlled to be the time length parameter, the data read error rate of the storage cell in the target storage area is counted, and a second mapping relationship between the plurality of second scan voltages and the read error rate under each second scan voltage is obtained.

[0023] The third sensing margin is calculated and obtained according to the second mapping relationship.

[0024] In some embodiments, the control method further comprises:

[0025] generating a plurality of second control scenarios, wherein each second control scenario comprises a time length parameter of the offset cancellation phase, a first time point at which the first power supply end switches from turning on the pre-charge voltage to turning on the power supply voltage in the charge sharing phase, and a second time point at which the second power supply end switches from turning on the pre-charge voltage to turning on the ground voltage in the charge sharing phase; the time length parameter of the offset cancellation phase in each second control scenario is the optimal offset cancellation time length, the first time point is later than the second time point in the same second control scenario, and the first time point is different in any two second control scenarios or the second time point is different in any two second control scenarios;

[0026] obtaining a sensing margin difference value of the sensitive amplifier under each second control scenario; taking the first time point corresponding to the minimum sensing margin difference value in the plurality of sensing margin difference values as the optimal first time point at which the first power supply end switches from turning on the pre-charge voltage to turning on the power supply voltage in the charge sharing phase, and taking the second time point corresponding to the minimum sensing margin difference value as the optimal second time point at which the second power supply end switches from turning on the pre-charge voltage to turning on the ground voltage in the charge sharing phase;

[0027] Correspondingly, the first power supply end is controlled to turn on the power supply voltage, the second power supply end is controlled to turn on the ground voltage, and the time point at which the first power supply end turns on the power supply voltage is later than the time point at which the second power supply end turns on the ground voltage, and the sensitive amplifier is controlled to amplify the voltage difference on the bit line and the complementary bit line, specifically comprising:

[0028] the time point at which the first power supply end switches from turning on the pre-charge voltage to turning on the power supply voltage in the charge sharing phase is the optimal first time point, the time point at which the second power supply end switches from turning on the pre-charge voltage to turning on the ground voltage in the charge sharing phase is the optimal second time point, and the sensitive amplifier is controlled to amplify the voltage difference on the bit line and the complementary bit line.

[0029] In some embodiments, obtaining the fourth sensing margin of the sensitive amplifier under each second control scenario specifically comprises:

[0030] obtaining the fourth sensing margin of the sensitive amplifier in the target storage area under the second control scenario when the condition that is not conducive to reading out the first data is set;

[0031] obtaining the fifth sensing margin of the sensitive amplifier in the target storage area under the second control scenario when the condition that is not conducive to reading out the first data is set;

[0032] calculating the difference between the fourth sensing margin and the fifth sensing margin as the sensing margin difference value.

[0033] In some embodiments, the fourth sensing margin of the sense amplifier in the target storage area under the second control scenario is obtained when a condition is set to be disadvantageous for reading out the first data, and specifically includes:

[0034] generating a plurality of third scan voltages greater than the lower plate reference voltage of the storage unit;

[0035] For each third scan voltage, adjusting the voltage in the storage unit in the target storage area according to the third scan voltage, controlling the length of the offset cancellation phase of the sense amplifier to be the optimal offset cancellation length, controlling the time when the first power supply end switches from being connected to the pre-charge voltage to being connected to the power supply voltage in the charge sharing phase to be the first time, and controlling the time when the second power supply end switches from being connected to the pre-charge voltage to being connected to the ground voltage in the charge sharing phase to be the second time, and counting the data read error rate of the storage unit in the target storage area, to obtain a third mapping relationship between the plurality of third scan voltages and the read error rate under each third scan voltage.

[0036] The fourth sensing margin is obtained according to the third mapping relationship.

[0037] In some embodiments, the fifth sensing margin of the sense amplifier in the target storage area under the second control scenario is obtained when a condition is set to be disadvantageous for reading out the second data, and specifically includes:

[0038] generating a plurality of fourth scan voltages greater than the lower plate reference voltage of the storage unit;

[0039] For each fourth scan voltage, adjusting the voltage in the storage unit in the target storage area according to the fourth scan voltage, controlling the length of the offset cancellation phase of the sense amplifier to be the optimal offset cancellation length, controlling the time when the first power supply end switches from being connected to the pre-charge voltage to being connected to the power supply voltage in the charge sharing phase to be the first time, and controlling the time when the second power supply end switches from being connected to the pre-charge voltage to being connected to the ground voltage in the charge sharing phase to be the second time, and counting the data read error rate of the storage unit in the target storage area, to obtain a fourth mapping relationship between the plurality of fourth scan voltages and the read error rate under each fourth scan voltage.

[0040] The fifth sensing margin is obtained according to the fourth mapping relationship, wherein the storage unit in the target storage area stores the second data, and the fourth scan voltage is generated according to the reference voltage corresponding to the second data.

[0041] Some embodiments of the present application provide a memory, comprising: a storage unit, a sense amplifier, and a controller, the storage unit is connected with a bit line, the sense amplifier is connected with the bit line, the controller is connected with the sense amplifier, and the controller is used to implement the method involved in the above embodiments.

[0042] Some embodiments of the present application provide a control method and memory for a sense amplifier. The operating phases of the sense amplifier include a precharge phase, an offset cancellation phase, a charge sharing phase, and a sense amplification phase. The offset cancellation phase is designed to have an optimal offset cancellation duration. Under this optimal offset cancellation duration, the sense amplifier's sensing margin is maximized, effectively eliminating most mismatch noise and other noise in the sense amplifier. During the sense amplification phase, the first power supply terminal is controlled to be connected to a power voltage later than the second power supply terminal is connected to a ground voltage. This adjusts the sensing margins on the bit line and complementary bit line, thereby reducing the data bias of the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0044] Figure 1 A schematic diagram of the memory architecture provided for some embodiments of the present disclosure;

[0045] Figure 2 An exemplary structural diagram of a storage unit according to some embodiments of the present disclosure is shown;

[0046] Figure 3 A circuit schematic diagram of a sense amplifier provided in some embodiments of the present disclosure;

[0047] Figure 4A for Figure 3 An operating timing diagram of the sense amplifier shown;

[0048] Figure 4B for Figure 3 Another working timing diagram of the sense amplifier shown;

[0049] Figure 5 A flowchart of a control method for a sense amplifier provided in some embodiments of the present disclosure;

[0050] Figure 6 A graph showing the relationship between offset cancellation time and compensation voltage provided in some embodiments of the present application;

[0051] Figure 7 for Figure 3 Another working timing diagram of the sense amplifier shown;

[0052] Figure 8 A schematic diagram of a first mapping relationship and a second mapping relationship in a first control scenario provided in some embodiments of the present application;

[0053] Figure 9 Schematic diagram of first mapping relationship and second mapping relationship in different first control scenarios provided by some embodiments of the present application;

[0054] Figure 10 Schematic diagrams of the third mapping relationship and the fourth mapping relationship under different second control scenarios provided in some embodiments of the present application.

[0055] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0056] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0057] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically specified.

[0058] In the description of this disclosure, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; and direct connections or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on the specific circumstances.

[0059] Currently, memory technology is developing rapidly. Taking DRAM as an example, the main applications include Synchronous Dynamic Random-Access Memory (SDRAM), various generations of Double Data Rate (DDR) SDRAM, and various generations of Low Power Double Data Rate (LPDDR) SDRAM.

[0060] Figure 1 This is an example diagram of a memory architecture, such asFigure 1 As shown, the DRAM includes address processing circuit 210, command decoding circuit 220, data input / output circuit 230, row decoder 240, column decoder 250, sense amplifier (SA) 260, and a storage array, as examples. Among them, address processing circuit 210, command decoding circuit 220, and data input / output circuit 230 belong to peripheral region circuit, and row decoder 240, column decoder 250, sense amplifier 260, and the storage array belong to array region circuit. The storage array is mainly composed of storage unit 270, bit line BL, and word line WL. The word line WL in the storage array extends in the row direction, the bit line BL in the storage array extends in the column direction, and the intersection of the word line WL and the bit line BL is the storage unit 270 of the storage array.

[0061] Among them, each storage unit 270 is used to store one bit of data. Figure 2 The structure of the storage unit shown in an embodiment is shown in the example diagram as Figure 2 As shown, the storage unit 270 includes a switch transistor M and a capacitor C, any one of the source or drain of the switch transistor M is connected with the upper plate of the capacitor, the other of the source or drain of the switch transistor M is connected with the bit line BL, the lower plate of the capacitor C is connected with a power supply end, the voltage of the power supply end is the lower plate reference voltage, and the gate of the switch transistor M is connected with the word line WL. Among them, the capacitor C is used to store data, and the switch transistor M is used to turn off or turn on according to the selected state.

[0062] The word line WL of the row where the storage unit is located can be selected by the row decoder 240, and the switch transistor M in the corresponding diagram is turned on. By setting the logic level of the bit line to 1, the upper plate of the capacitor C is charged, that is, data "1" is written to the storage unit. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the upper plate of the capacitor C is discharged, that is, data "0" is written to the storage unit.

[0063] With the increasing integration of chips, the feature size of the transistor process is continuously reduced, and the threshold voltage fluctuation of the MOS tube in the sensitive amplifier and the small voltage signal are susceptible to noise interference, and other problems are increasingly prominent, which seriously affects the correctness of the sensitive amplifier in sensing the data in the storage unit. The sensing margin (Sensing margin, referred to as SM) is an important indicator to measure the performance of the sensitive amplifier, and the calculation formula of the sensing margin SM is: SM = Supply dVBL- Required dVBL, wherein Supply dVBL specifically refers to the voltage difference between the bit line and the complementary bit line at the end of the charge sharing stage, and Supply dVBL is also referred to as the supply of the sensing margin. Required dVBL refers to the voltage difference required for the SA to correctly amplify, and Required dVBL is also referred to as the loss of the sensing margin. The loss of the sensing margin is caused by the mismatch of the threshold voltage of the MOS tube and the coupling noise. The offset calibration sensitive amplifier (Offset Calibration Sense Amplifier, referred to as OCSA) increases the offset cancellation operation to eliminate the mismatch caused by the threshold voltage of the transistor, and improves the sensing margin.

[0064] For the convenience of description, the offset calibration sensitive amplifier will be referred to as a sensitive amplifier below. As shown in Figure 2 The sensitive amplifier 260 is connected with the bit line BL and the complementary bit line BLB, and the bit line BL is connected with the storage unit 270. The working stage of the sensitive amplifier includes a pre-charge stage, an offset calibration stage, a charge sharing stage and a sensing amplification stage. In the pre-charge stage, the sensitive amplifier drives the voltage on the bit line BL and the complementary bit line BLB to the pre-charge voltage. In the offset calibration stage, the sensitive amplifier forms a compensation voltage on the bit line BL and the complementary bit line BLB to compensate for the mismatch between the MOS tubes. In the charge sharing stage, the storage unit 270 performs charge sharing with the bit line BL to form a charge sharing voltage on the bit line BL. In the sensing amplification stage, the sensitive amplifier amplifies the voltage difference on the bit line BL and the complementary bit line BLB.

[0065] Figure 3 It is a circuit schematic diagram of an amplifier, which is only an example of a sensitive amplifier and does not limit the structure of the sensitive amplifier. The sensitive amplifier includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a first switch unit 110, a second switch unit 120, a third switch unit 130 and a fourth switch unit 140.

[0066] The gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2, the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1, and the source of the first P-type transistor P1 is connected to the first power supply terminal PCS. The gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1, the drain of the second P-type transistor P2 is connected to the drain of the second N-type transistor N2, and the source of the second P-type transistor P2 is connected to the first power supply terminal PCS. The drain of the first P-type transistor P1 is connected to the complementary read bit line SABLB, and the drain of the second P-type transistor P2 is connected to the read bit line SABL. The gate of the first N-type transistor N1 is connected to the bit line BL, and the source of the first N-type transistor N1 is connected to the second power supply terminal NCS. The gate of the second N-type transistor N2 is connected to the complementary bit line BLB, and the source of the second N-type transistor N2 is connected to the second power supply terminal NCS.

[0067] The first end of the first switch unit 110 is connected to the gate of the first N-type transistor N1, the second end of the first switch unit 110 is connected to the drain of the first N-type transistor N1, and the control end of the first switch unit 110 receives the offset cancellation signal OC. The first end of the second switch unit 120 is connected to the drain of the second N-type transistor N2, the second end of the second switch unit 120 is connected to the gate of the second N-type transistor N2, and the control end of the second switch unit 120 receives the offset cancellation signal OC. The first end of the third switch unit 130 is connected to the bit line BL, the second end of the third switch unit 130 is connected to the drain of the second P-type transistor P2, and the control end of the third switch unit 130 receives the isolation control signal ISO. The first end of the fourth switch unit 140 is connected to the drain of the first P-type transistor P1, the second end of the fourth switch unit 140 is connected to the complementary bit line BLB, and the control end of the fourth switch unit 140 receives the isolation control signal ISO.

[0068] The sensitive amplifier further comprises an equalization module 150 connected to the read bit line SABL and / or the complementary read bit line SABLB, and the equalization module 150 is also connected to a pre-charge power supply terminal, the voltage of the pre-charge power supply terminal is a pre-charge voltage VBLP, and the pre-charge voltage VBLP is half of the power supply voltage VDD. The equalization module 150 receives an equalization control signal EQ. Figure 3 The equalization module 150 is connected to the read bit line SABL as an example.

[0069] The sensitive amplifier further comprises a third P-type transistor P3 and a seventh N-type transistor N7. The drain of the third P-type transistor P3 is connected to the first power terminal PCS of the sensitive amplifier, the source of the third P-type transistor P3 is connected to the first power line, the voltage on the power line is the power voltage VDD, and the gate of the third P-type transistor P3 receives the first power control signal SAP. The drain of the seventh N-type transistor N7 is connected to the second power terminal NCS of the sensitive amplifier, the source of the seventh N-type transistor N7 is connected to the second power line, the voltage on the second power line is the ground voltage VSS, and the gate of the seventh N-type transistor N7 receives the second power control signal SAN.

[0070] Figure 4A and Figure 4B for Figure 3 the working timing diagram of the sensitive amplifier shown in FIG. 6, with reference to Figure 4A and Figure 4B In the pre-charge phase T1, the offset cancellation signal OC is at a high level, the third N-type transistor N3 is controlled to be in a closed state, the bit line BL is connected to the complementary read bit line SABLB. The offset cancellation signal OC is at a high level, the fourth N-type transistor N4 is controlled to be in a closed state, the complementary bit line BLB is connected to the read bit line SABL. The isolation control signal ISO is at a high level, the fifth N-type transistor N5 is controlled to be in a closed state, the bit line BL is connected to the read bit line SABL. The isolation control signal ISO is at a high level, the sixth N-type transistor N6 is controlled to be in a closed state, the complementary bit line BLB is connected to the complementary read bit line SABLB. The first power control signal SAP is at a high level, the first power terminal PCS is disconnected from the first power line, the first power terminal PCS is at the pre-charge voltage VBLP, the second power control signal SAN is at a low level, the second power terminal NCS is disconnected from the second power line, and the second power terminal NCS is at the pre-charge voltage VBLP. The word line signal SWL is at a low level, and the word line WL is in an unopened state. Under the control of the equalization control signal EQ, the equalization module 150 connects the read bit line SABL to the pre-charge power terminal, so as to drive the voltages on the bit line BL and the complementary bit line BLB to the pre-charge voltage VBLP.

[0071] In the offset cancellation phase T2, the offset cancellation signal OC is high, controlling the third N-type transistor N3 to be in a closed state, the first N-type transistor N1 to be in a diode connection state, the offset cancellation signal OC is high, controlling the fourth N-type transistor N4 to be in a closed state, the second N-type transistor N2 to be in a diode connection state. The isolation control signal ISO is low, controlling the fifth N-type transistor N5 and the sixth N-type transistor N6 to be in an open state, the first power supply control signal SAP is low, the first power supply end PCS is connected to the first power supply line, and the voltage of the first power supply end PCS is the power supply voltage VDD. The second power supply control signal SAN is high, the second power supply end NCS is connected to the second power supply line, and the voltage of the second power supply end NCS is the ground voltage VSS. The word line signal SWL is low, and the word line WL is in an unopened state. By such setting, in the offset cancellation phase, the sense amplifier forms a compensation voltage on the bit line BL and the complementary bit line BLB to compensate for the mismatch between the MOS transistors.

[0072] In the charge sharing phase T3, the offset cancellation signal OC is low, controlling the third N-type transistor N3 and the fourth N-type transistor N4 to be in an open state. The isolation control signal ISO is high, controlling the fifth N-type transistor N5 and the sixth N-type transistor N6 to be in a closed state. The first power supply control signal SAP is high, the first power supply end PCS is disconnected from the first power supply line, and the first power supply end PCS is the pre-charge voltage VBLP. The second power supply control signal SAN is low, the second power supply end NCS is disconnected from the second power supply line, and the second power supply end NCS is the pre-charge voltage VBLP. The word line signal SWL is high, and the word line WL is in an opened state. By such setting, the storage unit and the bit line BL perform charge sharing, forming a charge sharing voltage on the bit line BL and the complementary bit line BLB.

[0073] In the sensing amplification phase T4, the offset cancellation signal OC is low, controlling the third N-type transistor N3 and the fourth N-type transistor N4 to be in an open state. The isolation control signal ISO is high, controlling the fifth N-type transistor N5 and the sixth N-type transistor N6 to be in a closed state. The first power supply control signal SAP is low, the first power supply end PCS is connected to the first power supply line, and the voltage of the first power supply end PCS is the power supply voltage VDD. The second power supply control signal SAN is high, the second power supply end NCS is connected to the second power supply line, and the voltage of the second power supply end NCS is the ground voltage VSS. The word line signal SWL is high, and the word line WL is in an opened state. By such setting, in the sensing amplification phase, the sense amplifier amplifies the voltage difference on the bit line BL and the complementary bit line BLB.

[0074] However, the sense amplifier has a data preference problem. More specifically, the sense amplifier is more favorable for sensing and amplifying data "1", and is less favorable for sensing and amplifying data "0". Figure 4A and Figure 4B illustrate. Figure 4A For the case of reading data "1" from the memory cell under the most unfavorable environmental conditions, Figure 4A The most unfavorable medium environment scenario occurs when the threshold voltage of the first N-type transistor N1 is lower than the threshold voltage of the second N-type transistor N2. Because the threshold voltage of the first N-type transistor N1 is lower than the threshold voltage of the second N-type transistor N2, during the offset cancellation phase, the voltage on the bitline BL connected to the first N-type transistor N1 is lower than the voltage on the complementary bitline BLB connected to the second N-type transistor N2. This means that the compensation voltage Vos is negative. Since the memory cell stores the data "1," the voltage in the memory cell is higher than the precharge voltage, resulting in a significant voltage difference between the memory cell and the bitline BL. After the charge sharing phase, driven by the voltage on the memory cell, the voltage difference between the bitline BL and the complementary bitline BLB is also larger, resulting in a larger sensing margin SM, which facilitates accurate data readout.

[0075] Figure 4B For the case of reading data "0" from the memory cell under the most unfavorable environmental conditions, Figure 4B The most unfavorable medium environment scenario occurs when the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2. Because the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2, during the offset cancellation phase, the voltage on the bit line BL connected to the first N-type transistor N1 is greater than the voltage on the complementary bit line BLB connected to the second N-type transistor N2. This means that the compensation voltage Vos is positive. Since the memory cell stores the data "0," the voltage in the memory cell is less than the precharge voltage, and the voltage difference between the memory cell and the bit line BL is relatively small. After the charge sharing phase, driven by the voltage on the memory cell, the voltage difference between the bit line BL and the complementary bit line BLB is relatively small, and the sensing margin SM is also smaller. This makes data flipping more likely to occur during the sensing amplification phase, hindering accurate data reading.

[0076] Furthermore, while the offset cancellation operation of the sense amplifier can eliminate the mismatch caused by the threshold voltage of the transistor, in memory, factors such as transistor mismatch, electrical signal noise, bit line parasitic capacitance, and bit line parasitic resistance in different sense amplifiers are random, resulting in different mismatches for all sense amplifiers. This still means that the mismatch of some sense amplifiers cannot be eliminated.

[0077] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following describes the solutions with examples in conjunction with some embodiments of the present disclosure.

[0078] like Figure 5 As shown, some embodiments of the present disclosure provide a control method for a sense amplifier, wherein the sense amplifier is connected to a bit line and a complementary bit line, the bit line is connected to a memory cell, and the sense amplifier includes a first power supply terminal and a second power supply terminal. The control method specifically includes the following steps:

[0079] S101 , in a precharge phase, controlling the first power supply terminal and the second power supply terminal to be connected to a precharge voltage, and controlling the sense amplifier to drive the voltage on the bit line and the complementary bit line to the precharge voltage.

[0080] In this step, the sense amplifier includes an equalization module connected to a precharge power supply terminal, the voltage of which is the precharge voltage. The first power supply terminal and the second power supply terminal are connected to the precharge voltage, so that the voltage of the first power supply terminal and the voltage of the second power supply terminal are both the precharge voltage. When the voltage of the first power supply terminal and the voltage of the second power supply terminal are both the precharge voltage, the equalization module connects the bit line and the complementary bit line to the precharge power supply terminal, driving the voltage on the bit line and the complementary bit line to the precharge voltage.

[0081] S102: During an offset cancellation phase, the first power supply terminal is controlled to be connected to a power supply voltage, the second power supply terminal is controlled to be connected to a ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line. The offset cancellation phase is performed for an optimal offset cancellation duration, at which the sensing margin of the sense amplifier is maximized.

[0082] In this step, the first power supply terminal is controlled to be connected to a power supply voltage, so that the voltage at the first power supply terminal is the power supply voltage, and the second power supply terminal is controlled to be connected to a ground voltage, so that the voltage at the second power supply terminal is the ground voltage. When the voltage at the first power supply terminal is the power supply voltage and the voltage at the second power supply terminal is the ground voltage, the sense amplifier is controlled to generate a compensation voltage on the bit line and the complementary bit line.

[0083] by Figure 3 The structure of the sense amplifier shown in FIG is an example to illustrate the process of forming the compensation voltage. Figure 3 As shown, by controlling the first switch unit 110 and the second switch unit 120 to be closed and the third switch unit 130 and the fourth switch unit 140 to be open, the sense amplifier forms a compensation voltage on the bit line and the complementary bit line.

[0084] The duration of the offset cancellation phase will affect the magnitude of the compensation voltage formed on the bit line and the complementary bit line, and thus will affect the magnitude of the sensing margin on the bit line and the complementary bit line. Figure 6As shown, if the offset cancellation phase lasts for a long time, such as tOC3, a large compensation voltage Vos3 will be formed on the bit line and complementary bit line, indicating overcompensation. If the offset cancellation phase lasts for a short time, such as tOC1, a small compensation voltage Vos1 will be formed on the bit line and complementary bit line, indicating undercompensation. By setting the offset cancellation phase to the optimal offset cancellation duration, for example, tOC2, the compensation voltage Vos2 on the bit line and complementary bit line is optimized, thereby maximizing the sensing margin on the bit line and complementary bit line.

[0085] Among them, the duration of the offset elimination phase refers to the time from the start moment of the offset elimination phase to the end moment of the offset elimination phase. The third moment when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power supply voltage during the offset elimination phase, or the fourth moment when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the offset elimination phase, is used as the start moment of the offset elimination phase. It can also be any moment between the third moment and the fourth moment as the start moment of the offset elimination phase. Among them, the third moment is the moment when the voltage of the first power supply terminal changes from the pre-charge voltage to the power supply voltage, or it can be the moment when the voltage of the first power supply terminal is the power supply voltage, or it can be the moment from the start of switching to the completion of switching. The fourth moment is defined similarly and will not be repeated here. The size relationship between the third moment and the fourth moment is not limited here.

[0086] The fifth moment when the first power supply terminal switches from being connected to the power supply voltage to being connected to the pre-charge voltage during the offset elimination phase, or the sixth moment when the second power supply terminal switches from being connected to the ground voltage to being connected to the pre-charge voltage during the offset elimination phase is the end moment of the offset elimination phase. Any moment between the fifth moment and the sixth moment may also be the end moment of the offset elimination phase. The fifth moment is the moment when the voltage of the second power supply terminal changes from the pre-charge voltage to the ground voltage, or the moment when the voltage of the second power supply terminal is the ground voltage, or the moment from the start of the switch to the completion of the switch. The definition of the sixth moment is similar and will not be repeated here. The size relationship between the fifth moment and the sixth moment is not limited here.

[0087] At the same time, the first switch unit 110 and the second switch unit 120 are closed at the third moment, the fourth moment, or any time between the third and fourth moments, and are opened at the fifth moment, the sixth moment, or any time between the fifth and sixth moments, so that the sense amplifier forms a compensation voltage on the bit line and the complementary bit line. Ideally, the third moment is equal to the fourth moment, and the fifth moment is equal to the sixth moment.

[0088] S103 , in the charge sharing stage, controlling the first power supply terminal and the second power supply terminal to be connected to the precharge voltage, the memory cell and the bit line perform charge sharing, and a charge sharing voltage is formed on the bit line and the complementary bit line.

[0089] The first power supply end and the second power supply end are controlled to be connected to the pre-charge voltage, the voltage of the first power supply end and the voltage of the second power supply end are both the pre-charge voltage, the word line is turned on, the switch transistor M in the storage unit is turned on, the storage unit capacitor C and the bit line share charges, and the charge sharing voltage is formed on the bit line and the complementary bit line. Since the length of the offset elimination stage is the optimal offset elimination length, the compensation voltage formed on the bit line and the complementary bit line in the offset elimination stage is optimal, and then the bit line shares charges with the storage unit, the charge sharing voltage is formed on the bit line and the complementary bit line, and the voltage difference between the bit line and the complementary bit line is the largest at the end of the charge sharing stage, that is, the supply amount of the sensing margin Supply dVBL is the largest, so that the sensing margin is the largest.

[0090] In the sensing amplification stage, the first power supply end is controlled to be connected to the power supply voltage, the second power supply end is controlled to be connected to the ground voltage, and the first power supply end is connected to the power supply voltage later than the second power supply end is connected to the ground voltage, and the voltage difference between the bit line and the complementary bit line is amplified by the sensitive amplifier.

[0091] The first time when the first power supply end is switched from being connected to the pre-charge voltage to being connected to the power supply voltage in the charge sharing stage can be used as the end time of the charge sharing stage. The second time when the second power supply end is switched from being connected to the pre-charge voltage to being connected to the ground voltage can also be used as the end time of the charge sharing stage. Alternatively, any time between the first time and the second time can be used as the end time of the charge sharing stage. The first time can be the time when the voltage of the first power supply end starts to be switched from the pre-charge voltage to the power supply voltage, the time when the voltage of the first power supply end becomes the power supply voltage, or the time between the start of the switching and the completion of the switching. The second time can be the time when the voltage of the second power supply end starts to be switched from the pre-charge voltage to the ground voltage, the time when the voltage of the second power supply end becomes the ground voltage, or the time between the start of the switching and the completion of the switching.

[0092] The first power supply end is controlled to be connected to the power supply voltage, and the voltage of the first power supply end is the power supply voltage. The second power supply end is controlled to be connected to the ground voltage, and the voltage of the second power supply end is the ground voltage.

[0093] The first power supply terminal is connected to the power voltage at a later time than the second power supply terminal is connected to the ground voltage. This causes the second power supply terminal to first pull down the voltage of the bit line and the complementary bit line, and then the first and second power supplies jointly drive the bit line and the complementary bit line. When the second power supply terminal is connected to the ground voltage, the voltage on the bit line turns on the transistor connected to both the second power supply terminal and the bit line, while the voltage on the complementary bit line turns on the transistor connected to both the second power supply terminal and the complementary bit line. The second power supply terminal pulls down the voltages on the bit line and the complementary bit line, thereby adjusting the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase, thereby adjusting the sensing margin on the bit line and the complementary bit line.

[0094] More specifically, when data "1" is stored in the memory cell, the second power supply terminal pulls down the voltage on the bit line and the complementary bit line. Under the most unfavorable environmental conditions, the threshold voltage of the first N-type transistor N1 is lower than the threshold voltage of the second N-type transistor N2, the bit line voltage is pulled down faster than the complementary bit line voltage, and the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase becomes smaller, thereby reducing the sensing margin on the bit line and the complementary bit line.

[0095] When storing data "0" in the memory cell, the second power supply terminal pulls down the voltage on the bit line and the complementary bit line. Under the most unfavorable environmental conditions, the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2, and the bit line voltage is pulled down at a slower rate than the complementary bit line voltage. The voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase increases, thereby increasing the sensing margin on the bit line and the complementary bit line. In this way, the difference between the sensing margin when storing data "1" in the memory cell and the sensing margin when storing data "0" in the memory cell can be reduced, thereby reducing the data bias of the sense amplifier.

[0096] In the above technical solution, the sense amplifier includes a precharge phase, an offset cancellation phase, a charge sharing phase, and a sense amplification phase. The offset cancellation phase is performed at an optimal offset cancellation duration, which maximizes the sense amplifier's sensing margin, thereby eliminating most mismatch noise and other noise in the sense amplifier. During the sense amplification phase, the first power supply terminal is controlled to be connected to a power voltage later than the second power supply terminal is connected to a ground voltage. This adjusts the sensing margin on the bit line and the complementary bit line, thereby reducing the data bias of the sense amplifier.

[0097] Below Figure 3 The structure of the sensitive amplifier shown in FIG. 1 illustrates the process of the control method provided by this application. Figure 7 As shown, Figure 4ADifferent is, in the sensing amplification stage, the starting time of the first power supply control signal SAP being low is later than the starting time of the second power supply control signal SAN being high, compared with the time when the first power supply end PCS is connected with the first power line, the time when the second power supply end NCS is connected with the second power line is early △t1, at this time, the first N-type transistor N1 is turned on under the control of the bit line voltage, in the most adverse case of environment, the threshold voltage of the first N-type transistor N1 is less than the threshold voltage of the second N-type transistor N2, the pull-down speed of the bit line voltage is greater than the pull-down speed of the complementary bit line voltage, the voltage difference of the bit line BL and the complementary bit line BLB at the end time of the charge sharing stage is small, so that the sensing margin on the bit line BL and the complementary bit line BLB is small.

[0098] An embodiment for obtaining an optimal offset cancellation duration is provided below, in particular:

[0099] S201, generate a plurality of first control scenarios.

[0100] Each first control scenario includes a duration parameter of a pre-charge phase, a duration parameter of an offset cancellation phase, a duration parameter of a charge sharing phase, and a duration parameter of a sensing amplification phase.

[0101] The duration parameter of the pre-charge phase, the duration parameter of the offset cancellation phase, the duration parameter of the charge sharing phase, and the duration parameter of the sensing amplification phase are all related to the time when the first power supply end is connected with the corresponding voltage and the time when the second power supply end is connected with the corresponding voltage.

[0102] Here, the duration parameter of the offset cancellation phase and the duration parameter of the charge sharing phase are taken as examples for illustration. The third time when the first power supply end switches from being connected with the pre-charge voltage to being connected with the power supply voltage in the offset cancellation phase, or the fourth time when the second power supply end switches from being connected with the pre-charge voltage to being connected with the ground voltage in the offset cancellation phase, is taken as the starting time of the offset cancellation phase. It can also be any time between the third time and the fourth time as the starting time of the offset cancellation phase.

[0103] The fifth time when the first power supply end switches from being connected with the power supply voltage to being connected with the pre-charge voltage in the offset cancellation phase, or the sixth time when the second power supply end switches from being connected with the ground voltage to being connected with the pre-charge voltage in the offset cancellation phase, is taken as the termination time of the offset cancellation phase. It can also be any time between the fifth time and the sixth time as the termination time of the offset cancellation phase.

[0104] The termination time of the offset cancellation phase is the starting time of the charge sharing phase. The starting time of the offset cancellation phase is the end time of the pre-charge phase.

[0105] The first moment when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power supply voltage during the charge sharing phase is used as the end time of the charge sharing phase. The second moment when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase is used as the end time of the charge sharing phase. Alternatively, the end time of the charge sharing phase may be any moment between the first and second moments.

[0106] The end time of the charge sharing phase is the start time of the sensing amplification phase.

[0107] The duration parameters of the offset elimination phase in any two first control scenarios are different, the duration parameters of the pre-charging phase in any two first control scenarios are the same, the duration parameters of the charge sharing phase in any two first control scenarios are the same, and the duration parameters of the sensing amplification phase in any two first control scenarios are the same.

[0108] S202: Acquire a first sensing margin of the sense amplifier in a first control scenario, and use a duration parameter of an offset cancellation phase corresponding to a maximum sensing margin among a plurality of first sensing margins as an optimal offset cancellation duration.

[0109] Acquiring a first sensing margin of the sense amplifier in the first control scenario refers to obtaining the sensing margin by testing the sense amplifier using the duration parameters of each stage in the first control scenario as test conditions.

[0110] More specifically, a condition that is unfavorable for reading the first data is set, and the duration parameters of each stage under the first control scenario are used as test conditions to test the sense amplifier to obtain a second sensing margin SM2. A condition that is unfavorable for reading the second data is set, and the duration parameters of each stage under the first control scenario are used as test conditions to test the sense amplifier to obtain a third sensing margin SM3. The sum of the second sensing margin SM2 and the third sensing margin SM3 is calculated as the first sensing margin.

[0111] The top plate of the capacitor is connected to the transistor. The first data is data "1", that is, the voltage of the top plate of the capacitor in the storage unit is greater than the voltage of the bottom plate of the capacitor. The second data is data "0", that is, the voltage of the top plate of the capacitor in the storage unit is less than the voltage of the bottom plate of the capacitor.

[0112] In the technical solution, a sensing margin under conditions that are unfavorable for reading the first data and a sensing margin under conditions that are unfavorable for reading the second data are obtained, and the sum of the two sensing margins is used as the sensing margin under the first control scenario. Considering the situation where two types of data are stored in the target storage area, the obtained sensing margin is more accurate.

[0113] To obtain a second sensing margin in a condition that is not conducive to reading out first data in a certain first control scenario, a plurality of first scanning voltages greater than a lower plate reference voltage of the memory cell are generated.

[0114] For each first scanning voltage, the voltage of the memory cell in the target storage area is adjusted according to the first scanning voltage, and the length of the offset elimination stage of the sensitive amplifier is controlled to be the length parameter in the first control scenario. The data read error rate of the memory cell in the target storage area is counted, and a first mapping relationship between the plurality of first scanning voltages and the read error rate under each first scanning voltage is obtained.

[0115] More specifically, taking one first scanning voltage as an example, the lower plate voltage of all memory cells in the target storage area is adjusted to the first scanning voltage. The length parameters of each stage in the first control scenario are used as test conditions, the length of the offset elimination stage of the sensitive amplifier is controlled to be the length parameter of the offset elimination stage in the first control scenario, and the sensitive amplifier in the target storage area is tested. The data is read out from the bit line in the target storage area, the data read error rate of the memory cell in the target storage area is counted, and the first mapping relationship X1 between the plurality of first scanning voltages and the read error rate under each first scanning voltage is obtained. Figure 8 One point, for example, point 1. The abscissa of point 1 is the lower plate voltage, and the ordinate of point 1 is the data read error rate.

[0116] By performing the above operation on each first scanning voltage, points 2, 3, …, 6 can be obtained, that is, the first mapping relationship X1 between the plurality of first scanning voltages and the read error rate under each first scanning voltage is obtained.

[0117] The second sensing margin SM2 in the first control scenario is calculated according to the first mapping relationship. More specifically, the range of lower plate voltages corresponding to the read error rate less than the preset threshold is calculated according to the first mapping relationship, and the second sensing margin is calculated according to the range of lower plate voltages. The first lower plate voltage corresponding to the preset threshold in the first mapping relationship is obtained, the first difference between the first lower plate voltage and the lower plate reference voltage corresponding to the preset threshold is calculated, and the first difference is used as the range of lower plate voltages corresponding to the read error rate less than the preset threshold.

[0118] In the above technical solution, by scanning the lower plate voltage of the memory cell, the data read error rate is counted, the data read error rate under different voltages of the memory cell is obtained, and then the second mapping relationship is obtained. The second sensing margin is obtained according to the second mapping relationship.

[0119] To obtain a third sensing margin in a condition that is not conducive to reading out second data in a certain first control scenario, a plurality of second scanning voltages less than the lower plate voltage of the memory cell are generated.

[0120] For each second scanning voltage, the voltage of the storage cell in the target storage area is adjusted according to the second scanning voltage, and the duration of the offset elimination phase of the sensitive amplifier is controlled to be the duration parameter under the first control scenario. The data read error rate of the storage cell in the target storage area is counted to obtain a second mapping relationship between multiple second scanning voltages and the read error rate under each second scanning voltage.

[0121] The process of obtaining points 7 to 12 to obtain the second mapping relationship between multiple second scanning voltages and the read error rate at each second scanning voltage is similar to the process of obtaining the first mapping relationship, and will not be repeated here.

[0122] The third sensing margin SM3 is calculated based on the second mapping relationship. More specifically, the lower plate voltage range corresponding to when the read error rate is less than a preset threshold is calculated based on the second mapping relationship, and the third sensing margin is calculated based on the lower plate voltage range. A second lower plate voltage corresponding to the preset threshold in the second mapping relationship is obtained, a second difference between the lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the second difference is used as the lower plate voltage range corresponding to when the read error rate is less than the preset threshold.

[0123] In the above technical solution, by scanning the lower plate voltage of the memory cell and counting the statistical data read error rate, the data read error rate under the lower plate voltage of different memory cells is obtained, and then the second mapping relationship is obtained, and the third sensing margin is obtained according to the second mapping relationship.

[0124] After obtaining the first sensing margin of the sense amplifier in the first control scenario, the duration parameter of the offset elimination phase corresponding to the maximum sensing margin among the plurality of first sensing margins is used as the optimal offset elimination duration. Figure 9 As shown, first mapping relationships and second mapping relationships of the sense amplifier under three first control scenarios are obtained. The three first control scenarios are the first control scenario Ca11, the first control scenario Ca12, and the first control scenario Ca13. The offset cancellation phase duration parameter under the first control scenario Ca11 is tOC1, the offset cancellation phase duration parameter under the first control scenario Ca12 is tOC2, and the offset cancellation phase duration parameter under the first control scenario Ca13 is tOC3. More specifically, the first mapping relationship X1 and the second mapping relationship X2 of the first control scenario Ca11 are obtained, and the first sensing margin of the first control scenario Ca11 is calculated based on the first mapping relationship X1 and the second mapping relationship X2. Similarly, the first sensing margins of the first control scenario Ca11 to the first sensing margins of the first control scenario Ca13 are obtained. From the three first sensing margins, the offset cancellation phase duration parameter corresponding to the largest first sensing margin is selected as the optimal offset cancellation duration.

[0125] In the above technical solution, the first sensing margin under each first control scenario is obtained by testing the storage cells and sense amplifiers in the target storage area, and then the duration parameter of the offset elimination phase under the largest sensing margin is selected from multiple first sensing margins as the optimal offset elimination duration. The optimal offset elimination duration can reduce or eliminate the mismatch noise and other noise of most sense amplifiers in the memory, thereby improving the data readout accuracy.

[0126] The following provides a method for obtaining an optimal starting time for connecting the first power terminal to the power voltage and a time for connecting the second power terminal to the ground voltage.

[0127] S301: Generate multiple second control scenarios.

[0128] Each second control scenario includes a duration parameter of a pre-charging phase, a duration parameter of an offset cancellation phase, a duration parameter of a charge sharing phase, and a duration parameter of a sensing amplification phase.

[0129] The duration parameters of the four stages have been explained in detail in S201 and will not be repeated here.

[0130] The duration parameter of the offset elimination phase of each second control scenario is the optimal offset elimination duration, and the first moment in the same second control scenario is later than the second moment. The first moments in any two second control scenarios are different, or the second moments in any two second control scenarios are different.

[0131] The duration parameters of the pre-charging phases in any two second control scenarios are the same, and the starting moments of the charge sharing phases in any two second control scenarios are the same.

[0132] S302 : Obtain a sensing margin difference of the sense amplifier in a second control scenario, and take a first moment corresponding to a minimum sensing margin difference among multiple sensing margin differences as an optimal first moment, and obtain a second moment corresponding to the minimum sensing margin difference as an optimal second moment.

[0133] Acquiring a sensing margin difference of the sense amplifier under the second control scenario involves testing the sense amplifier in the target storage area using the duration parameters of each stage under the second control scenario as test conditions, while setting conditions that are unfavorable for reading the first data, to obtain a fourth sensing margin. Acquiring a sensing margin difference of the sense amplifier in the target storage area using the duration parameters of each stage under the second control scenario as test conditions, while setting conditions that are unfavorable for reading the second data, to obtain a fifth sensing margin. Calculating a difference between the fourth sensing margin SM4 and the fifth sensing margin SM5 is used as a sensing margin difference value.

[0134] More specifically, the sensing amplifier is tested to obtain a fourth sensing margin SM4 in a first data readout unfavorable setting condition under a second control scenario, with the time length parameters of the stages in the second control scenario as test conditions. The sensing amplifier is tested to obtain a fifth sensing margin SM5 in a second data readout unfavorable setting condition under the second control scenario, with the time length parameters of the stages in the second control scenario as test conditions. The difference between the fourth sensing margin SM4 and the fifth sensing margin SM5 is calculated as a sensing margin difference.

[0135] To obtain the fourth sensing margin SM4 in the first data readout unfavorable setting condition under a certain second control scenario, a plurality of third scan voltages greater than the lower plate reference voltage of the memory cell are generated.

[0136] For each third scan voltage, the lower plate voltage of the memory cell in the target storage area is adjusted according to the third scan voltage, the time length of the offset cancellation stage of the sensing amplifier is controlled to be the optimal offset cancellation time length, the time when the first power supply end switches from being connected to the pre-charge voltage to being connected to the power supply voltage in the charge sharing stage is the first time under the second control scenario, and the time when the second power supply end switches from being connected to the pre-charge voltage to being connected to the ground voltage in the charge sharing stage is the second time under the second control scenario. The sensing amplifier in the target storage area is tested, the data readout error rate of the memory cell in the target storage area is counted, and a third mapping relationship between the plurality of third scan voltages and the readout error rate under each third scan voltage is obtained.

[0137] The fourth sensing margin SM4 under the second control scenario is calculated according to the third mapping relationship. More specifically, the range of the lower plate voltage corresponding to the readout error rate less than the preset threshold is calculated according to the third mapping relationship, and the fourth sensing margin is calculated according to the range of the lower plate voltage. The third lower plate voltage corresponding to the preset threshold in the third mapping relationship is obtained, the third difference between the third lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the third difference is taken as the range of the lower plate voltage corresponding to the readout error rate less than the preset threshold.

[0138] In the above technical solution, the voltage of the memory cell is scanned, the data readout error rate is counted, the data readout error rate under different voltages of the memory cell is obtained, and then the third mapping relationship is obtained. The fourth sensing margin is obtained according to the third mapping relationship.

[0139] To obtain the fifth sensing margin in the second data readout unfavorable setting condition under a certain second control scenario, a plurality of fourth scan voltages less than the lower plate voltage of the memory cell are generated.

[0140] For each fourth scanning voltage, the voltage in the storage cell in the target storage area is adjusted according to the fourth scanning voltage, and the duration of the offset elimination phase of the sensitive amplifier is controlled to be the optimal offset elimination duration, the moment when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power supply voltage during the charge sharing phase is controlled to be the first moment under the second control scenario, and the moment when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase is controlled to be the second moment under the second control scenario, the sensitive amplifier in the target storage area is tested, the data read error rate of the storage cell in the target storage area is counted, and a fourth mapping relationship between multiple fourth scanning voltages and the read error rate under each fourth scanning voltage is obtained.

[0141] A fifth sensing margin SM5 is calculated based on the fourth mapping relationship. More specifically, an upper plate voltage range corresponding to when the read error rate is less than a preset threshold is calculated based on the fourth mapping relationship, and a fifth sensing margin is calculated based on the upper plate voltage range. A fourth lower plate voltage corresponding to the preset threshold in the fourth mapping relationship is obtained, a fourth difference between the lower plate voltage corresponding to the preset threshold and the lower plate reference voltage is calculated, and the fourth difference is used as the lower plate voltage range corresponding to when the read error rate is less than the preset threshold.

[0142] In the above technical solution, by scanning the voltage of the memory cell and counting the statistical read error rate, the data read error rate under different memory cell voltages is obtained, and then the fourth mapping relationship is obtained, and the fifth sensing margin is obtained according to the fourth mapping relationship.

[0143] After obtaining the sensing margin difference of the sense amplifier in the second control scenario, the first moment corresponding to the minimum sensing margin difference among the multiple sensing margin differences is taken as the optimal first moment, and the second moment corresponding to the minimum sensing margin difference is taken as the optimal second moment. Figure 10 As shown, the third mapping relationship X3 and the fourth mapping relationship X4 of the sense amplifier in five second control scenarios are obtained. The five second control scenarios are the first second control scenario Ca21, the second second control scenario Ca22, the third second control scenario Ca23, the fourth second control scenario Ca24 and the fifth second control scenario Ca25. The first moments and the second moments corresponding to the five second control scenarios are shown in Table 1.

[0144] Table 1

[0145] Ca21 Ca22 Ca23 Ca24 Ca25 first time t11 t12 t13 t11 t11 second time t21 t21 t21 t22 t23

[0146] More specifically, the third mapping relationship X3 and the fourth mapping relationship X4 of the first second control scenario Ca21 are obtained, and the sensing margin difference of the first second control scenario Ca11 is calculated according to the third mapping relationship X3 and the fourth mapping relationship X4. In this way, the sensing margin difference of the first second control scenario Ca21 to the sensing margin difference of the fifth second control scenario Ca25 are obtained. The second time of the first second control scenario Ca21 to the third second control scenario Ca23 is the same, and the first time is different. The first time corresponding to the minimum sensing margin difference among the three sensing margin differences of the first second control scenario Ca21 to the third second control scenario Ca23 is selected as the best first time. The first time of the first second control scenario Ca21, the fourth second control scenario Ca24 and the fifth second control scenario Ca25 is the same, and the second time is different. The second time corresponding to the minimum sensing margin difference among the three sensing margin differences of the first second control scenario Ca21, the fourth second control scenario Ca24 to the fifth second control scenario Ca25 is selected as the best second time.

[0147] In the above technical solution, by testing the memory cells and the sense amplifier in the target storage area, the sensing margin difference under each second control scenario is obtained, and the first time under the minimum sensing margin difference is selected as the best first time or the second time as the best second time from the multiple sensing margin differences. The best first time is used as the time when the first power supply end switches from turning on the pre-charge voltage to turning on the power supply voltage in the charge sharing stage, and the best second time is the time when the second power supply end switches from turning on the pre-charge voltage to turning on the ground voltage in the charge sharing stage, which effectively eliminates the data preference of the sense amplifier.

[0148] Some embodiments of the present disclosure provide a control method of a sense amplifier, specifically comprising:

[0149] S201, in the pre-charge stage, the first power supply end and the second power supply end are controlled to turn on the pre-charge voltage, and the sense amplifier is controlled to drive the voltage on the bit line and the complementary bit line to the pre-charge voltage.

[0150] S202, in the offset elimination stage, the first power supply end is controlled to turn on the power supply voltage, the second power supply end is controlled to turn on the ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line. The length of the offset elimination stage is the best offset elimination length, and the sensing margin SM of the sense amplifier is the maximum value under the best offset elimination length.

[0151] S203, in the charge sharing stage, the first power supply end and the second power supply end are controlled to turn on the pre-charge voltage, the memory cell and the bit line are controlled to share the charge, and the charge sharing voltage is formed on the bit line and the complementary bit line.

[0152] S204, in the sensing amplification stage, the first power terminal is connected to the power voltage, the second power terminal is connected to the ground voltage, the time when the first power terminal is connected to the power voltage is the optimal first time, the time when the second power terminal is connected to the ground voltage is the optimal second time, and the sense amplifier amplifies the voltage difference on the bit line and the complementary bit line.

[0153] In the above technical solution, the sense amplifier includes a pre-charge stage, an offset cancellation stage, a charge sharing stage, and a sensing amplification stage. The length of the offset cancellation stage is the optimal offset cancellation length. Under the optimal offset cancellation length, the sensing margin of the sense amplifier is the maximum value, and most of the mismatch noise and other noise of the sense amplifier can be eliminated. In the sensing amplification stage, the time when the first power terminal is connected to the power voltage is the optimal first time, and the time when the second power terminal is connected to the ground voltage is the optimal second time. The sensing margin on the bit line and the complementary bit line can be adjusted, and the data preference degree of the sense amplifier is minimized.

[0154] Some embodiments of the present disclosure provide a memory, comprising: a memory cell, a sense amplifier, and a controller, the memory cell is connected to a bit line, the sense amplifier is connected to the bit line, and the controller is connected to the sense amplifier, and the controller is used to implement the method involved in the above embodiments.

[0155] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including modifications and equivalents of the present disclosure. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0156] It should be understood that the present disclosure is not limited to the precise construction that has been described and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A control method for a sense amplifier, characterized in that: The sense amplifier is connected to a bit line and a complementary bit line, the bit line is connected to a memory cell, the sense amplifier includes a first power supply terminal and a second power supply terminal, and the method includes: In the precharge phase, the first power supply terminal and the second power supply terminal are controlled to be connected to a precharge voltage, and the sense amplifier is controlled to drive the voltage on the bit line and the complementary bit line to the precharge voltage; During an offset cancellation phase, the first power supply terminal is controlled to be connected to a power supply voltage, the second power supply terminal is controlled to be connected to a ground voltage, and the sense amplifier is controlled to form a compensation voltage on the bit line and the complementary bit line. The duration of the offset cancellation phase is an optimal offset cancellation duration, and a sensing margin of the sense amplifier is maximized under the optimal offset cancellation duration. In the charge sharing stage, the first power supply terminal and the second power supply terminal are controlled to be connected to the precharge voltage, the memory cell and the bit line perform charge sharing, and a charge sharing voltage is formed on the bit line and the complementary bit line; In the sensing and amplification phase, the first power supply terminal is controlled to be connected to the power supply voltage, and the second power supply terminal is controlled to be connected to the ground voltage, wherein the first power supply terminal is connected to the power supply voltage later than the second power supply terminal is connected to the ground voltage, and the sense amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line; The control method further includes: generating a plurality of first control scenarios, wherein each of the first control scenarios includes a duration parameter of the offset elimination phase, and the duration parameters of the offset elimination phase in any two of the first control scenarios are different; Acquiring a first sensing margin of the sense amplifier in each of the first control scenarios; using a duration parameter of an offset cancellation phase corresponding to a maximum sensing margin among the plurality of first sensing margins as an optimal offset cancellation duration; Acquiring a first sensing margin of the sense amplifier in the first control scenario specifically includes: acquiring a second sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition unfavorable for reading the first data is set; acquiring a third sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition unfavorable for reading the second data is set; A sum of the second sensing margin and the third sensing margin is calculated as the first sensing margin.

2. The control method according to claim 1, characterized in that: Acquiring a second sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition unfavorable for reading the first data is set specifically includes: generating a plurality of first scanning voltages greater than a reference voltage of a bottom plate of a memory cell; For each first scanning voltage, adjusting the bottom plate voltage of the storage cells in the target storage area according to the first scanning voltage, controlling the duration of the offset cancellation phase of the sense amplifier to be the duration parameter within the first control scenario, and calculating the read error rate of the data of the storage cells in the target storage area to obtain a first mapping relationship between a plurality of the first scanning voltages and the read error rate at each of the first scanning voltages; The second sensing margin is obtained by calculation according to the first mapping relationship.

3. The control method according to claim 1, characterized in that: Obtaining a third sensing margin of the sense amplifier in the target storage area under the first control scenario when a condition is set that is unfavorable for reading the second data specifically includes: generating a plurality of second scanning voltages less than a reference voltage of a bottom plate of a memory cell; For each second scanning voltage, adjusting the bottom plate voltage of the storage cells in the target storage area according to the second scanning voltage, controlling the duration of the offset cancellation phase of the sense amplifier to be the duration parameter in the first control scenario, and calculating the read error rate of the data of the storage cells in the target storage area to obtain a second mapping relationship between multiple second scanning voltages and the read error rate at each second scanning voltage; The third sensing margin is obtained by calculation according to the second mapping relationship.

4. The control method according to claim 1, wherein: The control method further includes: Generate multiple second control scenarios, wherein each second control scenario includes a duration parameter of the offset cancellation phase, a first moment when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power supply voltage during the charge sharing phase, and a second moment when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase; the duration parameter of the offset cancellation phase of each second control scenario is the optimal offset cancellation duration, the first moment in the same second control scenario is later than the second moment, the first moments in any two second control scenarios are different, or the second moments in any two second control scenarios are different; Obtaining a sensing margin difference value of the sense amplifier in each second control scenario; using a first moment corresponding to a minimum sensing margin difference value among the plurality of sensing margin differences as an optimal first moment for the first power supply terminal to switch from being connected to the pre-charge voltage to being connected to the power voltage during the charge sharing phase; and using a second moment corresponding to the minimum sensing margin difference value as an optimal second moment for the second power supply terminal to switch from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase; Accordingly, controlling the first power supply terminal to be connected to the power supply voltage, controlling the second power supply terminal to be connected to the ground voltage, and controlling the sense amplifier to amplify the voltage difference between the bit line and the complementary bit line specifically includes: The first power supply terminal is controlled to switch from being connected to the pre-charge voltage to being connected to the power supply voltage during the charge sharing phase as the optimal first moment, the second power supply terminal is controlled to switch from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase as the optimal second moment, and the sensitive amplifier is controlled to amplify the voltage difference between the bit line and the complementary bit line.

5. The control method according to claim 4, characterized in that: Obtaining a fourth sensing margin of the sense amplifier in each second control scenario specifically includes: acquiring a fourth sensing margin of the sense amplifier in the target storage region under the second control scenario when a condition unfavorable for reading the first data is set; acquiring a fifth sensing margin of the sense amplifier in the target storage area under the second control scenario when a condition unfavorable for reading the second data is set; A difference between the fourth sensing margin and the fifth sensing margin is calculated as the sensing margin difference value.

6. The control method according to claim 5, characterized in that: Acquiring a fourth sensing margin of the sense amplifier in the target storage area under the second control scenario when a condition unfavorable for reading the first data is set specifically includes: generating a plurality of third scanning voltages greater than a reference voltage of a bottom plate of a memory cell; For each of the third scanning voltages, adjusting the bottom plate voltage of the storage cells in the target storage area according to the third scanning voltage, controlling the duration of the offset cancellation phase of the sense amplifier to be an optimal offset cancellation duration, controlling the time when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power voltage during the charge sharing phase to be a first time within the second control scenario, and controlling the time when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase to be a second time within the second control scenario, and calculating the read error rate of the data of the storage cells in the target storage area to obtain a third mapping relationship between the plurality of the third scanning voltages and the read error rate at each of the third scanning voltages; The fourth sensing margin is obtained by calculation according to the third mapping relationship.

7. The control method according to claim 5, characterized in that: Acquiring a fifth sensing margin of the sense amplifier in the target storage area under the second control scenario when a condition unfavorable for reading the second data is set specifically includes: generating a plurality of fourth scanning voltages that are less than a reference voltage of a bottom plate of a memory cell; For each of the fourth scanning voltages, adjusting the lower plate voltage of the storage cells in the target storage area according to the fourth scanning voltage, controlling the duration of the offset cancellation phase of the sense amplifier to be an optimal offset cancellation duration, controlling the moment when the first power supply terminal switches from being connected to the pre-charge voltage to being connected to the power voltage during the charge sharing phase to be a first moment within the second control scenario, and controlling the moment when the second power supply terminal switches from being connected to the pre-charge voltage to being connected to the ground voltage during the charge sharing phase to be a second moment within the second control scenario, calculating data read error rates of the storage cells in the target storage area, and obtaining a fourth mapping relationship between a plurality of the fourth scanning voltages and the read error rate at each of the fourth scanning voltages; The fifth sensing margin is obtained by calculation according to the fourth mapping relationship.

8. A memory, characterized in that: include: A memory cell, a sense amplifier, and a controller, wherein the memory cell is connected to the bit line, the sense amplifier is connected to the bit line, the controller is connected to the sense amplifier, and the controller is used to implement the method according to any one of claims 1 to 7.

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