Word line decoding circuit, word line driving circuit and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly to a word line decoding circuit, a word line driving circuit and a memory. The word line decoding circuit comprises: a decoder, comprising: n input terminals and 2 n The decoder is configured to decode the row address signals input from the n input terminals and select 2 n At least one of the output terminals corresponding to the output terminals outputs an initial driving signal; n 2 first control structures, each first control structure is configured to generate and output a corresponding word line enable signal based on the first indication signal, the second indication signal and the corresponding initial drive signal; n A second control structure is provided, each second control structure being configured to generate and output a corresponding word line drive signal based on a corresponding word line enable signal, a first indication signal, and a corresponding initial drive signal, so as to reduce the number of word lines that need to be refreshed during the execution of a single refresh command of the memory, thereby reducing the power burden of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a word line decoding circuit, a word line driving circuit, and a memory. Background Art

[0002] Semiconductor memory devices for storing data can be divided into volatile memory devices and non-volatile memory devices. Among volatile memory devices, dynamic random access memory (DRAM) stores data by charging or discharging capacitors in storage cells, and the stored data is lost when power is cut off. Non-volatile memory devices can retain stored data even when power is cut off.

[0003] Volatile memory devices are widely used as main memories of various devices, whereas non-volatile memory devices are widely used to store program codes and / or data in various electronic devices such as computers, mobile devices, and the like.

[0004] In volatile memory devices, the cell charge stored in a memory cell can be lost due to leakage current. Furthermore, when the word line connecting the capacitor in the memory cell frequently switches between an activated state and a precharged state, for example when the word line is frequently accessed, the memory cells connected to the word line adjacent to the frequently accessed word line may be affected and lose their stored charge, potentially leading to data loss. However, the charge stored in the memory cell can be retained by recharging it before data is lost due to charge leakage. This recharging of the cell charge is called a refresh operation, and the refresh operation can be performed repeatedly before a significant amount of cell charge is lost.

[0005] For DRAM, during the execution of a refresh command, many memory blocks need to be refreshed. Especially in individual refresh modes or refresh configurations, a large number of word lines need to be refreshed, which will bring a huge burden to the memory power supply. Summary of the Invention

[0006] The embodiments of the present disclosure provide a word line decoding circuit, a word line driving circuit, and a memory. By reasonably shielding the refresh process of word line addresses that have not been activated during the refresh period, the number of word lines that need to be refreshed during the execution of a single refresh command of the memory is reduced, thereby reducing the power burden of the memory.

[0007] An embodiment of the present disclosure provides a word line decoding circuit, comprising: a decoder, comprising: n input terminals and 2 n output terminals, n is a positive integer; the decoder is configured to decode the row address signals input from the n input terminals and select 2 nAt least one of the output terminals corresponding to the output terminals outputs an initial driving signal; n The first control structure, 2 n The first control structure and the decoder's 2 n The output terminals are connected in a one-to-one correspondence, and the first control structure is further used to receive a first indication signal and a second indication signal; wherein the first indication signal indicates whether the memory to which the word line decoding circuit belongs is in a row address selection period, and the second indication signal indicates whether the memory is in a refresh operation period; each first control structure is configured to generate and output a corresponding word line enable signal based on the first indication signal, the second indication signal and the corresponding initial drive signal; n A second control structure, respectively with 2 n The first control structure and the decoder's 2 n The output terminals are connected in a one-to-one correspondence, and each second control structure is configured to generate and output a corresponding word line drive signal based on the corresponding word line enable signal, the first indication signal and the corresponding initial drive signal.

[0008] For the above-mentioned word line decoding circuit, the word line address activated in the activation operation phase is more prone to data loss problems, so the corresponding word line address is normally output in the refresh phase to refresh the data of the activated word line address; while the word line address that was not activated in all activation operation phases before the current refresh operation is not prone to data loss problems, and refreshing the word line address can be regarded as a waste of memory refresh resources. Therefore, the activation of this part of the word line address is shielded in the refresh phase, thereby omitting the refresh process of this part of the word line address, so as to reduce the number of word lines that the memory needs to refresh during the execution of a single refresh command, that is, reduce the power consumption of the memory refresh device, thereby reducing the power burden of the memory.

[0009] Optionally, the first control structure is configured to generate and latch a corresponding word line enable signal at an active level based on the initial driving signal when the memory is currently in a row address selection period and not in a refresh operation period.

[0010] Optionally, the first control structure is further configured to receive a reset signal, and generate and latch a word line enable signal at an invalid level based on the reset signal; wherein the reset signal is a power-on reset signal.

[0011] Optionally, the first control structure includes: a first AND logic circuit, a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal; a first latch, configured as an RS latch based on a NOR gate, wherein the set terminal is connected to the first AND logic circuit, the reset terminal is used to receive a reset signal, and the output terminal is used to output a word line enable signal.

[0012] Optionally, the first control structure includes: a NAND logic circuit, a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal; a second inverter, an input terminal of which is used to receive a reset signal; and a second latch, configured as an SR latch based on a NAND gate, wherein the set terminal is connected to the NAND logic circuit, the reset terminal is connected to the output terminal of the second inverter, and the output terminal is used to output a word line enable signal.

[0013] Optionally, the first control structure includes: a second AND logic circuit, a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal; a trigger, an input terminal and a clock terminal are grounded, a set terminal is connected to the output terminal of the second AND logic circuit, a reset terminal is used to receive a reset signal, and an output terminal is used to output a word line enable signal.

[0014] Optionally, the second control structure is configured to output the corresponding initial driving signal currently output by the decoder as the corresponding word line driving signal based on the word line enable signal at the valid level during the period when the memory is currently in the row address selection period.

[0015] Optionally, the second control structure includes: a third AND logic circuit, a first input terminal for receiving a corresponding word line enable signal, a second input terminal for receiving a first indication signal, a third input terminal for receiving a corresponding initial drive signal, and an output terminal for outputting a corresponding word line drive signal.

[0016] Optionally, the second control structure is further configured to receive a mode selection signal, and when the mode selection signal is at a first level and the memory to which it belongs is currently in a row address selection period, based on a word line enable signal at a valid level, output the corresponding initial drive signal currently output by the decoder as a corresponding word line drive signal, and when the mode selection signal is at a second level, directly output the corresponding initial drive signal currently output by the decoder as a corresponding word line drive signal.

[0017] Optionally, the second control structure includes: a fourth AND logic circuit, wherein the first input terminal is used to receive the corresponding word line enable signal, the second input terminal is used to receive the first indication signal, the third input terminal is used to receive the corresponding initial drive signal, and the output terminal is used to output the corresponding first drive signal; a fifth AND logic circuit, wherein the first input terminal is used to receive the first indication signal, the second input terminal is used to receive the corresponding initial drive signal, and the output terminal is used to output the corresponding second drive signal; and a selection circuit, respectively connected to the fourth AND logic circuit and the fifth AND logic circuit, wherein the first input terminal of the selection circuit is used to receive the first drive signal, the second input terminal is used to receive the second drive signal, and the selection terminal is used to receive a mode selection signal, and the selection circuit is configured to select one of the first drive signal and the second drive signal as the word line drive signal output based on the mode selection signal.

[0018] Optionally, the word line decoding circuit further includes: a drive control circuit configured to configure the mode selection signal based on the mode control signal.

[0019] Optionally, the decoder is further configured to receive a second indication signal and a refresh operation mode signal, and when the second indication signal indicates that the memory to which it belongs is not in a refresh operation period, the decoder decodes each row address signal and selects only 2 n One of the output terminals corresponds to an output terminal outputting an initial driving signal; and during the refresh operation period when the second indication signal indicates that the memory to which it belongs is in operation, after decoding each row address signal according to the refresh operation mode signal, selecting 2 n One or more corresponding output terminals among the output terminals output an initial driving signal.

[0020] Another embodiment of the present disclosure further provides a word line driving circuit, comprising: a word line decoding circuit provided by at least one of the above embodiments; a word line driving signal output by the word line decoding circuit is used to turn on at least one of a selection word line, a main word line and a sub-word line; a row address signal comprises: at least one of a first row address signal corresponding to the selection word line, a second row address signal corresponding to the main word line and a third row address signal corresponding to the sub-word line; wherein, if the word line driving signal is used to turn on the selection word line, the word line decoding circuit is arranged in the selection word line decoding circuit, and is used to decode the first row address signal to output the selection word line driving signal for turning on the selection word line; if the word line driving signal is used to turn on the main word line, the word line decoding circuit is arranged in the main word line decoding circuit, and is used to decode the second row address signal to output the main word line driving signal for turning on the main word line; if the word line driving signal is used to turn on the sub-word line, the word line decoding circuit is arranged in the sub-word line decoding circuit, and is used to decode the third row address signal to output the sub-word line driving signal for turning on the sub-word line.

[0021] Optionally, the row address signal includes: a first row address signal, a second row address signal and a third row address signal; the word line driving circuit includes: a first word line decoding circuit, a second word line decoding circuit and a third word line decoding circuit; the first word line decoding circuit is arranged in the selection word line decoding circuit, for decoding the first row address signal to output a selection word line driving signal for turning on the selection word line; the second word line decoding circuit is arranged in the main word line decoding circuit, for decoding the second row address signal to output a main word line driving signal for turning on the main word line; the third word line decoding circuit is arranged in the sub-word line decoding circuit, for decoding the third row address signal to output a sub-word line driving signal for turning on the sub-word line.

[0022] Another embodiment of the present disclosure also provides a memory, including the word line decoding circuit provided by the above embodiment, which reduces the number of word lines that need to be refreshed during the execution of a single refresh command of the memory by reasonably shielding the refresh process of the word line addresses that have not been activated during the refresh period, thereby reducing the power burden of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic structural diagram of a word line decoding circuit provided in one embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram illustrating the timing principle of a word line decoding circuit provided in one embodiment of the present disclosure;

[0026] Figure 3 A timing diagram of a partial refresh principle of a memory provided by an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of a first control structure based on an RS latch provided in one embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram of a first control structure based on an SR latch according to an embodiment of the present disclosure;

[0029] Figure 6A schematic diagram of a first control structure based on an SR latch according to an embodiment of the present disclosure;

[0030] Figure 7 A schematic diagram of a first control structure based on an RS latch provided in one embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of a first control structure based on triggers provided in an embodiment of the present disclosure;

[0032] Figure 9 A schematic diagram of another second control structure provided in an embodiment of the present disclosure;

[0033] Figure 10 A structural diagram of a configuration method of a word line driving circuit provided by another embodiment of the present disclosure;

[0034] Figure 11 A structural diagram of another configuration of a word line driver circuit provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] As known from the background art, for DRAM, during the execution of a refresh command, many memory blocks need to be refreshed. Especially in individual refresh modes or refresh configurations, a large number of word lines need to be refreshed, which will bring a great burden to the memory power supply.

[0036] An embodiment of the present disclosure provides a word line decoding circuit that reduces the number of word lines that need to be refreshed during the execution of a single refresh command of the memory by reasonably shielding the refresh process of word line addresses that have not been activated during the refresh period, thereby reducing the power burden of the memory.

[0037] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0038] Figure 1 This is a schematic diagram of the structure of the word line decoding circuit provided in this embodiment. Figure 2 A schematic diagram of the timing principle of the word line decoding circuit provided in this embodiment is shown in FIG. Figure 3 A timing diagram of the partial refresh principle of the memory provided in this embodiment, Figure 4 This is a schematic diagram of a first control structure based on an RS latch provided in this embodiment. Figure 5 This is a schematic diagram of a first control structure based on an SR latch provided in this embodiment. Figure 6 This is a schematic diagram of a first control structure based on an SR latch provided in this embodiment. Figure 7 This is a schematic diagram of a first control structure based on an RS latch provided in this embodiment. Figure 8 This is a schematic diagram of the structure of the first control structure based on triggers provided in this embodiment. Figure 9 This is a schematic diagram of another second control structure provided by this embodiment. The word line decoding circuit provided by this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0039] For a storage system, the memory receives and identifies the row address signal provided by the storage controller to generate a corresponding word line drive signal. The word line drive signal is used to turn on the word line indicated by the corresponding row address signal (the "row" in the memory). The recognition of the row address signal in the memory is based on the word line decoding circuit in the memory.

[0040] refer to Figure 1 , a word line decoding circuit, comprising:

[0041] Decoder 101 includes n input terminals and 2 n output terminals, n is a positive integer; the decoder 101 is configured to receive the row address signal K inputted from the n input terminals. <n-1:0>Decode and select 2 according to the decoding result n At least one corresponding output terminal among the output terminals outputs the initial driving signal Q0.

[0042] Regarding the number of initial drive signals Q0 output by the decoder 101, specifically, the working premise of the decoder 101 in the memory is that the memory needs to be selected, and the memory needs to perform row selection during the activation operation in the non-refresh operation phase and the refresh operation in the refresh operation phase, that is, the decoder 101 works during the activation operation.

[0043] refer to Figure 3 When the memory is in the non-refresh operation phase, the memory opens an activation window based on each activation operation command ACT CMD, and in each activation window, the decoder 101 opens an activation window based on a row address signal K <n-1:0>The decoder outputs a valid initial drive signal Q0, for example Figure 3 As shown, the memory opens three activation windows based on three activation operation commands ACT CMD in the non-refresh operation phase. The three activation windows are used to open row address RA1, row address RA4, and row address RA7, respectively. Assuming that the memory receives a activation commands in the non-refresh operation phase, the memory needs to activate a row addresses accordingly.

[0044] Continue to refer Figure 3 In the refresh operation phase, the memory opens a refresh window based on a refresh operation command REF CMD, and multiple refresh operations can be performed within the refresh window, corresponding to Figure 3 In each tRAS window, the decoder 101 is based on at least one row address signal K <n-1:0>Decode and output at least one valid initial driving signal Q0 in sequence, for example Figure 3 As shown, the memory refreshes addresses RA0 and RA1 based on two tRAS windows in the refresh operation phase. Assuming that the memory has b tRAS windows in the refresh operation phase, and each tRAS window is used to refresh c row addresses, the memory needs to activate b*c row addresses accordingly.

[0045] Specifically, the number of initial drive signals Q0 output by the decoder 101 in each tRAS window is based on the refresh mode setting of the memory. For example, when the memory is configured as 1SWL Enable, that is, the memory is enabled for one word line in each tRAS window during the refresh operation, that is, the decoder 101 is based on one row address signal K <n-1:0>The decoder outputs a valid initial drive signal Q0; when the memory is configured as 2SWL Enable, that is, the memory is used to enable two word lines in each tRAS window during the refresh operation, that is, the decoder 101 is based on two row address signals K <n-1:0>Sequentially decode and output two valid initial drive signals Q0; when the memory is configured as 4SWL Enable, that is, the memory is in each tRAS window during the refresh operation, the decoder 101 is used to enable the four word lines, that is, the decoder 101 is based on the four row address signals K <n-1:0>Decode and output 4 valid initial drive signals Q0 in sequence; it can be seen that when the memory is configured as 2 m SWL Enable, that is, the memory is refreshed in each tRAS window during the operation, the decoder 101 is used for 2 m word lines are enabled, that is, the decoder 101 is based on 2 m row address signal K <n-1:0>Decode and output 2 in sequence m A valid initial drive signal Q0 is provided. For the refresh mode setting of the memory, one of the following table 1 can be selected in the specific setting:

[0046]

[0047]

[0048] Refer to Table 1, which shows how to set the tRC interval time under different refresh modes and word line times of a single refresh of the memory.

[0049] Regarding the working principle of the decoder 101, specifically, the number n of the input terminals of the decoder 101 corresponds to the row address signal K provided by the memory controller. <n-1:0>The number of bits, that is, the row address signal K <n-1:0>bit number; in one example, if the row address signal K is a 3-bit signal, that is, the row address signal K<2:0>, then the decoder 101 is correspondingly set to 3 input terminals; if the row address signal K is an 8-bit signal, that is, the row address signal K<7:0>, then the decoder 101 is correspondingly set to 8 input terminals; wherein, each input terminal of the decoder 101 receives the row address signal K <n-1:0>Each bit of .

[0050] The following describes the specific principles of the decoder 101 based on the 3-bit row address signal K<2:0> as an example. It should be noted that the description based on exemplary parameters does not constitute a limitation of this embodiment. Those skilled in the art can, based on the following description, analogize the 3-bit row address signal K<2:0> to the n-bit row address signal K<2:0>. <n-1:0>The working principle of the time decoder 101 is shown below.

[0051] In one example, for the initial driving signal Q0, it is assumed that the active level of the initial driving signal Q0 is “1” and the inactive level of the initial driving signal Q0 is “0”.

[0052] Specifically, the 3-bit row address signal K<2:0> includes 2 3 = 8 combinations, namely "000, 001, 010, 011, 100, 101, 110 and 111", where each combination corresponds to an output terminal of the decoder 101. For example, when K<2:0> = "000", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 1. <0> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="001", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 2. <1> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="010", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 3. <2> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="011", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 4. <3> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="100", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 5. <4> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="101", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 6. <5> is a valid level, and the initial drive signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="110", the decoder 101 outputs the initial drive signal Q0 based on the output terminal 7. <6> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; when K<2:0>="111", the decoder 101 outputs the initial driving signal Q0 based on the output terminal 8. <7> is a valid level, and the initial driving signal outputted by the other output terminals of the decoder 101 is an invalid level; Based on the above description, it can be seen that when the decoder 101 receives a row address signal K <n-1:0>After that, the decoder 101 has 2 n There is only one row address signal K in the output terminal <n-1:0>The output terminal outputs a valid initial driving signal Q0.

[0053] Continue to refer Figure 1 , the word line decoding circuit also includes: 2 n A first control structure 110, 2 n The first control structure 110 and the decoder 101 are n The output terminals are connected one-to-one, that is, each first control structure 110 is connected to an output terminal of the decoder 101; in an example, the eight output terminals (output terminal 1 to output terminal 8) of the decoder 101 are connected to eight first control structures 110 respectively.

[0054] The first control structure 110 is also used to receive a first indication signal and a second indication signal; wherein the first indication signal indicates whether the memory to which the word line decoding circuit belongs is in a row address selection period, and the second indication signal indicates whether the memory is in a refresh operation period. Each first control structure 110 is configured to generate and output a corresponding word line enable signal based on the first indication signal, the second indication signal and the corresponding initial drive signal.

[0055] For the first indication signal, when the first indication signal is at a valid level, the memory to which the word line decoding circuit belongs is in a row address selection period; when the first indication signal is at an invalid level, the memory to which the word line decoding circuit belongs is not in a row address selection period; in the subsequent description of this embodiment, an example is given in which the valid level of the first indication signal is "1" and the invalid level is "0" to facilitate those skilled in the art to understand the specific implementation method of this solution, and does not constitute a limitation of this embodiment. In other embodiments, the valid level of the first indication signal can also be set to "0" and the invalid level to "1".

[0056] For the second indication signal, when the second indication signal is at a valid level, the memory to which the word line decoding circuit belongs is in a refresh operation period; when the second indication signal is at an invalid level, the memory to which the word line decoding circuit belongs is not in a refresh operation period; in the subsequent description of this embodiment, an example is given in which the valid level of the second indication signal is "0" and the invalid level is "1" to facilitate those skilled in the art to understand the specific implementation method of this solution, and does not constitute a limitation of this embodiment. In other embodiments, the valid level of the second indication signal can also be set to "1" and the invalid level to "0".

[0057] Based on the above description, it can be seen that for the memory, the corresponding row address needs to be turned on during both the activation operation and the refresh operation of the memory, that is, when the memory is in the activation operation or the refresh operation, the memory is also in the row address selection period. Specifically, when the memory is in the activation operation, the first indication signal = "1" and the second indication signal = "1", when the memory is in the refresh operation, the first indication signal = "1" and the second indication signal = "0", and when the memory is in the inactivation operation and in the non-refresh operation, the first indication signal = "0" and the second indication signal = "1".

[0058] It should be noted that, in the circuit analysis of the memory, when a signal is at an invalid level, it is usually regarded as the absence of the signal in the circuit, and when a signal is at a valid level, it is usually regarded as the presence of the signal in the circuit.

[0059] The first control structure 110 can be considered to generate and latch a corresponding word line enable signal Q1 at an active level based on the initial drive signal Q0 when the memory is currently in a row address selection period and not in a refresh operation period. It can also be understood that when the memory is in an activation operation period, the first control structure 110 generates and latches a corresponding word line enable signal Q1 at an active level based on the initial drive signal Q0, wherein the active level of the word line enable signal Q1 is "1" and the inactive level of the word line enable signal Q1 is "0."

[0060] Specifically, during the activation operation (not during the refresh operation), in each activation window, the first control structure 110 generates and latches the corresponding word line enable signal Q1 at the valid level based on an initial drive signal Q0. If the memory receives q activation commands during the activation operation (not during the refresh operation), each activation command generates 1 activation window, that is, a total of q activation windows are included during the activation operation, then multiple first control structures 110 latch a total of q word line enable signals Q1 corresponding to the q activation windows, where if there are identical signals among the q word line enable signals Q1, the number of latched word line enable signals Q1 is q-the number of identical word line enable signals Q1.

[0061] Continue to refer Figure 1 , the word line decoding circuit also includes: 2 n A second control structure 120, respectively with 2 n The first control structure 110 and the decoder 101 are n The output terminals are connected one-to-one, that is, each second control structure 120 is connected to an output terminal of the decoder 101 and a first control structure 110; in an example, the eight output terminals (output terminal 1 to output terminal 8) of the decoder 101 and the eight output terminals (output terminal 1 to output terminal 8) of the decoder 101 are connected to eight first control structures 110 and eight second control structures 120.

[0062] Each second control structure 120 is configured to generate and output a corresponding word line driving signal based on a corresponding word line enable signal, a first indication signal, and a corresponding initial driving signal.

[0063] The second control structure 120 can be considered as outputting the corresponding initial drive signal Q0 currently output by the decoder 101 as the corresponding word line drive signal Q based on the word line enable signal Q1 at the valid level during the period when the memory to which it belongs is currently in the row address selection period. For the word line drive signal Q, the valid level of the word line drive signal Q is "1", and the invalid level of the word line drive signal Q is "0". The word line drive signal Q is used to turn on the word line indicated by the row address signal (the "row" in the memory).

[0064] For the word line decoding circuit provided in this embodiment, its working principle is as follows: Figure 2 , Figure 2 It is a schematic diagram of the principle of the word line decoding circuit in an activation window during the activation operation and the refresh operation, that is, a schematic diagram of the principle of the word line decoding circuit working based on a row address signal during the activation operation and the refresh operation.

[0065] refer to Figure 2 , combined with the above discussion, it can be seen that in the activation operation stage, that is, the Active stage, the first indication signal = "1", the second indication signal = "1", and in the refresh operation stage, that is, the Refresh stage, the first indication signal = "1", the second indication signal = "0".

[0066] In one example, it is assumed that in the Active phase and the Refresh phase, the output terminal 1 of the decoder 101 has an output, that is, in the Active phase and the Refresh phase, the initial driving signal Q0 <0> = "1". Specifically, in the Active phase, the initial drive signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "1", the first control module 110 generates and latches the word line enable signal Q1 at the active level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> = "1", the memory can conduct the corresponding word line address; in the Refresh phase, the initial drive signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "0", because the second indication signal turns off the first control module 110, the first control module 110 remains in the Active phase to generate and latch the word line enable signal Q1 at the valid level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> ="1", the memory can turn on the corresponding word line address.

[0067] In one example, it is assumed that there is an output at the output terminal 1 of the decoder 101 in the Active phase, that is, the initial driving signal Q0 in the Active phase <0> = "1", and the output terminal 1 of the decoder 101 does not have an output in the Refresh phase, that is, the initial driving signal Q0 in the Refresh phase <0> = "0". Specifically, in the Active phase, the initial driving signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "1", the first control module 110 generates and latches the word line enable signal Q1 at the active level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> = "1", the memory can conduct the corresponding word line address; in the Refresh phase, the initial drive signal Q0 <0> = "0", the first indication signal = "1", the second indication signal = "0", since the second indication signal turns off the first control module 110, the first control module 110 remains in the Active phase to generate and latch the word line enable signal Q1 at the valid level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> = "0", the memory does not conduct the corresponding word line address, and the memory does not need to conduct the corresponding word line address.

[0068] In one example, it is assumed that there is no output at the output terminal 1 of the decoder 101 in the Active phase, that is, the initial driving signal Q0 in the Active phase is <0> = "0", and the output terminal 1 of the decoder 101 has an output in the Refresh phase, that is, the initial driving signal Q0 in the Refresh phase <0> = "1". Specifically, in the Active phase, the initial drive signal Q0 <0> = "0", the first indication signal = "1", the second indication signal = "1", because the initial driving signal turns off the first control module 110, the first control module 110 has no valid output, the word line enable signal Q1 <0> ="0", word line enable signal Q1 <0> = "0" turns off the second control module 120, and the second control module 120 has no valid output, that is, the word line drive signal Q <0> = "0", the memory does not conduct the corresponding word line address, and the memory does not need to conduct the corresponding word line address; in the Refresh phase, the initial drive signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "0", because the second indication signal turns off the first control module 110, the first control module 110 remains in its original state, and the word line enable signal Q1 <0> ="0", word line enable signal Q1 <0> = "0" turns off the second control module 120, and the second control module 120 has no valid output, that is, the word line drive signal Q <0> = "0", the memory does not conduct the corresponding word line address, thereby shielding the initial drive signal Q0 as a valid signal <0> .

[0069] Based on the above description of the working principle of other activation windows, those skilled in the art can <0> Replace the description of Q0 <1> ~Q0<2 n -1>. Specifically, refer to Figure 3 In one example, assuming that the memory is in the Active phase, the decoder 101 generates Q0 <1> (used to turn on address RA1), Q0 <4> (used to turn on address RA4) and Q0 <7> (used to conduct address RA7) is at a valid level. In the Refresh phase, the Q0 generated by the decoder 101 <0> (used to turn on address RA0) and Q0 <1> (used to conduct address RA1) is a valid level. Based on the above discussion, it can be seen that in the Active phase, the memory can normally turn on Q0 <1> 、Q0 <4> and Q0 <7> The corresponding word line addresses are RA1, RA4 and RA7, and in the Refresh phase, the memory can open Q0 normally <1> The corresponding word line address RA1, the memory cannot open Q0 <0> The corresponding word line address RA0 is output, thereby avoiding the refresh of the word line address that has not been activated in all activation operation stages before the current refresh operation during the refresh operation stage. In summary, for the word line decoding circuit provided by this embodiment, the word line address activated in the activation operation stage is more likely to have data loss problems, so the corresponding word line address is normally output in the refresh stage to refresh the data of the activated word line address; while the word line address that has not been activated in all activation operation stages before the current refresh operation is not prone to data loss problems, and refreshing this word line address can be regarded as a waste of memory refresh resources. Therefore, the activation of this part of the word line address is shielded in the refresh stage, thereby omitting the refresh process of this part of the word line address, so as to reduce the number of word lines that the memory needs to refresh during the execution of a single refresh command, that is, reduce the power consumption of the memory refresh device, thereby reducing the power burden of the memory.

[0070] In some embodiments, the decoder 101 is further configured to receive a second indication signal and a refresh operation mode signal. When the second indication signal indicates that the memory to which it belongs is not in a refresh operation period, the decoder 101 receives a second indication signal and a refresh operation mode signal. <n-1:0>After decoding, only 2 are selected n One of the output terminals outputs the initial driving signal Q0, and during the period when the second indication signal indicates that the memory is in the refresh operation, the refresh operation mode signal is used to generate a signal for each row address signal K. <n-1:0>After decoding, select 2 n The decoder 101 controls the refresh operation mode signal to achieve the number of initial drive signals Q0 output in each activation window, so that the word line decoding circuit is applicable to memories in various scenarios.

[0071] refer to Figures 4 to 8 In some embodiments, the first control structure 110 is further configured to receive a reset signal and, based on the reset signal, generate and latch a wordline enable signal Q1 at an inactive level. The reset signal is a power-on reset signal. Specifically, during power-up, the first control structure 110 resets the output wordline enable signal Q1 to an inactive level, i.e., wordline enable signal Q1 = "0," based on the power-on reset signal.

[0072] refer to Figure 4 In some embodiments, the first control structure 110 includes a first AND logic circuit 201, having a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal Q0. A first latch 202 is configured as an RS latch based on a NOR gate, wherein a set terminal is connected to the first AND logic circuit 201, a reset terminal is used to receive a reset signal, and an output terminal Q is used to output a word line enable signal Q1.

[0073] It should be noted that if the effective level of the first indication signal, the second indication signal or the initial driving signal Q0 is adjusted, an inverter may be connected during the corresponding input process of the first AND logic circuit 201 .

[0074] Specifically, the set end of the RS latch serves as the "1" end. When the first indication signal = "1", the second indication signal = "1" and the initial drive signal Q0 = "1", the output end Q of the RS latch outputs and latches "1", that is, the valid word line enable signal Q1; when the reset signal is "1", the output end Q of the RS latch outputs and latches "0", that is, the invalid word line enable signal Q1, and when the reset signal is provided, the first indication signal, the second indication signal and the initial drive signal Q0 will not be 1 at the same time, and the output of the RS latch remains unchanged.

[0075] refer to Figure 5 In some embodiments, the first control structure 110 includes: a first AND logic circuit 201, having a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal Q0. A first latch 202 is configured as an SR latch based on a NOR gate, wherein a set terminal is connected to the first AND logic circuit 201, a reset terminal is used to receive a reset signal, an inverting output terminal Q- is connected to an input terminal of a first inverter 203, and an output terminal of the first inverter 203 is used to output a word line enable signal Q1.

[0076] It should be noted that if the effective level of the first indication signal, the second indication signal or the initial driving signal Q0 is adjusted, an inverter may be connected during the corresponding input process of the first AND logic circuit 201 .

[0077] refer to Figure 6 In some embodiments, the first control structure 110 includes: a NAND logic circuit 204, a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal Q0; an input terminal of a second inverter 206 for receiving a reset signal; and a second latch 205, configured as an SR latch based on a NAND gate, wherein a set terminal is connected to the NAND logic circuit 204, a reset terminal is connected to an output terminal of the second inverter 206, and a Q output terminal is used to output a word line enable signal Q1.

[0078] It should be noted that if the effective level of the first indication signal, the second indication signal or the initial driving signal Q0 is adjusted, an inverter may be connected during the corresponding input process of the NAND logic circuit 204 .

[0079] Specifically, the set end of the SR latch serves as the "0" end. When the first indication signal = "1", the second indication signal = "1" and the initial drive signal Q0 = "1", the output end Q of the SR latch outputs and latches "1", that is, the valid word line enable signal Q1; when the reset signal is "1", the output end Q of the SR latch outputs and latches "0", that is, the invalid word line enable signal Q1, and when the reset signal is provided, the first indication signal, the second indication signal and the initial drive signal Q0 will not be 1 at the same time, and the output of the SR latch remains unchanged.

[0080] refer to Figure 7 In some embodiments, the first control structure 110 includes: a NAND logic circuit 204, a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal Q0; an input terminal of a second inverter 206 for receiving a reset signal; and a second latch 205, configured as an RS latch based on a NAND gate, wherein a set terminal is connected to the NAND logic circuit 204, a reset terminal is connected to an output terminal of the second inverter 206, an inverting output terminal Q- is connected to an input terminal of a third inverter 207, and an output terminal of the third inverter 207 is used to output a word line enable signal Q1.

[0081] It should be noted that if the effective level of the first indication signal, the second indication signal or the initial driving signal Q0 is adjusted, an inverter may be connected during the corresponding input process of the NAND logic circuit 204 .

[0082] refer to Figure 8 In some embodiments, the first control structure 110 includes: a second AND logic circuit 301, a first input terminal for receiving a first indication signal, a second input terminal for receiving a second indication signal, and a third input terminal for receiving an initial drive signal Q0; a trigger 302, an input terminal D and a clock terminal CLK are grounded, a set terminal SET is connected to the output terminal of the second AND logic circuit 301, a reset terminal is used to receive a reset signal, and an output terminal Q is used to output a word line enable signal Q1.

[0083] Specifically, the input terminal D and the clock terminal CLK of the flip-flop 302 are grounded, so that the output data of the flip-flop 302 changes only with the set terminal SET. When the first indication signal = "1", the second indication signal = "1", and the initial drive signal Q0 = "1", the set terminal SET of the flip-flop 302 has a valid input, and the output data is set to "1", that is, a valid word line enable signal Q1; when any one of the first indication signal, the second indication signal, and the initial drive signal Q0 is 0, the set terminal SET of the flip-flop 302 has no valid input, and the output data remains unchanged. When the flip-flop 302 receives a valid enable signal, the output data of the flip-flop 302 is reset to "0", that is, an invalid word line enable signal Q1.

[0084] refer to Figures 4 to 8 The second control structure 120 includes: a third AND logic circuit 303, a first input terminal for receiving the corresponding word line enable signal Q1, a second input terminal for receiving the first indication signal, a third input terminal for receiving the corresponding initial drive signal Q0, and an output terminal for outputting the corresponding word line drive signal Q1.

[0085] Specifically, when the first indication signal = "1", the initial drive signal Q0 = "1" and the word line enable signal Q1 = "1", the output of the third AND logic circuit 303 is "1", that is, a valid word line drive signal Q. That is, it can be regarded as that when the first indication signal and the initial drive signal Q0 are valid signals, the level of the word line drive signal Q output by the third AND logic circuit 303 is equal to the level of the initial drive signal Q0 input to the third AND logic circuit 303; and the word line enable signal Q1 acts as a switching signal, which is used to whether to shield the output of the third AND logic circuit 303.

[0086] In some embodiments, the second control structure 120 is further configured to receive a mode selection signal, and when the mode selection signal is at a first level and the corresponding memory is currently in a row address selection period, based on the word line enable signal Q1 at a valid level, output the corresponding initial drive signal Q0 currently output by the decoder 101 as the corresponding word line drive signal Q, and when the mode selection signal is at a second level, directly output the corresponding initial drive signal Q0 currently output by the decoder 101 as the corresponding word line drive signal Q.

[0087] Specifically, when the mode selection signal is at the first level, the second control structure 120 selects the latching function of the first control structure 110, and based on the latching result of the first control structure 110, masks the refresh operation of the word line address that is not activated in the activation operation phase during the refresh phase; when the mode selection signal is at the second level, the latching function of the first control structure 110 is avoided, and the second control structure 120 directly outputs based on the output result of the decoder 101, and the memory performs a normal refresh operation; the second control module 120 is controlled by the mode selection signal to select different output modes to achieve the selective activation of the corresponding word line, thereby achieving the refresh retention of some word lines and the refresh restriction of some word lines. On the premise of ensuring the important functions of the memory, the number of some word lines that the memory needs to refresh during the execution of a single refresh command is reduced, that is, the power consumption of the memory refresh device is reduced, thereby reducing the power burden of the memory.

[0088] In some embodiments, reference Figure 9 The second control structure 120 includes: a fourth AND logic circuit 403, a first input terminal for receiving the corresponding word line enable signal Q1, a second input terminal for receiving the first indication signal, a third input terminal for receiving the corresponding initial drive signal Q0, and an output terminal for outputting the corresponding first drive signal; a fifth AND logic circuit 404, a first input terminal for receiving the first indication signal, a second input terminal for receiving the corresponding initial drive signal Q0, and an output terminal for outputting the corresponding second drive signal; a selection circuit 304, connected to the fourth AND logic circuit 403 and the fifth AND logic circuit 404, respectively, a first input terminal for receiving the first drive signal, a second input terminal for receiving the second drive signal, and a selection terminal for receiving a mode selection signal, the selection circuit 304 being configured to select one of the first drive signal and the second drive signal as the word line drive signal Q to be output based on the mode selection signal.

[0089] In some embodiments, the word line decoding circuit further includes: a driving control circuit 405 configured to configure a mode selection signal based on a mode control signal, thereby selecting an operating mode of each output terminal of the decoder 101 in the word line decoding circuit based on the mode control signal.

[0090] It should be noted that in the description of the above embodiment, the active level of the initial drive signal Q0, the word line enable signal Q1, and the word line drive signal Q is "1" and the inactive level is "0" is used as an example for description. This is only for those skilled in the art to understand the specific implementation of this solution and does not constitute a limitation of this embodiment. In other embodiments, the active level of the initial drive signal Q0, the word line enable signal Q1, and the word line drive signal Q can be "0" and the inactive level can be "1". In some embodiments, the active levels of the initial drive signal Q0, the word line enable signal Q1, and the word line drive signal Q can be different. In addition, in a specific application, if the active levels of the signals are set based on different methods, in actual applications, inverters can be connected to the corresponding positions of the word line decoding circuit to achieve the same effect as the above embodiment.

[0091] For the word line decoding circuit provided in this embodiment, the word line address activated in the activation operation phase is more likely to have data loss problems, so the corresponding word line address is normally output in the refresh phase to refresh the data of the activated word line address; while the word line address that was not activated in all activation operation phases before the current refresh operation is not prone to data loss problems, and refreshing the word line address can be regarded as a waste of memory refresh resources. Therefore, the activation of this part of the word line address is shielded in the refresh phase, thereby omitting the refresh process of this part of the word line address, so as to reduce the number of word lines that the memory needs to refresh during the execution of a single refresh command, that is, reduce the power consumption of the memory refresh device, thereby reducing the power burden of the memory.

[0092] It should be noted that the features disclosed in the word line decoding circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new word line decoding circuit embodiments.

[0093] Another embodiment of the present disclosure provides a word line driving circuit, including the word line decoding circuit provided in the above embodiment. By reasonably shielding the refresh process of word line addresses that have not been activated during the refresh period, the number of word lines that need to be refreshed during the execution of a single refresh command of the memory is reduced, thereby reducing the power burden of the memory.

[0094] Figure 10 A structural diagram of a setting method of a word line driving circuit provided in this embodiment is shown. Figure 11 This is a structural diagram of another configuration of a word line driver circuit provided in this embodiment. The word line driver circuit provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0095] Specifically, the word line driving circuit selects the word line in the memory, and the word line selection of the memory involves multiple levels, such as: selecting the word line level, the main word line level and the sub-word line level, wherein different levels correspond to different word line decoding circuits, that is, different levels correspond to different decoders.

[0096] For the word line driving circuit provided in this embodiment, refer to Figure 10 The word line driving circuit includes: at least one word line decoding circuit provided by the above-mentioned embodiment, and the word line driving signal output by the word line decoding circuit is used to turn on at least one of the selection word line, the main word line and the sub-word line, and the row address signal includes: at least one of: a first row address signal corresponding to the selection word line, a second row address signal corresponding to the main word line and a third row address signal corresponding to the sub-word line.

[0097] The first row address signal is used to turn on the corresponding selection word line, the second row address signal is used to turn on the corresponding main word line, and the third row address signal is used to turn on the corresponding sub-word line.

[0098] Among them, if the word line drive signal is used to turn on the selection word line, the word line decoding circuit is set in the selection word line decoding circuit, and is used to decode the first row address signal to output the selection word line drive signal for turning on the selection word line; if the word line drive signal is used to turn on the main word line, the word line decoding circuit is set in the main word line decoding circuit, and is used to decode the second row address signal to output the main word line drive signal for turning on the main word line; if the word line drive signal is used to turn on the sub-word line, the word line decoding circuit is set in the sub-word line decoding circuit, and is used to decode the third row address signal to output the sub-word line drive signal for turning on the sub-word line.

[0099] In specific applications, the word line driving circuit can be based on the word line decoding circuit provided in the above embodiment to only be used for the refresh optimization of the selected word line, or based on the word line decoding circuit provided in the above embodiment to only be used for the refresh optimization of the main word line, or based on the word line decoding circuit provided in the above embodiment to only be used for the refresh optimization of the sub-word line, and similarly, the word line decoding circuit provided in two of the above embodiments can be used to optimize the refresh of the selected word line and the main word line, or based on the word line decoding circuit provided in two of the above embodiments can be used to optimize the refresh of the selected word line and the sub-word line, and the word line decoding circuit provided in two of the above embodiments can be used to optimize the refresh of the main word line and the sub-word line, and similarly, the word line decoding circuit provided in three of the above embodiments can be used to simultaneously optimize the refresh of the selected word line, the main word line and the sub-word line.

[0100] For the refresh optimization method of the selected word line, main word line and sub word line, refer to Figure 11 The row address signal includes: a first row address signal, a second row address signal and a third row address signal, and the word line driving circuit includes: a first word line decoding circuit 10, a second word line decoding circuit 20 and a third word line decoding circuit 30; the first word line decoding circuit 10 is arranged in the selection word line decoding circuit, and is used to decode the first row address signal to output a selection word line driving signal for turning on the selection word line; the second word line decoding circuit 20 is arranged in the main word line decoding circuit, and is used to decode the second row address signal to output a main word line driving signal for turning on the main word line; the third word line decoding circuit 30 is arranged in the sub-word line decoding circuit, and is used to decode the third row address signal to output a sub-word line driving signal for turning on the sub-word line.

[0101] Those skilled in the art can Figure 11 The setting mode is based on the refresh optimization of the selected word line, the main word line and the sub-word line required in the specific application scenario, and the corresponding first word line decoding circuit 10, the second word line decoding circuit 20 and the third word line decoding circuit 30 are set.

[0102] Another embodiment of the present disclosure provides a memory, including the word line decoding circuit provided by the above embodiment, which reduces the number of word lines that need to be refreshed during the execution of a single refresh command of the memory by reasonably shielding the refresh process of the word line addresses that have not been activated during the refresh period, thereby reducing the power burden of the memory.

[0103] refer to Figure 2 In the activation operation phase, ie, the Active phase, the first indication signal = "1", the second indication signal = "1", in the refresh operation phase, ie, the Refresh phase, the first indication signal = "1", the second indication signal = "0".

[0104] In one example, it is assumed that in the Active phase and the Refresh phase, the output terminal 1 of the decoder 101 has an output, that is, in the Active phase and the Refresh phase, the initial driving signal Q0 <0> = "1". Specifically, in the Active phase, the initial drive signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "1", the first control module 110 generates and latches the word line enable signal Q1 at the active level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> = "1", the memory can conduct the corresponding word line address; in the Refresh phase, the initial drive signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "0", because the second indication signal turns off the first control module 110, the first control module 110 remains in the Active phase to generate and latch the word line enable signal Q1 at the valid level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> ="1", the memory can turn on the corresponding word line address.

[0105] In one example, it is assumed that there is an output at the output terminal 1 of the decoder 101 in the Active phase, that is, the initial driving signal Q0 in the Active phase <0> = "1", and the output terminal 1 of the decoder 101 does not have an output in the Refresh phase, that is, the initial driving signal Q0 in the Refresh phase <0> = "0". Specifically, in the Active phase, the initial driving signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "1", the first control module 110 generates and latches the word line enable signal Q1 at the active level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> = "1", the memory can conduct the corresponding word line address; in the Refresh phase, the initial drive signal Q0 <0> = "0", the first indication signal = "1", the second indication signal = "0", since the second indication signal turns off the first control module 110, the first control module 110 remains in the Active phase to generate and latch the word line enable signal Q1 at the valid level <0> , at this time the word line enable signal Q1 <0> = "1", the second control module 120 sets the initial driving signal Q0 <0> Output is word line drive signal Q <0> , that is, the word line drive signal Q <0> = "0", the memory does not conduct the corresponding word line address, and the memory does not need to conduct the corresponding word line address.

[0106] In one example, it is assumed that there is no output at the output terminal 1 of the decoder 101 in the Active phase, that is, the initial driving signal Q0 in the Active phase is <0> = "0", and the output terminal 1 of the decoder 101 has an output in the Refresh phase, that is, the initial driving signal Q0 in the Refresh phase <0> = "1". Specifically, in the Active phase, the initial drive signal Q0 <0> = "0", the first indication signal = "1", the second indication signal = "1", because the initial driving signal turns off the first control module 110, the first control module 110 has no valid output, the word line enable signal Q1 <0> ="0", word line enable signal Q1 <0> = "0" turns off the second control module 120, and the second control module 120 has no valid output, that is, the word line drive signal Q <0> = "0", the memory does not conduct the corresponding word line address, and the memory does not need to conduct the corresponding word line address; in the Refresh phase, the initial drive signal Q0 <0> = "1", the first indication signal = "1", the second indication signal = "0", because the second indication signal turns off the first control module 110, the first control module 110 remains in its original state, and the word line enable signal Q1 <0> ="0", word line enable signal Q1 <0> = "0" turns off the second control module 120, and the second control module 120 has no valid output, that is, the word line drive signal Q <0> = "0", the memory does not conduct the corresponding word line address, thereby shielding the initial drive signal Q0 as a valid signal <0> .

[0107] refer to Figure 3 In one example, assuming that the memory is in the Active phase, the decoder 101 generates Q0 <1> (used to turn on address RA1), Q0 <4> (used to turn on address RA4) and Q0 <7> (used to conduct address RA7) is at a valid level. In the Refresh phase, the Q0 generated by the decoder 101 <0> (used to turn on address RA0) and Q0 <1> (used to conduct address RA1) is a valid level. Based on the above discussion, it can be seen that in the Active phase, the memory can normally turn on Q0 <1> 、Q0 <4> and Q0 <7> The corresponding word line addresses are RA1, RA4 and RA7, and in the Refresh phase, the memory can open Q0 normally <1> The corresponding word line address RA1, the memory cannot open Q0 <0> The corresponding word line address RA0 is used to avoid refreshing the word line addresses that have not been activated in all activation operation stages before the current refresh operation during the refresh operation stage. In summary, for the memory provided by this embodiment, the word line addresses activated in the activation operation stage are more likely to have data loss problems, so the corresponding word line addresses are normally output in the refresh stage to refresh the data of the activated word line addresses; while the word line addresses that have not been activated in all activation operation stages before the current refresh operation are not prone to data loss problems, and refreshing these word line addresses can be regarded as a waste of memory refresh resources. Therefore, the activation of these word line addresses is shielded in the refresh stage, thereby omitting the refresh process for these word line addresses, so as to reduce the number of word lines that the memory needs to refresh during the execution of a single refresh command, that is, to reduce the power consumption of the memory refresh device, thereby reducing the power burden of the memory.

[0108] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0109] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A word line decoding circuit, characterized in that: include: Decoder, including: n input terminals and 2 n output terminals, n is a positive integer; The decoder is configured to decode the row address signals input from the n input terminals and select the two n At least one of the output terminals corresponding to the output terminals outputs an initial driving signal; 2 n A first control structure, the 2 n A first control structure and the two n The output terminals are connected in a one-to-one correspondence, and the first control structure is further used to receive a first indication signal and a second indication signal; wherein the first indication signal indicates whether the memory to which the word line decoding circuit belongs is in a row address selection period, and the second indication signal indicates whether the memory is in a refresh operation period; each of the first control structures is configured to generate and output a corresponding word line enable signal based on the first indication signal, the second indication signal and the corresponding initial drive signal; 2 n A second control structure, respectively with 2 n 2 of the first control structure and the decoder n The output terminals are connected in a one-to-one correspondence, and each of the second control structures is configured to generate and output a corresponding word line drive signal based on the corresponding word line enable signal, the first indication signal and the corresponding initial drive signal.

2. The word line decoding circuit according to claim 1, wherein: The first control structure is configured to generate and latch a corresponding word line enable signal at an active level based on the initial driving signal when the memory is currently in a row address strobe period and not in a refresh operation period.

3. The word line decoding circuit according to claim 2, wherein: The first control structure is further configured to receive a reset signal, and generate and latch the word line enable signal at an inactive level based on the reset signal; wherein the reset signal is a power-on reset signal.

4. The word line decoding circuit according to claim 3, wherein: The first control structure includes: a first AND logic circuit, wherein the first input terminal is used to receive the first indication signal, the second input terminal is used to receive the second indication signal, and the third input terminal is used to receive the initial driving signal; The first latch is configured as an RS latch based on a NOR gate, wherein the set terminal is connected to the first AND logic circuit, the reset terminal is used to receive the reset signal, and the output terminal is used to output the word line enable signal.

5. The word line decoding circuit according to claim 3, wherein: The first control structure includes: a NAND logic circuit, wherein the first input terminal is used to receive the first indication signal, the second input terminal is used to receive the second indication signal, and the third input terminal is used to receive the initial driving signal; a second inverter, an input end of which is used to receive the reset signal; The second latch is configured as an SR latch based on a NAND gate, wherein the set end is connected to the NAND logic circuit, the reset end is connected to the output end of the second inverter, and the output end is used to output the word line enable signal.

6. The word line decoding circuit according to claim 3, wherein: The first control structure includes: a second AND logic circuit, wherein the first input terminal is used to receive the first indication signal, the second input terminal is used to receive the second indication signal, and the third input terminal is used to receive the initial driving signal; The trigger has an input terminal and a clock terminal grounded, a set terminal connected to the output terminal of the second AND logic circuit, a reset terminal for receiving the reset signal, and an output terminal for outputting the word line enable signal.

7. The word line decoding circuit according to any one of claims 1 to 6, wherein: The second control structure is configured to, when the memory is currently in a row address selection period, output the corresponding initial driving signal currently output by the decoder as the corresponding word line driving signal based on the word line enable signal at an effective level.

8. The word line decoding circuit according to claim 7, wherein: The second control structure includes: a third AND logic circuit, a first input end for receiving the corresponding word line enable signal, a second input end for receiving the first indication signal, a third input end for receiving the corresponding initial drive signal, and an output end for outputting the corresponding word line drive signal.

9. The word line decoding circuit according to any one of claims 1 to 6, characterized in that: The second control structure is further configured to receive a mode selection signal, and when the mode selection signal is at a first level and the memory to which it belongs is currently in a row address selection period, based on the word line enable signal at a valid level, output the corresponding initial drive signal currently output by the decoder as the corresponding word line drive signal, and when the mode selection signal is at a second level, directly output the corresponding initial drive signal currently output by the decoder as the corresponding word line drive signal.

10. The word line decoding circuit according to claim 9, wherein: The second control structure includes: a fourth AND logic circuit, wherein the first input terminal is used to receive the corresponding word line enable signal, the second input terminal is used to receive the first indication signal, the third input terminal is used to receive the corresponding initial drive signal, and the output terminal is used to output the corresponding first drive signal; a fifth AND logic circuit, wherein the first input terminal is used to receive the first indication signal, the second input terminal is used to receive the corresponding initial driving signal, and the output terminal is used to output the corresponding second driving signal; A selection circuit is connected to the fourth AND logic circuit and the fifth AND logic circuit respectively, wherein a first input terminal of the selection circuit is used to receive the first drive signal, a second input terminal is used to receive the second drive signal, and a selection terminal is used to receive a mode selection signal. The selection circuit is configured to select one of the first drive signal and the second drive signal as the word line drive signal output based on the mode selection signal.

11. The word line decoding circuit according to claim 10, wherein: Also includes: The drive control circuit is configured to configure the mode selection signal based on a mode control signal.

12. The word line decoding circuit according to claim 1, wherein: The decoder is further configured to receive the second indication signal and the refresh operation mode signal, and when the second indication signal indicates that the memory to which it belongs is not in the refresh operation period, the decoder decodes each of the row address signals and selects only the 2 n A corresponding one of the output terminals outputs the initial driving signal; When the second indication signal indicates that the memory is in a refresh operation period, each row address signal is decoded according to the refresh operation mode signal, and the 2 n One or more corresponding output terminals among the output terminals output the initial driving signal.

13. A word line driving circuit, characterized in that: include: At least one word line decoding circuit according to any one of claims 1 to 12; The word line driving signal output by the word line decoding circuit is used to turn on at least one of a selected word line, a main word line, and a sub-word line; the row address signal includes: at least one of a first row address signal corresponding to the selected word line, a second row address signal corresponding to the main word line, and a third row address signal corresponding to the sub-word line; Among them, if the word line drive signal is used to turn on the selection word line, the word line decoding circuit is set in the selection word line decoding circuit, and is used to decode the first row address signal to output the selection word line drive signal for turning on the selection word line; if the word line drive signal is used to turn on the main word line, the word line decoding circuit is set in the main word line decoding circuit, and is used to decode the second row address signal to output the main word line drive signal for turning on the main word line; if the word line drive signal is used to turn on the sub-word line, the word line decoding circuit is set in the sub-word line decoding circuit, and is used to decode the third row address signal to output the sub-word line drive signal for turning on the sub-word line.

14. The word line driving circuit according to claim 13, wherein: The row address signal includes: the first row address signal, the second row address signal and the third row address signal; The word line driving circuit includes: a first word line decoding circuit, a second word line decoding circuit and a third word line decoding circuit; The first word line decoding circuit is provided in the selection word line decoding circuit, and is used for decoding the first row address signal to output a selection word line driving signal for turning on the selection word line; The second word line decoding circuit is arranged in the main word line decoding circuit, and is used to decode the second row address signal to output a main word line drive signal for turning on the main word line; the third word line decoding circuit is arranged in the sub-word line decoding circuit, and is used to decode the third row address signal to output a sub-word line drive signal for turning on the sub-word line.

15. A memory, characterized in that: The invention comprises the word line decoding circuit according to any one of claims 1 to 12.

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