Decoder, decoding method, memory controller, and memory system

Abstract

The embodiment of the invention provides a decoder. The decoder comprises a check node updating circuit and a variable node updating circuit, in the first time period, check node messages corresponding to different layers of the check matrix are obtained in different levels of first updating units in the a levels of first updating units; in the first time period, obtaining corresponding intermediate calculation values in different levels of second updating units in the a levels of second updating units; in a second time period after the first time period, all levels of second updating units except the ath level of second updating unit receive check node messages corresponding to all layers of the check matrix in sequence, and the received check node messages and the intermediate calculation value of the next level of second updating unit are calculated in sequence; variable node messages corresponding to different columns of the check matrix are obtained in different levels of second updating units in the a levels of second updating units.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a decoder, a decoding method, a memory controller, a memory system, and an electronic device. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices used by people, such as solid state drives (SSDs). SSDs have been widely used in military, automotive, industrial, medical and aviation fields due to their fast read and write speed, vibration resistance, low power consumption, no noise, low heat and light weight.

[0003] However, there are still many problems to be solved in the memory system in the related art. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a decoder is provided, wherein a check matrix corresponding to a frame of codewords includes a*a sub-matrices, multiple sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, and multiple sub-matrices located in the same column constitute a column of the check matrix, wherein a is a positive integer greater than 0, and the decoder includes:

[0005] A check node update circuit includes a first update unit of level a, and the first update units of each level are connected in sequence; a variable node update circuit is connected to the check node update circuit, and the variable node update circuit includes a second update unit of level a, and the second update units of each level are connected in sequence; wherein,

[0006] In the first time period, the check node update circuit is configured as follows: the first update units at all levels except the first-level first update unit sequentially receive the variable node messages corresponding to the columns of the check matrix, and sequentially calculate the received variable node messages with the messages in the first update unit at the previous level, and obtain the check node messages corresponding to different layers of the check matrix in the first update units at different levels in the a-level first update unit;

[0007] In the first time period, the variable node update circuit is configured as follows: the a-th level second update unit sequentially receives the variable node message corresponding to each column of the check matrix, and the second update units of each level except the a-th level second update unit sequentially receive the message of the next level second update unit and calculate, and obtain the corresponding intermediate calculation value in the different levels of the a-th level second update unit;

[0008] In a second time period after the first time period, the variable node update circuit is configured as follows: the second update units at each level except the a-th level second update unit sequentially receive the check node messages corresponding to each layer of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values ​​of the next-level second update unit, and obtain the variable node messages corresponding to different columns of the check matrix in the different levels of second update units in the a-th level second update unit.

[0009] In some embodiments, each level of the first update unit includes a first delay unit, the first level to the a-1 level first update units also include a first shift unit, and the second level to the a level first update units also include a comparison unit; the first delay unit is used to delay the output of the message updated in the first update unit of each level, the first shift unit is used to shift the message updated in the first update unit, and the comparison unit is used to compare the shifted message in the first update unit of the previous level with the received variable node message to obtain a minimum value.

[0010] In some embodiments, the check node update circuit is configured to:

[0011] During the second time period, the comparison units in the second to a-th stage first update units are turned off.

[0012] In some embodiments, each level of the second update unit includes a second delay unit, and the first to a-1 level second update units also include an adding unit and a second shift unit; the second delay unit is used to delay the output of the message updated in each level of the second update unit, the second shift unit is used to shift the message updated in the second update unit, and the adding unit is used to add the message in the second update unit of the next level to the received variable node message.

[0013] In some embodiments, the shift value of the first shift unit in the n-th level first update unit is equal to the shift value of the second shift unit in the n-th level second update unit; n is less than or equal to a.

[0014] In some embodiments, the delay length of the first delay unit of each level of the first update unit is h1, the delay length of the second delay unit of each level of the second update unit is h2, and h1=h2.

[0015] In some embodiments, the decoder further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal is connected to the a-th level first update unit, the second input terminal is used to receive an all-zero message, and the first output terminal is connected to the first level to the a-1-th level second update unit;

[0016] The first selector is configured to: in a first time period, select a message at the second input end as an output message at the first output end; and in a second time period, select a message at the first input end as an output message at the first output end.

[0017] In some embodiments, the decoder further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th-level second update unit;

[0018] The second selector is configured to: in a first time period, select a message at the third input terminal as an output message at the second output terminal; and in a second time period, select a message at the fourth input terminal as an output message at the second output terminal.

[0019] In some embodiments, the decoder further comprises a parity check circuit, wherein the parity check circuit is connected to the variable node update circuit;

[0020] The parity check circuit is configured to: receive the variable node message of the variable node update circuit, and substitute the received variable node message into the check equation for verification; if all the check equations are satisfied, the decoding is determined to be successful; if all the check equations are not satisfied, the decoding is determined to be failed, and the next iteration is required to update the check node message and the variable node message until the decoding is successful or the maximum number of iterations is reached.

[0021] In some embodiments, the decoder further comprises:

[0022] A third selector, the third selector comprising a fifth input terminal, a sixth input terminal, and a third output terminal, the fifth input terminal being used to receive the initial channel message corresponding to each column of the check matrix, the sixth input terminal being connected to the first-stage second update unit, and the third output terminal being connected to the second-stage to the a-th-stage first update units;

[0023] The third selector is configured to: in a first time period during a first iteration, select a message at the fifth input terminal as an output message at the third output terminal;

[0024] In the first time period of the next iteration process, the message of the sixth input terminal is selected as the output message of the third output terminal.

[0025] According to a second aspect of an embodiment of the present disclosure, a memory controller is provided, comprising a decoder as described in any one of the above embodiments.

[0026] According to a third aspect of an embodiment of the present disclosure, a memory system is provided, comprising the memory controller described in the above embodiment and a memory device coupled to the memory controller.

[0027] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, comprising the decoder described in any one of the above embodiments, and a memory device coupled to the decoder.

[0028] According to a fifth aspect of an embodiment of the present disclosure, a decoding method is provided. In a decoding process of a frame of codewords including a*a sub-matrices of a check matrix, a plurality of sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices located in the same column constitute a column of the check matrix. The method comprises:

[0029] In the first time period, the first update units at all levels except the first-level first update unit sequentially receive the variable node messages corresponding to the columns of the check matrix, and sequentially calculate the received variable node messages with the messages in the first update unit at the previous level, and obtain the check node messages corresponding to different layers of the check matrix in the first update units at different levels in the a-level first update unit;

[0030] In the first time period, the a-th level second update unit sequentially receives the variable node message corresponding to each column of the check matrix, and the second update units of each level except the a-th level second update unit sequentially receive the message of the next level second update unit and calculate, and obtain the corresponding intermediate calculation value in the different levels of the a-th level second update unit;

[0031] In the second time period, the second update units at all levels except the a-th level second update unit receive the check node messages corresponding to the layers of the check matrix in turn, and calculate the received check node messages with the intermediate calculation values ​​of the next-level second update unit in turn, and obtain the variable node messages corresponding to different columns of the check matrix in the different levels of second update units in the a-th level second update unit.

[0032] In some embodiments, each first update unit of each level includes a first delay unit, the first update units of the first level to the a-1th level also include a first shift unit, and the first update units of the second level to the ath level also include a comparison unit;

[0033] The method includes: the first delay unit delays the output of the message updated in each level of the first update unit, the first shift unit shifts the message updated in the first update unit, and the comparison unit compares the shifted message in the previous level of the first update unit with the received variable node message to obtain the minimum value.

[0034] In some embodiments, the method further comprises:

[0035] During the second time period, the comparison units in the second to a-th stage first update units are turned off.

[0036] In some embodiments, each level of the second update unit includes a second delay unit, and the first to a-1th level second update units also include an addition unit and a second shift unit;

[0037] The method also includes: the second delay unit delays the output of the message updated in each level of the second update unit, the second shift unit shifts the message updated in the second update unit, and the addition unit adds the message in the next level of the second update unit to the received variable node message.

[0038] In some embodiments, the decoder further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal is connected to the a-th level first update unit, the second input terminal is used to receive an all-zero message, and the first output terminal is connected to the first level to the a-1-th level second update unit;

[0039] The method further includes: in the first time period, selecting the message of the second input terminal as the output message of the first output terminal; and in the second time period, selecting the message of the first input terminal as the output message of the first output terminal.

[0040] In some embodiments, the decoder further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th-level second update unit;

[0041] The method further includes: in the first time period, selecting the message of the third input terminal as the output message of the second output terminal; and in the second time period, selecting the message of the fourth input terminal as the output message of the second output terminal.

[0042] In some embodiments, the decoder further comprises a parity check circuit, wherein the parity check circuit is connected to the variable node update circuit;

[0043] The method also includes: receiving the variable node message of the variable node update circuit, and substituting the received variable node message into the verification equation for verification. If all the verification equations are satisfied, the decoding is determined to be successful; if all the verification equations are not satisfied, the decoding is determined to be failed, and the next iteration is required to update the verification node message and the variable node message until the decoding is successful or the maximum number of iterations is reached.

[0044] In some embodiments, the decoder further includes: a third selector, the third selector including a fifth input terminal, a sixth input terminal, and a third output terminal, the fifth input terminal is used to receive the initial channel message corresponding to each column of the check matrix, the sixth input terminal is connected to the first-stage second update unit, and the third output terminal is connected to the second-stage to the a-th-stage first update units;

[0045] The method further comprises: in the first time period, selecting a message at the fifth input terminal as an output message at the third output terminal;

[0046] In the next iteration process, the message of the sixth input terminal is selected as the output message of the third output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0048] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0049] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0050] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0051] Figure 3b is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0052] Figure 4 is a cross-sectional schematic diagram of a memory array including memory strings according to an embodiment of the present disclosure;

[0053] Figure 5 A schematic diagram of an exemplary memory including a memory array and a peripheral circuit according to an embodiment of the present disclosure;

[0054] Figure 6 Schematic diagram of the framework structure of a decoder according to an embodiment of the present disclosure;

[0055] Figure 7 is a schematic structural diagram of a decoder according to an embodiment of the present disclosure;

[0056] Figure 8 is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0057] Fig. 9 A schematic diagram of an implementation flow of a decoding method according to an embodiment of the present disclosure;

[0058] Fig.10 The figure is a schematic diagram of a framework flow of a decoding method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0060] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0061] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0062] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0063] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0064] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0066] Figure 1 1 shows a block diagram of an exemplary system 100 having a memory according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit) or a system on a chip (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0067] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital card, a compact flash card, a universal serial bus flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card, which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0068] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols, such as a USB (Universal Serial Bus) protocol, an MMC (Multi-Media Card) protocol, a peripheral component interconnect protocol, a peripheral component interconnect high-speed protocol, an advanced technology attachment protocol, a serial advanced technology attachment protocol, a parallel advanced technology attachment protocol, a minicomputer mini interface protocol, an enhanced mini disk interface protocol, an integrated drive electronics protocol, a firmware protocol, etc.

[0069] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in FIG. 1 , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of SSD206 is greater than the storage capacity and / or operating speed of memory card 202.

[0070] Figure 3a A schematic diagram of the structure of a memory array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cells parallel to the gate isolation structure, and every four rows of memory cells are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory array into a plurality of memory blocks (expressed in English as Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (expressed in English as Finger), and the upper selection gate isolation structure provided in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A memory block shown in FIG. 1 includes 6 memory slices. In practical applications, the number of memory slices in a memory block is not limited thereto. A memory cell in a memory slice coupled to a word line can be called a memory page (expressed in English as Page), where the memory page is a physical page.

[0071] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0072] Figure 3b1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 306 are NAND memory cells, and the memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0073] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC), or four bits per cell (also known as a quad-level cell (QLC). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for an erased state.

[0074] like Figure 3bAs shown in , each memory string 308 may include a bottom select transistor (BST) 310 at its source terminal and a top select transistor (TST) 312 at its drain terminal. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read or written from the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TST312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TST312 via one or more TSLs (Top selected lines) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BST310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BST310 via one or more BSLs (Bottom Selected lines) 315.

[0075] like Figure 3bAs shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits may be related to the number of memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding memory page 320 and a gate line coupling the control gates. Figure 3a A memory page 320 includes a plurality of memory cells 306, wherein the plurality of memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and the plurality of memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into a plurality of memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. The memory cells in the memory slices sharing the same word line form a programmable (read / write) page.

[0076] Figure 4 2 shows a cross-sectional schematic diagram of an exemplary memory array 301 including memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of memory cells included in the memory array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0077] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0078] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0079] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0080] Return to reference Figure 3b, the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 316, the word line 318, the source line 314, the BSL 315, and the TSL 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSL 315, and the TSL 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic circuit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0081] The page buffer / sense amplifier 504 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic circuit 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic circuit 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0082] The row decoder / word line driver 508 may be configured to be controlled by the control logic circuit 512 and select / deselect the memory block 304 of the memory array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSL 315 and the TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word line 318. The voltage generator 510 may be configured to be controlled by the control logic circuit 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0083] The control logic circuit 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic circuit 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic circuit 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic circuit 512, and to buffer status information received from the control logic circuit 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0084] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0085] As a storage device that is more stable than traditional disk storage and has faster and more convenient data reading and writing, three-dimensional NAND memory has penetrated into every corner of daily life. In order to meet the increasing storage demand, the process size of three-dimensional NAND memory is constantly shrinking, and the number of information bits in a single flash memory unit is increasing. The type of storage unit is constantly developing from SLC to MLC, TLC, and QLC. As a result, the error probability of flash memory is constantly increasing. The traditional BCH (Bose Chaudhuri Hocquenghem) error correction code is no longer sufficient to ensure data security. Low-density parity check code (LDPC) is an error correction method with an error correction capability close to the Shannon limit. It is gradually replacing BCH and becoming the error correction coding method in the new generation of flash memory controllers.

[0086] Figure 6 FIG. 1 is a schematic diagram of a decoder framework structure proposed in an embodiment of the present disclosure. Figure 6 As shown, the decoder includes a posterior probability storage circuit, a permutation circuit, a message update circuit, an inverse permutation circuit, and a node message storage circuit. During the decoding process, the posterior probability message in the posterior probability storage circuit is permuted by the permutation circuit, the check node message is updated in the message update circuit, and the updated check node message is permuted by the inverse permutation circuit.

[0087] LDPC codes can be divided into several types according to their construction methods. One type is based on Euclidean geometry (EG) and projective geometry (PG) over finite fields, collectively known as finite geometric codes (FG). These codes are known to have excellent error correction performance and relatively large minimum distances. However, because EG-LDPC codes have higher row and column weights, they are not suitable for use in Figure 6 The decoding architecture shown in the figure may be implemented by using an algorithm such as the Method of Successive Algorithm (MSA). Currently, the decoding of Euclidean Geometries Low Density Parity Check (EG-LDPC) codes is mainly improved by algorithms, while the improvement of the decoder architecture is generally less. How to improve the decoder architecture to increase throughput and reduce resource utilization has become an urgent problem to be solved.

[0088] Based on one or more of the above problems, the present disclosure provides a decoder, such as Figure 7As shown, the check matrix corresponding to a frame of codewords includes a*a sub-matrices, multiple sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, and multiple sub-matrices located in the same column constitute a column of the check matrix. The decoder includes:

[0089] The check node update circuit 701 includes a first update unit of level a, and the first update units of each level are connected in sequence; the variable node update circuit 702 is connected to the check node update circuit 701, and the variable node update circuit 702 includes a second update unit of level a, and the second update units of each level are connected in sequence; wherein,

[0090] In the first time period, the check node update circuit 701 is configured as follows: the first update units at all levels except the first-level first update unit sequentially receive the variable node messages corresponding to the columns of the check matrix, and sequentially calculate the received variable node messages with the messages in the first update unit at the previous level, and obtain the check node messages corresponding to different layers of the check matrix in the first update units at different levels in the a-level first update unit;

[0091] In the first time period, the variable node update circuit 702 is configured as follows: the a-th level second update unit sequentially receives the variable node message corresponding to each column of the check matrix, and the second update units of each level except the a-th level second update unit sequentially receive the message of the next level second update unit and calculate, and obtain the corresponding intermediate calculation value in the different levels of the a-th level second update unit;

[0092] In a second time period after the first time period, the variable node update circuit 702 is configured as follows: the second update units at each level except the a-th level second update unit sequentially receive the check node messages corresponding to the layers of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values ​​of the next-level second update unit, and obtain the variable node messages corresponding to different columns of the check matrix in the different levels of second update units in the a-th level second update unit.

[0093] In some specific examples, the first update unit of each level is connected to the first update unit of the previous level and the next level, and the first update unit of the a-th level is connected to the first update unit of the first level; the second update unit of each level of the variable node update circuit 702 is connected to the second update unit of the previous level and the second update unit of the next level, and the second update unit of the a-th level is connected to the second update unit of the first level.

[0094] Here, a and n in the following text are positive integers greater than zero.

[0095] Table 1 gives an example of a check matrix. The following is an example of the check matrix given in Table 1. The check matrix given in Table 1 includes 5*5 sub-matrices. Multiple sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, with a total of 5 layers; multiple sub-matrices located in the same column constitute a column of the check matrix, with a total of 5 columns. i Represents a circulant permutation matrix, the value of i corresponds to the number of columns where the non-zero elements in the first row of the circulant permutation matrix are located, and -1 represents an all-zero matrix. Here, the variable node messages corresponding to the first to fifth columns of the check matrix are L0, L1, L2, L3, and L4, respectively, and the check node messages corresponding to the first to fifth layers of the check matrix are C0, C1, C2, C3, and C4, respectively.

[0096]

[0097] Table 1

[0098] The following uses the check matrix given in Table 1 as an example to exemplarily illustrate the situation of the decoder in the first iteration process of the above embodiment.

[0099] In the case where the check matrix includes 5*5 sub-matrices, the check node update circuit 701 of the decoder includes 5 levels of first update units, and the variable node update circuit 702 includes 5 levels of second update units. The first time period includes five first sub-time periods, and the second time period includes five second sub-time periods. The duration of each first sub-time period in the five first sub-time periods is equal, the duration of each second sub-time period in the five second sub-time periods is equal, and the duration of the first sub-time period is equal to the duration of the second sub-time period.

[0100] It should be noted that the check matrix and the corresponding number of first update units and second update units listed here are only exemplary demonstrations and are not used to limit the check matrix and the number of first update units and second update units in the embodiments of the present disclosure.

[0101] In the jth first sub-time period, the second to fifth first update units all receive the initial channel message L j-1, and compared with the message of the previous level first update unit in the previous time period, to obtain the minimum value, thereby obtaining the intermediate calculation value. In the next first sub-time period, the value of the intermediate calculation value in the previous level first update unit after substitution will be passed to the next level first update unit to participate in the calculation of the next level first update unit, and the intermediate calculation value of the next level first update unit in the next sub-time period is obtained. After five first sub-time periods, the check node message corresponding to the fifth layer of the check matrix is ​​obtained in the first level first update unit, the check node message corresponding to the fourth layer of the check matrix is ​​obtained in the second level first update unit, the check node message corresponding to the third layer of the check matrix is ​​obtained in the third level first update unit, the check node message corresponding to the second layer of the check matrix is ​​obtained in the fourth level first update unit, and the check node message corresponding to the first layer of the check matrix is ​​obtained in the fifth level first update unit.

[0102] In the jth first sub-time period, the fifth-level second updating unit receives the initial channel message L j-1 In the next first sub-time period, the intermediate calculation value in the next-level second update unit is passed to the previous-level second update unit to participate in the calculation of the previous-level second update unit, and the intermediate calculation value of the previous-level second update unit in the next first sub-time period is obtained. In the jth first sub-time period, the first to fourth-level second update units receive all-zero messages and perform calculations with the messages passed by the next-level second update unit.

[0103] In the jth second sub-time period, the fifth-level second update unit receives the message of the first-level second update unit after permutation, and each level of the second update unit from the first to the fourth level receives the message of the second update unit of the next level and the message transmitted by the fifth-level first update unit, and calculates the two. After five second sub-time periods, the variable node message corresponding to the fifth column of the check matrix is ​​obtained in the first-level second update unit, the variable node message corresponding to the fourth column of the check matrix is ​​obtained in the second-level second update unit, the variable node message corresponding to the third column of the check matrix is ​​obtained in the third-level second update unit, the variable node message corresponding to the second column of the check matrix is ​​obtained in the fourth-level second update unit, and the variable node message corresponding to the first column of the check matrix is ​​obtained in the fifth-level second update unit.

[0104] In some embodiments, the decoder further includes: a first selector 703, the first selector 703 includes a first input terminal 709, a second input terminal 710, and a first output terminal 706, the first input terminal 709 is connected to the a-th level first update unit, the second input terminal 710 is used to receive an all-zero message, and the first output terminal 706 is connected to the first to a-1-th level second update units;

[0105] The first selector 703 is configured to: select the message of the second input terminal 710 as the output message of the first output terminal 706 in the first time period; and select the message of the first input terminal 709 as the output message of the first output terminal 706 in the second time period.

[0106] In some embodiments, the decoder further includes: a second selector 704, the second selector 704 includes a third input terminal 711, a fourth input terminal 712, and a second output terminal 707; the third input terminal 711 is used to receive variable node messages corresponding to each column of the check matrix, the fourth input terminal 712 is connected to the first-level second update unit, and the second output terminal 707 is connected to the a-th level second update unit;

[0107] The second selector 704 is configured to: select the message of the third input terminal 711 as the output message of the second output terminal 707 in the first time period; and select the message of the fourth input terminal 712 as the output message of the second output terminal 707 in the second time period.

[0108] In some embodiments, the decoder further comprises:

[0109] A third selector 705, wherein the third selector 705 comprises a fifth input terminal 713, a sixth input terminal 714, and a third output terminal 708, wherein the fifth input terminal 713 is used to receive the initial channel message corresponding to each column of the check matrix, the sixth input terminal 714 is connected to the first-stage second update unit, and the third output terminal 708 is connected to the second-stage to the a-th-stage first update units;

[0110] The third selector 705 is configured to: in the first time period of the first iteration process, select the message of the fifth input terminal 713 as the output message of the third output terminal 708;

[0111] In the first time period of the next iteration process, the message of the sixth input terminal 714 is selected as the output message of the third output terminal 708 .

[0112] It can be understood that each iteration process is divided into a first time period and a second time period. In the first iteration process, the variable node messages received by the variable node update circuit 702 and the check node update circuit 701 are all initial channel messages (L0L1L2L3L4), where L iis the initial channel message corresponding to the i-th layer of the check matrix. During the first iteration, in the first time period, the first selector 703 selects the all-zero message (00000) of the second input terminal 710 as the output message of the first output terminal 706, the second selector 704 selects the message (L0L1L2L3L4) of the third input terminal 711 as the output message of the second output terminal 707, and the third selector 705 selects the message (L0L1L2L3L4) of the fifth input terminal 713 as the output message of the third output terminal 708. During the first iteration, in the second time period, the first selector 703 receives the message of the first update unit of the a-th level in the check node update circuit 701 as the output message of the first output terminal 706, the second selector 704 receives the message of the second update unit of the first level in the variable node update circuit 702 as the output message of the second output terminal 707, and the third output terminal 708 of the third selector 705 does not output a message. The difference between the second iteration process and the first iteration process is that, in the second iteration process, in the first time period, the third selector 705 selects the message of the sixth input terminal 714 as the output message of the third output terminal 708, that is, selects the variable node message updated in the previous iteration process as the output message of the third output terminal 708.

[0113] In some embodiments, each level of the first update unit includes a first delay unit, the first level to the a-1 level first update units also include a first shift unit, and the second level to the a level first update units also include a comparison unit; the first delay unit is used to delay the output of the message updated in the first update unit of each level, the first shift unit is used to shift the message updated in the first update unit, and the comparison unit is used to compare the shifted message in the first update unit of the previous level with the received variable node message to obtain a minimum value.

[0114] Here, the comparison unit includes but is not limited to a comparator, and the comparison unit can compare to obtain a minimum value or a second minimum value. The first to fourth level update units in the variable node update circuit 702 can also include a selection unit, and the selection unit is used to select the corresponding minimum value or the second minimum value. Figure 7 In the figure, comp is used to represent the comparison unit, and sel0-sel3 are used to represent the selection unit.

[0115] In some embodiments, the check node update circuit 701 is configured to:

[0116] During the second time period, the comparison units in the second to a-th stage first update units are turned off.

[0117] It is understandable that in the second time period, the comparison unit in the check node update circuit 701 does not work, that is, in the second time period, the value in the first update unit of the previous level is passed to the first update unit of the next level without comparison.

[0118] In some embodiments, each level of the second update unit includes a second delay unit, and the first to a-1 level second update units also include an adding unit and a second shift unit; the second delay unit is used to delay the output of the message updated in each level of the second update unit, the second shift unit is used to shift the message updated in the second update unit, and the adding unit is used to add the message in the second update unit of the next level to the received variable node message.

[0119] Here, the adding unit includes but is not limited to an adder.

[0120] Figure 7 In the figure, + represents the adding unit, and D represents the first delay unit and the second delay unit.

[0121] In some embodiments, the shift value of the first shift unit in the n-th level first update unit is equal to the shift value of the second shift unit in the n-th level second update unit; n is less than or equal to a.

[0122] Figure 7 In the figure, P0-P3 represent the first shifting units in the first to fourth stages of the first updating units, respectively, and P0-P3 represent the second shifting units in the first to fourth stages of the second updating units, respectively.

[0123] Here, the first shift unit of the first update unit of the nth stage is represented by P n-1 Indicates that the second shift unit of the second update unit of the nth level is represented by P n-1 , where n-1 represents the shift value of the shift unit, and the shift value of the first shift unit of the n-th level first update unit is equal to the shift value of the second shift unit of the n-th level second update unit.

[0124] In some embodiments, the delay length of the first delay unit of each level of the first update unit is h1, the delay length of the second delay unit of each level of the second update unit is h2, and h1=h2.

[0125] In some specific examples, the delay duration of the first delay unit is equal to the duration of the first sub-time period and the duration of the second sub-time period, the delay duration of the second delay unit is equal to the duration of the first sub-time period and the duration of the second sub-time period, and the duration of the first sub-time period is equal to the duration of the second sub-time period.

[0126] In some specific examples, during the first iteration process, at the initial moment before the first time period, the value after the first delay unit in the check node update circuit 701 is set to the maximum value, and the value after the second delay unit in the variable node update circuit 702 is set to 0.

[0127] The following will specifically introduce the intermediate calculation values in each stage of the first update unit and each stage of the second update unit during the first iteration process of decoding.

[0128] During the first first sub - time period of the first iteration process, the initial channel message L0 enters the 2nd - 5th stage first update units in the check node update circuit 701 through the third output terminal 708 of the third selector 705. In each stage of the 2nd - 5th stage first update units, L0 is compared with the value (initially set maximum value) after its respective first delay unit and temporarily recorded as D i ; at the same time, during the first first sub - time period of the first iteration process, the initial channel message L0 enters the 5th stage second update unit in the variable node update circuit 702 through the second output terminal 707 of the second selector 704. The all - zero message at the second input terminal 710 of the first selector 703 enters the 1st - 4th stage second update units through the first output terminal 706 and is added to the value (initially set to 0) after the second delay unit in the 1st - 4th stage second update units. During the second - fifth first sub - time periods, the initial channel message L m-1 successively enters the check node update circuit 701. After being compared with the value obtained by permuting the intermediate calculation value updated in the previous first sub - time period in the previous stage first update unit, the updated intermediate calculation value is obtained in each stage of the second update unit. At the same time, the initial channel message L m-1 enters the variable node update circuit 702 and is added to 0.

[0129] The values after the first delay units in the 1st - 5th stage first update units are respectively denoted as D0 - D4, and the values after the second delay units in the 1st - 5th stage second update units are respectively denoted as D5 - D9. Taking D4 in the fifth first sub - time period as an example for illustration, during the first first sub - time period, L0 enters the check node update circuit 701. After being compared with the maximum value Max, L0 is obtained. At this time, D i = L0(0 < i < 5), D0 = Max. During the second first sub - time period, L1 enters the check node update circuit 701. After being compared with the value of D0 through the permutation matrix P0, D1 = min(L1, Max 0), where the upper 0 indicates the replacement unit identifier. In the third first sub-time period, L2 enters the check node update circuit 701 and is compared with the value of D1 through the replacement unit P1 to obtain D2 = min (L2L1 1 In the fourth first sub-time period, L3 enters the check node update circuit 701 and is compared with the value of D2 through the replacement unit P2 to obtain D3=min(L3(L2L1 1 ) 2 In the fifth first sub-time period, L4 enters the check node update circuit 701 and is compared with the value of D3 through the replacement unit P3 to obtain D4=min(L4(L3(L2L1 1 ) 2 ) 3 ). Similarly, the values ​​of other first update units in the fifth first sub-time period can be derived. Table 2 shows the D values ​​corresponding to the initial time period, the first first sub-time period to the fifth first sub-time period. i The value of .

[0130]

[0131] Table 2

[0132] After the fifth first sub-time period, each level of the first update unit in the check node update circuit 701 completes the minimum sum comparison process corresponding to one layer of the check matrix, and obtains the updated check node messages of each layer of the check matrix. In the following second time period, the check node update circuit 701 only passes the updated check node messages obtained in each level of the first update unit to the variable node update circuit 702 for calculation after being permuted by the permutation unit.

[0133] The following table analyzes P i The specific shift in the fifth first sub-time period is analyzed as an example. In the fifth first sub-time period, the value corresponding to D4 is D4=min(L4(L3(L2L1 1 ) 2 ) 3 ). The variable node message corresponding to the first column of the check matrix is ​​L0, which does not exist in D4. Combining the check matrix, it can be seen that D4 is the check node message of the first layer (the first column block of the first layer is 0); the check node message corresponding to the second column block B0 of the first layer is L1, which is obtained after P1 in D4 (L1 1 ); The check node message corresponding to the third column block B1 is L2, which is the same as (L1 1 ) compare to get min(L2L1 1), so at this time, the message order B0 in the second column block needs to be converted to the message order B1 in the third column block. In this example, the size of the small matrix is 3*3, so the shift value of B1 is r(P1) = (r(B0) - r(B1) + 3), where r(P1) is the shift value of P1 and 3 is the rank of the small matrix; the check node message corresponding to the fourth column block B2 is L3, and after comparison with ((L2L1 1 ) 2 ) we get min(L3(L2L1 1 ) 2 ). At this time, the message order B1 in the third column block needs to be converted to the message order B2 in the fourth column block, so the shift value of P2 is r(P2) = (r(B1) - r(B2) + 3); and so on, the shift value of P x is r(P x ) = (r(B x-1 ) - r(B x ) + 3).

[0134] Based on the obtained message order of the check node message B3, that is, the message order of the last column, then consider the second layer of the check matrix. At the fifth first sub-time period, the message value for D3, at this time its order is the order of B2. After another P3 permutation, it becomes the order of B3 in the sixth second sub-time period and enters the variable node update circuit 702. The same is true for the remaining layers. After several permutations, they all become the order of B3 and enter the variable node update circuit 702. At the same time, it should be noted that during the 1st to 5th second sub-time periods, the check node update circuit 701 only outputs the calculated check node messages in sequence. To prevent the comparison unit from comparing the messages corresponding to the subsequent layers with the messages passing through the first selector 703 when outputting the check node messages corresponding to the previous layers and obtaining incorrect results, the comparison unit should be suspended at this time and the permuted data should be directly transmitted to the next-level first update unit.

[0135] Next, specifically introduce the value corresponding to D i in the variable node update circuit 702. Denote the message obtained in the check node update circuit 701 as C i (i is the number of layers):

[0136] In the first first sub-time period, the first selector 703 outputs 0, and the second selector 704 outputs L0. At this time, D i = 0 (4 < i < 9), D9 = L0; in the second first sub-time period, the first selector 703 outputs 0, and the second selector 704 outputs L1. At this time, D i= 0 (4 < i < 8), D8 = L0, D9 = L1; In the third first sub - time period, the output of the first selector 703 is 0, and the output of the second selector 704 is L2. At this time, D i = 0 (4 < i < 7), D7 = L0 3 , D8 = L1, D9 = L2; In the fourth first sub - time period, the output of the first selector 703 is 0, and the output of the second selector 704 is L3. At this time, D i = 0 (4 < i < 6), D6 = L0 32 , D7 = L1 3 , D8 = L2, D9 = L3; In the fifth first sub - time period, the output of the first selector 703 is 0, and the output of the second selector 704 is L4. At this time, D5 = L0 321 , D6 = L1 32 , D7 = L2 3 , D8 = L3, D9 = L4.

[0137] In the first second sub - time period, the updated check node message C0 corresponding to the first layer of the check matrix in the 5th - level first update unit, that is, min(L4(L3(L2L1 1 ) 2 ) 3 ) directly enters the first - level to fourth - level second update units in the variable node update circuit 702, and is added to the value obtained by permuting the intermediate calculation value updated by the next - level second update unit in the variable node update circuit 702 in the previous sub - time period. In the second - fifth second sub - time periods, the check node messages of the 2nd - 5th layers of the updated check matrix in the first - level to fourth - level first update units enter the first - level to fourth - level second update units in the variable node update unit in turn after passing through the comparison unit (turned off in the second time period) and the permutation unit, and are added to the value obtained by permuting the intermediate calculation value updated by the next - level second update unit in the variable node update circuit 702 in the previous sub - time period.

[0138] Next, specifically introduce the values of D in the variable node update circuit 702 during the first - fifth second sub - time periods i Let the message obtained in the check node update circuit 701 be denoted as C i (i is the number of layers). Taking D5 in the fifth second sub - time period as an example:

[0139] In the first second sub - time period, C0 enters the variable node update circuit 702 and is added to D i (5 < i ≤ 9). After that, at this time, D i = D i+1 + C0 (5 ≤ i < 9), In the second second sub-period, C1 enters the variable node update circuit 702 and is added to the value of D9 to obtain D8=C1+L0. 3210 ; In the third second sub-period, C2 enters the variable node update circuit 702 and is added to the value of D8 to obtain D7=C2+(C1+L0 3210 ) 3 In the fourth second sub-time period, C3 enters the variable node update circuit 702 and is added to the value of D7 to obtain D6=C3+(C2+(C1+L0 3210 ) 3 ) 2 ; In the fifth second sub-time period, C4 enters the variable node update circuit 702 and is added to the value of D6 to obtain D5=C4+(C3+(C2+(C1+L0 3210 ) 3 ) 2 ) 1 .

[0140] Table 3 shows the D corresponding to the first second sub-time period to the fifth second sub-time period. i The value of .

[0141]

[0142] Table 3

[0143] Similarly, the specific shift value in the variable node update circuit 702 is analyzed. The analysis principle is roughly the same as that in the check node update circuit 701. Similarly, D9 in the fifth second sub-time period is briefly described as an example. At this time, D9=(C3+(C2+(C 1 +(C0+L4) 3 ) 2 ) 1 ) 0 The first layer check node message (C0) transmitted from the check node update circuit 701 is accumulated with the corresponding initial channel message (L4), and then accumulated with the check node message (C1) of the next layer after passing through P3. Here, the check node messages transmitted from the check node update circuit 701 are all in the order of B3, but the second layer is in the order of B2. When accumulating, (C0+L4) needs to be replaced by P3 to become the order of B2, and then accumulated with C1, so r(P3)=(r(B2)-r(B3)+3), which is consistent with the shift value in the check node update circuit 701.

[0144] In some embodiments, the decoder further includes a parity check circuit, and the parity check circuit is connected to the variable node update circuit 702;

[0145] The parity check circuit is configured to: receive the variable node message of the variable node update circuit 702, and substitute the received variable node message into the check equation for verification; if all the check equations are satisfied, the decoding is determined to be successful; if all the check equations are not satisfied, the decoding is determined to be failed, and the next iteration is required to update the check node message and the variable node message until the decoding is successful or the maximum number of iterations is reached.

[0146] Here, the parity check circuit may be specifically connected to the second delay unit in the first-stage second update unit in the variable node update circuit 702 .

[0147] It can be understood that after five first sub-time periods and five second sub-time periods, a check node message and a variable node message update are completed, and the output in the variable node update circuit 702 will be divided into two paths, one path is used for hard judgment to see whether the decoding is successful, and the other path is output to the check node update circuit 701 for the next iterative decoding. In another iteration process, the third output terminal 708 of the third selector 705 selects the message of the sixth input terminal 714 to input into the check node update circuit 701, and the rest remains unchanged until the entire decoding process is completed.

[0148] It can be understood that a new architecture of a decoder is provided in the embodiment of the present disclosure, which utilizes the first shift unit, the second shift unit, the first delay unit, the second delay unit, the comparison unit, and the addition unit in different first update units and second update units, uses a simple shift delay function, and adjusts the duration of the first delay unit and the second delay unit to complete the update of information.

[0149] In the embodiment of the present disclosure, a first update unit of level a is used to complete the update of the check node messages corresponding to each layer of the check matrix in the first time period, and a second update unit of level a is used to complete the update of the variable node messages corresponding to each column of the check matrix in the first time period and the second time period, which can improve throughput and reduce resource utilization.

[0150] Based on the above decoder, an embodiment of the present disclosure further provides a memory controller, comprising the decoder described in any one of the above embodiments.

[0151] Based on the above memory controller, an embodiment of the present disclosure further provides a memory system, including the memory controller described in the above embodiment and a memory device coupled to the memory controller.

[0152] Figure 8A block diagram of a memory system 601 is shown. The memory system 601 includes: a memory controller 602 and a memory device 603. The memory controller 602 is used to control the memory device 603 to perform read and write operations. Here, the memory controller 602 and the memory device 603 can be coupled in any suitable manner. The memory controller 602 includes a control unit (such as a central processing unit) 608, a data buffer 609, an error correction module 606, a host I / F 605, and a memory I / F 607. In the embodiment of the present disclosure, the memory device 603 can be a semiconductor memory for storing data in a non-volatile manner, such as a NAND type memory. The memory system 601 is connected to a host 604. Among them, the host I / F 605 outputs the commands, valid data (write data), etc. received from the host 604 to the internal bus 610, and sends the valid data (read data) read from the memory device 603, the response from the control unit 608, etc. to the host 604.

[0153] The control unit 608 can instruct the memory I / F 607 to write valid data, parity check data, and a check matrix to the memory device 603 according to a command from the host 604. In addition, the control unit can instruct the memory I / F 607 to read valid data, parity check data, and a check matrix from the memory device according to a command from the host 604.

[0154] The error correction module 606 here includes an encoding unit and a decoding unit. The encoding unit encodes the valid data of a predetermined size to generate parity check data (such as a low-density parity check code) and a corresponding check matrix. The parity check data and the corresponding check matrix generated by the encoding unit can be stored in a memory device. The decoding unit uses the parity check data and the corresponding check matrix for decoding. The decoding unit here includes a decoder. The parity check code and the corresponding check matrix during decoding can be obtained from the memory device.

[0155] Based on the above memory system, an embodiment of the present disclosure further provides an electronic device, comprising the decoder described in any one of the above embodiments, and a memory device coupled to the decoder.

[0156] Here, the decoder may be built into the memory controller, or may not be built into the memory controller but be arranged outside the memory controller.

[0157] Here, the specific structure and composition of the memory controller, memory system, and electronic device can refer to the above Figure 1 , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4 , Figure 5For the sake of brevity, the detailed introduction is not repeated here.

[0158] Based on the above decoder, the embodiment of the present disclosure further provides a decoding method. In the process of decoding a frame of codewords including a*a sub-matrices of the check matrix, multiple sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, and multiple sub-matrices located in the same column constitute a column of the check matrix, such as Fig. 9 As shown, the method includes:

[0159] In the first time period, the first update units at all levels except the first-level first update unit sequentially receive the variable node messages corresponding to the columns of the check matrix, and sequentially calculate the received variable node messages with the messages in the first update unit at the previous level, and obtain the check node messages corresponding to different layers of the check matrix in the first update units at different levels in the a-level first update unit;

[0160] In the first time period, the a-th level second update unit sequentially receives the variable node message corresponding to each column of the check matrix, and the second update units of each level except the a-th level second update unit sequentially receive the message of the next level second update unit and calculate, and obtain the corresponding intermediate calculation value in the different levels of the a-th level second update unit;

[0161] In the second time period, the second update units at all levels except the a-th level second update unit receive the check node messages corresponding to the layers of the check matrix in turn, and calculate the received check node messages with the intermediate calculation values ​​of the next-level second update unit in turn, and obtain the variable node messages corresponding to different columns of the check matrix in the different levels of second update units in the a-th level second update unit.

[0162] In some embodiments, each first update unit of each level includes a first delay unit, the first update units of the first level to the a-1th level also include a first shift unit, and the first update units of the second level to the ath level also include a comparison unit;

[0163] The method includes: the first delay unit delays the output of the message updated in each level of the first update unit, the first shift unit shifts the message updated in the first update unit, and the comparison unit compares the shifted message in the previous level of the first update unit with the received variable node message to obtain the minimum value.

[0164] In some embodiments, the method further comprises:

[0165] During the second time period, the comparison units in the second to a-th stage first update units are turned off.

[0166] In some embodiments, each level of the second update unit includes a second delay unit, and the first to a-1th level second update units also include an addition unit and a second shift unit;

[0167] The method also includes: the second delay unit delays the output of the message updated in each level of the second update unit, the second shift unit shifts the message updated in the second update unit, and the addition unit adds the message in the next level of the second update unit to the received variable node message.

[0168] In some embodiments, the decoder further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal is connected to the a-th level first update unit, the second input terminal is used to receive an all-zero message, and the first output terminal is connected to the first level to the a-1-th level second update unit;

[0169] The method further includes: in the first time period, selecting the message of the second input terminal as the output message of the first output terminal; and in the second time period, selecting the message of the first input terminal as the output message of the first output terminal.

[0170] In some embodiments, the decoder further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th-level second update unit;

[0171] The method further includes: in the first time period, selecting the message of the third input terminal as the output message of the second output terminal; and in the second time period, selecting the message of the fourth input terminal as the output message of the second output terminal.

[0172] In some embodiments, the decoder further comprises a parity check circuit, wherein the parity check circuit is connected to the variable node update circuit;

[0173] The method also includes: receiving the variable node message of the variable node update circuit, and substituting the received variable node message into the verification equation for verification. If all the verification equations are satisfied, the decoding is determined to be successful; if all the verification equations are not satisfied, the decoding is determined to be failed, and the next iteration is required to update the verification node message and the variable node message until the decoding is successful or the maximum number of iterations is reached.

[0174] In some embodiments, the decoder further includes: a third selector, the third selector including a fifth input terminal, a sixth input terminal, and a third output terminal, the fifth input terminal is used to receive the initial channel message corresponding to each column of the check matrix, the sixth input terminal is connected to the first-stage second update unit, and the third output terminal is connected to the second-stage to the a-th-stage first update units;

[0175] The method further comprises: in the first time period, selecting a message at the fifth input terminal as an output message at the third output terminal;

[0176] In the next iteration process, the message of the sixth input terminal is selected as the output message of the third output terminal.

[0177] Fig.10 A schematic diagram of a decoding method provided by an embodiment of the present disclosure is shown below. Fig.10 The decoding method of the embodiment of the present disclosure is further introduced.

[0178] In the first iteration process, the initial channel message is first stored in the posterior probability storage circuit, and the check node update circuit receives the initial channel messages L0, L1, L2, L3, and L4 in sequence in the first time period. The initial channel message obtains the minimum or second minimum value after passing through the comparison unit, and after five first sub-time periods, the check node messages corresponding to the first to fifth layers of the updated check matrix are obtained; in the variable node update circuit, the variable node update circuit accumulates the initial channel message and the updated check node message to obtain the updated variable node message, and after five second sub-time periods, the updated variable node message is obtained; after updating the variable node message, it is determined whether the maximum number of iterations has been reached. If the maximum number of iterations has been reached, the codeword is output, and if the maximum number of iterations has not been reached, the next iteration is performed.

[0179] The above decoding method has been introduced in detail on the decoder side and will not be repeated here for the sake of brevity.

[0180] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0181] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0182] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A decoder, characterized in that: The check matrix corresponding to a frame of codewords includes a*a sub-matrices, and multiple sub-matrices located in the same row of the check matrix constitute a layer of the check matrix, and multiple sub-matrices located in the same column constitute a column of the check matrix. The decoder includes: A check node update circuit includes a first update unit of level a, and the first update units of each level are connected in sequence; a variable node update circuit is connected to the check node update circuit, and the variable node update circuit includes a second update unit of level a, and the second update units of each level are connected in sequence; wherein, In the first time period, the check node update circuit is configured as follows: the first update units at all levels except the first-level first update unit sequentially receive the variable node messages corresponding to the columns of the check matrix, and sequentially calculate the received variable node messages with the messages in the first update unit at the previous level, and obtain the check node messages corresponding to different layers of the check matrix in the first update units at different levels in the a-level first update unit; In the first time period, the variable node update circuit is configured as follows: the a-th level second update unit sequentially receives the variable node message corresponding to each column of the check matrix, and the second update units of each level except the a-th level second update unit sequentially receive the message of the next level second update unit and calculate, and obtain the corresponding intermediate calculation value in the different levels of the a-th level second update unit; In a second time period after the first time period, the variable node update circuit is configured as follows: the second update units at each level except the a-th level second update unit sequentially receive the check node messages corresponding to each layer of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values ​​of the next-level second update unit, and obtain the variable node messages corresponding to different columns of the check matrix in the different levels of second update units in the a-th level second update unit.

2. The decoder according to claim 1, characterized in that The first update unit of each level includes a first delay unit, the first update units from the first level to the a-1 level also include a first shift unit, and the first update units from the second level to the a level also include a comparison unit; the first delay unit is used to delay the output of the message updated in the first update unit of each level, the first shift unit is used to shift the message updated in the first update unit, and the comparison unit is used to compare the shifted message in the first update unit of the previous level with the received variable node message to obtain a minimum value.

3. The decoder according to claim 2, characterized in that The check node update circuit is configured as follows: During the second time period, the comparison units in the second to a-th stage first update units are turned off.

4. The decoder according to claim 2, characterized in that Each level of the second update unit includes a second delay unit, and the first to a-1 level second update units also include an adding unit and a second shift unit; the second delay unit is used to delay the output of the message updated in each level of the second update unit, the second shift unit is used to shift the message updated in the second update unit, and the adding unit is used to add the message in the second update unit of the next level to the received variable node message.

5. The decoder according to claim 4, characterized in that The shift value of the first shift unit in the n-th level first update unit is equal to the shift value of the second shift unit in the n-th level second update unit; n is less than or equal to a.

6. The decoder according to claim 4, characterized in that The delay length of the first delay unit of each level of the first update unit is h1, the delay length of the second delay unit of each level of the second update unit is h2, and h1=h2.

7. The decoder according to claim 1, characterized in that: The decoder further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal is connected to the first update unit of the ath level, the second input terminal is used to receive an all-zero message, and the first output terminal is connected to the second update units of the first level to the a-1th level; The first selector is configured to: in a first time period, select a message at the second input end as an output message at the first output end; and in a second time period, select a message at the first input end as an output message at the first output end.

8. The decoder according to claim 1, characterized in that The decoder further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th-level second update unit; The second selector is configured to: in a first time period, select a message at the third input terminal as an output message at the second output terminal; and in a second time period, select a message at the fourth input terminal as an output message at the second output terminal.

9. The decoder according to claim 1, characterized in that: The decoder further includes a parity check circuit, wherein the parity check circuit is connected to the variable node update circuit; The parity check circuit is configured to: receive the variable node message of the variable node update circuit, and substitute the received variable node message into the check equation for verification; if all the check equations are satisfied, the decoding is determined to be successful; if all the check equations are not satisfied, the decoding is determined to be failed, and the next iteration is required to update the check node message and the variable node message until the decoding is successful or the maximum number of iterations is reached.

10. The decoder according to claim 9, characterized in that The decoder also includes: A third selector, the third selector comprising a fifth input terminal, a sixth input terminal, and a third output terminal, the fifth input terminal being used to receive the initial channel message corresponding to each column of the check matrix, the sixth input terminal being connected to the first-stage second update unit, and the third output terminal being connected to the second-stage to the a-th-stage first update units; The third selector is configured to: in a first time period during a first iteration, select a message at the fifth input terminal as an output message at the third output terminal; In the first time period of the next iteration process, the message of the sixth input terminal is selected as the output message of the third output terminal.

11. A memory controller comprising the decoder according to any one of claims 1 to 10.

12. A memory system comprising the memory controller according to claim 11 and a memory device coupled to the memory controller.

13. An electronic device comprising the decoder according to any one of claims 1 to 10, and a memory device coupled to the decoder.

14. A decoding method, characterized in that: In a decoding process of a frame of codewords including a*a submatrices of a check matrix, a plurality of submatrices located in the same row of the check matrix constitute a layer of the check matrix, and a plurality of submatrices located in the same column constitute a column of the check matrix, the method comprising: In the first time period, the first update units at all levels except the first-level first update unit sequentially receive the variable node messages corresponding to the columns of the check matrix, and sequentially calculate the received variable node messages with the messages in the first update unit at the previous level, and obtain the check node messages corresponding to different layers of the check matrix in the first update units at different levels in the a-level first update unit; In the first time period, the a-th level second update unit sequentially receives the variable node message corresponding to each column of the check matrix, and the second update units of each level except the a-th level second update unit sequentially receive the message of the next level second update unit and calculate, and obtain the corresponding intermediate calculation value in the different levels of the a-th level second update unit; In the second time period, the second update units at all levels except the a-th level second update unit receive the check node messages corresponding to the layers of the check matrix in turn, and calculate the received check node messages with the intermediate calculation values ​​of the next-level second update unit in turn, and obtain the variable node messages corresponding to different columns of the check matrix in the different levels of second update units in the a-th level second update unit.

15. The method according to claim 14, characterized in that Each first updating unit of each level includes a first delay unit, the first updating units of the first level to the a-1th level also include a first shifting unit, and the first updating units of the second level to the ath level also include a comparing unit; The method includes: the first delay unit delays the output of the message updated in each level of the first update unit, the first shift unit shifts the message updated in the first update unit, and the comparison unit compares the shifted message in the previous level of the first update unit with the received variable node message to obtain the minimum value.

16. The method according to claim 15, characterized in that The method further comprises: During the second time period, the comparison units in the second to a-th stage first update units are turned off.

17. The method according to claim 15, characterized in that Each level of the second updating unit includes a second delay unit, and the first level to the a-1th level of the second updating unit also include an adding unit and a second shifting unit; The method also includes: the second delay unit delays the output of the message updated in each level of the second update unit, the second shift unit shifts the message updated in the second update unit, and the addition unit adds the message in the next level of the second update unit to the received variable node message.

18. The method according to claim 14, characterized in that The decoder further includes: a first selector, the first selector including a first input terminal, a second input terminal, and a first output terminal, the first input terminal is connected to the first update unit of the ath level, the second input terminal is used to receive an all-zero message, and the first output terminal is connected to the second update units of the first level to the a-1th level; The method further includes: in the first time period, selecting the message of the second input terminal as the output message of the first output terminal; and in the second time period, selecting the message of the first input terminal as the output message of the first output terminal.

19. The method according to claim 14, characterized in that The decoder further includes: a second selector, the second selector including a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal is used to receive variable node messages corresponding to each column of the check matrix, the fourth input terminal is connected to the first-level second update unit, and the second output terminal is connected to the a-th-level second update unit; The method further includes: in the first time period, selecting the message of the third input terminal as the output message of the second output terminal; and in the second time period, selecting the message of the fourth input terminal as the output message of the second output terminal.

20. The method according to claim 14, characterized in that The decoder further comprises a parity check circuit, wherein the parity check circuit is connected to the variable node update circuit; The method also includes: receiving the variable node message of the variable node update circuit, and substituting the received variable node message into the verification equation for verification. If all the verification equations are satisfied, the decoding is determined to be successful; if all the verification equations are not satisfied, the decoding is determined to be failed, and the next iteration is required to update the verification node message and the variable node message until the decoding is successful or the maximum number of iterations is reached.

21. The method according to claim 20, characterized in that The decoder further includes: a third selector, the third selector including a fifth input terminal, a sixth input terminal, and a third output terminal, the fifth input terminal is used to receive the initial channel message corresponding to each column of the check matrix, the sixth input terminal is connected to the first-stage second update unit, and the third output terminal is connected to the second-stage to the a-th-stage first update units; The method further comprises: in the first time period, selecting a message at the fifth input terminal as an output message at the third output terminal; In the next iteration process, the message of the sixth input terminal is selected as the output message of the third output terminal.

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