A chip selection signal control circuit, processing circuit and memory

Abstract

The embodiment of the present disclosure discloses a chip selection signal control circuit, comprising: a first control signal generation circuit, a second control signal generation circuit, a chip selection signal sampling circuit and a logic control circuit. Wherein, the first control signal generation circuit outputs a first control signal according to a first chip selection sampling signal and a first command address sampling signal sampled in the previous two system sampling periods; the second control signal generation circuit outputs a second control signal according to a second chip selection sampling signal and a second command address sampling signal sampled in the previous system sampling period; and the logic control circuit controls the output of the current chip selection sampling signal according to the first control signal and the second control signal.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a chip select signal control circuit. 、 Processing circuitry and memory. Background Technology

[0002] In memory, command address signals are transmitted via the command address bus, while the chip select signal indicates whether the command address signal is valid. Because various command address signals converge on the command address bus, different decoding errors may occur under certain circumstances. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a chip select signal control circuit. 、 The processing circuitry and memory can prevent decoding errors of command address signals.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a chip select signal control circuit, the chip select signal control circuit comprising:

[0006] The first control signal generation circuit is configured to receive a first chip select sampling signal and a first command address sampling signal. When the levels of the first chip select sampling signal and the first command address sampling signal conform to a first preset rule, it outputs a first control signal at a first level; otherwise, it outputs a first control signal at a second level. The first chip select sampling signal is obtained by sampling the initial chip select signal during the first two system sampling cycles, and the first command address sampling signal is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0007] The second control signal generation circuit is configured to receive a second chip select sampling signal and a second command address sampling signal. When the levels of the second chip select sampling signal and the second command address sampling signal conform to a second preset rule, it outputs a second control signal at a first level; otherwise, it outputs a second control signal at a second level. The second chip select sampling signal is obtained by sampling the initial chip select signal during the previous system sampling cycle, and the second command address sampling signal is obtained by sampling the initial command address signal during the previous system sampling cycle.

[0008] The chip select signal sampling circuit is configured to receive the initial chip select signal and the first divided clock signal, sample the initial chip select signal according to the first divided clock signal, and output the current chip select sampling signal;

[0009] A logic control circuit, connected to the first control signal generation circuit, the second control signal generation circuit, and the chip select signal sampling circuit, is configured to receive the first control signal, the second control signal, and the current chip select sampling signal, and output the current chip select sampling signal when the first control signal and the second control signal meet a third preset rule.

[0010] In some embodiments, the second control signal generation circuit is further configured to receive the first control signal after a first delay and a second frequency-divided clock signal, sample the first control signal after the first delay according to the second frequency-divided clock signal, and output the second control signal.

[0011] In some embodiments, the first control signal generation circuit is further configured to apply a second delay to the first control signal and then output it in a first operating mode; or to output the first control signal in a second operating mode.

[0012] In some embodiments, the chip select signal control circuit further includes: a command address signal sampling circuit, configured to receive an initial command address signal, a first frequency-divided clock signal, and a second frequency-divided clock signal; sample the initial command address signal into a first command address sampling signal according to the first frequency-divided clock signal; and sample the initial command address signal into a second command address sampling signal according to the second frequency-divided clock signal.

[0013] In some embodiments, the first control signal generation circuit includes: a first NAND gate, a first inverter, and a second inverter; the input terminal of the first NAND gate receives the first chip select sampling signal and the first command address sampling signal, respectively; the output terminal of the first NAND gate is connected to the input terminal of the first inverter; the output terminal of the first inverter is connected to the input terminal of the second inverter; the first NAND gate outputs the first control signal; the first inverter outputs the first control signal after the first delay; and the second inverter outputs the first control signal after the second delay.

[0014] In some embodiments, the first control signal generation circuit further includes: a first data selector; a first input terminal of the first data selector receives the first control signal after the second delay; a second input terminal of the first data selector receives the first control signal; and a control terminal of the first data selector receives a working mode enable signal.

[0015] In some embodiments, the first control signal generation circuit further includes: a first level trigger; the data input terminal of the first level trigger is connected to the output terminal of the first data selector; the clock input terminal of the first level trigger receives the first frequency-divided clock signal; and the output terminal of the first level trigger serves as the output terminal of the first control signal generation circuit.

[0016] In some embodiments, the second control signal generation circuit includes: a second NAND gate, a first D flip-flop, and a second data selector; the input terminals of the second NAND gate receive the second chip select sampling signal and the second command address sampling signal, respectively; the output terminal of the second NAND gate is connected to the first input terminal of the second data selector; the data input terminal of the first D flip-flop receives the first control signal after the first delay, and the clock input terminal of the first D flip-flop receives the second frequency-divided clock signal; the non-inverting output terminal of the first D flip-flop is connected to the second input terminal of the second data selector; the control terminal of the second data selector receives a working mode enable signal.

[0017] In some embodiments, the second control signal generation circuit further includes: a second level flip-flop; the data input terminal of the second level flip-flop is connected to the output terminal of the second data selector; the clock input terminal of the second level flip-flop receives the first frequency-divided clock signal; and the output terminal of the second level flip-flop serves as the output terminal of the second control signal generation circuit.

[0018] In some embodiments, the chip select signal sampling circuit includes: a second D flip-flop, a third inverter, and a fourth inverter; the data input terminal of the second D flip-flop receives the initial chip select signal, and the clock input terminal of the second D flip-flop receives the first frequency-divided clock signal; the non-inverting output terminal of the second D flip-flop is connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the fourth inverter; and the fourth inverter outputs the current chip select sampling signal.

[0019] In some embodiments, the logic control circuit includes: an OR gate and a third NAND gate; the first input of the OR gate is connected to the output of the first control signal generation circuit; the second input of the OR gate is connected to the output of the second control signal generation circuit; the output of the OR gate is connected to the first input of the third NAND gate; the second input of the third NAND gate receives the current chip select sampling signal; and the output of the third NAND gate serves as the output of the logic control circuit.

[0020] In some embodiments, the command address signal sampling circuit includes: a third D flip-flop and a fourth D flip-flop; the data input terminal of the third D flip-flop receives the initial command address signal, the clock input terminal of the third D flip-flop receives the first frequency-divided clock signal, and the third D flip-flop outputs the first command address sampling signal; the data input terminal of the fourth D flip-flop receives the initial command address signal, the clock input terminal of the fourth D flip-flop receives the second frequency-divided clock signal, and the fourth D flip-flop outputs the second command address sampling signal.

[0021] This disclosure also provides a chip select signal processing circuit, characterized in that it includes: a chip select signal control circuit as described in the above scheme, and a decoding circuit; the decoding circuit is connected to the chip select signal control circuit and is configured to receive a current chip select sampling signal, decode the current chip select sampling signal, and output it.

[0022] This disclosure also provides a memory that includes a chip select signal processing circuit as described in the above embodiments.

[0023] In some embodiments, the memory is DDR5 DRAM.

[0024] Therefore, this disclosure provides a chip select signal control circuit, including: a first control signal generation circuit, a second control signal generation circuit, a chip select signal sampling circuit, and a logic control circuit. The first control signal generation circuit outputs a first control signal based on a first chip select sampling signal and a first command address sampling signal obtained from the previous two system sampling cycles. The second control signal generation circuit outputs a second control signal based on a second chip select sampling signal and a second command address sampling signal obtained from the previous system sampling cycle. The logic control circuit controls the output of the current chip select sampling signal based on the first and second control signals. By using the signals from the previous two system sampling cycles for logical checking, it ensures that the command address signal in the current system sampling cycle is correctly decoded, avoiding decoding errors. Attached Figure Description

[0025] Figure 1 Signal illustration provided for embodiments of this disclosure Figure 1 ;

[0026] Figure 2 Signal illustration provided for embodiments of this disclosure Figure 2 ;

[0027] Figure 3 A schematic diagram of the chip select signal control circuit provided in the embodiments of this disclosure. Figure 1 ;

[0028] Figure 4 Signal illustration provided for embodiments of this disclosure Figure 3 ;

[0029] Figure 5 Signal illustration provided for embodiments of this disclosure Figure 4 ;

[0030] Figure 6 A schematic diagram of the chip select signal control circuit provided in the embodiments of this disclosure. Figure 2 ;

[0031] Figure 7 A schematic diagram of the chip select signal control circuit provided in the embodiments of this disclosure. Figure 3 ;

[0032] Figure 8 A schematic diagram of the chip select signal control circuit provided in the embodiments of this disclosure. Figure 4 ;

[0033] Figure 9 Schematic diagram of the command address sampling circuit provided in the embodiments of this disclosure Figure 1 ;

[0034] Figure 10 A schematic diagram of the chip select signal control circuit provided in the embodiments of this disclosure. Figure 5 ;

[0035] Figure 11 Signal illustration provided for embodiments of this disclosure Figure 5 ;

[0036] Figure 12 Signal illustration provided for embodiments of this disclosure Figure 6 ;

[0037] Figure 13 Schematic diagram of the command address sampling circuit provided in the embodiments of this disclosure Figure 2 ;

[0038] Figure 14 This is a schematic diagram of the chip select signal processing circuit provided in an embodiment of the present disclosure;

[0039] Figure 15 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] If similar descriptions such as "first / second" appear in the invention document, the following description shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0044] It should be noted that the chip select signal is used to select the corresponding chip. When multiple chips are connected to the same bus, the chip select signal distinguishes which chip is responsible for processing data and addresses on the bus; that is, the chip select signal triggers the corresponding chip to enter its working state. For example, in a memory, there are multiple memory chips; for the CPU (processor) to access memory cells, it first selects a memory chip using the chip select signal, i.e., performs chip selection; then, it selects the corresponding memory cell from the selected memory chip based on its address code, i.e., performs word selection, to read / write data. The chip select signal is usually active low; in this embodiment, the description assumes the chip select signal is active low.

[0045] On the other hand, the command address signal includes both command signals and address signals, which are transmitted via the bus. For example, in DRAM (Dynamic Random Access Memory), the command address signal may include: Row Address Strobe (RAS), Column Address Strobe (CAS), Write command (WE), Active command (ACT), and other command signals, as well as address signals (such as A13 to A0).

[0046] Furthermore, the command address signal needs to be indicated as valid by the chip select signal. (See reference) Figure 1Taking DDR5 DRAM (5th generation Double Data Rate Synchronous Dynamic Random Access Memory) design as an example, the command address signal CA<12:0> can be sampled as both an address and an instruction for decoding. In other words, the command address signal CA<12:0> includes the command signal CMD and the address signal ADD. After the chip select signal CS_n is valid (i.e., CS_n is low), the command address signal CA<12:0> is sampled by the even clock signal CLK_ET for decoding. The odd clock signal CLK_OT and the even clock signal CLK_ET are obtained by dividing the clock signal CK_t and are used to sample the command address signal CA<12:0>.

[0047] It should be noted that DDR5 DRAM has two command modes: 1T CMD and 2TCMD. 1T CMD only requires one system sampling cycle to output the command address signal as both instruction and address; while 2T CMD requires two system sampling cycles to transmit the command address signal.

[0048] It should also be noted that the clock signal CK_t is the basic reference clock in the chip system; the system sampling period mentioned in the embodiments of this disclosure refers to the period of the clock signal CK_t, which will not be repeated below.

[0049] Figure 1 In the signal waveform diagram shown, the command address signal CA<12:0> corresponds to the 2T CMD mode. (Reference) Figure 1 The command address signal CA<12:0> requires two system sampling cycles to transmit the instruction and address. Specifically, in the 0th cycle of the clock signal CK_t, the command address signal CA<12:0> transmits the instruction and a portion of the address (i.e., CMD+ADD); in the 2nd cycle of the clock signal CK_t, the command address signal CA<12:0> transmits the other portion of the address (i.e., ADD).

[0050] Figure 1 The example chip select signal CS_n has an active level (i.e., low level) that lasts for only one system sampling cycle. However, there are cases where the active level of the chip select signal CS_n lasts for multiple system sampling cycles. For example, in a two-rank chip architecture, the chip select signal corresponding to the on-chip termination command NT_ODT_CMD of a non-target chip has an active level that lasts for two system sampling cycles.

[0051] Figure 2 The example shows partial waveforms of the command address signal and chip select signal for a non-target chip. For example... Figure 2As shown, the command address signal CA includes the read command NT_RD (one of the on-chip termination commands) for non-target chips. Correspondingly, the effective level of the chip select signal CS_n lasts for two cycles of the clock signal CK_t. Thus, during the second system sampling cycle of the effective level of the chip select signal CS_n, the address transmitted by the command address signal CA (the part highlighted in the dashed box) may be mistakenly interpreted as an instruction, potentially leading to incorrect sampling and decoding.

[0052] Figure 3 This is a schematic diagram of an optional structure of the chip select signal control circuit provided in an embodiment of this disclosure. For example... Figure 3 As shown, the chip select signal control circuit 80 includes: a first control signal generation circuit 10, a second control signal generation circuit 20, a chip select signal sampling circuit 30, and a logic control circuit 40.

[0053] The first control signal generation circuit 10 is configured to receive the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB. When the levels of the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB conform to the first preset rule, it outputs the first control signal CS_EVEN_PP_T at the first level; otherwise, it outputs the first control signal CS_EVEN_PP_T at the second level. The first chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n during the first two system sampling cycles, and the first command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0054] The second control signal generation circuit 20 is configured to receive the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB. When the levels of the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB meet the second preset rule, it outputs the second control signal CS_EVEN_P_T at the first level; otherwise, it outputs the second control signal CS_EVEN_P_T at the second level. The second chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n during the previous system sampling period, and the second command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal during the previous system sampling period.

[0055] The chip select signal sampling circuit 30 is configured to receive the initial chip select signal CS_n and the first frequency divided clock signal CLK_ET (i.e., even clock signal), sample the initial chip select signal CS_n according to the first frequency divided clock signal CLK_ET, and output the current chip select sampling signal CS.

[0056] The logic control circuit 40 is connected to the first control signal generation circuit 10, the second control signal generation circuit 20, and the chip select signal sampling circuit 30. It is configured to receive the first control signal CS_EVEN_PP_T, the second control signal CS_EVEN_P_T, and the current chip select sampling signal CS. When the first control signal CS_EVEN_PP_T and the second control signal CS_EVEN_P_T meet the third preset rule, the current chip select sampling signal CS is output.

[0057] It should be noted that, in Figure 3 In the above, the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB are obtained by sampling the even clock signal CLK_ET; the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB are obtained by sampling the odd clock signal CLK_OT. Figure 3 (Not shown) Sampled.

[0058] Combination Figure 1 It can be seen that the odd clock signal CLK_OT and the even clock signal CLK_ET are obtained by dividing the clock signal CK_t; that is, the frequency of the odd clock signal CLK_OT and the even clock signal CLK_ET is half the frequency of the clock signal CK_t; and the period of the odd clock signal CLK_OT and the even clock signal CLK_ET is twice the period of the clock signal CK_t.

[0059] Continue to refer to Figure 1 Since the odd clock signal CLK_OT and the even clock signal CLK_ET are out of phase, if any sampling edge (rising edge) of the even clock signal CLK_ET is taken as the current sampling edge, then the sampling edge (rising edge) of the odd clock signal CLK_OT is one system sampling period earlier (i.e., half a period of the even clock signal CLK_ET) ahead of the current sampling edge; furthermore, the previous sampling edge (rising edge) of the even clock signal CLK_ET is two system sampling periods earlier (i.e., one period of the even clock signal CLK_ET) ahead of the current sampling edge.

[0060] Combination Figure 1 and Figure 3Since the chip select signal sampling circuit 30 receives and samples the initial chip select signal CS_n according to the even clock signal CLK_ET, the current chip select sampling signal CS is obtained. Therefore, the sampling time of the current chip select sampling signal CS is two system sampling cycles earlier than the sampling edge of the even clock signal CLK_ET; that is, when the first chip select sampling signal EVEN_CS_OT is two system sampling cycles earlier, it is obtained by sampling the initial chip select signal CS_n by the even clock signal CLK_ET; correspondingly, when the first command address sampling signal EVEN_CA1_OB is two system sampling cycles earlier, it is obtained by sampling the initial command address signal by the even clock signal CLK_ET. Similarly, the sampling time of the current chip select sampling signal CS is one system sampling period earlier than the sampling edge of the odd clock signal CLK_OT; that is, the second chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n by the odd clock signal CLK_OT when the previous system sampling period is one system sampling period; correspondingly, the second command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal by the odd clock signal CLK_OT when the previous system sampling period is one system sampling period.

[0061] Figure 4 and Figure 5 The waveforms of the different command address signals CA are shown, with the chip select signal CS_n remaining active for multiple system sampling cycles.

[0062] refer to Figure 4 The command address signal CA includes two consecutive commands in 1T CMD mode (i.e., PRE and PDE), and the effective level of the chip select signal CS_n lasts for two system sampling cycles. Therefore, sampling based on the chip select signal CS_n may cause the second command, PDE, to be canceled.

[0063] refer to Figure 3 In this embodiment, the second control signal generation circuit 20 outputs the second control signal CS_EVEN_P_T based on the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB obtained in the previous system sampling cycle. That is, combined with... Figure 4 The second control signal generation circuit 20 can make a comprehensive judgment based on the levels of the chip select signal CS_n and the command address signal CA in the previous system sampling cycle. For example, if the chip select signal CS_n is low and the identifier signal in the command address signal CA is high in the previous system sampling cycle, then the current command PDE can be determined to be a complete command, and the current command PDE can be sampled and decoded normally when the chip select signal CS_n is low.

[0064] refer to Figure 5 The read command NT_RD (a type of on-chip termination command) from a non-target chip lasted for two system sampling cycles, followed immediately by a command PRE. Thus, sampling based on the chip select signal CS_n might incorrectly treat the PRE command as the second system sampling cycle in 2T CMD mode.

[0065] refer to Figure 3 In this embodiment, the first control signal generation circuit 10 outputs the first control signal CS_EVEN_PP_T based on the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB obtained from the previous two system sampling cycles. That is, combined with... Figure 5 The first control signal generation circuit 10 can make a comprehensive judgment based on the levels of the chip select signal CS_n and the command address signal CA in the first two system sampling cycles. For example, if the chip select signal CS_n is low in the first two system sampling cycles, and the command address signal CA represents a read command NT_RD for a non-target chip, then the current command PDE can be determined to be a complete command. The current command PDE can be sampled and decoded normally when the chip select signal CS_n is low, which also avoids the read command NT_RD being incorrectly decoded in the second system sampling cycle.

[0066] It is understandable that various command address signals are gathered on the command address bus, which may lead to various decoding errors. In this embodiment, the first control signal generation circuit obtains a first control signal based on the levels of the chip select signal and the command address signal in the previous two system sampling cycles; the second control signal generation circuit obtains a second control signal based on the levels of the chip select signal and the command address signal in the previous system sampling cycle; then, the logic control circuit controls the output of the current chip select sampling signal based on the first and second control signals, that is, controls whether the chip select signal affects the current command address signal. In this way, by using the signals from the previous two system sampling cycles for logic checks, it can be ensured that the command address signal in the current system sampling cycle is decoded normally, avoiding decoding errors.

[0067] Figure 6 This is a schematic diagram of another optional structure of the chip select signal control circuit provided in an embodiment of this disclosure. Figure 6 The example illustrates how the chip select signal sampling circuit 30 receives and samples the initial chip select signal CS_n according to the odd clock signal CLK_OT to obtain the current chip select sampling signal CS. In other words, Figure 6 The example shows the relationship with Figure 3 The corresponding circuit structure, Figure 6 The examples of each signal can be referenced. Figure 3 Pushed.

[0068] For details, please refer to Figure 6 The first control signal generation circuit 10 is configured to receive the first chip select sampling signal ODD_CS_OT and the first command address sampling signal ODD_CA1_OB. When the levels of the first chip select sampling signal ODD_CS_OT and the first command address sampling signal ODD_CA1_OB conform to the first preset rule, it outputs the first control signal CS_ODD_PP_T at the first level; otherwise, it outputs the first control signal CS_ODD_PP_T at the second level. The first chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n during the first two system sampling cycles, and the first command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0069] The second control signal generation circuit 20 is configured to receive the second chip select sampling signal EVEN_CS_OT and the second command address sampling signal EVEN_CA1_OB. When the levels of the second chip select sampling signal EVEN_CS_OT and the second command address sampling signal EVEN_CA1_OB conform to the second preset rule, it outputs the second control signal CS_ODD_P_T at the first level; otherwise, it outputs the second control signal CS_ODD_P_T at the second level. The second chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n during the previous system sampling period, and the second command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal during the previous system sampling period.

[0070] The chip select signal sampling circuit 30 is configured to receive the initial chip select signal CS_n and the odd clock signal CLK_OT, sample the initial chip select signal CS_n according to the odd clock signal CLK_OT, and output the current chip select sampling signal CS.

[0071] The logic control circuit 40 is connected to the first control signal generation circuit 10, the second control signal generation circuit 20, and the chip select signal sampling circuit 30. It is configured to receive the first control signal CS_ODD_PP_T, the second control signal CS_ODD_P_T, and the current chip select sampling signal CS. When the first control signal CS_ODD_PP_T and the second control signal CS_ODD_P_T meet the third preset rule, the current chip select sampling signal CS is output.

[0072] Understandable, Figure 3 and Figure 6 The circuit structure is illustrated, corresponding to different sampling clocks. If the initial chip select signal CS_n is sampled using the even clock signal CLK_ET, then the circuit will run... Figure 3 The circuit shown; if the initial chip select signal CS_n is sampled with an odd clock signal CLK_OT, then it will run. Figure 6 The circuit shown can be configured according to the specific conditions of the chip system.

[0073] Correspondingly, Figure 6 In the circuit shown, the first chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n from the odd clock signal CLK_OT during the first two system sampling cycles; the first command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal from the odd clock signal CLK_OT during the first two system sampling cycles; the second chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n from the even clock signal CLK_ET during the previous system sampling cycle; and the second command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal from the even clock signal CLK_ET during the previous system sampling cycle.

[0074] In some embodiments of this disclosure, reference is made to Figure 7 The second control signal generation circuit 20 is also configured to receive the first control signal EVEN_CHK1 after a first delay and the second frequency-divided clock signal CLK_OT (i.e., odd clock signal), sample the first control signal EVEN_CHK1 after the first delay according to the second frequency-divided clock signal CLK_OT, and output the second control signal CS_EVEN_P_T.

[0075] Continue to refer to Figure 7 The first control signal generation circuit 10 is also configured to output the first control signal after applying a second delay in the first operating mode; or to output the first control signal in the second operating mode.

[0076] It should be noted that there are two operating modes in memory (such as DRAM): 1N mode and 2N mode. In 1N mode, both the odd clock signal CLK_OT and the even clock signal CLK_ET are sampled; while in 2N mode, only one of the odd clock signal CLK_OT and the even clock signal CLK_ET is sampled.

[0077] exist Figure 7In this context, the level of the operating mode enable signal EN indicates the operating mode of the memory. For example, when the operating mode enable signal EN is high, the memory is in 1N mode (i.e., the first operating mode); when the operating mode enable signal EN is low, the memory is in 2N mode (i.e., the second operating mode). In other words, the chip select signal control circuit 80 provided in this embodiment will also make corresponding adjustments according to the different operating modes of the memory.

[0078] refer to Figure 7 For the first control signal generation circuit 10, in 1N mode, the first control signal CS_EVEN_PP_T output by the first control signal generation circuit 10 is subject to a second delay; in 2N mode, the first control signal CS_EVEN_PP_T output by the first control signal generation circuit 10 is not subject to a second delay. Applying a second delay allows the timing of the output first control signal CS_EVEN_PP_T to match that of other signals in 1N mode.

[0079] Continue to refer to Figure 7 For the second control signal generation circuit 20, in 1N mode, the second control signal generation circuit 20 outputs the second control signal CS_EVEN_P_T based on the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB; in 2N mode, the second control signal generation circuit 20 outputs the first control signal EVEN_CHK1 after the first delay.

[0080] It should be noted that, Figure 7 In the illustrated circuit, in 2N mode, the even clock signal CLK_ET samples the initial chip select signal CS_n, meaning that the odd clock signal CLK_OT is not sampled. Therefore, the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB obtained from the odd clock signal CLK_OT cannot be applied to 2N mode. Consequently, in 2N mode, the second control signal generation circuit 20 can sample the first control signal EVEN_CHK1 after a first delay based on the odd clock signal CLK_OT, thereby replacing the logical check of the signal in the previous system sampling cycle, to output the second control signal CS_EVEN_P_T.

[0081] Correspondingly, Figure 8 In the circuit shown, in 2N mode, the initial chip select signal CS_n is sampled by the odd clock signal CLK_OT. (Reference) Figure 8The second control signal generation circuit 20 is also configured to receive the first control signal ODD_CHK1 after a first delay and the second frequency-divided clock signal CLK_ET (i.e., even clock signal), sample the first control signal ODD_CHK1 after the first delay according to the second frequency-divided clock signal CLK_ET, and output the second control signal CS_EVEN_P_T.

[0082] It is understood that the chip select signal control circuit provided in this disclosure can make corresponding adjustments according to different operating modes of the memory. This allows for better adaptation to different operating modes of the memory and expands the application range of the circuit.

[0083] In some embodiments of this disclosure, the chip select signal control circuit further includes a command address signal sampling circuit. The command address signal sampling circuit is configured to receive an initial command address signal, a first divided clock signal, and a second divided clock signal; to sample the initial command address signal into a first command address sampling signal based on the first divided clock signal; and to sample the initial command address signal into a second command address sampling signal based on the second divided clock signal.

[0084] In other words, reference Figure 9 The command address signal sampling circuit 50 can sample the initial command address signal CA according to the odd clock signal CLK_OT, and output the command address sampling signal ODD_CA1_OB. The command address signal sampling circuit 50 can also sample the initial command address signal CA according to the even clock signal CLK_ET, and output the command address sampling signal EVEN_CA1_OB. The command address sampling signals ODD_CA1_OB and EVEN_CA1_OB serve as... Figure 3 , Figure 6 , Figure 7 and Figure 8 The input signal in.

[0085] Figure 10 This is a schematic diagram of an optional structure of the chip select signal control circuit provided in an embodiment of the present disclosure. Figure 11 and Figure 12 Then it is Figure 10 A schematic diagram of the waveform of the middle part of the signal. Among them, Figure 11 The example illustrates the waveforms of some signals in 1N mode; that is, Figure 11 Both the odd clock signal CLK_OT and the even clock signal CLK_ET are sampled. Figure 12 This example illustrates the waveforms of some signals in the memory in 2N mode; Figure 12 In this process, only the even clock signal CLK_ET is sampled.

[0086] In some embodiments of this disclosure, reference is made to Figure 10 The first control signal generation circuit 10 includes: a first NAND gate Nand1, a first inverter Inv1, and a second inverter Inv2. The inputs of the first NAND gate Nand1 receive a first chip select sampling signal EVEN_CS_OT and a first command address sampling signal EVEN_CA1_OB, respectively. The output of the first NAND gate Nand1 is connected to the input of the first inverter Inv1. The output of the first inverter Inv1 is connected to the input of the second inverter Inv2. Specifically, the first NAND gate Nand1 outputs a first control signal EVEN_CHK, the first inverter Inv1 outputs a first control signal EVEN_CHK1 after a first delay, and the second inverter Inv2 outputs a first control signal EVEN_CHK2 after a second delay.

[0087] Continue to refer to Figure 10 The first control signal generation circuit 10 further includes a first data selector Mux1. The first input terminal (i.e., the "1" input terminal) of the first data selector Mux1 receives the first control signal EVEN_CHK2 after a second delay, the second input terminal (i.e., the "0" input terminal) of the first data selector Mux1 receives the first control signal EVEN_CHK, and the control terminal of the first data selector Mux1 receives the operating mode enable signal EN.

[0088] In this embodiment, the level of the operating mode enable signal EN represents the operating mode of the memory. When the memory is in 1N mode (i.e., the first operating mode), the operating mode enable signal EN is high; therefore, the first data selector Mux1 selects to output the first control signal EVEN_CHK2 (i.e., the signal received at the "1" input terminal) after a second delay. When the memory is in 2N mode (i.e., the second operating mode), the operating mode enable signal EN is low; therefore, the first data selector Mux1 selects to output the first control signal EVEN_CHK (i.e., the signal received at the "0" input terminal).

[0089] In some embodiments of this disclosure, reference is made to Figure 10 The first control signal generation circuit 10 further includes a first level flip-flop T1. The data input terminal D of the first level flip-flop T1 is connected to the output terminal of the first data selector Mux1, the clock input terminal of the first level flip-flop T1 receives the first frequency divided clock signal CLK_ET, and the output terminal of the first level flip-flop T1 serves as the output terminal of the first control signal generation circuit 10.

[0090] In this embodiment of the disclosure, 10 and Figure 12The initial command address signal CA includes the PRE and PDE signals. The PDE signal is the signal that needs to be sampled and decoded, while the PRE signal is two system sampling cycles before the PDE signal. The PRE signal is initially sampled as a high-level pre-sampled command address CA1(PRE) by the even clock signal CLK_ET, and further sampled as a low-level first command address sampling signal EVEN_CA1_OB.

[0091] Additionally, the initial chip select signal CS_n is active (low) two system sampling cycles prior, meaning the PRE signal corresponding to the initial chip select signal CS_n is low. Thus, two system sampling cycles prior, the initial chip select signal CS_n is sampled high by the even clock signal CLK_ET to form the first chip select sampling signal EVEN_CS_OT.

[0092] Furthermore, the first command address sampling signal EVEN_CA1_OB is low, and the first chip select sampling signal EVEN_CS_OT is high. After the NAND operation of the first NAND gate Nand1, the high-level first control signal EVEN_CHK is obtained. Thus, the PRE signal representing the first two system sampling cycles is a 1T CMD mode command, and therefore, the PDE signal of the current system sampling cycle is a new command that can be decoded normally.

[0093] In this embodiment of the disclosure, 10 and Figure 12 If the initial chip select signal CS_n and the pre-sampling command address CA1(PRE) are both low in the first two system sampling cycles, then it will be recognized as a 2T CMD mode command in the first two system sampling cycles. In this case, including the on-chip termination command NT_ODT_CMD (not shown in the figure) allows normal decoding in the current system sampling cycle, thus eliminating the possibility of commands being canceled after the on-chip termination command NT_ODT_CMD.

[0094] In some embodiments of this disclosure, reference is made to Figure 10The second control signal generation circuit 20 includes: a second NAND gate (Nand2), a first D flip-flop (DFF1), and a second data selector (Mux2). The inputs of the second NAND gate (Nand2) receive the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB, respectively. The output of the second NAND gate (Nand2) is connected to the first input (i.e., the "1" input) of the second data selector (Mux2). The data input D of the first D flip-flop (DFF1) receives the first control signal EVEN_CHK1 after a first delay. The clock input of the first D flip-flop (DFF1) receives the second divided clock signal CLK_OT. The non-inverting output Q of the first D flip-flop (DFF1) is connected to the second input (i.e., the "0" input) of the second data selector (Mux2). The control terminal of the second data selector (Mux2) receives the operating mode enable signal EN.

[0095] In this embodiment, the level of the operating mode enable signal EN represents the operating mode of the memory. When the memory is in 1N mode (i.e., the first operating mode), the operating mode enable signal EN is high; therefore, the second data selector Mux2 selects to output the signal received at its "1" input terminal. When the memory is in 2N mode (i.e., the second operating mode), the operating mode enable signal EN is low; therefore, the first data selector Mux1 selects to output the signal received at its "0" input terminal.

[0096] In some embodiments of this disclosure, reference is made to Figure 10 The second control signal generation circuit 20 further includes a second level flip-flop T2. The data input terminal D of the second level flip-flop T2 is connected to the output terminal of the second data selector Mux2, the clock input terminal of the second level flip-flop T2 receives the first frequency-divided clock signal CLK_ET, and the output terminal Q of the second level flip-flop T2 serves as the output terminal of the second control signal generation circuit 20.

[0097] In this embodiment of the disclosure, combined with Figure 10 and Figure 11 The initial command address signal CA includes the PRE and PDE signals. The PDE signal is the signal that needs to be sampled and decoded, while the PRE signal is one system sampling cycle before the PDE signal. The PRE signal is initially sampled as a high-level pre-sampled command address CA1(PRE), and further sampled as a low-level second command address sampling signal ODD_CA1_OB by the odd clock signal CLK_OT.

[0098] Additionally, the initial chip select signal CS_n is active (low level) one system sampling period prior, meaning that the PRE signal corresponding to the initial chip select signal CS_n is low. Thus, one system sampling period prior, the initial chip select signal CS_n is sampled high by the odd clock signal CLK_OT to form the second chip select sampling signal ODD_CS_OT.

[0099] Furthermore, the second command address sampling signal ODD_CA1_OB is low, and the second chip select sampling signal ODD_CS_OT is high. After the NAND operation of the second NAND gate Nand2, a high-level second control signal is obtained (i.e., point A is high). Thus, the PRE signal representing the previous system sampling period is a 1T CMD mode command, and therefore, the PDE signal of the current system sampling period is a new command that can be decoded normally.

[0100] In this embodiment of the disclosure, 10 and Figure 11 If the initial chip select signal CS_n of the previous system sampling cycle is high, or if the initial chip select signal CS_n was low while the initial command address signal CA was high in the previous system sampling cycle, then it will be identified as the previous system sampling cycle not performing any instruction operation, or performing a 1T CMD mode command. In this way, the current system sampling cycle can decode the instruction normally, thus avoiding two consecutive 1T CMD mode commands being mistakenly identified as the second cycle of the on-chip termination command NT_ODT_CMD.

[0101] In some embodiments of this disclosure, reference is made to Figure 10 The chip select signal sampling circuit 30 includes a second D flip-flop DFF2, a third inverter Inv3, and a fourth inverter Inv4. The data input D of the second D flip-flop DFF2 receives the initial chip select signal CS_n, and the clock input of the second D flip-flop DFF2 receives the first divided clock signal CLK_ET. The non-inverting output Q of the second D flip-flop DFF2 is connected to the input of the third inverter Inv3. The output of the third inverter Inv3 is connected to the input of the fourth inverter Inv4. The fourth inverter Inv4 outputs the current chip select sampling signal CS.

[0102] In this embodiment of the disclosure, reference is made to Figure 10 The second D flip-flop DFF2, triggered by the first divided clock signal CLK_ET (i.e., the even clock signal), samples the initial chip select signal CS_n. After passing through two stages of inverters Inv3 and Inv4, the current chip select sampling signal CS is obtained.

[0103] In some embodiments of this disclosure, reference is made to Figure 10The logic control circuit 40 includes an OR gate OR1 and a third NAND gate Nand3. The first input of OR gate OR1 is connected to the output of the first control signal generation circuit 10, and the second input of OR gate OR1 is connected to the output of the second control signal generation circuit 20. The output of OR gate OR1 is connected to the first input of the third NAND gate Nand3. The second input of the third NAND gate Nand3 receives the current chip select sampling signal CS, and the output of the third NAND gate Nand3 serves as the output of the logic control circuit 40.

[0104] In this embodiment of the disclosure, reference is made to Figure 10 The two inputs of OR gate Or1 receive the first control signal CS_EVEN_PP_T and the second control signal CS_EVEN_P_T respectively, and perform a logical judgment based on them. The judgment result is represented by the level at point B. Since the first control signal CS_EVEN_PP_T is obtained from the previous two system sampling cycles, and the second control signal CS_EVEN_P_T is obtained from the previous system sampling cycle, the judgment result output by OR gate Or1 is a logical check that combines the signals from the previous two system sampling cycles.

[0105] Furthermore, the third NAND gate (NAND3) outputs or masks the current chip select sampling signal CS (i.e., the level at point B) based on the judgment result of the OR gate (Or1). Combined with... Figure 11 or Figure 12 When the level at point B is high, the output at point D is determined by the level at point C. In other words, when the level at point B is high, the low level at point C (i.e., the current chip select sampling signal CS that is sampled as valid) is output as the high level at point D. Thus, the valid level of the current chip select sampling signal CS is output, and the current system sampling period can proceed with decoding normally.

[0106] It is understandable that various command address signals are gathered on the command address bus, which may lead to various decoding errors. In this embodiment, the first control signal generation circuit obtains a first control signal based on the levels of the chip select signal and the command address signal in the previous two system sampling cycles; the second control signal generation circuit obtains a second control signal based on the levels of the chip select signal and the command address signal in the previous system sampling cycle; then, the logic control circuit controls the output of the current chip select sampling signal based on the first and second control signals, that is, controls whether the chip select signal affects the current command address signal. In this way, by using the signals from the previous two system sampling cycles for logic checks, it can be ensured that the command address signal in the current system sampling cycle is decoded normally, avoiding decoding errors.

[0107] In some embodiments of this disclosure, reference is made to Figure 13 The command address signal sampling circuit 50 includes a third D flip-flop DFF3 and a fourth D flip-flop DFF4. The data input D of the third D flip-flop DFF3 receives the initial command address signal CA, and the clock input DFF3 receives the first divided clock signal CLK_ET. The third D flip-flop DFF3 outputs the first command address sampling signal EVEN_CA1_OB. The data input D of the fourth D flip-flop DFF4 receives the initial command address signal CA, and the clock input DFF4 receives the second divided clock signal CLK_OT. The fourth D flip-flop DFF4 outputs the second command address sampling signal ODD_CA1_OB.

[0108] In this embodiment of the disclosure, combined with Figure 12 and Figure 13 The third D flip-flop, DFF3, under the trigger of the first divided clock signal CLK_ET (i.e., the even clock signal), samples the PRE signal of the first two system sampling cycles in the initial command address signal CA, and outputs the first command address sampling signal EVEN_CA1_OB. The first command address sampling signal EVEN_CA1_OB is output to the inverted output terminal (i.e., the non-Q terminal) of the third D flip-flop DFF3. Therefore, Figure 12 The first command address sampling signal EVEN_CA1_OB shown in the figure is sampled as low level.

[0109] Correspondingly, combined Figure 11 and Figure 13 The fourth D flip-flop, DFF4, under the trigger of the second divided clock signal CLK_OT (i.e., the odd clock signal), samples the PRE signal of the previous system sampling cycle in the initial command address signal CA, and outputs the second command address sampling signal ODD_CA1_OB. The second command address sampling signal ODD_CA1_OB is output to the inverted output terminal (i.e., the non-Q terminal) of the fourth D flip-flop DFF4. Therefore, Figure 11 The second command address sampling signal ODD_CA1_OB shown in the figure is sampled as low level.

[0110] This disclosure also provides a chip select signal processing circuit, such as... Figure 14 As shown, the signal processing circuit 70 includes a chip select signal control circuit 80 and a decoding circuit 60, wherein the chip select signal control circuit 80 includes the technical features described in the foregoing embodiments.

[0111] refer to Figure 14 The decoding circuit 60 is connected to the chip select signal control circuit 80. The decoding circuit 60 is configured to receive the current chip select sampling signal CS, decode the current chip select sampling signal CS, and output the decoded chip select sampling signal CS1.

[0112] This disclosure also provides a memory, such as... Figure 15 As shown, the memory 90 includes a chip select signal processing circuit 70, wherein the chip select signal processing circuit 70 includes the technical features described in the foregoing embodiments.

[0113] In some embodiments of this disclosure, reference is made to Figure 15 The memory 90 is DDR5 DRAM.

[0114] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0115] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0116] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip select signal control circuit, characterized in that, The chip select signal control circuit includes: The first control signal generation circuit is configured to receive a first chip select sampling signal and a first command address sampling signal. When the levels of the first chip select sampling signal and the first command address sampling signal conform to a first preset rule, it outputs a first control signal at a first level; otherwise, it outputs a first control signal at a second level. The first chip select sampling signal is obtained by sampling the initial chip select signal during the first two system sampling cycles, and the first command address sampling signal is obtained by sampling the initial command address signal during the first two system sampling cycles. The second control signal generation circuit is configured to receive a second chip select sampling signal and a second command address sampling signal. When the levels of the second chip select sampling signal and the second command address sampling signal conform to a second preset rule, it outputs a second control signal at a first level; otherwise, it outputs a second control signal at a second level. The second chip select sampling signal is obtained by sampling the initial chip select signal during the previous system sampling cycle, and the second command address sampling signal is obtained by sampling the initial command address signal during the previous system sampling cycle. The chip select signal sampling circuit is configured to receive the initial chip select signal and the first divided clock signal, sample the initial chip select signal according to the first divided clock signal, and output the current chip select sampling signal; A logic control circuit, connected to the first control signal generation circuit, the second control signal generation circuit, and the chip select signal sampling circuit, is configured to receive the first control signal, the second control signal, and the current chip select sampling signal, and output the current chip select sampling signal when the first control signal and the second control signal meet a third preset rule.

2. The chip select signal control circuit according to claim 1, characterized in that, The second control signal generation circuit is further configured to receive the first control signal after a first delay and the second frequency-divided clock signal, sample the first control signal after the first delay according to the second frequency-divided clock signal, and output the second control signal.

3. The chip select signal control circuit according to claim 2, characterized in that, The first control signal generation circuit is further configured to apply a second delay to the first control signal and then output it in a first operating mode; or to output the first control signal in a second operating mode.

4. The chip select signal control circuit according to claim 1, characterized in that, The chip select signal control circuit also includes: The command address signal sampling circuit is configured to receive an initial command address signal, a first frequency-divided clock signal, and a second frequency-divided clock signal; to sample the initial command address signal into a first command address sampling signal based on the first frequency-divided clock signal; and to sample the initial command address signal into a second command address sampling signal based on the second frequency-divided clock signal.

5. The chip select signal control circuit according to claim 3, characterized in that, The first control signal generation circuit includes: a first NAND gate, a first inverter, and a second inverter; The inputs of the first NAND gate receive the first chip select sampling signal and the first command address sampling signal, respectively; the output of the first NAND gate is connected to the input of the first inverter; the output of the first inverter is connected to the input of the second inverter. The first NAND gate outputs the first control signal; the first inverter outputs the first control signal after the first delay; the second inverter outputs the first control signal after the second delay.

6. The chip select signal control circuit according to claim 3 or 5, characterized in that, The first control signal generation circuit further includes: a first data selector; The first input terminal of the first data selector receives the first control signal after the second delay; the second input terminal of the first data selector receives the first control signal; and the control terminal of the first data selector receives a working mode enable signal.

7. The chip select signal control circuit according to claim 6, characterized in that, The first control signal generation circuit further includes: a first level trigger; The data input terminal of the first level flip-flop is connected to the output terminal of the first data selector; the clock input terminal of the first level flip-flop receives the first frequency-divided clock signal; and the output terminal of the first level flip-flop serves as the output terminal of the first control signal generation circuit.

8. The chip select signal control circuit according to claim 2 or 3, characterized in that, The second control signal generation circuit includes: a second NAND gate, a first D flip-flop, and a second data selector; The inputs of the second NAND gate receive the second chip select sampling signal and the second command address sampling signal, respectively; the output of the second NAND gate is connected to the first input of the second data selector. The data input terminal of the first D flip-flop receives the first control signal after the first delay, and the clock input terminal of the first D flip-flop receives the second frequency-divided clock signal; the non-inverting output terminal of the first D flip-flop is connected to the second input terminal of the second data selector. The control terminal of the second data selector receives the operating mode enable signal.

9. The chip select signal control circuit according to claim 8, characterized in that, The second control signal generation circuit further includes: a second level trigger; The data input terminal of the second level flip-flop is connected to the output terminal of the second data selector; the clock input terminal of the second level flip-flop receives the first frequency-divided clock signal; and the output terminal of the second level flip-flop serves as the output terminal of the second control signal generation circuit.

10. The chip select signal control circuit according to any one of claims 1 to 4, characterized in that, The chip select signal sampling circuit includes: a second D flip-flop, a third inverter, and a fourth inverter; The data input terminal of the second D flip-flop receives the initial chip select signal, and the clock input terminal of the second D flip-flop receives the first frequency-divided clock signal; The non-inverting output of the second D flip-flop is connected to the input of the third inverter; the output of the third inverter is connected to the input of the fourth inverter. The fourth inverter outputs the current chip select sampling signal.

11. The chip select signal control circuit according to any one of claims 1 to 4, characterized in that, The logic control circuit includes: an OR gate and a third NAND gate; The first input terminal of the OR gate is connected to the output terminal of the first control signal generation circuit; the second input terminal of the OR gate is connected to the output terminal of the second control signal generation circuit. The output of the OR gate is connected to the first input of the third NAND gate; the second input of the third NAND gate receives the current chip select sampling signal; and the output of the third NAND gate serves as the output of the logic control circuit.

12. The chip select signal control circuit according to claim 4, characterized in that, The command address signal sampling circuit includes: a third D flip-flop and a fourth D flip-flop; The data input terminal of the third D flip-flop receives the initial command address signal, the clock input terminal of the third D flip-flop receives the first frequency-divided clock signal, and the third D flip-flop outputs the first command address sampling signal. The data input terminal of the fourth D flip-flop receives the initial command address signal, the clock input terminal of the fourth D flip-flop receives the second frequency-divided clock signal, and the fourth D flip-flop outputs the second command address sampling signal.

13. A chip select signal processing circuit, characterized in that, include: The chip select signal control circuit as described in any one of claims 1 to 12, and the decoding circuit; The decoding circuit, connected to the chip select signal control circuit, is configured to receive the current chip select sampling signal, decode the current chip select sampling signal, and output it.

14. A memory, characterized in that, The memory includes the chip select signal processing circuit as described in claim 13.

15. The memory according to claim 14, characterized in that, The memory is DDR5 DRAM.

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