Ferroelectric memory write method and associated device

Abstract

An FRAM memory device may include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor may be configured to store data bits. The memory device may also include a local bit line configured to carry data to be written into the multi-memory cell. The memory device may further include a global bit line configured to communicate with the local bit line to deliver data to be written to the plurality of memory cells. The memory device may additionally include a local sense amplifier configured to amplify a signal from the global bit line based on a reference signal and to pass the amplified signal to the local bit line. The local sense amplifier is configured to generate an amplified signal based on a comparison with the reference signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to the following applications: co-pending U.S. application No., attorney case number: 10022-01-0012-US2, filed on the same date, entitled “FERROELECTR IC MEMORY REFERENCE GENERAT ION”; co-pending U.S. application No., attorney case number: 10022-01-0013-US2, filed on the same date, entitled “FERROELECTR I CMEMORY LOCAL SENSE AMPL IFI CAT ION”; and co-pending U.S. application No., attorney case number: 10022-01-0015-US2, filed on the same date, entitled “FERROELECTR I CMEMORY REFERENCE GENERAT ION”, the entire contents of which are hereby incorporated by reference into this application. Background Art

[0003] Embodiments of the present disclosure relate to a writing method for a ferroelectric memory device.

[0004] The demand for non-volatile memory with high durability, low operating voltage, low power consumption and high-speed operation suitable for various electronic devices such as portable terminals and integrated circuit (IC) cards has increased. Ferroelectric memory such as ferroelectric RAM (FeRAM or FRAM) uses a ferroelectric material layer to achieve non-volatility. Ferroelectric materials have a nonlinear relationship between the applied electric field and the apparent stored charge, and therefore can switch polarity in the electric field. The advantages of ferroelectric memory include low power consumption, fast read and write performance, and excellent maximum read and write durability. Summary of the invention

[0005] A writing method for a ferroelectric memory device is disclosed herein.

[0006] In one aspect, a memory device may include a plurality of memory cells, each memory cell including at least one transistor and a capacitor electrically coupled to the at least one transistor. The capacitor may be configured to store data bits. The memory device may also include a local bit line configured to convey data to be written into the plurality of memory cells. The memory device may further include a global bit line configured to communicate with the local bit line to convey data to be written into the plurality of memory cells. The memory device may additionally include a local sense amplifier configured to amplify a signal from the global bit line based on a reference signal and transmit the amplified signal to the local bit line. The local sense amplifier may be configured to generate an amplified signal based on a comparison with a reference signal.

[0007] In another aspect, a method of operating a memory device may include storing corresponding data bits in a plurality of memory cells, each memory cell including at least one transistor and a capacitor electrically coupled to the at least one transistor. The method may also include transmitting data to be read from or written to the plurality of memory cells on local bit lines. The method may further include communicating with the local bit lines using global bit lines to transmit data to be written to the plurality of memory cells. The method may additionally include amplifying a signal from the global bit line based on a reference signal using a local sense amplifier and transmitting the amplified signal to the local bit line. The local sense amplifier may be configured to generate an amplified signal based on a comparison with the reference signal.

[0008] On the other hand, the memory device may include a plurality of memory cell array groups connected by global bit lines. Each group of arrays may include a plurality of arrays. Each array in the array group has a local bit line. The memory device may also include a local sense amplifier connected between the array pairs of the array group and connected to each local bit line of the array group. The memory device may further include a plurality of memory cells in each array, each memory cell including at least one transistor and a capacitor electrically coupled to the at least one transistor. The capacitor may be configured to store data bits. The local sense amplifier may be configured to amplify a signal from the global bit line to the local bit line of the corresponding array based on a reference signal. The local sense amplifier may be configured to generate an amplified signal based on a comparison with the reference signal.

[0009] In another aspect, a method of operating a memory device may include storing corresponding data bits in a plurality of memory cells. Each memory cell may include a transistor and a capacitor electrically coupled to the at least one transistor. The method may also include transmitting data to be read from or written to the plurality of memory cells on a local bit line. The method may further include communicating with the local bit line using a global bit line to transmit data to be written to the plurality of memory cells. The method may additionally include amplifying a signal from the global bit line based on a reference signal using a local sense amplifier and transmitting the amplified signal to the local bit line. The method may also include providing a reference signal using an amplifier or a buffer.

[0010] On the other hand, the memory device may include a plurality of memory cell array groups connected by global bit lines. Each group of arrays may include a plurality of arrays. Each array in the array group may have a local bit line. The memory device may also include a local sense amplifier connected between the array pairs of the array group and connected to each local bit line of the array group. The memory device may further include a plurality of memory cells in each array. Each memory cell may include a transistor and a capacitor electrically coupled to the at least one transistor. The capacitor may be configured to store data bits. The local sense amplifier may be configured to amplify a signal from the global bit line to the local bit line of the corresponding array based on a reference signal. The memory device may also include an amplifier or a buffer configured to provide a reference signal to drive a plurality of local sense amplifiers including the local sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in this application and constitute a part of the specification, illustrate various aspects of the disclosure and, together with the description, serve to further explain the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0012] Figure 1 A method of generating a reference voltage in a ferroelectric memory cell is shown.

[0013] Figure 2 A method of generating a reference voltage in a ferroelectric memory cell according to some embodiments of the present disclosure is shown.

[0014] Figure 3 Local sense amplification is shown.

[0015] Figure 4A Details of a local sense amplifier are shown in accordance with some embodiments.

[0016] Figure 4B Additional details of local sense amplifier implementations according to some embodiments are shown.

[0017] Figure 4C Additional details regarding enlarged components of certain embodiments of the present disclosure are shown.

[0018] Figure 4D The corresponding embodiment of the present disclosure is shown. Figure 4B and 4C control signal.

[0019] Figure 4E Write control waveforms according to certain embodiments of the present disclosure are shown.

[0020] Figure 5 An arrangement of a memory device according to some embodiments is shown.

[0021] Figure 6 A unity gain buffer with large signal zero insertion is shown according to some embodiments of the present disclosure.

[0022] Figure 7 A single-transistor, single-capacitor cell of a memory device in accordance with some embodiments is shown.

[0023] Fig. 8A A method of operating a memory device according to some embodiments is shown.

[0024] Figure 8B Another method of operating a memory device according to some embodiments is shown.

[0025] Fig. 9 Additional methods according to certain embodiments of the present disclosure are shown.

[0026] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present invention may also be used in a variety of other applications.

[0028] It should be noted that references to "one embodiment", "embodiment", "example embodiment", "some embodiments", etc. in the specification indicate that the described embodiments may include specific features, structures or characteristics, but each embodiment may not necessarily include the specific features, structures or characteristics. In addition, such wording does not necessarily refer to the same embodiment. In addition, when a specific feature, structure or characteristic is described in conjunction with an embodiment, whether or not it is explicitly described, a person skilled in the relevant art will be able to implement such feature, structure or characteristic in conjunction with other embodiments within the scope of knowledge. In general, terms can be understood at least in part from their use in the context. For example, the term "one or more" used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "one", "an" or "the" can also be understood to express singular or plural usage, at least in part depending on the context. In addition, also at least in part depending on the context, the term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but rather to allow for the presence of additional factors that may not be explicitly described.

[0029] The memory cell array of the ferroelectric memory device may include a plurality of bit lines and a plurality of word lines extending across each other, and a plurality of memory cells may be arranged in a matrix form at positions corresponding to the respective intersections of the lines. Each memory cell may include: at least one memory cell selection transistor, wherein the gate electrode of the memory cell selection transistor may receive a signal from the word line; and at least one ferroelectric capacitor, whose top plate is connected to the source of the memory cell selection transistor and whose bottom plate is connected to the cell plate line. This simplest structure may be referred to as "1T1 C". The ferroelectric capacitor has a residual polarization characteristic to generate positive or negative residual polarization according to the high / low relationship between the voltage applied to the ferroelectric capacitor from the bit line via the memory cell selection transistor and the voltage applied from the cell plate line to the bottom plate of the ferroelectric capacitor.

[0030] Some embodiments may be particularly beneficial for 1T1 C cells, which are different from two-transistor, two-capacitor (2T2C) cells. In the latter, self-referencing can be achieved using two ferroelectric capacitors: a true memory cell and a complementary memory cell to store storage states of opposite polarity in pairs. 2T2C can read (or sense) 0 / 1 or write 0 / 1 using a comparator without any additional reference voltage. After the comparator is used to amplify the signal on the true / complementary bit line to the appropriate voltage level to complete the write operation, the write back can be performed while the read operation is in progress.

[0031] In the case of 1T1 C cells, it may be necessary to generate a reference voltage to distinguish the cell information. In addition to the normal array, an additional FRAM reference cell pair storing 0 and 1 can be physically added to the memory array. In read, after the 0 / 1 reference cell charge is dumped onto the two local reference bit lines, the average of the two local reference bit line voltages after sharing the charge with the FRAM 1 / 0 cells in read represents the reference voltage level that can be used for 1T1 C sensing.

[0032] In 2T2C, one bit of information may require two transistors and two FRAM capacitors to store. In contrast, in 1T1 C, where a properly generated reference voltage can be used by multiple 1T1 C cells in operation, the one bit of information may rely on as few as one transistor and one FRAM capacitor to store. The number of additional reference cell pairs may depend on process, cell device engineering, and circuit performance. The array efficiency (area) of the 1T1 C scheme can be higher than that of the 2T2C scheme, potentially by up to 50%.

[0033] For 1T1 C in a write operation, the global bit line is driven to a logic 0 or 1 with actual data. The global bit line can be driven with a rail-to-rail supply voltage. Due to the architecture, the global bit line signal may not be able to drive the local bit line to the rail-to-rail supply voltage. The local bit line may require a reference voltage and a local comparator / amplifier in a write operation to amplify the local bit line voltage to the full rail-to-rail supply voltage. Differential sensing can be used to convert potentially weak signals on the local bit line to a rail-to-rail data signal. The local bit line can address, for example, 256 individual 1T1 C cells connected to a single local bit line.

[0034] Certain embodiments place op amps / buffers precisely at array boundaries. This implementation can allow for identical capacitance between data bit lines and reference bit lines, and properly average the 0 and 1 reference bit line voltages, as well as buffering the generated reference voltage to drive local sense amplifiers (of any type) for 1T1 C sensing. This can be a fundamental aspect of 1T1 CFRAM architecture.

[0035] Figure 1 A method of generating a reference voltage for a 1T1 C architecture in a ferroelectric memory cell array is shown. In this method, two reference cells storing "0" and "1" information are used on each selected word line (same as conventional memory cells). 1 is the total charge released by a cell storing logic 1 during a read operation, Q 0 is the total charge released by cells storing logic 0. In a read operation, when the charge is dumped out to the local bit line, a voltage is generated on the corresponding local bit line. Figure 1 In , gm represents a transconductance circuit and TI represents a transimpedance circuit. The transconductance circuit performs a conversion from an input voltage to an output current, and the transimpedance circuit performs a conversion from an input current to an output voltage. The output of the transconductance circuit of the reference cell can be summed and fed to the input of two subsequent transimpedance circuits to generate an output reference voltage, which can then be shared by the comparators of all bit lines. A word line (WL) can have more than one cell (c) including a reference cell, which is identified as 1 and 0 for the logic values ​​stored therein. There may be a cell bit line capacitance (Cb1) associated with each bit line. For practical design considerations (offset, mismatch, kickback noise, and speed, etc.), the transimpedance circuit and transconductance circuit of each bit line may consume a large chip size and may not have production value in practical applications.

[0036] Figure 2 A new method of generating a reference voltage for a 1T1 C architecture in a ferroelectric memory cell array according to some embodiments of the present disclosure is shown. Figure 1 The circuit, for each word line, Figure 2 The circuit may include two reference cells, which store logic 1 and logic 0 respectively. Figure 2 In the method, each local bit line of the actual cell or the reference cell can be terminated by a comparator just at the boundary of the local bit line. The architecture can allow the same local bit line capacitance in the read operation of the data cell and the reference cell. In the read operation, by summing the charges of the "0" and "1" cells on the two local bit line capacitors, Vref can be generated as the average of V1 (the local bit line voltage derived from the logic 1 charge dumped into the local bit line capacitor) and V0 (the local bit line voltage derived from the logic 0 charge dumped into the local bit line capacitor). The local bit lines can be matched in the cell array, and the bit line capacitances can also be matched.

[0037] Although Vref generated in this manner may be an appropriate voltage, it will not be able to directly drive the large capacitive load of the subsequent comparator. Therefore, the unity gain amplifier / buffer 210 may be provided with sufficient drive capability to buffer the reference voltage Vref. Other ways of generating Vref are also allowed.

[0038] The unity gain buffer 210 can be implemented using an operational amplifier (op-amp). The connection of the op-amp as a unity gain amplifier is illustrated by using a feedback path. The unity gain buffer 210 can avoid drawing any current from the input source. Instead, the unity gain buffer can isolate the input side (reference cell) from the output side (comparator). Figure 2As shown, the output of unity gain buffer 210 can be loaded with a capacitance associated with, for example, a reference bias. For each comparator, each local bit line and each connection of the reference bias can be viewed as the same capacitive load for matching. The exact interconnection and circuit configuration of the comparators is not shown because it can vary. Figure 1 Compared to the reference voltage approach in , the unity-gain amplifier is much smaller in size and can implement an active circuit with a closed-loop response and low output impedance for the highest drive capability.

[0039] Figure 3 shows the local sensing amplification. Figure 3 As shown, the local sense amplifier - where some connections are omitted for simplicity of explanation - can include a sense transistor 310, which is shown as a p-type transistor. There can also be a pair of p-type transistors 320a, 320b and a pair of n-type transistors 330a, 330b, which can be connected to amplify the signal from the local bit line (such as in the case of a read operation). The second pair of n-type transistors 340a, 340b can be used as a passgate. Thus, for example, during a read operation, the charge can be sampled and held by the passgate n-type transistors 340a / 340b (for the cell signal and the reference voltage, respectively), and the power supply voltage such as vcc is provided by transistor 310, and the p-type transistors 320a and 320b and the n-type transistors 330a and 330b can amplify the signal in the hold mode. Subsequently, 340a will be turned on to allow the local bit line to be driven to the rail-to-rail supply voltage. Finally, transistor 350 can be turned on to allow the local bit line to drive the global bit line and pass the sensed data to the peripheral circuit.

[0040] Other local sensing circuits / operations are also allowed. Figure 3 The particular arrangements shown in should be regarded as examples rather than limitations.

[0041] Figure 4A The local sense amplifier implementation is shown in FIG. Figure 4AAs shown, for a read operation, it may be necessary to sample the local bit line and REFSA signal onto the internal nodes of the cross-coupled pair, turn off the pass transistors on both sides, use local amplification to obtain the logic 0 / 1 on the internal nodes of the cross-coupled pair, and then release the transmission gate on the local bit line side to amplify only the local bit line to the rail-to-rail supply voltage. This is not required on the reference side. FRAM may use destructive read technology. Therefore, it may be necessary to write back each bit at the end of the read. The 1T1 C write-back operation here can be automatically performed at the end of the read of the FRAM cell. On the reference side, the write-back can use a dedicated driver that simply always writes 1 and 0 back to the reference cell respectively with any algorithm (such as always the same value, always the opposite value to the previous write-back, or any other desired algorithm).

[0042] Figure 4A In particular, some details of the local sense amplifier according to some embodiments are shown. Figure 4A As shown, based on the reference voltage VREF, a reference voltage REFSA can be provided to the local sense amplifier via the unity gain buffer 210. The reference voltage can be as shown above. Figure 2 As shown, or obtained by any other desired technique. The local sense amplifier may be referred to as a local sense amplifier because, in a sense, the amplifier may need to sense whether the data level is high or low relative to the reference voltage REFSA / VREF, and then drive the data signal level on the LBL to the rail. In other words, if the voltage of the signal is higher than the buffered reference voltage REFSA, the local sense amplifier may drive the signal to a high power supply level, and if the signal is lower than the buffered reference current REFSA, the local sense amplifier circuit may drive the signal to a low power supply level.

[0043] The reference voltage can be provided to the local sense amplifier through the first gate 410a used as a transmission gate. Similarly, the second gate 410b can be used as a transmission gate for the read operation of the memory device. During the write operation, the third gate 420 can allow the signal from the global bit line (GBL) to pass to the local bit line (LBL). On the contrary, during the read operation, the signal from the local bit line can first pass through the second gate 410b and be amplified by the rail-to-rail amplifier 430, which can be connected to drive the signal to high when the signal is higher than the reference voltage and drive the signal to low when the signal is lower than the reference voltage. Other amplification circuits are also allowed. Once the signal has been amplified, the third gate 420 can allow the signal to pass to the global bit line to the secondary sensing operation away from the local bit line.

[0044] In a write operation, the write data passed from the global bit line to the local bit line may need to be amplified. For example, in this case, the signal from the global bit line can pass through the third gate 420 and the second gate 410b. The signal can then be amplified by the rail-to-rail amplifier 430. The signal can then be returned through the second gate 410b at the full logic supply level and passed to the local bit line. The first gate 410a, the second gate 410b, and the third gate 420 can each be implemented by one or more transistors.

[0045] In a write operation, the reference can be generated in any desired manner. For example, the write reference voltage can be generated exactly the same as the read reference voltage. Other ways of generating the write reference can also be used because the write signal can have a very large signal margin between 1 and 0, which comes from the global bit line as a full track signal.

[0046] Figure 4B Additional details of local sense amplifier implementations according to some embodiments are shown. Figure 4B As shown, for a read operation, it may be necessary to sample the local bit line and REFSA signal onto the internal nodes of the cross-coupled pair, turn off the pass transistors on both sides, use local amplification to obtain the logic 0 / 1 on the internal nodes of the cross-coupled pair, and then release the transmission gate on the local bit line side to amplify only the local bit line to the rail-to-rail supply voltage. This will not be needed on the reference side. FRAM may use destructive read technology. Therefore, it may be necessary to write back each bit at the end of the read. The 1T1C write-back operation here can be automatically performed at the end of the read of the FRAM cell. On the reference side, the write-back can use a dedicated driver that simply always writes 1 and 0 back to the reference cell respectively with any algorithm (for example, always the same value, always the opposite value to the previous write-back, or any other desired algorithm).

[0047] Figure 4B In particular, details of a local sense amplifier according to some embodiments are shown. Figure 4B As shown, based on the reference voltage VREF, a reference voltage REFSA can be provided to the local sense amplifier via the unity gain buffer 210. The reference voltage can be as shown above. Figure 2As shown, or obtained by any other desired technique. The local sense amplifier may be referred to as a local sense amplifier because, in a sense, the amplifier may need to sense whether the data level is high or low relative to the reference voltage REFSA / VREF, and then drive the data signal level on LBL to the rail. In other words, if the voltage of the signal is higher than the buffered reference voltage REFSA, the local sense amplifier may drive the signal to a high power supply level, and if the signal is lower than the buffered reference current REFSA, the local sense amplifier circuit may drive the signal to a low power supply level.

[0048] The reference voltage can be provided to the local sense amplifier by the first complementary transistor pair 440a used as a transmission gate. If an n-channel transistor with a boosted gate bias is used, a transmission gate may not be required. Similarly, the second complementary transistor pair 440b can be used as a transmission gate for the read operation of the memory device. During the write operation, the first transistor 450 can allow the signal from the global bit line (GBL) to be passed to the local bit line (LBL). On the contrary, during the read operation, the signal from the local bit line can first pass through the second complementary transistor pair 440b and be amplified by the amplification component 460, which can be connected to drive the signal to high when the signal is higher than the reference voltage and drive the signal to low when the signal is lower than the reference voltage. Other such amplification circuits are also allowed to be used. Once the signal has been amplified, the first transistor 450 can allow the signal to be passed to the global bit line to the secondary sensing operation away from the local bit line.

[0049] In a write operation, the write data passed from the global bit line to the local bit line may need to be amplified. For example, in this case, the signal from the global bit line can pass through the first transistor 450 and the second complementary transistor pair 440b. The signal can then be amplified by the amplification unit 460. The signal can then be returned through the second complementary transistor pair 440b at a full logic supply level and passed to the local bit line.

[0050] In some embodiments, the first complementary transistor pair 440a and the second complementary transistor pair 440b can be simply replaced by n-type transistors, thereby reducing chip size. This is feasible when the n-channel gate voltage can be increased.

[0051] Figure 4C Additional details of the enlarged components of certain embodiments of the present disclosure are shown. Figure 4CAs shown, the amplification unit 460 may include a first p-type transistor 470a controlled by a signal SENn, which may be used to provide Vcc to the node NC. A reference voltage may be provided at the node NB. The signal DI SSA may provide a path for the voltage (i.e., Vss) at the node ND for the node NA and the node NB, respectively, through an n-type transistor 470f or an n-type transistor 470g, which may be a low voltage or a ground voltage. The signal DI SSA may be considered as a sense amplifier disable signal that resets the internal node to VSS, and SENn may be considered as a sense enable signal.

[0052] When n-type transistor 470f and n-type transistor 470g are turned off, n-type transistors 470d and 470e can be controlled by the voltages at nodes NA and NB, respectively. When the voltage at NA is initially higher than the voltage at NB, the voltage at NA can be driven toward Vcc by the operation of interconnected transistors 470b, 470c, 470d, and 470e. Similarly, when the voltage at NA is initially lower than the voltage at NB, the voltage at NA can be driven toward Vss by the operation of interconnected transistors 470b, 470c, 470d, and 470e. This configuration can be considered a rail-to-rail amplifier because the voltage at NA can be driven to one of the two rail voltages: either Vcc or Vss, depending on whether the voltage at NA is initially higher or lower than the voltage at NB. Therefore, the arrangement of transistors 470b, 470c, 470d, and 470e can provide a comparison result based on the relative values ​​of nodes NA and NB, in combination with other circuit elements shown or similar or equivalent circuit elements.

[0053] Figure 4D The corresponding embodiment of the present disclosure is shown. Figure 4B and 4C control signal. Figure 4D It shows how signals such as DI SSA and SENn can be applied in coordination with each other. Figure 4D The pattern shown in may correspond to a single read cycle. The same pattern may be repeated again for additional read cycles. For example, Figure 4D As shown, initially at time T0, signal DI SSA may be high, thereby disabling the rail-to-rail amplifier and maintaining nodes NA and NB at VSS.

[0054] At the same time, also at time T0, ENLBL and ENREFBL can be high, while complementary signals ENLBLn and ENREFBLn can be low. Likewise, SENn can be high, thereby preventing Vcc from being provided to node NC. LSOUTEN can be high, thereby allowing the signal from GBL to reach node NA through the second complementary transistor pair 440b.

[0055] At time T1, signal DI SSA may be set low. Then, at T2, ENLBL may be set low, while ENLBLn may be set high, effectively closing the gate at the local bit line. Similarly, at T2, ENLREFBL may be set low, while ENLREFBLn may be set high, effectively closing the gate to the reference voltage source. At T3, SENn may be set low to allow Vcc to be provided to node NC.

[0056] After some stabilization, at T4, the gate at the local bit line can be effectively reopened by taking ENLBLn low and ENLBL high. Thereafter, at time T5, LSOUTEN can be taken low, effectively closing the gate between the global bit line and the local bit line after the read operation is completed.

[0057] Figure 4E 1 shows a write control waveform according to some embodiments of the present disclosure. Figure 4E The method shown can be used, for example Figure 4A , 4B and / or the circuit shown in 4C. The write control method using these waveforms can be used with waveforms such as Figure 4D The read control method shown is used in conjunction with Figure 4D and 4E Similar timeline labels T0, T1, etc. are used in , but for a given memory cell, these processes occur at different times. Therefore, timeline references should be understood relative to a specific process, such as a read process or a write process, and should not be understood as absolute terms. Figure 4E The pattern shown in may correspond to a single write cycle. The same pattern may be repeated again for additional write cycles.

[0058] like Figure 4E As shown, T0 may be a pre-write stage. At this time, DI SSA and ENLREFBL may be low, while ENLBL and SENn may be high. Therefore, at time T0, ENLBL and ENREFBL may be high, while complementary signals ENLBLn and ENREFBLn may be low. Similarly, SENn may be high, thereby preventing Vcc from being provided to node NC.

[0059] At time T1, DI SSA may be set high to reset the internal node comparator, and ENLBL may be set low. Then, around time T2, a "1" or "0" from the global bit line may arrive. In the case of a "1", the voltages on the global and local bit lines may ramp up, crossing the reference voltage REFSA around the middle of T2. At T3, after some ramp-up time has been allowed, DI SSA may be set low again, and ENLBL and ENLREFBL may be set high.

[0060] At T4, in the case of writing a "1", the global bit line has pulled the local bit line to a sufficiently high level. Also at T4, SENn can be set low to enable the comparator to place the local bit line at the full power rail level. This can pull the local bit line to Vcc in the case of writing a "1", or keep the local bit line at VSS in the case of writing a "0".

[0061] At T5, ENLBL and ENREFBL can be set low, while complementary signals ENLBLn and ENREFBLn can be set high. This can isolate the internal nodes of the comparator from external capacitive loads on the local bit line and REFSA signal line. This can be provided for comparator accuracy and signal development speed. The gap between T4 and T5 can be very small on a time scale. Then, at T6, with minimal and balanced capacitive loads on the internal nodes, the comparator can fully amplify the write signal to the appropriate logic level on its internal node. At T7, ENBLBL can be set high again to fully drive the local bit line to the full VCC / VSS level.

[0062] Figure 5 An arrangement of a memory device according to some embodiments is shown. Figure 5 A plurality of sectors are shown, which are labeled Sector 1 and Sector 0 for convenience. Figure 5 As shown, each sector may include multiple memory arrays with local sense amplifiers (SA) between them. Each array may have local bit lines.

[0063] The local sense amplifiers may operate as described above to amplify signals to and / or from the global bit lines. Additionally, there may be a global sense amplifier 510 and a write / back controller. There may be other elements and components of the memory, these features are highlighted only for convenience and not limitation.

[0064] Figure 5The architecture shown in may be similar to that of a dynamic random access memory (DRAM). The architecture may be based on chip size and performance considerations. Other architectures are also allowed. The overall structure may be designed to allow for pre-amplification and / or multiple stages of amplification (e.g., one stage of amplification may be between the local and global bit lines, and another stage of amplification may be after the global bit lines). Although the architecture may have some similarities to the DRAM architecture, the physical characteristics of the FRAM 1T1 C cell may involve very different operations and related structures. Likewise, although FRAM and DRAM may appear to have similar abbreviations, the characteristics of the different memory types may be very different from each other.

[0065] Figure 6 FIG. 4 shows a unity gain buffer with large signal zero insertion according to some embodiments of the present disclosure. Figure 6 As shown, the amplifier circuit 610 can be configured to provide a reference value REFSA. A zero resistor Rz and a balancing capacitor Cz can be provided. Compared with the two reference cells, the balancing capacitor Cz can have the following size: the size is configured to balance the number of normal cells on the bit line. Therefore, in the case of 256 cells, the capacitance of Cz can be about two hundred and fifty-six times the capacitance of the capacitor in the 1T1 C cell of the bit line to provide a balance of matched impedance for noise elimination. This large capacitance may have a large stabilization time. Therefore, the bias circuit 620 can provide a bias voltage to the capacitor Cz to improve the stabilization time.

[0066] Figure 7 A single transistor, single capacitor cell of a memory device according to some embodiments is shown. Figure 7 As shown, in a 1T1 C cell, there may be one transistor 710 and one ferroelectric capacitor 720. The capacitor may be connected to the plate line as well as the transistor 710. As shown, the transistor 710 may be connected to the bit line and the word line so that the word line may select whether to provide the bit line charge to the ferroelectric capacitor 720 using the transistor 710.

[0067] Fig. 8A A method of operating a memory device according to some embodiments is shown. The method may include: at 810, corresponding data bits are present in the plurality of memory cells, for example, because they have been previously stored in the plurality of memory cells in a previous write cycle. Each memory cell, for example, Figure 7 The device may include a transistor and a capacitor electrically coupled to the at least one transistor. The capacitor may be a ferroelectric capacitor.

[0068] like Fig. 8AAs shown, the method may include: at 820a, transmitting data to be read from multiple memory cells on the local bit lines. The method may also include: at 830a, using the global bit lines to communicate with the local bit lines to transmit data to be read from multiple memory cells.

[0069] The method may further include: at 840a, amplifying a signal in the local bit line based on the reference signal using a local sense amplifier and transmitting the amplified signal to the global bit line. Figure 4A and Figure 4B The circuit example in is used to illustrate.

[0070] The method may further include: at 850, providing a reference signal using an amplifier or a buffer. The method may also include: at 852, storing a logic 1 and a logic 0 by a reference cell pair. These values ​​may be considered reference values. Storing a logic 1 and a logic 0 may include storing the same logic value by each reference cell in the reference cell pair, which may be Fig. 8A At 854, the same value is shown in each cell (e.g., one cell is always written with a 0 and the other cell is always written with a 1). As another alternative, at 856, storing a logical 1 and a logical 0 may include alternating logical values ​​by each reference cell in the reference cell pair.

[0071] The amplifying at 840a may include amplifying a signal when data is to be written to the memory cell and amplifying an additional signal when additional data is to be read from the memory cell.

[0072] As described above, the method may include providing a reference signal using an amplifier or a buffer at 850. The buffer may be a unity gain buffer, such as Figure 2 4. The unit gain buffer 210 and / or the inputs to the unit gain buffer 210 can be considered as a reference voltage source individually or in combination. The unit gain buffer can buffer the voltage provided by the reference cell pair configured to store logic 1 and logic 0.

[0073] As shown in the figure, for example Figure 2 In the embodiment, the reference cell pair may be configured to provide an average voltage of the reference cell pair as the voltage.

[0074] As shown in the figure, for example Figure 5 In , multiple units can be arranged into array pairs. Therefore, Fig. 8AThe amplification at 840a may include amplifying the signals of both arrays of the array pair through local sense amplifiers. Thus, there may be a two-to-one ratio of arrays to local sense amplifiers in the memory device. In addition, each array in the array pair may have its own separate local bit line. Both arrays in the array pair may be connected to a global bit line. Fig. 8A The method may further include, at 860, amplifying a signal transmitted on or to the global bit line by a global sense amplifier connected to the global bit line and remote from the local sense amplifier. Figure 5 The global sense amplifier 510 shown in the example of FIG. 5 can be constructed similarly to the local sense amplifier. Alternatively, other forms of structures for the global sense amplifier are allowed.

[0075] Figure 8B Another method of operating a memory device according to some embodiments is shown. Fig. 8A Examples focusing on the reading process can be provided, but Figure 8B An example focusing on a write process may be provided. The method may include: at 815, storing corresponding data bits in a plurality of memory cells. Fig. 8A In the case of Figure 8B In the case of, each memory cell may include a transistor and a capacitor electrically coupled to the at least one transistor, for example Figure 7 The capacitor may be a ferroelectric capacitor.

[0076] like Figure 8B As shown, at 820b, the method may include transmitting data to be written into the plurality of memory cells on the local bit lines. The method may also include: at 830b, using the global bit lines to communicate with the local bit lines to transmit the data to be written into the plurality of memory cells.

[0077] The method may also include: at 840b, amplifying a signal based on a reference signal using a local sense amplifier and transmitting the amplified signal from the global bit line to the local bit line. The method may also include: at 855, providing a reference signal using an amplifier or a buffer. As described above, the reference signal may be generated by any desired circuit. In other aspects, Fig. 8A The method can be similar to Figure 8B The method includes applicability to a memory device including an array of memory cells.

[0078] Fig. 9 Another method according to certain embodiments of the present disclosure is shown. Fig. 9 The method can be considered as Fig. 8A A portion of or at least associated with the amplification at 840a in FIG. Fig. 9As shown, the method may include isolating the local bit line node and the reference voltage node. This may be accomplished using, for example, Figure 4B Elements 440a and 440b or Figure 4A The third gate 420 can also be considered to provide further isolation of the local bit line.

[0079] Fig. 9 The method may further include: driving the local bit line at 920. Figure 4D The control signals shown and Figure 4B and Figure 4C The circuit shown in FIG. 1 is used to perform driving of the local bit lines. Once the local bit lines have been driven to a high voltage or a low voltage, such as one of two rail voltages in a rail-to-rail arrangement, at 930, the global bit lines can be enabled for second-level sensing / signaling, such as using a remote global bit line sensor. This can be accomplished by using signals LSOUTEN and Figure 4B The first transistor 450 or Figure 4A The third gate 420 in performs the enabling.

[0080] According to one aspect of the present disclosure, a memory device may include a plurality of memory cells, each memory cell including at least one transistor and a capacitor electrically coupled to the at least one transistor. The capacitor may be configured to store data bits. The memory device may also include a local bit line configured to convey data to be written into the plurality of memory cells. The memory device may further include a global bit line configured to communicate with the local bit line to convey data to be written into the plurality of memory cells. The memory device may additionally include a local sense amplifier configured to amplify a signal from the global bit line based on a reference signal and transmit the amplified signal to the local bit line. The local sense amplifier may be configured to generate an amplified signal based on a comparison with a reference signal.

[0081] In some embodiments, the memory device may further include a reference voltage source configured to generate a reference signal.The memory device may further include a first gate between a node of the local sense amplifier configured to receive the reference signal and the reference voltage source.

[0082] In some embodiments, the first gate may include a complementary pair of transistors.

[0083] In some embodiments, during a write cycle, the gate can be configured to isolate a reference signal at the node before generating the amplified signal.

[0084] In some embodiments, the memory device may further include a second gate between the global bit line and the local bit line. The second gate may be configured to isolate the local bit line from the local sense amplifier prior to generating the amplified signal during a write cycle.

[0085] In some embodiments, the second gate may include a complementary pair of transistors.

[0086] In some embodiments, the local sense amplifier may be configured to amplify a signal when data is to be written to the memory cell and to amplify an additional signal when additional data is to be read from the memory cell.

[0087] In some embodiments, the local sense amplifier can be configured to drive the local bit line to a high voltage when the signal is higher than a reference signal.

[0088] In some embodiments, the local sense amplifier can be configured to drive the local bit line to a low voltage when the signal is lower than a reference signal.

[0089] In some embodiments, a plurality of memory cells may be arranged into an array pair, and both arrays of the array pair may be configured to be amplified by a local sense amplifier.

[0090] In some embodiments, each array in the array pair may include a local bit line, and both arrays of the array pair may be connected to a global bit line.

[0091] In some embodiments, the memory device may further include a global sense amplifier connected to the global bit line, remote from the local sense amplifier and configured to amplify a signal conveyed on the global bit line.

[0092] According to another aspect of the present disclosure, a method of operating a memory device may include storing corresponding data bits in a plurality of memory cells, each memory cell including at least one transistor and a capacitor electrically coupled to the at least one transistor. The method may also include transmitting data to be read from or written to the plurality of memory cells on local bit lines. The method may further include communicating with the local bit lines using global bit lines to transmit data to be written to the plurality of memory cells. The method may additionally include amplifying a signal from the global bit line based on a reference signal using a local sense amplifier and transmitting the amplified signal to the local bit line, wherein the local sense amplifier generates the amplified signal based on a comparison with the reference signal.

[0093] In some embodiments, the method may further include isolating the local bit line from the global bit line by the local sense amplifier during a write cycle prior to amplifying.

[0094] In some embodiments, the method may further include providing a reference signal using a reference voltage generator.The method may further include isolating the local sense amplifier from the reference voltage generator during a write cycle prior to amplification.

[0095] In some embodiments, the method may further include driving the local bit line with the amplified signal.

[0096] In some embodiments, amplification may include amplifying a signal when data is to be written to the memory cell and amplifying another signal when additional data is to be read from the memory cell.

[0097] In some embodiments, the plurality of memory cells may be arranged in an array pair, and the amplifying may include amplifying signals of both arrays of the pair of arrays via local sense amplifiers.

[0098] In some embodiments, the method may further include amplifying a signal conveyed on the global bit line by a global sense amplifier connected to the global bit line and remote from the local sense amplifier.

[0099] According to another aspect of the present disclosure, a memory device may include a plurality of memory cell array groups connected by global bit lines. Each array group may include a plurality of arrays. Each array in the array group has a local bit line. The memory device may also include a local sense amplifier connected between array pairs of the array group and connected to each local bit line of the array group. The memory device may further include a plurality of memory cells in each array, each memory cell including at least one transistor and a capacitor electrically coupled to the at least one transistor. The capacitor may be configured to store data bits. The local sense amplifier may be configured to amplify a signal from a global bit line to a local bit line of a corresponding array based on a reference signal. The local sense amplifier may be configured to generate an amplified signal based on a comparison with a reference signal.

[0100] The foregoing description of specific embodiments will fully reveal the general nature of the present disclosure, so that others can easily modify and / or adapt these specific embodiments for various applications without departing from the general concept of the present disclosure and without excessive experimentation by applying knowledge within the technical scope of the art. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation, so that the terms or wording of this specification will be interpreted by those skilled in the art based on teaching and guidance.

[0101] The embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined here. Alternative boundaries may be defined as long as the specified functions and their relationships are properly performed.

[0102] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0103] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, comprising: a plurality of memory cells, each memory cell comprising at least one transistor and a capacitor electrically coupled to the at least one transistor, wherein the capacitor is configured to store a data bit; local bit lines configured to convey data to be written to the plurality of memory cells; a global bit line configured to communicate with the local bit lines to carry data to be written to the plurality of memory cells; as well as a local sense amplifier configured to amplify a signal from the global bit line based on a reference signal and transmit the amplified signal to the local bit line; Wherein the local sense amplifier is configured to generate the amplified signal based on a comparison with the reference signal.

2. The memory device according to claim 1, further comprising: a reference voltage source, configured to generate the reference signal; as well as A first gate is located between a node of the local sense amplifier configured to receive the reference signal and the reference voltage source.

3. The memory device of claim 2, wherein the first gate comprises a complementary pair of transistors. 4 . The memory device of claim 2 , wherein during a write cycle, the gate is configured to isolate the reference signal at the node before generating the amplified signal.

5. The memory device according to claim 1, further comprising: A second gate is located between the global bit line and the local bit line, wherein the second gate is configured to isolate the local bit line from the local sense amplifier during a write cycle before generating the amplified signal. The memory device of claim 5 , wherein the second gate comprises a complementary pair of transistors. 7 . The memory device of claim 1 , wherein the local sense amplifier is configured to amplify the signal when data is to be written to the memory cell and to amplify an additional signal when additional data is to be read from the memory cell. 8 . The memory device of claim 1 , wherein the local sense amplifier is configured to drive the local bit line to a high voltage when the signal is higher than the reference signal. 9 . The memory device of claim 8 , wherein the local sense amplifier is configured to drive the local bit line to a low voltage when the signal is lower than the reference signal.

10. The memory device of claim 1, wherein the plurality of memory cells are arranged in an array pair, and both arrays of the array pair are configured to be amplified by the local sense amplifier.

11. The memory device of claim 10, wherein each array of the array pair comprises a local bit line, and wherein both arrays of the array pair are connected to the global bit line.

12. The memory device according to claim 1, further comprising: A global sense amplifier is connected to the global bit line, remote from the local sense amplifier and configured to amplify a signal transmitted on the global bit line.

13. A method of operating a memory device, the method comprising: storing corresponding data bits in a plurality of memory cells, each memory cell comprising at least one transistor and a capacitor electrically coupled to the at least one transistor; conveying data to be read from or written to the plurality of memory cells on local bit lines; communicating with the local bit lines using global bit lines to convey data to be written to the plurality of memory cells; as well as A signal from a global bit line is amplified based on a reference signal using a local sense amplifier and the amplified signal is transmitted to a local bit line, wherein the local sense amplifier generates the amplified signal based on a comparison with the reference signal.

14. The method according to claim 13, further comprising: During a write cycle prior to amplification, the local bit line is isolated from the global bit line by the local sense amplifier.

15. The method according to claim 13, further comprising: Using a reference voltage generator to provide the reference signal; as well as The local sense amplifier is isolated from the reference voltage generator during a write cycle prior to amplification.

16. The method according to claim 13, further comprising: The local bit line is driven using the amplified signal.

17. The method of claim 13, wherein the amplifying comprises amplifying the signal when data is to be written to the memory cell and amplifying an additional signal when additional data is to be read from the memory cell.

18. The method of claim 13, wherein the plurality of memory cells are arranged in an array pair, and wherein the amplifying comprises amplifying signals of both arrays of the array pair by the local sense amplifiers.

19. The method of claim 13, further comprising: The signal conveyed on the global bit line is amplified by a global sense amplifier connected to the global bit line and remote from the local sense amplifiers.

20. A memory device comprising: a plurality of memory cell array groups connected by global bit lines; Each array group includes a plurality of arrays; Each array of the array group has a local bit line; a local sense amplifier connected between the array pairs of the array group and connected to each local bit line of the array group; as well as A plurality of memory cells in each array, each memory cell comprising at least one transistor and a capacitor electrically coupled to the at least one transistor, wherein the capacitor is configured to store a data bit, wherein the local sense amplifier is configured to amplify a signal from the global bit line to the local bit line of the corresponding array based on a reference signal, wherein the local sense amplifier is configured to generate an amplified signal based on a comparison with the reference signal.

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